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18 F 2620

This document describes the configuration settings for the PIC18F2620 microcontroller. It lists the configuration registers and bits that control features such as the oscillator selection, watchdog timer, code protection, and more. Each bit is described in terms of its function and the value that enables or disables the associated feature.

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74 views6 pages

18 F 2620

This document describes the configuration settings for the PIC18F2620 microcontroller. It lists the configuration registers and bits that control features such as the oscillator selection, watchdog timer, code protection, and more. Each bit is described in terms of its function and the value that enables or disables the associated feature.

Uploaded by

librian_30005821
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PIC18F2620

CONFIG1H (address:0x300001, mask:0xCF, default:0x07)


OSC -- Oscillator Selection bits (bitmask:0x0F)
OSC = LP
0xF0 LP oscillator.
OSC = XT
0xF1 XT oscillator.
OSC = HS
0xF2 HS oscillator.
OSC = RC
0xF3 External RC oscillator, CLKO function on RA6.
OSC = EC
0xF4 EC oscillator, CLKOUT function on RA6.
OSC = ECIO6
0xF5 EC oscillator, port function on RA6.
OSC = HSPLL
0xF6 HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1).
OSC = RCIO6
0xF7 External RC oscillator, port function on RA6.
OSC = INTIO67 0xF8 Internal oscillator block, port function on RA6 and RA7.
Internal oscillator block, CLKOUT function on RA6, port function
OSC = INTIO7 0xF9
on RA7.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x40)
FCMEN = OFF 0xBF Fail-Safe Clock Monitor disabled.
FCMEN = ON
0xFF Fail-Safe Clock Monitor enabled.
IESO -- Internal/External Oscillator Switchover bit (bitmask:0x80)
IESO = OFF
0x7F Oscillator Switchover mode disabled.
IESO = ON
0xFF Oscillator Switchover mode enabled.
CONFIG2L (address:0x300002, mask:0x1F, default:0x1F)

PWRT = ON
PWRT = OFF

PWRT -- Power-up Timer Enable bit (bitmask:0x01)


0xFE PWRT enabled.
0xFF PWRT disabled.

BOREN -- Brown-out Reset Enable bits (bitmask:0x06)


BOREN = OFF 0xF9 Brown-out Reset disabled in hardware and software.
Brown-out Reset enabled and controlled by software (SBOREN is
BOREN = ON
0xFB
enabled).
BOREN =
Brown-out Reset enabled in hardware only and disabled in Sleep
0xFD
NOSLP
mode (SBOREN is disabled).
BOREN =
0xFF Brown-out Reset enabled in hardware only (SBOREN is disabled).
SBORDIS

BORV = 0
BORV = 1
BORV = 2
BORV = 3

BORV -- Brown Out Reset Voltage bits (bitmask:0x18)


0xE7 Maximum setting.
0xEF
0xF7
0xFF Minimum setting.
CONFIG2H (address:0x300003, mask:0x1F, default:0x1F)

WDT = OFF
WDT = ON

WDT -- Watchdog Timer Enable bit (bitmask:0x01)


0xFE WDT disabled (control is placed on the SWDTEN bit).
0xFF WDT enabled.

WDTPS -- Watchdog Timer Postscale Select bits (bitmask:0x1E)


WDTPS = 1
0xE1 1:1.
WDTPS = 2
0xE3 1:2.
WDTPS = 4
0xE5 1:4.
WDTPS = 8
0xE7 1:8.
WDTPS = 16
0xE9 1:16.
WDTPS = 32
0xEB 1:32.
WDTPS = 64
0xED 1:64.
WDTPS = 128
0xEF 1:128.
WDTPS = 256
0xF1 1:256.
WDTPS = 512
0xF3 1:512.
WDTPS = 1024 0xF5 1:1024.
WDTPS = 2048 0xF7 1:2048.
WDTPS = 4096 0xF9 1:4096.
WDTPS = 8192 0xFB 1:8192.
WDTPS = 16384 0xFD 1:16384.
WDTPS = 32768 0xFF 1:32768.
CONFIG3H (address:0x300005, mask:0x87, default:0x83)
CCP2MX -- CCP2 MUX bit (bitmask:0x01)
CCP2MX =
PORTBE
CCP2MX =
PORTC

0xFE CCP2 input/output is multiplexed with RB3.


0xFF CCP2 input/output is multiplexed with RC1.

PBADEN -- PORTB A/D Enable bit (bitmask:0x02)


PBADEN = OFF 0xFD PORTB<4:0> pins are configured as digital I/O on Reset.
PBADEN = ON 0xFF PORTB<4:0> pins are configured as analog input channels on Reset.
LPT1OSC -- Low-Power Timer1 Oscillator Enable bit (bitmask:0x04)
LPT1OSC = OFF 0xFB Timer1 configured for higher power operation.
LPT1OSC = ON 0xFF Timer1 configured for low-power operation.

MCLRE = OFF
MCLRE = ON

MCLRE -- MCLR Pin Enable bit (bitmask:0x80)


0x7F RE3 input pin enabled; MCLR disabled.
0xFF MCLR pin enabled; RE3 input pin disabled.
CONFIG4L (address:0x300006, mask:0xC5, default:0x85)

STVREN -- Stack Full/Underflow Reset Enable bit (bitmask:0x01)


STVREN = OFF 0xFE Stack full/underflow will not cause Reset.
STVREN = ON 0xFF Stack full/underflow will cause Reset.

LVP = OFF
LVP = ON

LVP -- Single-Supply ICSP Enable bit (bitmask:0x04)


0xFB Single-Supply ICSP disabled.
0xFF Single-Supply ICSP enabled.

XINST -- Extended Instruction Set Enable bit (bitmask:0x40)


Instruction set extension and Indexed Addressing mode disabled
XINST = OFF
0xBF
(Legacy mode).
XINST = ON
0xFF Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
Background debugger enabled, RB6 and RB7 are dedicated to InDEBUG = ON
0x7F
Circuit Debug.
Background debugger disabled, RB6 and RB7 configured as general
DEBUG = OFF 0xFF
purpose I/O pins.
CONFIG5L (address:0x300008, mask:0x0F, default:0x0F)

CP0 = ON
CP0 = OFF

CP0 -- Code Protection bit (bitmask:0x01)


0xFE Block 0 (000800-003FFFh) code-protected.
0xFF Block 0 (000800-003FFFh) not code-protected.

CP1 = ON
CP1 = OFF

CP1 -- Code Protection bit (bitmask:0x02)


0xFD Block 1 (004000-007FFFh) code-protected.
0xFF Block 1 (004000-007FFFh) not code-protected.

CP2 = ON
CP2 = OFF

CP2 -- Code Protection bit (bitmask:0x04)


0xFB Block 2 (008000-00BFFFh) code-protected.
0xFF Block 2 (008000-00BFFFh) not code-protected.

CP3 = ON
CP3 = OFF

CP3 -- Code Protection bit (bitmask:0x08)


0xF7 Block 3 (00C000-00FFFFh) code-protected.
0xFF Block 3 (00C000-00FFFFh) not code-protected.
CONFIG5H (address:0x300009, mask:0xC0, default:0xC0)

CPB = ON
CPB = OFF

CPB -- Boot Block Code Protection bit (bitmask:0x40)


0xBF Boot block (000000-0007FFh) code-protected.
0xFF Boot block (000000-0007FFh) not code-protected.

CPD = ON
CPD = OFF

CPD -- Data EEPROM Code Protection bit (bitmask:0x80)


0x7F Data EEPROM code-protected.
0xFF Data EEPROM not code-protected.
CONFIG6L (address:0x30000A, mask:0x0F, default:0x0F)

WRT0 = ON
WRT0 = OFF

WRT0 -- Write Protection bit (bitmask:0x01)


0xFE Block 0 (000800-003FFFh) write-protected.
0xFF Block 0 (000800-003FFFh) not write-protected.

WRT1 = ON
WRT1 = OFF

WRT1 -- Write Protection bit (bitmask:0x02)


0xFD Block 1 (004000-007FFFh) write-protected.
0xFF Block 1 (004000-007FFFh) not write-protected.

WRT2 = ON
WRT2 = OFF

WRT2 -- Write Protection bit (bitmask:0x04)


0xFB Block 2 (008000-00BFFFh) write-protected.
0xFF Block 2 (008000-00BFFFh) not write-protected.
WRT3 -- Write Protection bit (bitmask:0x08)

WRT3 = ON
WRT3 = OFF

0xF7 Block 3 (00C000-00FFFFh) write-protected.


0xFF Block 3 (00C000-00FFFFh) not write-protected.
CONFIG6H (address:0x30000B, mask:0xE0, default:0xE0)

WRTC -- Configuration Register Write Protection bit (bitmask:0x20)


WRTC = ON
0xDF Configuration registers (300000-3000FFh) write-protected.
WRTC = OFF
0xFF Configuration registers (300000-3000FFh) not write-protected.

WRTB = ON
WRTB = OFF

WRTB -- Boot Block Write Protection bit (bitmask:0x40)


0xBF Boot Block (000000-0007FFh) write-protected.
0xFF Boot Block (000000-0007FFh) not write-protected.

WRTD -- Data EEPROM Write Protection bit (bitmask:0x80)


WRTD = ON
0x7F Data EEPROM write-protected.
WRTD = OFF
0xFF Data EEPROM not write-protected.
CONFIG7L (address:0x30000C, mask:0x0F, default:0x0F)

EBTR0 = ON
EBTR0 = OFF

EBTR1 = ON
EBTR1 = OFF

EBTR2 = ON
EBTR2 = OFF

EBTR0 -- Table Read Protection bit (bitmask:0x01)


Block 0 (000800-003FFFh) protected from table reads executed in
0xFE
other blocks.
Block 0 (000800-003FFFh) not protected from table reads executed
0xFF
in other blocks.
EBTR1 -- Table Read Protection bit (bitmask:0x02)
Block 1 (004000-007FFFh) protected from table reads executed in
0xFD
other blocks.
Block 1 (004000-007FFFh) not protected from table reads executed
0xFF
in other blocks.
EBTR2 -- Table Read Protection bit (bitmask:0x04)
Block 2 (008000-00BFFFh) protected from table reads executed in
0xFB
other blocks.
Block 2 (008000-00BFFFh) not protected from table reads executed
0xFF
in other blocks.
EBTR3 -- Table Read Protection bit (bitmask:0x08)

EBTR3 = ON
EBTR3 = OFF

Block 3 (00C000-00FFFFh) protected from table reads executed in


other blocks.
Block 3 (00C000-00FFFFh) not protected from table reads executed
0xFF
in other blocks.
0xF7

CONFIG7H (address:0x30000D, mask:0x40, default:0x40)


EBTRB -- Boot Block Table Read Protection bit (bitmask:0x40)
Boot Block (000000-0007FFh) protected from table reads executed
EBTRB = ON
0xBF
in other blocks.
Boot Block (000000-0007FFh) not protected from table reads
EBTRB = OFF
0xFF
executed in other blocks.

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