Ultra Area Efficient Reversible Quantum Radix-2

Booths Recoding Multiplier for Low Power

Applications
Kaveri Talawar

Poonam Hosamani

Assistant Professor, E&C,

SDM College of Engineering and Technology,
Dharwad, India.
[email protected]

Trainee Engineer,
SAI-TEC,
Bangalore, India.
[email protected]

Abstract Reversible logic plays a vital role in Quantum

computing and Nanotechnology which in future can be applied
for low power processor applications. In this paper, we propose,
ultra area efficient reversible quantum multiplier based on
Radix-2 Booths recoding algorithm. The Non-Fault tolerant
Radix-2 Booths recoding architecture is designed and optimized
for Quantum Cost and Garbage Outputs. The proposed
methodology for reversible quantum multiplier shows the
improvement in terms of Quantum Cost, Garbage Outputs and
gates count compared to all the existing reversible quantum
multiplier designs.
Keywords Quantum Cost; Reversible; Multiplier; Booths
recoding; Non-fault tolerant

I.

INTRODUCTION

The standard gates used in the design of digital circuits are

irreversible in nature and every irreversible computation results
in the energy dissipation due to loss of information. According
to Landauers principle [1], erasure of each bit of information
dissipates KTln2 joule of energy where, K is the Boltzmanns
constant and T is the temperature at which the computation is
performed. This particular problem of energy dissipation was
realized by Feynman and Bennett in 1970s. In 1973, Bennett
[2] had shown that the energy dissipation problem of VLSI
circuits can be circumvented by using reversible logic. In
reversible logic, every computed data is preserved so that there
is no loss of information and hence no energy dissipation and
also it was proved that irreversible general purpose computing
automaton can be made reversible at every step, while retaining
their simplicity and ability to do general computations. This
result proves that the thermodynamically reversible computers
can be made physically possible which could perform useful
computations at useful speed with less than KT joule of energy
dissipation per logical step.
Reversible logic also known as the energy recovery logic is
the most challenging technology which is in demand for
designing of low power circuits. Reversible logic supports the
process of running the system both forward and backward. It
means not only the outputs are generated from inputs but the
inputs can be uniquely recovered from the outputs by
computing backwards along the computation history. Every
computed data is preserved and hence there is no loss of

978-1-4799-3975-6/14/$31.00 2014 IEEE

information in a reversible system. Therefore, the energy

dissipation can be reduced or even eliminated if the
computation becomes information lossless. Multipliers are the
fundamental components of computing systems and hence, it is
necessary to optimize the multiplier in terms of delay and
power.
The paper is organized as follows: Related works are
discussed in section II. In section III, the most popular
reversible logic gates are discussed in brief. Booths recoding
algorithm and the proposed work are discussed in Section IV.
Section V contains the comparison and discussion of results.
Finally, the conclusion is presented.
II.

RELATED WORKS

Several reversible multipliers designed using different

reversible logic gates exist in the literature. Most of these
designs are based on the conventional multiplication
algorithms like array multiplication and there is a
comparatively less research directed towards the improvement
in multiplication algorithms.
The 4 bits reversible parallel multiplier was designed using
TS gate (TSG) and Fredkin gates (FRG) [3]. Bhagyalakshmi et
al., [4] proposed a 4 bits multiplier using a new reversible gate
BVPPG and Toffoli gate (TG). Maryam [5] presented parallel
multiplier designed using Peres gate (PG) and modified full
adder (MFA). The reversible multiplier was designed with the
aim of decreasing the depth of the circuit [6] by generating the
partial products in parallel and addition is done using reversible
multi-operand adders. Reversible floating point multipliers [7,
8] were designed based on operand decomposition approach.
An unsigned 4 bits array multiplier and signed Baugh-Wooley
multiplier circuits [9] were implemented using reversible logic.
A novel 4 4 reversible multiplier was designed using Fredkin
gates (FRG) and IG [10, 11] gates for partial product
generation and parallel addition respectively. High
performance 4 4 reversible multiplier [12] was designed
using Peres gates and Modified HNG (MHNG) gates.
Haghparast et al., [13] designed a 4 4 novel reversible
multiplier using Peres gates and HNG gates. An improved
reversible multiplier [14] was designed by using Peres gates
and Double Peres gates (DPG).

2014 IEEE International Conference on Computational Intelligence and Computing Research

III.

REVERSIBLE LOGIC GATES

A reversible logic gate is an N-input N-output device with

one-to-one mapping between its input and output vectors. The
reversible gate must have equal number of inputs and outputs
and each input pattern must generate a unique output pattern.
Also, the fan-out of every signal is equal to one i.e. the gate
output can be used only once. The important parameters known
as reversible design metrics which play a major role in the
design of an optimized reversible logic gate are Gate count,
Constant Input (CI), Garbage Output (GO) and Quantum Cost
(QC). The gate representations of Feynman gate (FG), Fredkin
gate (FRG), Peres gate (PG) and Haghparast Navi gate (HNG)
are shown in Fig. 1. Input vector and output vector for these
gates are the combinations of I (A, B, C, D) and O (P, Q, R, S)
respectively. The Feynman gate is a 2 2 reversible gate with
the QC of 1. The FG gate can be used as a copying gate.
Fredkin gate and Peres gate are 3 3 reversible gates with QC
of 5 and 4 respectively. HNG is a 4 4 reversible gate with the
QC of 6.

multiplier are stored in the shift register. The two least

significant bits of the multiplier are recoded using XOR gate.
The output of this XOR gate i.e., Xnew is the select line of the
multiplexer which selects 0 or Y as the output. The multiplexer
output and the bit X0 of shift register are fed to the XOR gate.
The output of XOR gate are added with 4 most significant bits
of the shift register and Cin bit to generate the partial product
and fed as input to the shift register for the next stage of
operation. The final product will be stored in the shift register
after all the bits of the multiplier are recoded and the generated
partial products are added.

Fig. 2. Architecture for Radix-2 Booths recoding multiplier

This architecture is used for the design of proposed

reversible multiplier. The design of individual block using
reversible logic gates is explained in further sections.
Fig. 1. Gate representations of (a) Feynman gate (b) Fredkin gate (c) Peres
gate (d) Haghparast Navi gate

IV.

PROPOSED WORK

Booths algorithm [15] is mainly used for the multiplication

of signed binary numbers. Negative numbers are represented in
2s complement form. The signed value of a binary number X
is given by (1),

1) Design of shift register using reversible logic gates:

The shift register performs the arithmetic right shift
operation and is designed using PG gates as shown in Fig. 3.
The first input of PG gate is set to 0, to pass other two inputs
as it is to the output. The second output of each PG gate is the
output bit of shift register and the third output is fed as input to
the next PG gate.

n 2

Val(X) = - Xn-1 2n-1 + Xi 2i

(1)

i =0

2 J + 2 J -1 + 2 J -2 + ..... + 2 K = 2 J +1 - 2 K

(2)

The multiplication of the multiplier X and the multiplicand

Y is carried out as in (3),
n2

Y Val(X) = Y [-Xn-1 2n -1 + Xi 2i ]

Fig. 3. Design of shift register using Peres gate

(3)

i =0

A. Design of multiplier based on Booths recoding algorithm

using reversible logic
The architecture is designed for Radix-2 Booths recoding
multiplier as shown in Fig. 2. It consists of a shift register, 2:1
multiplexer, XOR gates and 4 bits adder. Initially the bits of the

The PG gate which has 2 XOR operations and 1 AND

operation is used alternate to FRG [16] gate which has 2 XOR
operations, 4 AND operations and 2 NOT operations, resulting
in reduced logical calculations. It is also observed that the QC
of PG gate is 4 compared to FRG gate [16] of 5, which helps
in reducing the overall QC of the proposed shift register to 29
compared to the existing design [16] of 36.

2014 IEEE International Conference on Computational Intelligence and Computing Research

2) Design of multiplexer and XOR gates using reversible

logic gates:
The 2:1 multiplexer is designed using FRG gates. The first
input is the select line of multiplexer. Depending on the value
of select line, either of the remaining two inputs of FRG gate
will be selected at the output. The second output of FRG gate
is the output of multiplexer. The 4 bits multiplexer needed for
the proposed work is designed by cascading 4 FRG gates as
shown in Fig. 4.

Fig. 6. Design of 4 bits full adder using HNG gate

The proposed reversible multiplier is analyzed in terms of

reversible design metrics i.e., gates count, CI, GO and QC of
the design are calculated. The hardware complexity is
measured by knowing the logical calculations [5, 12, 13]
involved in the design. Let = two-input XOR gate
calculation, = two-input AND gate calculation, = NOT
gate calculation and T = Total logical calculation.
Fig. 4. Design of 4 bits multiplexer using Fredkin gate

The Feynman gate (FG) is used for XOR operation. The 4

bits XOR gate designed using the cascade of 4 FG gates is as
shown in Fig. 5.

Fig. 5. Design of 4 bits XOR gate using Feynman gate

3) Design of adder using reversible logic gates:

The PG gate can be configured as half adder by setting the
third input to zero and the full adder was designed by
cascading 2 PG gates [17] which have 1 CI and 2 GO. The QC
of full adder comes out to be 8, since the QC of single PG gate
is 4. The 3 designs of full adder were proposed in [16], one
using PG gate, second design using MIG gate and in the third
design, one NFT (New Fault Tolerant) gate and 3 F2G
(Feynman Double Gate) gates were used. The IG gates [10,
11] were used for the design of half and full adders. Cascade
of 2 IG gates forms a full adder with 2 CI and 3 GO.
Multiplier circuits with adders designed using HNG gates
have less logical calculations, less QC, less number of CI and
GO compared to the adders designed with other reversible
gates [5, 12, 14].
In the proposed work, HNG [13, 18, 19] gates are used for
the design of full adder. A single HNG gate can be configured
as full adder when the last input is set to zero. There are four
outputs of which two are the adder outputs i.e., sum and Cout
and remaining two (G1, G2) are the GO. The 4 bits full adder
designed by cascading 4 HNG gates, is shown in Fig. 6. In our
design for adder, HNG gate which has the QC of 6 is used
compared with the adder using PG gate [16] which has QC of
8. This, results in the reduction of total QC of proposed 4 bits
full adder to 24 compared to the existing design [16] of 32.

The logical calculation of 1 PG gate which has 2

XOR operations and 1 AND operation is equal to
[2, 1].

The logical calculation of 1 FRG gate which has 2

XOR, 4 AND operations and 2 NOT operations is
equal to [2, 4, 2].

The logical calculation of 1 FG gate which has 1

XOR operation is equal to [1].

The logical calculation of 1 HNG gate which has

5 XOR operations and 2 AND operations is equal
to [5, 2].

The shift register is designed using 9 reversible gates

including 1 PG gate for appended zero while recoding the
multiplier bits. It has 2 CI and 1 GO with the QC of 33. The
logical calculation of this block is [17, 8]. The number of
FG gates used for copying and XOR operation is 10 with 5 CI
and 4 GO. The QC of these gates is 10 with the logical
calculation of [10]. The multiplexer consists of 4 FRG gates
with 5 GO. The QC of this block is 20 with the logical
calculation of [8, 16, 8]. The adder block consists of 4
HNG gates with 4 CI and 9 GO. The QC of this block is 24
with the logical calculation of [20, 8]. The design metrics of
individual blocks are added to get the total values as shown in
TABLE I. Therefore, the proposed reversible Booths
recoding multiplier is designed using 27 reversible logic gates
with 11 CI and 19 GO. The QC is 87 with the Total logical
calculation of 55 + 32 + 8.
TABLE I.

DESIGN METRICS OF PROPOSED REVERSIBLE BOOTHS

RECODING MULTIPLIER

Design metrics
Gate count

Values
9 + 10 + 4 + 4 = 27

Number of constant inputs

2 + 5 + 4 = 11

Number of garbage outputs

1 + 4 + 5 + 9 = 19

Quantum cost

33 + 10 + 20 + 24 = 87

Total logical calculation

55 + 32 + 8

2014 IEEE International Conference on Computational Intelligence and Computing Research

V.

[2]

RESULTS AND DISCUSSION

The proposed reversible multiplier is compared with the

existing reversible multipliers in the literature in terms of
reversible design metrics as shown in TABLE II. In Design 1
[17], 32 reversible gates are used which has the QC of 136 with
number of GO as 28. In Design 2 [17], 28 reversible gates are
used which has the QC of 144 with number of GO as 24. The
reversible multiplier based on Booths recoding [16] for nonfault tolerant operation is designed using 46 reversible gates
which have the QC of 155 with number of GO as 41. The
proposed design uses 27 reversible gates compared to 28 of
existing designs [12, 13, 17, 20] with GO of 19 compared to 22
of existing designs [16] and also the QC is less i.e., 87
compared to 114 of K-Algorithm [16]. Therefore the proposed
design is having less gates count, minimum number of CI and
GO compared to all the existing designs and also minimum QC
and less logical calculation compared to most of the existing
designs.
TABLE II.

COMPARISON OF PROPOSED REVERSIBLE BOOTHS

RECODING MULTIPLIER WITH OTHER DESIGNS

Multiplier designs

Gates count

Garbage
output

Quantum cost

Proposed

27

19

87

Kartikeya and
Bharat B-ReM [16]

46

41

155

Kartikeya and
Bharat K-Algorithm
[16]

31

22

114

Mariam and Keivan

Design1 [17]

32

28

136

Mariam and Keivan

Design2 [17]

28

24

144

Rakshith and
Saligram [18]

37

62

162

Saligram and
Rakshith [19]

33

43

164

Amrutha and Dayal

[20]

28

23

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

VI.

CONCLUSIONS

In this paper, we proposed an ultra area efficient reversible

quantum multiplier based on Radix-2 Booths recoding
algorithm. The proposed architecture was designed to improve
the factors of reversible design metrics. The gate count and
quantum cost were reduced to design the architecture suitable
for area efficiency. The proposed architecture was compared
with existing non-fault tolerant designs and was observed that
the design metrics obtained such as gates count, GO, QC and
logical calculations were better compared to existing
methodologies.
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