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RTL Synthesis: Choice-1: Target Expression-1 Choice-2: Target Expression-2 Choice-N: Target Expression-N

RTL synthesis transforms Verilog design descriptions at the register-transfer level into gate-level implementations. It can perform operations on single-bit and multi-bit signals, such as logical, bit-wise, shift, conditional, and concatenation operations, which synthesis tools can implement. Synthesis tools typically do not support real numeric values and operations due to their complexity. Synthesis tools can infer multiplexers from case statements if the choice values are distinct and include all possible select expression values, connecting the select inputs to the select expression output and each assignment expression to its choice value input. For if statements, each expression and condition implies combinational logic, with condition logic driving decision logic connected to expression outputs, potentially resulting in longer propagation

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Harshal Ambatkar
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40 views2 pages

RTL Synthesis: Choice-1: Target Expression-1 Choice-2: Target Expression-2 Choice-N: Target Expression-N

RTL synthesis transforms Verilog design descriptions at the register-transfer level into gate-level implementations. It can perform operations on single-bit and multi-bit signals, such as logical, bit-wise, shift, conditional, and concatenation operations, which synthesis tools can implement. Synthesis tools typically do not support real numeric values and operations due to their complexity. Synthesis tools can infer multiplexers from case statements if the choice values are distinct and include all possible select expression values, connecting the select inputs to the select expression output and each assignment expression to its choice value input. For if statements, each expression and condition implies combinational logic, with condition logic driving decision logic connected to expression outputs, potentially resulting in longer propagation

Uploaded by

Harshal Ambatkar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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RTL Synthesis

1. To transform Verilog design descriptions expressed at the register-transfer level of abstraction


into implementations at the gate level.
2. We can perform operations on single-bit nets and variables for single-bit signals and vector nets
and variables for multibit signals, such as logical operations (&&, || and !), bit-wise operations
(&, |, ~ etc.), shift operations (<<, >> etc.), the conditional operator (... ?... : ...), concatenation
({..., ...}), bit select and part select. These operations can be implemented by synthesis tools.
3. Synthesis tools typically do not support use of real numeric values and operations, since the
hardware required to implement them is much more complex than that for integer types
4. Consider conditional statements in the always block implementing same logic
Case i: case statement
always @*
case (select-expression)
choice-1: target = expression-1;
choice-2: target = expression-2;
...
choice-n: target = expression-n;
endcase
A synthesis tool could infer a multiplexer, provided the choice values were distinct and included all
possible values of the select expression. The select inputs of the multiplexer are connected to the output of
the combinational logic inferred from the select expression.
Each of the assignment expressions would be synthesized to combinational logic connected to the
particular data input of the multiplexer identified by the corresponding choice value. The choice values
are expressions, but they must not involve any inputs. Usually, they are just literal values.

Case i: if statement, containing nested assignments.


always @*
if (condition-1) target = expression-1;
else if (condition-1) target = expression-1;
...
else target = expression-n;
Each of the expressions and conditions implies combinational logic. The outputs of the expression logic
are connected to decision logic driven by the condition logic, such as that shown in Figure C.3. Since the
conditions are tested one by one until a true condition is found, the decision logic is priority based, with
conditions appearing earlier in the conditional assignment having priority over those appearing later. As a
consequence, the propagation delay for the inferred logic may be as long as the sum of propagation delays
of the inferred decision component. Of course, a synthesis tool may optimize the circuit, and may be able
to implement the assignment as a single multiplexer if the conditions are mutually exclusive.

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