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9 - Mux Decoder PLD - 2

This document discusses multiplexers, decoders, buffers, and programmable logic devices (PLDs). It begins by introducing multiplexers and describing their basic structure and applications. It then discusses buffers and tri-state buffers. decoders and encoders are covered next, along with examples of different types. The document concludes by covering programmable logic devices including PLDs, PALs, CPLDs, and FPGAs. Application examples are provided throughout to illustrate the concepts.

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Huan Luu Minh
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59 views36 pages

9 - Mux Decoder PLD - 2

This document discusses multiplexers, decoders, buffers, and programmable logic devices (PLDs). It begins by introducing multiplexers and describing their basic structure and applications. It then discusses buffers and tri-state buffers. decoders and encoders are covered next, along with examples of different types. The document concludes by covering programmable logic devices including PLDs, PALs, CPLDs, and FPGAs. Application examples are provided throughout to illustrate the concepts.

Uploaded by

Huan Luu Minh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 36

Ch 9.

Multiplexers, Decoders,
and PLDs
Youngsoo Shin
KAIST
Fall 2016

9.1 Introduction
Various logic gates (AND, OR, INV, NAND, ...)
are basic building blocks for designing
combinational logic
More complex building blocks
Multiplexer, Tri-state buffer, Decoder, Encoder,
PLDs

9.2 Multiplexer
Multiplexer (MUX, data selector)
Data inputs, control inputs, output

A = 0 Z = I0
A = 1 Z = I1

I0

I1

9.2 Multiplexer

4-to-1 MUX

8-to-1 MUX

2n-to-1 MUX

AB = 00 Z = I0
AB = 01 Z = I1
AB = 10 Z = I2
AB = 11 Z = I3

9.2 Multiplexer
Application of MUX: Quad MUX

A=0 x0x1x2x3, A=1 y0y1y2y3

9.2 Multiplexer
Application of MUX: 4-bit Binary Adder & Subtracter

9.3 Buffer
Buffer

9.3 Buffer
Tri-state buffer (Three-state buffer)
B=1 buffer (C = A)
B=0 Hi-Z (no connection)

9.3 Buffer
Example: 2-to-1 MUX

Example: two tri-state


buffers

9.3 Buffer
Example: 4-bit adder with four sources for one
operand

Example: Bi-directional I/O

10

9.4 Decoder and Encoder


3-to-8 Line Decoder
a b c

y0

y1

y2

y3

y4

y5

y6

y7

0
0
0
0
1
1
1
1

1
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

00
0 1
1 0
1 1
0 0
0 1
1 0
1 1

11

9.4 Decoder and Encoder


4-to-10 Line Decoder
BCD Input

Decimal Output

A B C D

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
12

9.4 Decoder and Encoder


Example: Realization of 2-level circuit using a
decoder
f1(a, b, c, d) = m1 + m2 + m4 = (m1m2m4)
f2(a, b, c, d) = m4 + m7 + m9 = (m4m7m9)

13

9.4 Decoder and Encoder


8-to-3 Priority Encoder
y0 y1 y2 y3 y4 y5 y6 y7 a

0
1
X
X
X
X
X
X
X

0
0
0
1
1
0
0
1
1

0
0
1
0
1
0
1
0
1

0
1
1
1
1
1
1
1
1

0
0
1
X
X
X
X
X
X

0
0
0
1
X
X
X
X
X

0
0
0
0
1
X
X
X
X

0
0
0
0
0
1
X
X
X

0
0
0
0
0
0
1
X
X

0
0
0
0
0
0
0
1
X

0
0
0
0
0
0
0
0
1

0
0
0
0
0
1
1
1
1

14

9.5 Read-Only Memory


Types of ROM
ROM
Mask-programmable ROM
PROM (Programmable ROM)
EPROM (Erasable PROM)
EEPROM (Electrically Erasable PROM)

15

9.5 Read-Only Memory


8-Word x 4-Bit ROM
A

F0

F1

F2

F3

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
0
0
1
0
1
0

0
0
1
1
1
0
1
1

1
1
1
0
0
0
1
0

0
0
1
1
0
1
1
1

data stored
in ROM
(23 words of
4-bits each)

16

9.5 Read-Only Memory


ROM with n-inputs & m-outputs
n input
Variables
00
00
00
00

11
11
11
11

m output
Variables
00
01
10
11

100
010
101
110

00
01
10
11

001
110
011
111

110
111
101
010

011
110
000
101

data stored
in ROM
(2n words of
m-bits each)

17

9.5 Read-Only Memory


Basic ROM structure

18

9.5 Read-Only Memory


ROM as a PLD

F0 = m(0,1, 4, 6) = A' B'+ AC '


F1 = m(2, 3, 4, 6, 7) = B + AC '
F2 = m(0,1, 2, 6) = A' B'+ BC '
F3 = m(2, 3, 5, 6, 7) = AC + B

19

9.5 Read-Only Memory


Example: Hexadecimal to ASCII code converter

Input
W

Hex
Digit

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

ASCII Code for Hex Digit


A6

A5

A4

A3

A2

A1

A0

0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1

0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0

16 words 5-bits

20

9.6 Programmable Logic Device


Programmable Logic Device (PLD)
Digital Integrated Circuit (IC), which can be
programmed to implement logic functions
Can realize 2~10 functions of 4~16 variables
PLA, PAL
CPLD
FPGA

21

9.6 Programmable Logic Device


Programmable Logic Array (PLA)
Introduced in 1975 by Signetics
Direct implementation of SOP
Mask-programmable, Field-programmable

m functions of n variables

22

9.6 Programmable Logic Device


Example: PLA with 3 inputs, 5 product terms, and 4 outputs

ROM

PLA

F0 = AB + AC
F1 = AC + B
F2 = AB + BC
F3 = B + AC
23

9.6 Programmable Logic Device


Example: PLA with 3 inputs, 5 product terms, and 4 outputs
F0 = AB + AC
F1 = AC + B
F2 = AB + BC
F3 = B + AC

Product
Term

Inputs

Outputs

F0

F1

F2

F3

AB
AC
B
BC
AC

0
1
1

0
1
1
-

0
0
1

1
1
0
0
0

0
1
1
0
0

1
0
0
1
0

0
0
1
0
1

24

9.6 Programmable Logic Device


Example: Implement following functions using PLA
f1 = abd + abd + abc + bc, f2 = c + abd, f3 = bc + abc + abd

25

9.6 Programmable Logic Device


Programmable Array Logic (PAL)
Programming is limited to AND plane: special case of PLA,
less expensive and easier to program
Introduced in 1978 by Monolithic Memories, Inc. (MMI)
AND array

OR array

- AND terms not shared among OR gates:


each function can be simplified independently
- # AND terms feeding OR gate is limited
I1I2
I1I2
26

9.6 Programmable Logic Device


Example: Implement a full adder using PAL
Sum = XYCin + XYCin + XYCin + XYCin, Cout = XCin + YCin + XY

27

9.7 CPLD
CPLD
Many PALs or PLAs on a single chip

Example: Xilinx XCR3064XL CPLD


28

9.7 CPLD
Example: CPLD function block and macrocell (Xilinx
XCR3064XL CPLD)

29

9.8 FPGA

A device that can be programmed by designers many times


Used for prototyping or for small-volume product
Generally worse than ASIC design
Identical logic cells + programmable interconnections

Configurable
Logic Block (CLB)

Switch
Box

I/O
30

9.8 FPGA
Configurable Logic Block (CLB)
Lookup Table (ROM)

0
0

0
0

0
0

0
1

0
1

LUT: 16 x 1-bit ROM

4-input, 1-output
function generator

31

9.8 FPGA
If CLB is a 4-input function generator, how can
functions of more than 4 inputs be implemented?
Shannons expansion theorem for
decomposition of switching functions
If y = f (x1,..., xn ) with xi being independent,

y = xi f xi + xi f xi
where

f xi = f (x1, x2 ,..., xi = 1,..., xn )


f xi = f (x1, x2 ,..., xi = 0,..., xn )

are the cofactors of f with respect to xi


32

9.8 FPGA
Example: Decompose f into two 3-input functions
f (a, b, c, d) = c'd '+ a'b'c + bcd + ac'

33

9.8 FPGA
Example: Implement f(a, b, c, d, e) in FPGA of 4-input
CLBs

34

9.8 FPGA
Example: Implement G(a, b, c, d, e, f) in FPGA of 4input CLBs

35

Summary
Macro building blocks
Multiplexer, Tri-state buffer, Decoder & Encoder
ROM

PLD: PLA, PAL


CPLD
FPGA

36

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