White Paper: Technical Contact
White Paper: Technical Contact
Technical Contact:
Rick Sturdivant, President
Microwave Packaging Technology, Inc.
Mobile: 310-980-3039
[email protected]
Business Contact:
Craig Parrish, VP Strategic Business Development
Microwave Packaging Technology, Inc.
310-696-9066
[email protected]
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Out
ADC
To Digital
Processing
tx
(10.1)
Where:
Fs = sample rate of the ADC (MSPS)
N = number of bits in the ADC
ADC = analog to digital converter
Control Bits = the data rate of the control bits that control the function of the ADC
Status Bits = the data rate of the status bits out of the ADC such as the over range bit
In most applications the data rate of Control Bits and Status Bits will be much lower than the
Data Rate at RXout and so we will neglect their contribution to the overall data bandwidth.
Consider an example where the ADC has 16 bits and a sample rate of 100 MSPS. In this case,
the Data Rate at RXout will be equal to 100 x 16 = 1.6GSPS per element in the array. This
means that for an 8 x 8 array, the total data rate out of the RXout ports will be 1.6 GSPS/element
x 64 elements = 102.4 GSPS. This illustrates one of the important design considerations for
digital beam forming which is the handling of the data. While it is true that some systems can
achieve performance with few bits in the ADC, and some systems do not need to sample at 100
MSPS, the trend in radar systems is more bits for increased resolution and higher sampling rate
for increased bandwidth.
Another concern about digital beam forming is the power consumption required by the
processing. While it is possible to procure ADCs with reasonable power dissipation, the FPGA
and other processors require significant power. The FPGA and processors perform the important
function of combining the signals from multiple elements, processing of the signals, and data
packaging for transport to the next level in the system (additional processing and signal
analysis). Because of the limitation in data bandwidth, there is a practical limit on the number of
elements (channels) in the array that a FPGA can handle. For instance, if a FPGA is used to
capture data from four elements in an array with 16 bit ADCs running at 100MSPS, then the data
rate out of the FPGA will be 1.6GSPS x 4 = 6.4GSPS. While the FPGA may be able to handing
pumping out that data rate, the digital interface to the next level becomes a concern even if high
speed interfaces are used.