Basic Electronics - Flip-Flops
Basic Electronics - Flip-Flops
Flip-Flops
Syllabus: Flip-Flops: Introduction to Flip-Flops, NAND Gate Latch/ NOR Gate Latch, RS Flip-Flop,
Gated Flip-Flops: Clocked RS Flip-Flop. (5 Hours)
Introduction to Flip-Flops
Digital circuits are classified into two types – Combinational circuits and Sequential
circuits. Combinational circuits are the circuits in which the output depends on the present
inputs only. Sequential circuits are the circuits in which the output depends on the present
input as well as the previous state of the system. The sequential circuits have memory. A flip-
flop is the basic element of all sequential systems.
Flip-Flop
A flip-flop is an electronic circuit which has memory. It is a bistable digital circuit, i.e.,
its outputs have two stable states: logic 1 and logic 0. It is the basic element of all sequential
systems.
Latches Flip-Flops
Latches are controlled by an enable signal Flip-flops are controlled by a clock signal
Latches are positive or negative level- Flip-flops are positive or negative edge-
triggered, i.e., the output changes whenever triggered, i.e., the output changes whenever
the enable is 1 (for positive level-triggered) the clock changes from 0 to 1 (for positive
or 0 (for negative level-triggered) edge-triggered) or 1 to 0 (for negative edge-
triggered)
Latches are building blocks of sequential Flip-flops are also building blocks of
circuits and are built from basic gates sequential circuits and are built from latches
A latch continuously checks its inputs and A flip-flop continuously checks its inputs
changes its output whenever the enable is and changes its output only at times
HIGH determined by the clock signal
The operation of a latch is faster as they do Flip-flops are comparatively slower as they
not have to wait for clock signal have to wait for clock signal
Operation
The inputs are 𝑅̅ and 𝑆̅. Hence there are four conditions:
i. ̅=̅
If 𝑹 𝑺=𝟏
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 2 are (0,1). So its output is 𝑄̅ = 1.
(The output does not change).
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (1,0).
So its output is 𝑄 = 1. The inputs to the gate 2 are (1,1). So its output is 𝑄̅ = 0.
(The output does not change).
That is, if 𝑅̅ = 𝑆̅ = 1, there is no change in the output.
ii. If 𝑹 ̅=𝟎
̅ = 𝟏, 𝑺
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (0,1).
So its output is 𝑄 = 1. The inputs to the gate 2 are (1,1). So its output is 𝑄̅ = 0.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 2 are (1,1). So its output is 𝑄̅ = 0.
That is, if 𝑅̅ = 1, 𝑆̅ = 0, the output is set (𝑄 = 1).
iii. If 𝑹 ̅=𝟏
̅ = 𝟎, 𝑺
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 2 are (0,0). So its output is 𝑄̅ = 1.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 2 are (1,0).
So its output is 𝑄̅ = 1. The inputs to the gate 1 are (1,1). So its output is 𝑄 = 0.
That is, if 𝑅̅ = 0, 𝑆̅ = 1, the output is reset (𝑄 = 0).
iv. If 𝑹 ̅=𝟎
̅=𝑺
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (0,1).
So its output is 𝑄 = 1. The inputs to the gate 2 are (1,0). So its output is 𝑄̅ = 1.
Here 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 2 are (1,0). So its output is 𝑄̅ = 1.
Again 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
That is, if 𝑅̅ = 𝑆̅ = 0, the output is not valid. Hence this is forbidden.
Considering all the four cases, the truth table is written as below.
Truth Table:
̅
𝑹 ̅
𝑺 𝑸𝒏 𝑸𝒏+𝟏 State ̅
𝑹 ̅
𝑺 𝑸𝒏+𝟏 State
1 1 0 0 1 1 𝑄𝑛 No change
No change
1 1 1 1
1 0 1 Set
1 0 0 1
Set 0 1 0 Reset
1 0 1 1
Forbidden
0 1 0 0 0 0 ?
Reset (Illegal)
0 1 1 0
0 0 0 ? Forbidden
𝑄𝑛 - Present state output
0 0 1 ? (Illegal)
𝑄𝑛+1 - Next state output
Operation
The inputs are 𝑅 and 𝑆. Hence there are four conditions:
i. If 𝑹 = 𝑺 = 𝟎
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (0,1).
So its output is 𝑄 = 0. The inputs to the gate 2 are (0,0). So its output is 𝑄̅ = 1.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 2 are (1,0). So its output is 𝑄̅ = 0.
That is, if 𝑅 = 𝑆 = 0, there is no change in the output.
ii. If 𝑹 = 𝟎, 𝑺 = 𝟏
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 2 are (0,1).
So its output is 𝑄̅ = 0. The inputs to the gate 1 are (0,0). So its output is 𝑄 = 1.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 2 are (1,1). So its output is 𝑄̅ = 0.
That is, if 𝑅 = 0, 𝑆 = 1, the output is set (𝑄 = 1).
iii. If 𝑹 = 𝟏, 𝑺 = 𝟎
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 2 are (0,0). So its output is 𝑄̅ = 1.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (1,0).
So its output is 𝑄 = 0. The inputs to the gate 2 are (0,0). So its output is 𝑄̅ = 1.
That is, if 𝑅 = 1, 𝑆 = 0, the output is reset (𝑄 = 0).
iv. If 𝑹 = 𝑺 = 𝟏
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 2 are (0,1). So its output is 𝑄̅ = 0.
Here 𝑄 = 0 and 𝑄̅ = 0, which is not possible. So the output is not valid.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (1,0).
So its output is 𝑄 = 0. The inputs to the gate 2 are (0,1). So its output is 𝑄̅ = 0.
Again 𝑄 = 0 and 𝑄̅ = 0, which is not possible. So the output is not valid.
That is, if 𝑅 = 𝑆 = 1, the output is not valid. Hence this is forbidden.
4 Shrishail Bhat, Dept. of ECE, AITM Bhatkal
Basic Electronics Flip-Flops
Considering all the four cases, the truth table is written as below.
Truth Table:
0 0 0 0 0 0 𝑄𝑛 No change
No change
0 0 1 1
0 1 1 Set
0 1 0 1
Set 1 0 0 Reset
0 1 1 1
Forbidden
1 0 0 0 1 1 ?
Reset (Illegal)
1 0 1 0
RS Flip-Flop
In RS flip-flop, the inputs are 𝑅 and 𝑆. We want to achieve 𝑄 = 0 (Reset) when 𝑅 = 1
and 𝑄 = 1 (Set) when 𝑆 = 1. Fig. 4 shows the logic diagram and symbol of an RS flip-flop
(latch).
Operation
The inputs are 𝑅 and 𝑆. NAND gates 1 and 2 act as inverters and produce 𝑆̅ and 𝑅̅
respectively which are the inputs to gates 3 and 4. The gates 3 and 4 form a NAND gate latch.
The operation can be analyzed for the four conditions:
i. If 𝑹 = 𝑺 = 𝟎
If 𝑅 = 𝑆 = 0, then 𝑅̅ = 𝑆̅ = 1.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 4 are (0,1). So its output is 𝑄̅ = 1.
(The output does not change).
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (1,0).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
(The output does not change).
That is, if 𝑅 = 𝑆 = 0, there is no change in the output.
ii. If 𝑹 = 𝟎, 𝑺 = 𝟏
If 𝑅 = 0, 𝑆 = 1, then 𝑅̅ = 1, 𝑆̅ = 0.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (0,1).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
That is, if 𝑅 = 0, 𝑆 = 1, the output is set (𝑄 = 1).
iii. If 𝑹 = 𝟏, 𝑺 = 𝟎
If 𝑅 = 1, 𝑆 = 0, then 𝑅̅ = 0, 𝑆̅ = 1.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 4 are (0,0). So its output is 𝑄̅ = 1.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 4 are (1,0).
So its output is 𝑄̅ = 1. The inputs to the gate 3 are (1,1). So its output is 𝑄 = 0.
That is, if 𝑅 = 1, 𝑆 = 0, the output is reset (𝑄 = 0).
iv. If 𝑹 = 𝑺 = 𝟏
If 𝑅 = 𝑆 = 1, then 𝑅̅ = 𝑆̅ = 0.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (0,1).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,0). So its output is 𝑄̅ = 1.
Here 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,0). So its output is 𝑄̅ = 1.
Again 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
That is, if 𝑅 = 𝑆 = 1, the output is not valid. Hence this is forbidden.
Considering all the four cases, the truth table is written as below.
Truth Table:
0 0 0 0 0 0 𝑄𝑛 No change
No change
0 0 1 1
0 1 1 Set
0 1 0 1
Set 1 0 0 Reset
0 1 1 1
Forbidden
1 0 0 0 1 1 ?
Reset (Illegal)
1 0 1 0
Gated Flip-Flops
An RS flip-flop (or latch) is said to be transparent, that is, any change in 𝑅 or 𝑆 is
immediately transmitted to the outputs 𝑄 and 𝑄̅ . If an enable or clock signal is connected to
the NAND gates 1 and 2, we get Gated Flip-Flops.
Clocked RS Flip-Flops
In a clocked RS flip-flop, a clock (CLK) signal is fed to the NAND gates 1 and 2 as
shown in Fig. 5.
Operation
The inputs are 𝑅 and 𝑆. The gates 3 and 4 form a NAND gate latch.
When the clock is HIGH, the outputs of gates 1 and 2 are 𝑆̅ and 𝑅̅ respectively. So the
latch operates normally.
When the clock is LOW, the output of the gates 1 and 2 are (1,1), which implies that
the output does not change and the latch is said to be disabled.
The operation can be analyzed for the following conditions:
i. If 𝑪𝑳𝑲 = 𝟏 and 𝑹 = 𝑺 = 𝟎
In this case, the outputs of gates 1 and 2 are (1,1) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 4 are (0,1). So its output is 𝑄̅ = 1.
(The output does not change).
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (1,0).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
(The output does not change).
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 𝑆 = 0, there is no change in the output.
ii. If 𝑪𝑳𝑲 = 𝟏 𝐚𝐧𝐝 𝑹 = 𝟎, 𝑺 = 𝟏
In this case, the outputs of gates 1 and 2 are (0,1) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (0,1).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 0, 𝑆 = 1, the output is set (𝑄 = 1).
iii. If 𝑪𝑳𝑲 = 𝟏 𝐚𝐧𝐝 𝑹 = 𝟏, 𝑺 = 𝟎
In this case, the outputs of gates 1 and 2 are (1,0) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (1,1).
So its output is 𝑄 = 0. The inputs to the gate 4 are (0,0). So its output is 𝑄̅ = 1.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 4 are (1,0).
So its output is 𝑄̅ = 1. The inputs to the gate 3 are (1,1). So its output is 𝑄 = 0.
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 1, 𝑆 = 0, the output is reset (𝑄 = 0).
iv. If 𝑪𝑳𝑲 = 𝟏 𝐚𝐧𝐝 𝑹 = 𝑺 = 𝟏
In this case, the outputs of gates 1 and 2 are (0,0) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (0,1).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,0). So its output is 𝑄̅ = 1.
Here 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (0,0).
So its output is 𝑄 = 1. The inputs to the gate 4 are (1,0). So its output is 𝑄̅ = 1.
Again 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 𝑆 = 1, the output is not valid. Hence this is forbidden.
v. If 𝑪𝑳𝑲 = 𝟎
In this case, the output of the gates 1 and 2 are (1,1), which implies that the
output does not change and the latch is said to be disabled.
Considering all the cases, the truth table is written as below.
Truth Table:
1 0 0 0 0 1 0 0 𝑄𝑛 No change
No change
1 0 0 1 1
1 0 1 1 Set
1 0 1 0 1
Set 1 1 0 0 Reset
1 0 1 1 1
Forbidden
1 1 0 0 0 1 1 1 ?
Reset (Illegal)
1 1 0 1 0
0 X X 𝑄𝑛 No change
1 1 1 0 ? Forbidden
1 1 1 1 ? (Illegal)
𝑄𝑛 - Present state output
0 X X 0 0
No change 𝑄𝑛+1 - Next state output
0 X X 1 1
X – Don’t care
(May be 0 or 1)
Fig. 6 Input and output waveforms for positive and negative edge-triggered RS flip-flops
Table 2 shows the traditional logic symbols and their IEEE counterparts. All IEEE logic
symbols are rectangular and there is an identifying character or symbol inside.
Questions
1. What is a flip-flop? Distinguish between a latch and a flip-flop.
(Dec ’17 – 4M, Jun ’17 – 4M, Dec ’16 – 2M, Jun ‘16, Dec ‘15, Jun ‘15 – 4M, MQP ‘14 –
4M)
2. What is a latch? (Dec ‘17)
3. With a logic diagram and truth table, explain the operation of NAND gate latch.
(Dec ’17 – 10M, Jun ’17 – 8M, Jun ‘16 – 5M)
4. With a logic diagram and truth table, explain the operation of NOR gate latch.
(Dec ’17, Dec ‘16 – 5M, Jun ‘16 – 8M, Dec ‘15 – 6M, MQP ‘14 – 6M)
5. What is RS flip-flop? Explain its operation with circuit diagram, logic symbol and
truth table.
(Dec ’17 – 6M, Jun ’17 – 8M, Jun ‘16 – 5M, Dec ‘15 – 5M, Jun ‘15 – 6M, MQP ‘15 – 6M)
6. With a logic diagram and truth table, explain the operation of a clocked (or gated) RS
flip-flop using NAND gates.
(Dec ’17 – 8M, Jun ’17 – 8M, Dec ’16 – 8M, Jun ‘16 – 5M, Dec ‘15 – 8M, Dec ‘14 – 6M,
MQP ‘15 - 4M, MQP ‘14 – 5M)
7. Draw the traditional and IEEE logic symbols of AND, OR, NOT, NAND, NOR, XOR
and XNOR. (MQP ‘15 – 4M)
References
1. D.P. Kothari, I. J. Nagrath, “Basic Electronics”, McGraw Hill Education (India) Private
Limited, 2014.
2. John M. Yarbrough, “Digital Logic Applications and Design”, Thomson Learning,
2001.
3. Donald D. Givone, “Digital Principles and Design”, McGraw Hill, 2002.