Practices For Improving The PCB
Practices For Improving The PCB
Practices For Improving The PCB
Cheryl Tulkoff
DfR Solutions
ctulkoff@dfrsolutions.com
512-913-8624
SMTAI 2013]
design
Foundation
Management
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Design
Manufacturing
Purchasing
Quality/Reliability
Time in business
Revenue
Growth
Employee Turnover
Training Program
Certified to the standards you require (IPC, MIL-SPEC,
ISO, etc.)
Capable of producing the technology you need as part of
their mainstream capabilities
Dont exist in PCB process niches where suppliers claim
capability but have less than ~ 15% of their volume built
there
Have quality and problem solving methodologies in place
Have a technology roadmap
Have a continuous improvement program in place
Sample
PCB Relationship
Management
Monthly calls with PCB commodity team and each PCB supplier
Twice per year, QBRs should be joint onsite meetings which alternate
between your site and the supplier factory site.
Factory supplier site QBR visit can double as the annual on site visit and audit
that you perform.
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On Time Delivery
PPM Defect Rates
Communication speed, accuracy, channels, responsiveness to
quotes
Quality Excursions / Root Cause Corrective Action Process
Resolution
Supplier Corrective Action Requests
Discuss recalls, notifications, or scrap events exceeding a
certain dollar amount
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solder float,
etc.)
Review IPC-9151B, Printed Board Process
Capability, Quality, and Relative Reliability (PCQR2)
Benchmark Test Standard and Database at:
http://www.ipc.org/html/IPC-9151B.pdf
PCB suppliers may be part of this activity already.
Ask if they participate and if you can get a copy of their results.
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PCB Prototype
Development
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In
Knowledge is key!
Processes are
complex, chemistry
intensive and there
are a lot of steps
More than
180
individual steps
required
to manufacture typical
printed circuit boards
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Audit Focus
Process
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Communicate Requirements
Define the standards needed
Communicate both quality & reliability
objectives!
Help
Both laminates are identical in all properties EXCEPT one laminate has
a CTEz of 40 and the other has a CTEz of 60.
The vias in the laminate with the lower CTEz will be MORE reliable in a
long term, aggressive thermal cycling environment than the CTEz 60
laminate.
A CTEz 40 laminate built to IPC class 2 could be MORE reliable than
the CTEz 60 laminate built to Class 3.
Appropriate materials selection for the environment is key!
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High Volume
Required
Cost Sensitive
Product
Cosmetics of
Finish is
Important
Pb-Free Wave
Solder
(PCB > 62mil)
SF
Type
Fine Pitch
Components
Used
Pb-Free
Shock/Drop is a
Concern
Corrosion Failure
is Possible
Wire bonding to
Finish is Required
Is Important
to Product
Is not required
for the Product
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Cross Sections
In
Inspections
Visual
Inspections
Automatic Optical
Inspection (AOI)
X-Ray
Inspection
Drilling Performance
Layer alignment
Cleanliness
Measurements
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The ROSE test method is used as a process control tool to detect the
presence of bulk ionics. The IPC upper limit is set at 10.0 mg/NaCl/in2.
This test is performed using a Zero-Ion or similar style ionic testing unit
that detects total ionic contamination, but does not identify specific ions
present. This process draws the ions present on the PCB into the
solvent solution. The results are reported as bulk ions present on the
PCB per square inch.
The modified ROSE test method involves a thermal extraction. The PCB
is exposed in a solvent solution at an elevated temperature for a
specified time period. This process draws the ions present on the PCB
into the solvent solution. The solution is tested using an Ionograph-style
test unit. The results are reported as bulk ions present on the PCB per
square inch.
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Knowledge
can be used by an
organization to monitor supplier
performance over time
Insufficient Plating, Voids, Nodules,
Folds, Etch Pits, Fiber Protrusion
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Plating Folds
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Plating Nodules
Plating Voids
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Electrical Test
IPC-D-356
netlist is
uploaded into the
tester.
Each PCB is manually
placed on fixture and
tested for continuity
and resistance
Final Inspection
Visually
inspect 100%
of the finished product
Review of:
Fabrication drawing
requirements
Dimensional properties
Board size
Finished hole sizes
Customer specification
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Vacuum Sealer
Conclusions
Speaker Biography
Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech.
She is a published author, experienced public speaker and trainer and a Senior
member of both ASQ and IEEE. She has held leadership positions in the IEEE
Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR
(Accelerated Stress Testing and Reliability) sections. She chaired the annual IEEE
ASTR workshop for four years, is an ASQ Certified Reliability Engineer and a member
of SMTA and iMAPS.
She has a strong passion for pre-college STEM (Science, Technology, Engineering,
and Math) outreach and volunteers with several organizations that specialize in
encouraging pre-college students to pursue careers in these fields.
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Thank You!
Questions?
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