M8051EW Debugger

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TRACE32 Documents ......................................................................................................................

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

M8051EW ..................................................................................................................................

M8051EW Debugger .............................................................................................................

General Note ......................................................................................................................

Brief Overview of Documents for New Users .................................................................

Warning ..............................................................................................................................

Quick Start .........................................................................................................................

Troubleshooting ................................................................................................................

SYStem.Up Errors

KEIL OMF-51 and OMF2

Breakpoints

10

M8051EW Breakpoint Types

10

Why does the M8051EW not stop at my Breakpoint?

11

Why do my On-chip Breakpoints not work as expected?

12

Debugging with Low Target Frequencies

12

Mapping Memory

13

FAQ .....................................................................................................................................

13

Configuration .....................................................................................................................

14

General SYStem Settings and Restrictions ....................................................................

15

SYStem.state
SYStem.CONFIG

Open SYStem.state window

Configure debugger according to target topology

15
16

Daisy-chain Example

18

TapStates

19

SYStem.CONFIG.CORE
SYStem.CPU

Select CPU

21
21

Define JTAG clock

22

Lock and tristate the debug port

22

Select memory access mode

23

Establish communication with the target

23

SYStem.JtagClock
SYStem.LOCK
SYStem.MemAccess

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M8051EW Debugger

20

Select CPU access mode

SYStem.CpuAccess

SYStem.Mode

Assign core to TRACE32 instance

SYStem.Option IMASKASM

Disable interrupts while single stepping

SYStem.Option IMASKHLL

25

Disable interrupts while HLL single stepping

25

Core is part of Intel SoC

25

SYStem.Option PATCHBP

Use patch unit for on-chip breakpoints

26

SYStem.Option PRDELAY

Set delay time after RESET

26

Request break after reset

27

Enable TRAP_EN flag in EOR

27

SYStem.Option IntelSOC

SYStem.Option ResBreak
SYStem.Option TRAPEN
Memory Classes

28

SYMbol Commands ...........................................................................................................

Special Function Register (SFR) symbols

29
29

PUBSFR section in KEIL OMF-251

29

M8051EW SFR Symbol Definition with PRACTICE

30

TrOnchip Commands ........................................................................................................

TrOnchip.view
TrOnchip.CONVert

31

Display on-chip trigger window

31

Adjust range breakpoint in on-chip resource

31

TrOnchip.RESet

Set on-chip trigger to default state

31

Adjust complex breakpoint in on-chip resource

32

JTAG Connectors ..............................................................................................................

33

TrOnchip.VarCONVert

Target Board Connectors

33

FS2 TAP Connector

33

16pin Connector

35

LAUTERBACH Adapters

37

LA-7848 M8051EW 14-pin Adapter (MIPS EJTAG compatible)

37

LA-7849 M8051EW 16-pin Adapter

37

ARM 20-pin Adapter

38

Support ...............................................................................................................................

39

Available Tools

39

Compilers

39

Realtime Operation Systems

39

3rd Party Tool Integrations

40

Products .............................................................................................................................

41

Product Information

41

Order Information

41

1989-2016 Lauterbach GmbH

M8051EW Debugger

M8051EW Debugger
Version 24-May-2016

1989-2016 Lauterbach GmbH

M8051EW Debugger

General Note
This documentation describes the processor specific settings and features for TRACE32-ICD for the
Mentor Graphics M 8051Enterprise Warp (M8051EW) CPU family.
This CPU core is one of several 8051 compatible IP designs available from Mentor Graphics. The unique
property of the M8051EW compared to the other members of the family is its JTAG On-Chip Instrumentation
(OCI) support.

Brief Overview of Documents for New Users

Architecture-independent information:

Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.

T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.

General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.

Architecture-specific information:

Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-

Choose Help menu > Processor Architecture Manual.

RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.

1989-2016 Lauterbach GmbH

M8051EW Debugger

General Note

Warning

NOTE:

To prevent debugger and target from damage it is recommended to connect or

disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1.

Disconnect the debug cable from the target while the target power is
off.

2.

Connect the host system, the TRACE32 hardware and the debug
cable.

3.

Power ON the TRACE32 hardware.

4.

Start the TRACE32 software to load the debugger firmware.

5.

Connect the debug cable to the target.

6.

Switch the target power ON.

7.

Configure your debugger e.g. via a start-up script.

Power down:
1.

Switch off the target power.

2.

Disconnect the debug cable from the target.

3.

Close the TRACE32 software.

4.

Power OFF the TRACE32 hardware.

1989-2016 Lauterbach GmbH

M8051EW Debugger

Warning

Quick Start
Starting up the debugger is done as follows:
Select the device prompt for the ICD Debugger and reset the system.
b::

The device prompt B:: is normally already selected in the command line. If this is not the case enter B:: to
set the correct device prompt. The RESet command is only necessary if you do not start directly after
booting the TRACE32 development tool.
5.

Specify the CPU specific settings.

SYStem.CPU <cputype>

The default values of all other options are set to values that should allow to start work without
modification. Please consider that these values are possibly not the best configuration for your target.
6.

Set up the JTAG electrical interface clock speed.

SYStem.JtagClock <frequency>

The default frequency is 10 MHz. If your JTAG connection does not support the RESET signal,
please press your target board reset button before the next command to ensure a HARD RESET.
7.

Enter debug mode.

SYStem.Up

This command resets the CPU and enters debug mode. After this command is executed it is possible
to access memory and registers.
8.

Load your application program.

Data.LOAD.Omf2 myprogram /verify

; OMF2 specifies the format,

; myprogram is the file name

The format of the Data.LOAD command depends on the file format generated by the compiler.
Please refer to Supported Compilers to find the command, that is necessary for your compiler. It is
recommended to use the option /verify that verifies all written data. This test spots any problems with
the electrical connection, wrong chip configurations or linker command file settings.
A detailed description of the Data.LOAD command and all available options is given in the
General Commands Reference.

1989-2016 Lauterbach GmbH

M8051EW Debugger

Quick Start

The start up can be automated using the programming language PRACTICE. A typical start sequence for
M8051EW-based CPUs is shown below:
b::

; Select the ICD device prompt

WinCLEAR

; Clear all windows

SYStem.CPU SDA80D51

; Select CPU

SYStem.Up

; Reset the target and enter debug mode

Data.LOAD.OMF APP.ABS /Verify

; Load the application, verify the

; process

Go main

; Run and break at main()

PER.view

;
;
;
;

Data.List

; Open source code window *)

Register /SpotLight

; Open register window *)

Var.Local

; Open window with local variables *)

Frame.view /Locals /Caller

; Open the stack frame with

; local variables *)

Var.Watch flags ast

; Open watch window for the variables

; flags and ast *)

Open a window to display and

manipulate special function registers
of peripherals and SoC function
blocks. *)

*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.

1989-2016 Lauterbach GmbH

M8051EW Debugger

Quick Start

Troubleshooting

SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.

The JTAG lines are not connected correctly.

The target has no power.

The pull-up resistor between the JTAG[VTREF] pin and the target VCC is too large.

The target is in reset:

The debugger controls the processor reset and use the RESET line to reset the CPU on every
SYStem.Up. Additionally it executes an M8051EW soft reset. If you have no RESET line
connected, please make sure you manually hard-reset the target board before continuing.

There is logic added to the JTAG state machine:

The debugger is configured at start-up to expect only one M8051EW core in the JTAG chain.
Please use the SYStem.CONFIG command (CONFIG button) to configure the JTAG chain
position of the core in a multi-core configuration.

There are additional loads or capacities on the JTAG lines

The core you want to debug has to be started first by another core, or target board has additional
RESET delay logic. Please use SYStem.Option PRDELAY.

You have additional logic on your board that requires special handling of JTAG lines during or at
the end of system RESET. Please make sure the JTAG port is enabled correctly.

1989-2016 Lauterbach GmbH

M8051EW Debugger

Troubleshooting

KEIL OMF-51 and OMF2

For M8051EW debugging, the KEIL compiler currently supports only the Intel MCS-51 Object
Module Format (OMF-51/OMF-251). KEIL extended this format to store some additional
information within the OMF file, e.g. to support banking.

The KEIL linkers can generate OMF (OMF-51) and OMF2 (OMF-251) format, depending on your
project settings. Please select the appropriate TRACE32 command for loading OMF or OMF2.
Load your OMF-51 application program with:
Data.LOAD.Omf myprogram /verify

; OMF specifies the format,

; myprogram is the file name

Load your OMF2 application program with:

Data.LOAD.Omf2 myprogram /verify

; OMF2 specifies the format,

; myprogram is the file name

A detailed description of the Data.LOAD command and all available options is given in the
General Commands Reference Guide D (general_ref_d.pdf).

OMF-51 specifies source files by name only, and does not include directories.
If your project is split into several subdirectories, and your HLL source code is not found, please
either provide a list of source directories using the Data.LOAD /PATH option, or by using the
sYmbol.SourcePATH.SetRecurseDir command.

1989-2016 Lauterbach GmbH

M8051EW Debugger

Troubleshooting

Breakpoints
M8051EW Breakpoint Types

For a description of the general breakpoint types and commands, please see Break.Set.

To combine on-chip breakpoint actions, please set additional on-chip breakpoints of the
appropriate type and the same address/range/data values.
TRACE32/PowerView will combine as many breakpoints as possible.

If you combine an on-chip/stop/program breakpoint with an on-chip breakpoint with the actions
Delta, Echo, TraceOn or TraceOff, it will be overridden. If you require an additional
CodeExecution breakpoint, please add another Charly breakpoint.

If your patch unit can only be used to patch code in ROM, E2PROM or FLASH, for code in RAM
please use on-chip/Delta or SOFT breakpoints.
Implem.

Action

Type

Function

SOFT

stop

Program

Replaces program code in memory (RAM or FLASH)

with an 0A5h instruction (TRAP).
Please make sure that TRAP_EN is set, otherwise
your program will not stop.

Onchip

stop

Program

CodeExecution breakpoint, works similar to SOFT

breakpoints, by stuffing an 0A5h opcode into the
processor instruction pipeline.
If a patch unit is available, more breakpoints of this
type can be set (see SYStem.Option PATCHBP).
Please make sure that TRAP_EN is set, otherwise
your program will not stop.

Onchip

Charly

default

Sets an explicit on-chip CodeExecution breakpoint

when you combine other on-chip breakpoints.
(Onchip combination disables any on-chip/stop/
program Breakpoint for the same address/range).
Please make sure that TRAP_EN is set, otherwise
your program will not stop.

Onchip

Delta

default

DebugAssert action, works by setting an internal processor signal. The signal is sampled at the start of the
next instruction.
Can be combined with other on-chip breakpoint
types.

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M8051EW Debugger

10

Troubleshooting

Onchip

Echo

default

TrigOut action, sets an internal processor signal that a

chip designer can route to an external chip pad or use
for SoC internal triggering.
Can be combined with other on-chip breakpoint
types.

Onchip

TraceON

Program

TraceOn action, starts use of the internal M8051EW

on-chip trace unit (if configured).
Can be combined with other on-chip breakpoint types
except TraceOFF.

Onchip

TraceOFF

Program

TraceOff action, stops use of the internal M8051EW

on-chip trace unit (if configured).
Can be combined with other on-chip breakpoint types
except TraceON.

Why does the M8051EW not stop at my Breakpoint?

The M8051EW extends the 8051 instruction set with the special command
MOVC @(DPTR++),A
to write data (e.g. from a I2C LPC memory IC) into program RAM. As the 8051 instruction set is
only 8 bit wide, and there were no unused opcodes available, the M8051EW designers re-used
the TRAP opcode 0A5h for this instruction.

The functionality of the 0A5h opcode is determined by the bit TRAP_EN in the Extended
Operations (EO) register (usually EO.4):.
TRAP_EN=1 (set)

0A5h means TRAP

TRAP_EN=0 (reset)

0A5h means MOVC @(DPTR++),A

After a RESET, the bit TRAP_EN=0 (reset), therefore any encountered opcode 0A5h will be
interpreted as MOVC command.

This conflicts with the operation of software breakpoints and on-chip code execution (stop)
breakpoints.
Software breakpoints are set by replacing an instruction with a TRAP instruction. When the
processor stops in debug mode, the original instruction is restored. The next STEP or GO
command then executes the instruction.
Similarly, OnChip stop breakpoints work by stuffing a TRAP instruction into the program flow the program memory content is not altered, but the processor sees an 0A5h opcode.

Therefore a breakpoint may be illegally interpreted as an MOVC operation if you:

-

disable the TRAP_EN check box (at next RESET, TRAC32 will not try to set TRAP_EN),

manually reset the TRAP_EN bit (EO.4) in your program code. (NOTE: This can also be done
by your compiler as a side effect if it uses multiple DPTRs.), or

issue a manual or watchdog time (WDT) RESET to the M8051EW.

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M8051EW Debugger

11

Troubleshooting

Why do my On-chip Breakpoints not work as expected?

M8051EW supports a number of Triggers. These are used as on-chip breakpoints.

Depending on your core configuration, none, one, two or four triggers are available.
If two or four triggers are available, ranges can be defined.
Triggers can be defined to activate at a certain address/bank and data value.
Triggers can issue a code execution breakpoint, assert an internal DebugReq signal, assert an
external TrigOut signal (if defined in your core design), and can start or stop a trace.

Code execution breakpoint triggers (standard on-chip stop breakpoints) work by instruction
stuffing an 0A5h opcode into the processor pipeline. To use them, it must be ensured that the
TRAP_EN flag in the M8051EW EOR register is set.
If a Patch Unit is available and usable for Breakpoints (SYStem.Option PATCHBP is set), then
additional Code execution breakpoints can be used. For these, code bytes are replaced
(patched) with the M8051EW TRAP instruction 0A5h. If you execute program code from RAM,
please note that your patch unit may be restricted to patch (X)ROM and FLASH memory only - in
this case for the RAM area you can and should use SOFT breakpoints.

Assert DebugReq triggers set an internal processor debug request signal (DebugReq) within
the on-chip instrumentation (OCI) logic. They are set using Delta on-chip breakpoints.
The DebugReq signal is sampled at the beginning of the next processor instruction, and the
processor goes into DEBUG state after this instruction finishes.
When you set an on-chip breakpoint, the processor will stop after the instruction where you set
the breakpoint.
When you set an Assert DebugReq breakpoint directly after an instruction that alters the
program flow, e.g. a RET opcode, the internal address counter may still trigger the breakpoint.
Then the DebugReq signal is asserted, and the processor stops after the execution of the RET
opcode - at a completely different address from your original breakpoint!

Debugging with Low Target Frequencies

When designing and testing your new chip with the M8051EW core, you might use an emulator that
supports only a fraction of normal JTAG and processor frequencies. In this case:

You can reduce the update rate of the TRACE32-PowerView GUI with
SETUP.URATE <rate per second | time>

You can cache program and data areas with

MAP.UpdateOnce P:0--0FFFFF
Please remember to access your data with the correct memory type specifiers (D:, I:, P:, X:), do
not use C:. The cache is invalidated with each STEP or GO command.

Please restrict data windows to the minimum required address ranges.

E.g. instead of d d:0 and d i:0, use d d:80--0FF and d i:00--0FF.

Minimizing windows you dont currently need also reduces the amount of data that has to be
transferred between host and target.

1989-2016 Lauterbach GmbH

M8051EW Debugger

12

Troubleshooting

Mapping Memory

Processor designs with Harvard architecture, such as the M8051EW, have separate program
and data memory buses.

For various purposes it may be useful or necessary to map data space to program space and
vice versa. Often during development a read-writable data memory area is mirrored into a readonly program memory area, or e.g. program flash is mapped to a read-only data area.

An unlimited number of software breakpoints can only be set within read-writable memory. For
read-only memory only a very limited number of hardware on-chip breakpoints can be used.

If you have a read-writable data area that is mapped into read-only program space, you can
redirect the debugger breakpoint setting from program memory to data memory with the
TRANSlation command.
TRANSlation.Create <logical_range> [<physical_range>] [/<option>]

TRANSlation.Create P:0100--0FFFF X:4100

TRANSlation.ON

To automatically set on-chip breakpoints in read-only program memory areas, you can use
MAP.BOnchip <addressrange>

MAP.BOnchip P:0--0FF

NOTE:

Formerly, the MMU command group was used for address translation inside the
debugger. With the wide-spread adoption of hardware MMUs, it was necessary
to rename this command group to TRANSlation to avoid confusion with
hardware MMUs.

FAQ
No information available

1989-2016 Lauterbach GmbH

M8051EW Debugger

13

FAQ

Configuration

PC

Target
Debug Cable
PODBUS IN

USB
Cable

POWER DEBUG INTERFACE / USB2

JTAG
Connector

LAUTERBACH
POWER
TRIG

DEBUG CABLE

DEBUG CABLE

USB

POWER
7-9 V

LAUTERBACH

SELECT
EMULATE

PODBUS OUT

POWER DEBUG INTERFACE / USB 2

AC/DC Adapter

HUB

PC or
Workstation

100 MBit Ethernet

Target
Debug Cable
TRIG

LAUTERBACH

RECEIVE
COLLISION

PODBUS OUT

DEBUG CABLE

ETHERNET

CON ERR

POWER
7-9 V

LAUTERBACH

TRIGGER

TRANSMIT

DEBUG CABLE

EMULATE
RECORDING

RESERVED FOR POWER TRACE

SELECT
USB

Ethernet
Cable

POWER DEBUG / ETHERNET

JTAG
Connector

PODBUS IN

POWER

POWER DEBUG / ETHERNET

AC/DC Adapter

The processor type must be selected by the SYStem.CPU command before issuing any other target related
commands.
1989-2016 Lauterbach GmbH

M8051EW Debugger

14

Configuration

General SYStem Settings and Restrictions

SYStem.state

Format:

Open SYStem.state window

SYStem.state

Opens a window with settings of CPU specific system commands. Settings can also be changed here.

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M8051EW Debugger

15

General SYStem Settings and Restrictions

SYStem.CONFIG

Configure debugger according to target topology

Format:

SYStem.CONFIG <parameter> <number_or_address>

SYStem.MultiCore <parameter> <number_or_address> (deprecated)

<parameter>
(General):

state
CORE

(JTAG):

DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave
[ON | OFF]

<core>

The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
TriState has to be used if several debuggers (via separate cables) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs needs to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).

1989-2016 Lauterbach GmbH

M8051EW Debugger

16

General SYStem Settings and Restrictions

state

Show multicore settings.

CORE

For multicore debugging one TRACE32 GUI has to be started per core.
To bundle several cores in one processor as required by the system this
command has to be used to define core and processor coordinates within
the system topology.
Further information can be found in SYStem.CONFIG.CORE.

DRPRE

(default: 0) <number> of TAPs in the JTAG chain between the core of

interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.

DRPOST

(default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.

IRPRE

(default: 0) <number> of instruction register bits in the JTAG chain

between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.

IRPOST

(default: 0) <number> of instruction register bits in the JTAG chain

between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.

TAPState

(default: 7 = Select-DR-Scan) This is the state of the TAP controller when

the debugger switches to tristate mode. All states of the JTAG TAP
controller are selectable.

TCKLevel

(default: 0) Level of TCK signal when all debuggers are tristated.

TriState

(default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.

Slave

(default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the master - is allowed to control the signals
nTRST and nSRST (nRESET).

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M8051EW Debugger

17

General SYStem Settings and Restrictions

Daisy-chain Example

TDI

Core A

Core B

Core C

Chip 0

Core D

TDO

Chip 1

Below, configuration for core C.

Instruction register length of

Core A: 3 bit

Core B: 5 bit

Core D: 6 bit
SYStem.CONFIG.IRPRE 6

; IR Core D

SYStem.CONFIG.IRPOST 8

; IR Core A + B

SYStem.CONFIG.DRPRE 1

; DR Core D

SYStem.CONFIG.DRPOST 2

; DR Core A + B

SYStem.CONFIG.CORE 0. 1.

; Target Core C is Core 0 in Chip 1

1989-2016 Lauterbach GmbH

M8051EW Debugger

18

General SYStem Settings and Restrictions

TapStates
0

Exit2-DR

Exit1-DR

Shift-DR

Pause-DR

Select-IR-Scan

Update-DR

Capture-DR

Select-DR-Scan

Exit2-IR

Exit1-IR

10

Shift-IR

11

Pause-IR

12

Run-Test/Idle

13

Update-IR

14

Capture-IR

15

Test-Logic-Reset

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M8051EW Debugger

19

General SYStem Settings and Restrictions

SYStem.CONFIG.CORE

Assign core to TRACE32 instance

Format:

SYStem.CONFIG.CORE <coreindex> <chipindex>

SYStem.MultiCore.CORE <coreindex> <chipindex> (deprecated)

<chipindex>:

1i

<coreindex>:

1k

Default coreindex: depends on the CPU, usually 1. for generic chips

Default chipindex: derived from CORE= parameter of the configuration file (config.t32). The CORE
parameter is defined according to the start order of the GUI in T32Start with ascending values.
To provide proper interaction between different parts of the debugger the systems topology must be mapped
to the debuggers topology model. The debugger model abstracts chips and sub-cores of these chips. Every
GUI must be connect to one unused core entry in the debugger topology model. Once the SYStem.CPU is
selected a generic chip or none generic chip is created at the default chipindex.
None Generic Chips
None generic chips have a fixed amount of sub-cores with a fixed CPU type.
First all cores have successive chip numbers at their GUIs. Therefore you have to assign the coreindex and
the chipindex for every core. Usually the debugger does not need further information to access cores in
none generic chips, once the setup is correct.
Generic Chips
Generic chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information
how to connect to the individual cores e.g. by setting the JTAG chain coordinates.
Start-up Process
The debug system must not have an invalid state where a GUI is connected to a wrong core type of a none
generic chip, two GUI are connected to the same coordinate or a GUI is not connected to a core. The initial
state of the system is value since every new GUI uses a new chipindex according to its CORE= parameter
of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must
be merged by calling SYStem.CONFIG.CORE.

1989-2016 Lauterbach GmbH

M8051EW Debugger

20

General SYStem Settings and Restrictions

SYStem.CPU

Select CPU

Format:

SYStem.CPU <cpu>

<cpu>:

M8051EW, SDA80D51, PMB8710, PMB8720, PMB8725, PMB9604

VCT6TV, VCT7TV, VCT8TV, VCT9TV

Selects the processor type. The available types depend on your adapter type and license.

SYStem.CpuAccess

Select CPU access mode

Format:

SYStem.CpuAccess <mode>

<mode>:

Enable
Denied
Nonstop

Default: Denied.
The option controls whether the debugger may (briefly) interrupt program execution in order to access
system memory for updating memory display windows or setting breakpoints etc.
Enable

In order to perform a memory read or write while the CPU is executing

the program the debugger stops the program execution shortly.
Each short stop takes 1 100 ms depending on the speed of the debug
interface and on the size of the read/write accesses required.

Denied

No intrusive memory read or write is possible while the CPU is executing

the program.

Nonstop

Nonstop ensures that the program execution cannot be stopped and that
the debugger doesnt affect the real-time behavior of the CPU.

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M8051EW Debugger

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General SYStem Settings and Restrictions

SYStem.JtagClock

Define JTAG clock

Format:

SYStem.JtagClock [<frequency>]
SYStem.BdmClock [<frequency>] (deprecated)

<frequency>

1.0MHz | 5.0MHz | 10.0MHz | <other>=6 kHz 80 MHz

Selects the JTAG port frequency (TCK) used by the debugger to communicate with the processor. This
influences e.g. the download speed. It may be required to reduce the JTAG frequency if there are buffers,
additional loads or high capacities on the JTAG lines or if VTREF is very low. A very high frequency will not
work on all systems and will result in an erroneous data transfer.
<frequency>:

(default is 10 MHz)

The debugger cannot select all frequencies accurately. It chooses the next possible frequency and displays
the real value in the System Settings window.
Instead of decimal numbers like 100000., abbreviated forms like 10kHz or 15MHz may be used. This
short form implies a decimal value, although no . is used.
When the debugger is not working correctly (e.g. memory display flickers), decrease the JtagClock.

NOTE:

A deprecated form of this command (SYStem.BdmClock) is also accepted.

SYStem.LOCK

Format:

Lock and tristate the debug port

SYStem.LOCK [ON | OFF]

Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the lock command is to give debug
access to another tool.

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M8051EW Debugger

22

General SYStem Settings and Restrictions

SYStem.MemAccess

Select memory access mode

Format:

SYStem.MemAccess <mode>
SYStem.ACCESS <mode> (deprecated)

<mode>:

Denied

CPU

The mode CPU cannot be selected, because there is no way to do runtime

access to the memory while the M8051EW core is running.

Denied

The mode CPU cannot be selected, because there is no way to do runtime

access to the memory while the M8051EW core is running.

SYStem.Mode

Establish communication with the target

Format:

SYStem.Mode <mode>

<mode>:

Down
NoDebug
Go
Attach
Up

Down

The CPU is held in reset (if the RESET signal is attached), debug mode
is not active. Default state and state after fatal errors.

NoDebug

Disables the debugger. The state of the CPU remains unchanged. The
JTAG port is tri-stated.

Go

Resets the target and enables the debugger and start the program
execution. Program execution can be stopped by the break command or
if any break condition occurs.

Attach

User program remains running (no reset) and the debug mode is
activated. After this command the user program can be stopped with the
break command or if any break condition occurs.

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M8051EW Debugger

23

General SYStem Settings and Restrictions

Up

Resets the target, sets the CPU to debug mode and stops the CPU. After
the execution of this command the CPU is stopped and all registers are
set to the default level.

StandBy

Not supported.

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M8051EW Debugger

24

General SYStem Settings and Restrictions

SYStem.Option IMASKASM

Format:

Disable interrupts while single stepping

SYStem.Option IMASKASM [ON | OFF]

Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.

SYStem.Option IMASKHLL

Format:

Disable interrupts while HLL single stepping

SYStem.Option IMASKHLL [ON | OFF]

Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored.

SYStem.Option IntelSOC

Format:

Core is part of Intel SoC

SYStem.Option IntelSOC [ON | OFF]

Default: OFF.
Inform the debugger that the M8051EW core is part of an Intel SoC. When enabled, all IR and DR pre/post
settings are handled automatically, no manuel configuration is necessary.
Requires that the M8051EW debugger is slave in a multicore setup with x86 as the master debugger and
that SYStem.Option.CLTAPOnly is enabled in the x86 debugger.

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M8051EW Debugger

25

General SYStem Settings and Restrictions

SYStem.Option PATCHBP

Format:

Use patch unit for on-chip breakpoints

SYStem.Option PATCHBP [ON | OFF]

Default: OFF.
If enabled, additionally to the M8051EW on-chip trigger unit, an available patch unit is used for code
execution breakpoints. The instruction at the breakpoint address is replaced (patched) by an opcode 0A5h make sure the TRAP_EN flag is set to have the CPU stop at this address, either by setting TRAP_EN in your
code or by using SYStem.Option TRAPEN.

NOTE:

This option is only enabled for platforms that provide a patch unit. If enough free onchip triggers are available, these are used instead of the patch unit, even when this
option is set.

SYStem.Option PRDELAY

Set delay time after RESET

Format:

SYStem.Option PRDELAY [<time in ms>]

<time>

0 60000ms

Set a wait time after releasing the RESET signal before JTAG communication with the target is continued.
Useful for target boards with an on-board reset delay unit, or if another core has to enable the target core
before JTAG communication is possible.
<time>:

(default is 0us)

Instead of decimal numbers like 1000., abbreviated forms like 1s or 500ms may be used.This command
always implies a decimal value, although no . is used. Fractional values can be entered (e.g. 1000.250)
but the fractional part is ignored.

NOTE:

Use this option for VCT9** AutoJTAG if you have a debug cable (e.g. LA-7848) that
does not have a line to sample RESETo (system reset out).

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M8051EW Debugger

26

General SYStem Settings and Restrictions

SYStem.Option ResBreak

Format:

Request break after reset

SYStem.Option ResBreak [ON | OFF]

When you issue the SYStem.Option ResBreak ON command, the debugger instructs the SoC to issue an
M8051EW DebugReq (debug request) signal at the next target reset.

NOTE:

Currently only available for I8051 core.

Works only for SoCs with special M8051EW-Break-after-Reset logic.

SYStem.Option TRAPEN

Format:

Enable TRAP_EN flag in EOR

SYStem.Option TRAPEN [ON | OFF]

Default: ON.
When the SYStem.Option TRAPEN check box is checked, the debugger sets the TRAP_EN flag in the
Extended Operation (EO) register before executing the next STEP or GO command.

NOTE:

When you disable this option, the TRAP_EN flag is not actively reset.

1989-2016 Lauterbach GmbH

M8051EW Debugger

27

General SYStem Settings and Restrictions

Memory Classes
The following memory classes are available:
Memory Class

Description

Program

External data (XRAM)

Internal RAM (Indirect Address)

Special Function Registers + Internal RAM (Direct Address)

The low 128 bytes of the internal data memory are mirrored in the memory classes I and D.
The upper 128 bytes in the memory class D represent the Special Function Registers SFR
(standard, non-banked).
If the peripheral configuration of your chip supports SFR banking, then the banked SFR contents are visible
in the address range beyond 0x80--0xFF.
E.g. the SFR Bank 5 would be visible in the upper 128 bytes of D:0500--05FF.

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M8051EW Debugger

28

General SYStem Settings and Restrictions

SYMbol Commands

Special Function Register (SFR) symbols

Special Function Registers (SFRs) for all 8051 derivatives are located within the memory range D:80--FF
and accessed via MOV direct memory opcodes.
All SFRs with an address where bits 0..2 are not set (e.g. D:80, D:88, D:90, D:98, etc.) are bit-adressable
like the memory in the range D:20--2F.
One problem for disassembly is to distinguish normal addresses and constants in the range 0x80..0xFF
from SFR and SFR bit definitions. Some registers (A, B, PSW) are available on all 8051 derivatives. For
these, default names and addresses (that can be overwritten by an external definition) are hard-coded into
the disassembler. But the majority of platforms will have different peripherals located on different addresses.

PUBSFR section in KEIL OMF-251

KEILs OMF-251 (OMF2) format contains a special PUBSFR section for SFR and SBIT definitions.
Here is an example for a KEIL definition for the PSW and its bit flags:
sfr PSW
= 0xD0; // Program Status Word
sbit P
= 0xD0; // Parity Flag
sbit F1
= 0xD1; // General Purpose Flag
sbit OV
= 0xD2; // Overflow Flag
sbit RS0
= 0xD3; // Register Bank Select
sbit RS1
= 0xD4; // Register Bank Select
sbit F0
= 0xD5; // General Purpose Flag
sbit AC
= 0xD6; // Auxiliary Carry Flag
sbit CY
= 0xD7; // Carry Flag

1
0
1
0

When such a definition is included in a C or ASM source file and the output format is set to OMF2, the
compiler/linker emits this definition in the ABS file. After symbol load the special function register is available
in the dis/assembler.
Pure symbol definitions (and no code) can be loaded from an OMF-251 file with:
Data.LOAD.Omf2 my_symbols.om2 /NOCODE

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M8051EW Debugger

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SYMbol Commands

M8051EW SFR Symbol Definition with PRACTICE

For M8051EW cores, SFR symbols can be created in PRACTICE with the D: and B: addressing modes.
D:00xx addresses (xx=0x80--0xFF) are SFR byte definitions, B:0yyy bit addresses are computed by
multiplying the SFR base address with 8 and then adding the bit offset.
Example: for the PSW at address 0xD0, the PSW_3 bit address (RS0) is (0xD0 * 8) + 3 = 0x683.
This is the PRACTICE definition for the M8051EW PSW:
sYmbol.CREATE.RESet
sYmbol.CREATE
sYmbol.NEW PSW
D:00D0
sYmbol.NEW P
B:0680
sYmbol.NEW F1
B:0681
sYmbol.NEW OV
B:0682
sYmbol.NEW RS0
B:0683
sYmbol.NEW RS1
B:0684
sYmbol.NEW F0
B:0685
sYmbol.NEW AC
B:0686
sYmbol.NEW CY
B:0687
sYmbol.CREATE.Done

NOTE:

;
;
;
;
;
;
;
;
;
;
;
;

erase all user-defined symbols

start symbol creation
Program Status Word
Parity Flag
(0xD0 * 8 + 0)
General Purpose Flag 1
(0xD0 * 8 + 1)
Overflow Flag
(0xD0 * 8 + 2)
Register Bank Select 0
(0xD0 * 8 + 3)
Register Bank Select 1
(0xD0 * 8 + 4)
General Purpose Flag 0
(0xD0 * 8 + 5)
Auxiliary Carry Flag
(0xD0 * 8 + 6)
Carry Flag
(0xD0 * 8 + 7)
finish symbol creation

If the SYStem.CPU selection is not set to an M8051EW derivative, all D:xxxx

definitions will be mapped to I:xxxx definitions. These do not represent SFR
addresses.

1989-2016 Lauterbach GmbH

M8051EW Debugger

30

SYMbol Commands

TrOnchip Commands

TrOnchip.view

Format:

Display on-chip trigger window

TrOnchip.view

Open TrOnchip window.

TrOnchip.CONVert

Format:

Adjust range breakpoint in on-chip resource

TrOnchip.CONVert [ON | OFF]

The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the
breakpoint it will automatically be converted into a single address breakpoint when this option is active. This
is the default. Otherwise an error message is generated.
TrOnchip.CONVert ON
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write

; sets breakpoint at range

; 1000--17ff sets single breakpoint
; at address 1001

TrOnchip.CONVert OFF
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write

; sets breakpoint at range

; 1000--17ff
; gives an error message

TrOnchip.RESet

Format:

Set on-chip trigger to default state

TrOnchip.RESet

Sets the TrOnchip settings and trigger module to the default settings.

1989-2016 Lauterbach GmbH

M8051EW Debugger

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TrOnchip Commands

TrOnchip.VarCONVert

Format:

Adjust complex breakpoint in on-chip resource

TrOnchip.VarCONVert [ON | OFF]

The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a
complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole
structure. If the option TrOnchip.VarCONVert is on the breakpoint will automatically be converted into a
single address breakpoint. This is the default setting. Otherwise an error message is generated.

1989-2016 Lauterbach GmbH

M8051EW Debugger

32

TrOnchip Commands

JTAG Connectors

Target Board Connectors

To allow easy interfacing from the LAUTERBACH Adapters to the Target Boards, here is a list of the most
common Target Board Connectors.

FS2 TAP Connector

Signal
TCK
TDO
TMS
N/C
TDI

Pin
1
3
5
7
9

Pin
2
4
6
8
10

Signal
GND
VTREF
N/C
RSTGND

The FS2 connector on the target is usually a standard 2 x 5 pin header

(pin to pin spacing: 0.1 inch = 2.54 mm).

Do not connect the N/C pins.

Connect all GND pins for shielding purposes.

Connect VTREF via a low-value resistor to the processor power supply voltage. It is used to
detect if target power is on and to supply the output buffers of the debugger.
Therefore the output voltage of the debugger signals (TMS, TDI, TCLK) depends directly on
VTREF. VTREF can be 2.25 5.5 V. The output buffer takes about 2 mA.

RST- is controlled by an open drain driver.

An external watchdog must be switched off if the In-Circuit Debugger is used.

For the input pin TDO VIHmin = 2.0 V, VILmax = 0.8 V.

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M8051EW Debugger

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JTAG Connectors

Pins

Connection

Description

Recommendations

TCLK

Test clock

None.

2, 10

GND

System Ground
Plane

Connect to digital ground.

TDO

Test Data Out

If there are multiple devices on the JTAG

chain, connect TDO to the TDI signal of the
next device in the chain.

VTREF

VCC reference

Connect to Chip I/O voltage VCC.

TMS

Test Mode Select

None.

6, 7

NC

Not Connected

None.

RST-

Reset Target CPU

Connect to debugger RESET- line. Do not

connect to TRST-.

TDI

Test Data In

None.

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M8051EW Debugger

34

JTAG Connectors

16pin Connector
Signal
TMS
TDO
RESETO
TDI
N/C
TCK
N/C
N/C

Pin
1
3
5
7
9
11
13
15

Pin
2
4
6
8
10
12
14
16

Signal
VTREF
GND
GND
DBRESET
N/C
GND
N/C
N/C

The 16pin connector on the target is usually a standard 2 x 8 pin header

(pin to pin spacing: 0.1 inch = 2.54 mm). The signal layout is HITEXTM compatible.

Do not connect the N/C pins.

Connect all GND pins for shielding purposes.

Connect VTREF via a low-value resistor to the processor power supply voltage. It is used to
detect if target power is on and to supply the output buffers of the debugger.
Therefore the output voltage of the debugger signals (TMS, TDI, TCLK) depends directly on
VTREF. VTREF can be 2.25 5.5 V. The output buffer takes about 2 mA.

An external watchdog must be switched off if the In-Circuit Debugger is used.

For the input pins TDO and RESETo VIHmin = 2.0 V, VILmax = 0.8 V.

If there are multiple devices on the JTAG chain, connect TDO to the TDI signal of the next device
in the chain. The device with the lowest possible JTAG clock speed determines the maximum
overall JTAG clock frequency for chained set-ups.

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M8051EW Debugger

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JTAG Connectors

Pins

Connection

Description

Recommendations

TMS

Test Mode Select

None.

VTREF

VCC reference

Connect to Chip I/O voltage VCC.

TDO

Test Data Out

None.

GND

Digital Ground

Connect to System Ground Plane.

RESETo

Reset out (Target)

HIGH level until end of System Reset.

GND

Digital Ground

Connect to System Ground Plane.

TDI

Test Data In

None.

DBRESET

Debug Reset

HIGH during reset request from debugger.

9, 10

NC

Not Connected

None.

11

TCLK

Test clock

None.

12

GND

Digital Ground

Connect to System Ground Plane.

13, 14,
15, 16

NC

Not Connected

None.

1989-2016 Lauterbach GmbH

M8051EW Debugger

36

JTAG Connectors

LAUTERBACH Adapters
These are the pin assignments for the LAUTERBACH M8051EW and (for reference only) ARM adapters.

LA-7848 M8051EW 14-pin Adapter (MIPS EJTAG compatible)

Signal
TRSTTDI
TDO
TMS
TCK
RSTDINT

Pin
1
3
5
7
9
11
13

Pin
2
4
6
8
10
14

Signal
GND
GND
GND
GND
GND
Key
VIO (Reference Voltage)

The signal DINT is not used for M8051EW debugging.

For the interfacing to your target board, please see Target Board Connectors.

LA-7849 M8051EW 16-pin Adapter

Signal
TMS
TDO
RESETO
TDI
N/C
TCK
N/C
N/C

Pin
1
3
5
7
9
11
13
15

Pin
2
4
6
8
10
12
14
16

Signal
VTREF
GND
GND
DBRESET
N/C
GND
N/C
N/C

For the interfacing to your target board, please see Target Board Connectors.

1989-2016 Lauterbach GmbH

M8051EW Debugger

37

JTAG Connectors

ARM 20-pin Adapter

Signal
VREF-DEBUG
TRSTTDI
TMS|TMSC|SWDIO
TCK|TCKC|SWCLK
RTCK
TDO
RESETDBGRQ
DBGACK

Pin
1
3
5
7
9
11
13
15
17
19

Pin
2
4
6
8
10
12
14
16
18
20

Signal
VSUPPLY (not used)
GND
GND
GND
GND
GND
GND
GND
GND
GND

For the interfacing to your target board, please see Target Board Connectors.

1989-2016 Lauterbach GmbH

M8051EW Debugger

38

JTAG Connectors

Support

M8051EW
VCT6xxxP
VCT7xxxP
VCT8xxxP
VCT9xxxP

YES
YES
YES
YES
YES

YES

INSTRUCTION
SIMULATOR

POWER
INTEGRATOR

ICD
TRACE

ICD
MONITOR

ICD
DEBUG

FIRE

ICE

CPU

Available Tools

YES

Compilers
Language

Compiler

Company

Option

Comment

ASM

A8051

SYM

with converter

ASM

A8051

Ashling Microsystems
Ltd.
IAR Systems AB

UBROF

Source level
debugging

C
C
C
C

C51
CC
ICC8051
CC51

ARM Germany GmbH

Generic
IAR Systems AB
TASKING

EOMF-51
COFF
UBROF
IEEE

Banking support
Banking support

Realtime Operation Systems

Not supported yet.

1989-2016 Lauterbach GmbH

M8051EW Debugger

39

Support

3rd Party Tool Integrations

CPU

Tool

Company

ALL
ALL
ALL

ADENEO
X-TOOLS / X32
CODEWRIGHT

ALL

CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER

Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL

ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW

CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER

Host
Windows
Windows
Windows

Code Confidence Ltd

Linux

EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation

Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows

NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software

Windows

Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows

Vector Software

Windows

Windows

Windows

1989-2016 Lauterbach GmbH

M8051EW Debugger

40

Support

Products

Product Information
OrderNo Code

Text

LA-7848

JTAG Debugger for M8051EW 14 Pins (ICD)

JTAG-M8051EW-14

supports M8051EW core

includes software for Windows, Linux and MacOSX
requires Power Debug Module
debug cable with 14 pin connector

LA-7848A

JTAG Debugger for M8051EW Add.

JTAG-M8051EW-A

supports M8051EW core

please add the base serial number of your debug
cable to your order

LA-7849

JTAG Debugger for M8051EW 16 Pins (ICD)

JTAG-M8051EW-16

supports M8051EW core

includes software for Windows, Linux and MacOSX
requires Power Debug Module
debug cable with 16 pin connector (HITEX compatible)

Order Information

Order No.

Code

Text

LA-7848
LA-7848A
LA-7849

JTAG-M8051EW-14
JTAG-M8051EW-A
JTAG-M8051EW-16

JTAG Debugger for M8051EW 14 Pins (ICD)

JTAG Debugger for M8051EW Add.
JTAG Debugger for M8051EW 16 Pins (ICD)

Additional Options
LA-7760A EJTAG-MIPS32-A

EJTAG Debugger License for MIPS32 Add.

1989-2016 Lauterbach GmbH

M8051EW Debugger

41

Products