Digital Number System

A digital system can understand positional number system only where there are a few symbols called digits and these symbols
represent different values depending on the position they occupy in the number.
A value of each digit in a number can be determined using

The digit

The position of the digit in the number

The base of the number system (where base is defined as the total number of digits available in the number
system).

Decimal Number System

The number system that we use in our day-to-day life is the decimal number system. Decimal number system has base 10 as it
uses 10 digits from 0 to 9. In decimal number system, the successive positions to the left of the decimal point represents units,
tens, hundreds, thousands and so on.
Number System
Binary Number System
Octal Number System
Hexa Decimal Number System

Description
Base 2. Digits used: 0, 1
Base 8. Digits used: 0 to 7
Base 16. Digits used: 0 to 9, Letters used: A- F
Conversion

Decimal to Other Base System

Steps

Step 1 Divide the decimal number to be converted by the value of the new base.

Step 2 Get the remainder from Step 1 as the rightmost digit (least significant digit) of new base number.

Step 3 Divide the quotient of the previous divide by the new base.

Step 4 Record the remainder from Step 3 as the next digit (to the left) of the new base number.

Repeat Steps 3 and 4, getting remainders from right to left, until the quotient becomes zero in Step 3. The last
remainder thus obtained will be the Most Significant Digit (MSD) of the new base number.

Example

Step
Step 1
Step 2
Step 3
Step 4
Step 5

Decimal Number: 2910

Calculating Binary Equivalent

Operation
29 / 2
14 / 2
7/2
3/2
1/2

Result
14
7
3
1
0

Remainder
1
0
1
1
1

Decimal Number 2910 = Binary Number 111012.

As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so that the first remainder
becomes the Least Significant Digit (LSD) and the last remainder becomes the Most Significant Digit (MSD).
Other Base System to Decimal System
Steps

Step 1 Determine the column (positional) value of each digit (this depends on the position of the digit and
the base of the number system).

Step 2 Multiply the obtained column values (in Step 1) by the digits in the corresponding columns.

Step 3 Sum the products calculated in Step 2. The total is the equivalent value in decimal.

Example

Binary
Decimal Number
Number
Step 1 111012
((1 24) + (1 23) + (1 22) + (0 21) + (1 20))10
Step 2 111012
(16 + 8 + 4 + 0 + 1)10
Step 3 111012
2910
Step

Binary Number 111012

Calculating Decimal Equivalent

Binary Number 111012

Decimal Number 2910

Other Base System to Non-Decimal System

Steps

Step 1 Convert the original number to a decimal number (base 10).

Step 2 Convert the decimal number so obtained to the new base number.

Example
Octal Number 258
Calculating Binary Equivalent

Step 1 Convert to Decimal

Step 2 Convert Decimal to Binary

Step Octal Number Decimal Number

Step 1 258
((2 81) + (5 80))10
Step 2 258
(16 + 5 )10
Step 3 258
2110

Step
Operation
Result
Remainder
Step 1 21 / 2
10
1
Step 2 10 / 2
5
0
Step 3 5 / 2
2
1
Step 4 2 / 2
1
0
Step 5 1 / 2
0
1
Decimal Number 2110 = Binary Number 101012
Octal Number 258 = Binary Number 101012

Octal Number 258 = Decimal Number 2110

Binary Codes
In the coding, when numbers, letters or words are represented by a specific group of symbols, it is said that the
number, letter or word is being encoded. The group of symbols is called as a code. The digital data is represented,
stored and transmitted as group of binary bits. This group is also called as binary code. The binary code is
represented by the number as well as alphanumeric letter.
Advantages of Binary Code
Following is the list of advantages that binary code offers.

Binary codes are suitable for the computer applications.

Binary codes are suitable for the digital communications.

Binary codes make the analysis and designing of digital circuits if we use the binary codes.

Since only 0 & 1 are being used, implementation becomes easy.

Classification of binary codes

The codes are broadly categorized into following four categories.

Weighted Codes
Non-Weighted Codes

Weighted Codes

Non-Weighted Codes
In this type of binary codes, the positional weights are not assigned. The examples of non-weighted codes are
Excess-3 code and Gray code.
Excess-3 code
The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal numbers. The
Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or (3)10 to each code word in
8421. The excess-3 codes are obtained as follows

Example

Gray Code
It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the
bit position. It has a very special feature that, only one bit will change each time the decimal number is incremented

as shown in fig. As only one bit changes at a time, the gray code is called as a unit distance code. The gray code is a
cyclic code. Gray code cannot be used for arithmetic operation.
Application of Gray code

Gray code is popularly used in the shaft

position encoders.

A shaft position encoder produces a code

word which represents the angular position of
the shaft.

Binary Coded Decimal (BCD) code

In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express each of the decimal
digits with a binary code. In the BCD, with four bits we can represent sixteen numbers (0000 to 1111). But in BCD
code only first ten of these are used (0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are
invalid in BCD.

Advantages of BCD Codes

It is very similar to decimal system.

We need to remember binary equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes

The addition and subtraction of BCD have different rules.

The BCD arithmetic is little more complicated.

BCD needs more number of bits than binary to represent the decimal number. So BCD is less efficient than
binary.

De Morgan's Theorems
De Morgan has suggested two theorems which are
extremely useful in Boolean Algebra. The two
theorems are discussed below.
Theorem 1

The left hand side (LHS) of this theorem

represents a NAND gate with inputs A and B,
whereas the right hand side (RHS) of the
theorem represents an OR gate with inverted
inputs.

This OR gate is called as Bubbled OR.

Table showing verification of the De Morgan's first theorem

Theorem 2

The LHS of this theorem represents a NOR gate

with inputs A and B, whereas the RHS represents
an AND gate with inverted inputs.

This AND gate is called as Bubbled AND.

Table showing verification of the De Morgan's second
theorem

SOP AND POS

The minterms and maxterms may be used to define the two standard forms for logic expressions, namely the sum of
products (SOP), or sum of minterms, and the product of sums (POS), or product of maxterms. Boolean functions
expressed as a sum of products or a product of sums are said to be in canonical form.
Resistortransistor logic
Resistortransistor logic (RTL) is a class of digital circuits built using resistors as the input network and bipolar
junction transistors (BJTs) as switching devices. RTL is the earliest class of transistorized digital logic circuit used.
One-transistor RTL NOR gate
With two or more base resistors (R3 and R4) instead of one, the inverter becomes a two-input RTL NOR gate (see
the figure on the right). The logical operation OR is performed by applying consecutively the two arithmetic
operations addition and comparison (the input resistor network acts as a parallel voltage summer with equally
weighted inputs and the following common-emitter transistor stage as a voltage comparator with a threshold about
0.7 V). The equivalent resistance of all the resistors connected to logical "1" and the equivalent resistance of all the
resistors connected to logical "0" form the two legs of a composed voltage divider driving the transistor. The base
resistances and the number of the inputs are chosen (limited) so that only one logical "1" is sufficient to create
base-emitter voltage exceeding the threshold and, as a result, saturating the transistor. If all the input voltages are
low (logical "0"), the transistor is cut-off. The pull-down resistor R1 biases the transistor to the appropriate on-off
threshold. The output is inverted since the collector-emitter voltage of transistor Q1 is taken as output, and is high
when the inputs are low. Thus, the analog resistive network and the analog transistor stage perform the logic
function NOR.

Fig- Schematic of a one-transistor RTL NOR gate.

Advantages
The primary advantage of RTL technology was that it used a minimum number of transistors. In circuits using
discrete components, before integrated circuits, transistors were the most expensive component to produce. Early
IC logic production used the same approach briefly, but quickly transitioned to higher-performance circuits such
as diodetransistor logic and then transistortransistor logic, since diodes and transistors were no more
expensive than resistors in the IC.
Limitations
The disadvantage of RTL is its high power dissipation when the transistor is switched on, by current flowing in the
collector and base resistors. This requires that more current be supplied to and heat be removed from RTL circuits.
In contrast, TTL circuits with "totem-pole" output stage minimize both of these requirements.
Another limitation of RTL was its limited fan-in: 3 inputs being the limit for many circuit designs, before it completely
lost usable noise immunity.[citation needed] It has a low noise margin. Lancaster says that integrated circuit RTL NOR
gates (which have one transistor per input) may be constructed with "any reasonable number" of logic inputs, and
gives an example of an 8-input NOR gate.
A standard integrated circuit RTL NOR gate can drive up to 3 other similar gates. Alternatively, it has enough output
to drive up to 2 standard integrated circuit RTL "buffers", each of which can drive up to 25 other standard RTL NOR
gates
Speeding up RTL
Various companies applied the following speed-up methods to discrete RTL.
Placing a capacitor in parallel with each input resistor decreases the time needed for a driving stage to forward-bias
a driven stage's base-emitter junction.
Using a high collector supply voltage and diode clamping decreased collector-base and wiring capacitance charging
time.
Another method that was familiar in discrete-device logic circuits used a diode and a resistor, a germanium and a
silicon diode, or three diodes in a negative feedback arrangement.

Transistortransistor logic
Transistortransistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and
resistors. It is called transistortransistor logic because both the logic gating function (e.g., AND) and the amplifying
function are performed by transistors.TTL is notable for being a widespread integrated circuit (IC) family used in
many applications such as computers, industrial controls, test equipment and instrumentation, consumer electronics,
synthesizers, etc. The designation TTL is sometimes used to mean TTL-compatible logic levels, even when not
associated directly with TTL integrated circuits.
TTL became the foundation of computers and other digital electronics. Even after much larger scale integrated
circuits made multiple-circuit-board processors obsolete, TTL devices still found extensive use as the "glue" logic
interfacing more densely integrated components. TTL devices were originally made in ceramic and plastic dual-inline (DIP) packages, and flat-pack form. TTL chips are now also made in surface-mount packages. Successors to
the original bipolar TTL logic often are interchangeable in function with the original circuits, but with improved speed
or lower power dissipation.
Implementation
Fundamental TTL gate

TTL inputs are the emitters of a multiple-emitter transistor. This IC structure is functionally equivalent to multiple
transistors where the bases and collectors are tied together. The output is buffered by a common emitter amplifier.

Fig - Two-input TTL NAND gate with a simple output stage (simplified)

Inputs both logical ones. When all the inputs are held at high voltage, the baseemitter junctions of the multipleemitter transistor are reverse-biased. Unlike DTL, a small collector current (approximately 10A) is drawn by each
of the inputs. This is because the transistor is in reverse-active mode. An approximately constant current flows from
the positive rail, through the resistor and into the base of the multiple emitter transistor. This current passes through
the base-emitter junction of the output transistor, allowing it to conduct and pulling the output voltage low (logical
zero).
An input logical zero. Note that the base-collector junction of the multiple-emitter transistor and the base-emitter
junction of the output transistor are in series between the bottom of the resistor and ground. If one input voltage
becomes zero, the corresponding base-emitter junction of the multiple-emitter transistor is in parallel with these two
junctions. A phenomenon called current steering means that when two voltage-stable elements with different
threshold voltages are connected in parallel, the current flows through the path with the smaller threshold voltage.
That is, current flows out of this input and into the zero (low) voltage source. As a result, no current flows through the
base of the output transistor, causing it to stop conducting and the output voltage becomes high (logical one). During
the transition the input transistor is briefly in its active region; so it draws a large current away from the base of the
output transistor and thus quickly discharges its base. This is a critical advantage of TTL over DTL that speeds up the
transition over a diode input structure.

Applications
Before the advent of VLSI devices, TTL integrated circuits were a standard method of construction for the processors
of mini-computer and mainframe processors, and for equipment such as machine tool numerical controls, printers
and video display terminals. As microprocessors became more functional, TTL devices became important for "glue
logic" applications, such as fast bus drivers on a motherboard, which tie together the function blocks realized in VLSI
elements
shift registers
The binary data in a register can be moved within the register from one flip-flop to another. The registers that allow
such data transfers are called as shift registers. There are four mode of operations of a shift register. The Shift
Register is another type of sequential logic circuit that can be used for the storage or the transfer of data in the form
of binary numbers. This sequential device loads the data present on its inputs and then moves or shifts it to its
output once every clock cycle, hence the name shift register.
1)Serial Input Serial Output

2)Serial Input Parallel Output

3)Parallel Input Serial Output

4)Parallel Input Parallel Output

5) Universal

shift reg.
Serial Input Serial Output
A block diagram of a serial-in/serial-out
shift register, which is 4-stages long.
Data at the input will be delayed by
four clock periods from the input to the
output of the shift register.
Data at data in, above, will be present at the Stage A output after the first clock pulse. After the second pulse stage
A data is transfered to stage B output, and data in is transfered to stage A output. After the third clock, stage C is
replaced by stage B; stage B is replaced by stage A; and stage A is replaced by data in. After the fourth clock, the
data originally present at data in is at stage D, output. The first in data is first out as it is shifted from data in to
data out.
Serial Input Parallel Output
Above, four data bits will be shifted in
from data in by four clock pulses and be
available at QA through QD for driving
external circuitry such as LEDs, lamps,
relay drivers, and horns.

After the first clock, the data at data in appears at Q A. After the second clock, The old Q A data appears at QB; QA
receives next data from data in. After the third clock, Q B data is at QC. After the fourth clock, QC data is at QD. This
stage contains the data first present at data in. The shift register should now contain four data bits.
Parallel Input Serial Output
Data is loaded into all stages at once of a
parallel-in/serial-out shift register. The data is
then shifted out via data out by clock pulses.
Since a 4- stage shift register is shown
above, four clock pulses are required to shift
out all of the data.

In the diagram above, stage D data will be present at the data out up until the first clock pulse; stage C data will be
present at data out between the first clock and the second clock pulse; stage B data will be present between the
second clock and the third clock; and stage A data will be present between the third and the fourth clock. After the
fourth clock pulse and thereafter, successive bits of data in should appear at data out of the shift register after a
delay of four clock pulses.
Parallel Input Parallel Output
A parallel-in/parallel-out shift register combines the function of the parallel-in, serial-out shift register with the function
of the serial-in, parallel-out shift register to yield the universal shift register. The do anything shifter comes at a
price the increased number of I/O (Input/Output) pins may reduce the number of stages which can be packaged.
Data presented at DA through DD is
parallel loaded into the registers.
This data at QA through QD may be
shifted by the number of pulses
presented at the clock input. The
shifted data is available at QA
through QD. The mode input, which
may be more than one input,
controls parallel loading of data from
DA through DD, shifting of data, and
the direction of shifting. There are
shift registers which will shift data
either left or right.
Universal Shift Register
A register which is capable of shifting data both to the right and left is called bidirectional shift register. A reg that can
shift in only one direction is called uni direction shift reg. if the reg has shift and parallel load capabilities, then it is
called a shift reg with parallel load or universal shift register. A register which can capable to transfer data in both the
shift-right and shift-left, along with the necessary input and output terminals for parallel transfer.
Shift Registers are used in digital electronic devices like computers as
Temporary data storage
Data manipulation
Data transfer
As counters.
Digital Counters
Counter is a sequential circuit. A digital circuit which is used for counting pulses is known counter. Counter is the
widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters are of two types.
1)Asynchronous or ripple counters.

2)Synchronous counters.

Asynchronous Counters
This type of counters have JK Flop-Flops arranged in a way that the output of one flip-flip feeds the clock of the
following flip-flop [1] as shown in the figure below:

Synchronous Counters
This type of counters has each flip-flop clocked by the same clock source, thus eliminating the cumulative delay
found in asynchronous counters [1]:

Triggering of FLIP FLOP

Flip Flops are synchronous bistable devices. The term synchronous means that the changes in the output occur at a
specified point on a triggering input called the clock, that is, changes in the output occur in synchronization with the
clock based on the specific interval or point in the clock during or at which triggering of flip flops takes place, it can be
classified into two different types:(1) Level triggering ( high level & low level Triggering)
(2) Edge triggering ( positive edge & negative edge triggering)
High Level Triggering
When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used. It is mainly identified
from the straight lead from the clock input. Take a look at the symbolic representation shown below.

2. Low Level Triggering

When a flip flop is required to respond at its LOW state, a LOW level triggering method is used.. It is mainly identified
from the clock input lead along with a low state indicator bubble. Take a look at the symbolic representation shown
below.
3. Positive Edge Triggering
When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge triggering method is used.
It is mainly identified from the clock input lead along with a triangle. Take a look at the symbolic representation shown
below.

ERROR DETECTION AND CORRECTION

There are many reasons such as noise, cross-talk etc., which may help data to get corrupted during transmission.
The upper layers work on some generalized view of network architecture and are not aware of actual hardware data
processing. Hence, the upper layers expect error-free transmission between the systems. Most of the applications
would not function expectedly if they receive erroneous data. Applications such as voice and video may not be that
affected and with some errors they may still function well.
Data-link layer uses some error control mechanism to ensure that frames (data bit streams) are transmitted with
certain level of accuracy. But to understand how errors is controlled, it is essential to know what types of errors may
occur.
Types of Errors
There may be three types of errors:

Single bit error - In a frame, there is only one bit, anywhere though, which is corrupt.

Multiple bits error - Frame is received with more than one bits in corrupted state.

Burst error - Frame contains more than1 consecutive bits corrupted.

Error control mechanism may involve two possible ways:

Error detection

Error correction

Error Detection
Errors in the received frames are detected by means of Parity Check and Cyclic Redundancy Check (CRC). In both
cases, few extra bits are sent along with actual data to confirm that bits received at other end are same as they were
sent. If the counter-check at receiver end fails, the bits are considered corrupted.
Parity Check
One extra bit is sent along with the original bits to make number of 1s either even in case of even parity, or odd in
case of odd parity.
The sender while creating a frame counts the number of 1s in it. For example, if even parity is used and number of
1s is even then one bit with value 0 is added. This way number of 1s remains even.If the number of 1s is odd, to
make it even a bit with value 1 is added.
EVEN PARITY - The receiver simply counts the number of 1s in a frame. If the count of 1s is even and even parity is
used, the frame is considered to be not-corrupted and is accepted. If the count of 1s is odd and odd parity is used,
the frame is still not corrupted.
If a single bit flips in transit, the receiver can detect it by counting the number of 1s. But when more than one bits are
erroneous, then it is very hard for the receiver to detect the error
Cyclic Redundancy Check (CRC)
CRC is a different approach to detect if the received frame contains valid data. This technique involves binary
division of the data bits being sent. The divisor is generated using polynomials. The sender performs a division
operation on the bits being sent and calculates the remainder. Before sending the actual bits, the sender adds the
remainder at the end of the actual bits. Actual data bits plus the remainder is called a codeword. The sender
transmits data bits as codewords.
At the other end, the receiver performs division operation on codewords using the same CRC divisor. If the
remainder contains all zeros the data bits are accepted, otherwise it is considered as there some data corruption
occurred in transit.
Error Correction
In the digital world, error correction can be done in two ways:

Backward Error Correction When the receiver detects an error in the data received, it requests
back the sender to retransmit the data unit.

Forward Error Correction When the receiver detects some error in the data received, it executes
error-correcting code, which helps it to auto-recover and to correct some kinds of errors.

The first one, Backward Error Correction, is simple and can only be efficiently used where retransmitting is not
expensive. For example, fiber optics. But in case of wireless transmission retransmitting may cost too much. In the
latter case, Forward Error Correction is used.
To correct the error in data frame, the receiver must know exactly which bit in the frame is corrupted. To locate the bit
in error, redundant bits are used as parity bits for error detection. For example, we take ASCII words (7 bits data),
then there could be 8 kind of information we need: first seven bits to tell us which bit is error and one more bit to tell
that there is no error.
For m data bits, r redundant bits are used. r bits can provide 2r combinations of information. In m+r bit codeword,
there is possibility that the r bits themselves may get corrupted. So the number of r bits used must inform about m+r
bit locations plus no-error information, i.e. m+r+1
CMOS
CMOS stands for Complementary Metal Oxide Semiconductor
Complementary: there are N-type and P-type transistors. N-type transistors use electrons as the current carriers. P-type
transistors use holes as the current carriers.
Metal: the gate of the transistor was made of aluminum metal in the early days, but is made of polysilicon today.
Oxide: silicon dioxide is the material between the gate and the channel
Semiconductor: the semiconductor material is silicon, a type IV element in the periodic chart.
CMOS NFET and PFET Transistors

N channel device: built directly in the P substrate with N-doped source and drain junctions and normally Ndoped gate conductor

Requires positive voltage applied to gate and drain (with respect to source) for electrons to flow from
source to drain (thought of as positive drain current)

P channel device: built in an N-well (a deep N-type junction diffused into the P substrate) with P-doped
source and drain junctions and N or P-doped gate

Requires negative voltage applied to gate and drain (with respect to source) for electrons to flow from
drain to source (thought of as negative drain current)

N-FET and P-FET Devices as Switches

NFET Device:

positive voltage (1 or high) on gate relative to source turns device ON and allows positive current to
flow from drain to source (switch closed)

zero volts on gate (0 or low) turns device OFF (open circuit)

Source (vs drain) is the most negative terminal

PFET Device:

Negative voltage (0 or low) on gate relative to source turns device ON and allows (negative) current
to flow from drain to source (closes switch)

Zero volts on gate relative to source (1 or high) turns device OFF (closes switch)

source (vs drain) is the most positive terminal

Simple CMOS Circuits: The Inverter Gate

The simplest complementary MOS (CMOS) circuit is the inverter:

NFET & PFET gates are connected together as the input

NFET & PFET drains are connected together as the output

NFET & PFET sources are connected to Gnd and Vdd, respectively.

NFET substrate is normally connected to Gnd for all NFET devices in the circuit

PFET well is normally connected to Vdd (most positive voltage in circuit) for all PFET devices

Operation:

If Vin is down (0 volts), NFET is OFF and PFET is ON pulling Vout to Vdd (high = 1)

If Vin is up (at Vdd), NFET is ON hard and PFET is OFF pulling Vout low to Gnd (0)

With Vin at 0 or Vdd, no dc current flows in inverter

4 bit adder
Binary adders are implemented to add two binary numbers. So in order to add two 4 bit binary numbers we need to use 4 full-adders. The
connection of full-adders to create binary adder circuit is discussed in block diagram below.

In this implementation, carry of each full-adder is connected to previous

carry.
Example - Lets discuss one example for 4 bit binary Adder. In this example we will use some terms from Register Transfer Level (RTL)
implementations.
Q. Add two binary numbers 7 and 15 with previous carry = 0
Sol. Load the values in two registers R1 and R2.
So, R1 = 7 (decimal) = 0111 (in binary A3A2A1A0)

& R2 = 15 (decimal) = 1111 (in binary B3B2B1B0)

So from the above implementation we have

Sum of two binary numbers 7 and 15 from above table

Is C4S3S2S1S0 = 10110 (In Binary) = 16 (decimal)
In the results we have appended C4 in front of the sum digits to
accommodate overflow bit from the binary addition flow.

Bidirectional Shift Register

If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is
shifted right by one position then it is equivalent to dividing the original number by 2. Hence if we want to use the shift register to multiply and
divide the given binary number, then we should be able to move the data in either left or right direction. Such a register is called bi-directional
register. A four bit bi-directional shift register is shown in fig. There are two serial inputs namely the serial right shift data input DR, and the
serial left shift data input DL along with a mode select input (M).

Operation
S.no

Operation
Condition

1
With M=1

If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the remaining AND gates 2, 4, 6 and 8 will be
disabled.

shift right operation

The data at DR is shifted to right bit by bit from FF-3 to FF-0 on the application of clock pulses. Thus with M = 1 we
get the serial right shift operation.

with M=0
shift left operation

When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7 are
disabled.
The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of clock pulses. Thus with M = 0 we get
the serial right shift operation.

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R inputs. It has only one input.
The input data is appearing at the output after some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be
the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem is
avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram

Truth Table

Operation
S.N
o.

Conditio
n

E=0

Operation

Latch is disabled. Hence no change in output.

E = 1 and
D=0

E = 1 and
D=1

If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the present state, the next state is Q n+1 = 0 and
Qn+1 bar = 1. This is the reset condition.

If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Q n+1 = 1 and Qn+1 bar = 0 irrespective of the
present state.
Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It has only input denoted by T as shown in the
Symbol Diagram. The symbol for positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram

Block Diagram

Truth Table

Operation
S.N.

Condition

Operation

T = 0, J = K = 0

The output Q and Q bar won't change

T = 1, J = K = 1

Output will toggle corresponding to every leading edge of clock signal.