Advanced Computer Arc. EXAM
Advanced Computer Arc. EXAM
Published by :
Think Tanks
Biyani Group of Colleges
Edition : 2011
Price :
While every effort is taken to avoid errors or omissions in this Publication, any mistake or
omission that may have crept in is not intentional. It may be taken note of that neither the
publisher nor the author will be responsible for any damage or loss of any kind arising to
anyone in any manner on account of such errors and omissions.
Preface
am glad to present this book, especially designed to serve the needs of the
students. The book has been written keeping in mind the general weakness in
understanding the fundamental concepts of the topics. The book is self-explanatory and
adopts the Teach Yourself style. It is based on question-answer pattern. The language of
book is quite easy and understandable based on scientific approach.
Any further improvement in the contents of the book by making corrections, omission
and inclusion is keen to be achieved based on suggestions from the readers for which the
author shall be obliged.
I acknowledge special thanks to Mr. Rajeev Biyani, Chairman & Dr. Sanjay Biyani,
Director (Acad.) Biyani Group of Colleges, who are the backbones and main concept
provider and also have been constant source of motivation throughout this Endeavour. They
played an active role in coordinating the various stages of this Endeavour and spearheaded
the publishing work.
I look forward to receiving valuable suggestions from professors of various educational
institutions, other faculty members and students for improvement of the quality of the book.
The reader may feel free to send in their comments and suggestions to the under mentioned
address.
Author
Syllabus
B.C.A. Part-III
Content
S. No.
Name of Topic
1.
2.
3.
4.
5.
5.1
6.
4.4
Symbolic Processors
4.5
Virtual Memory
4.6
Backplane Bus
Pipeline processors
Characteristics of Pipeline
5.2
Linear pipeline processors
5.3
Non Linear pipeline processors
5.4
Reservation table in linear pipelining & non
linear pipelining
5.5.
Instruction pipeline design
5.6
Arithmetic pipeline design
Unsolved Papers 2011 - 2006
Chapter 1
CU
IS
PU
DS
MM
10
PU1
PU2
DS1
DS2
MM1
MM2
CU
PUn
DSn
MMn
IS
IS1
CU1
IS2
CU2
IS1
IS2
11
PU1
PU2
MM1
MM2
ISn
IS3
CUn
ISn
MMn
IS2
IS1
DS
PUn
CU1
CU2
PU1
PU2
CUn
ISn
PUn
MM1
DS1
DS2
DSn
MM2
MMn
ISn
IS2
IS1
Ans. Modern computers are equipped with powerful hardware facilitates driven
by extensive software packages. To asses the state of computing we first
review historical milestones in the development of computers.
12
Computer Generations
Over the past five decades, electronic computers have gone through fine
generations of development. Each of first three generations lasted about 10
years. The fourth generations covered a time span of 15 years. We have just
entered the fifth generations with the use of processors & memory devices
with more than 1 million transistors on solo silicon chip. The table shows the
new hardware and software features introduced with each generation. Most
features introduced in earlier generations have been passed to later
generations.
Five Generations of Electronic Computers
Generation
First
(1945-54)
Second
(1955-64)
Third
(1965-74)
Fourth
(1975-90)
Fifth
(1991
present)
Representative
System
ENIAC, Princeton,
IAS, IBM 701
architectures.
In other words, the latest generation computers have inherited all the bad
ones found in previous generations.
Q.4.
Ans. Over the past four decades, computer architecture has gone through
evolutional rather than revolution changes sustaining features are those that
were proven performance delivers.
According to the figure we started with the Von Neumann architecture
built as a sequential machine executing scalar data. Sequential computers
improved from bit serial to word-parallel operations & from fixed point to
floating point operations. The Von Neumann architecture is slow due to
sequential execution of instructions in programme.
Lookahead, Paralleism and Pipelining : Lookahead techniques were begin to
prefetch instructions in order to overlap I/E (instruction fetch/decod e and
execution) operations and to enable functional parallelism. Functional
parallelism was supported by two approaches: One is to use multiple
functional units simultaneously and the other is to practice pipelining at
various processing levels.
The latter embrace pipelined instruction execution, pipelined arithmetic
computations and memory access operations. Pipelining has proven
especially attractive in performing identical operations repeatedly over vector
data strings. Vectors operations were originally carried out implicitly by
software controlled looping using scalar pipeline processors.
Flynns Classification: Michael Flynn (1972) established nomenclature of a
variety of computer architectures based on concept of instruction and data
streams. Traditional sequential machines are SISD (single instruction stream
over
a
single
data
stream).
Vector
computers
are
set
with scalar and vector hardware or emerge as SIMD (single instruction
stream over multiple data streams). Parallel computers are called MIMD
(multiple instruction streams over multiple data streams) machines.
Q.5.
Ans. Parallelism is the major concept used in today computer use of multiple
functional units is a form of parallelism within the CPU. In early computer
only one arithmetic & functional units are there so it cause only one operation
to execute at a time. So ALU function can be distributed to multiple
functional units, which are operating in parallel.
H.T. Kung has recognized that there is a need to move in three areas namely
computation model for parallel computing, inter process communication in
parallel architecture & system integration for incorporating parallel systems
into general computing environment.
13
14
Conditions of Parallelism :
1. Data and resource dependencies : A program is made up of several part,
so the ability of executing several program segment in parallel requires that
each segment should be independent other segment. Dependencies in various
segment of a program may be in various form like resource dependency,
control depending & data depending. Dependence graph is used to describe
the relation. Program statements are represented by nodes and the directed
edge with different labels shows the ordered relation among the statements.
After analyzing dependence graph, it can be shown that where opportunity
exist for parallelization & vectorization.
Data Dependencies: Relation between statements is shown by data
dependences. There are 5 types of data dependencies given below:
(a) Antidependency: A statement S2 is antidependent on statement ST1 if ST2
follows ST1 in order and if the output of ST2 overlap the input to ST1 .
(b) Input dependence: Read & write are input statement input dependence
occur not because of same variables involved put because of same file is
referenced by both input statements.
(c) Unknown dependence: The dependence relation between two statement
cannot be found in following situation
The subscript of variable is itself subscribed.
The subscript does not have the loop index variable.
Subscript is non linear in the loop index variable.
(d) Output dependence: Two statements are output dependence if they
produce the same output variable.
(e) Flow dependence: The statement ST2 is flow dependent if an statement
ST1 , if an expression path exists from ST1 to ST2 and at least are output of ST,
feeds in an input to ST2 .
2. Bernsteins condition : Bernstein discovered a set of conditions depending
on which two process can execute in parallel. A process is a program that is in
execution. Process is an active entity. Actually it is an stumbling block of a
program fragment defined at various processing levels. I i is the input set of
process Pi which is set of all input variables needed to execute the process
similarly the output set of consist of all output variable generated after
execution of all process P i. Input variables are actually the operands which
are fetched from the memory or registers. Output variables are the result to
be stored in working registers or memory locations.
15
16
that MIMD execution mode. But here major efforts are requisite by the
programmer to reorganize a program at this level.
4. Subprogram Level : Subprogram level communicate to job steps and
related subprograms. Grain size here have less than 1000 instructions. Job
steps can overlap across diverse jobs. Multiprogramming an uniprocessor or
multiprocessor is conducted at this level.
5. Job Level : It corresponds to parallel executions of independent tasks on
parallel computer. Grain size here can be tens of thousands of instructions. It
is handled by program loader and by operating system. Time sharing & space
sharing multiprocessors explores this level of parallelism.
Q.7.
Ans. Program & data are first loaded into the main memory from a host computer.
All instructions are first decoded by the scalar control unit. If the decoded
instruction is a scalar operation or program control operation it will be
directly executed by scalar processor using the scalar functional pipelines.
If the instruction is decoded as a vector procedure, it will be sent to the vector
control unit. This control unit will supervise the flow of vector data amid the
main memory & vector functional pipelines. The vector data flow is
synchronized by control unit. A number of vector functional pipelines may be
built into a vector processor.
Computers with vector processing capabilities are in demand in specialized
applications. The following are symbolized application areas where vector
processing is of utmost importance.
Long Range weather forecasting
Petroleum explorations
Medical diagnosis
Space flight simulations
17
Scalar Instructions
Vector
control
unit
Scalar
control
unit
Control
Instructions
Main
menory
Scalar
data
Mass
storage
Vector
func. pipe
Vector
registers
Host
computer
Vector
function pipe
Ans. The most popular parallel computers are those that execute programs in
MIMD mode. There are two major classes of parallel computers: shared
memory multiprocessor & message passing multi computers. The major
distinction between multiprocessors & multicomputer lies in memory sharing
and the mechanisms used for interprocessor communication. The processor
in multiprocessor system communicate with each other through shared
variable in a common memory. Each computer node in a multicomputer
system has a local memory, unshared with other nodes. Inter process
communication is done through message passing among nodes.
There are three shared memory multiprocessor models:1. Uniform memory access (UMA) model
2. Non-uniform memory access (NUMA) model
3. Cache only memory Architecture (COMA) model
These models are differ in how the memory & peripheral resources are
shared or distributed.
18
1. UMA Model:
P1
P2
Processor
Pn
System Interconnect
(Bus, Crossbar, Multistage network)
I/O
SM1
Shard manery
SMm
In this model the physical memory is uniformly shared by all the processors.
All processors have equal access time to all memory words, which is why it is
called uniform memory access. Each processor may use a private cache.
Peripherals are also shared.
Multiprocessors are called tightly coupled systems for its high degree of
resource sharing.
UMA model is suitable for time sharing applications by multiple users. It can
be used to speed up the execution of single large program in time critical
application.When all processors have equal access to all peripheral devices,
the system is called a symmetric multiprocessor. In this case, all the
processors are equally capable of running programme, such as kernel.
In an asymmetric multiprocessor, only one or subset of processors are
executive capable. An executive or master processor can execute the
operating system and handle I/O. The remaining processors called attached
processors (AP) runs user code under the supervision of master processor.
19
LM1
P1
LM2
P2
LMn
Pn
Inter
Connection
Network
20
GSM
GSM
GSM
P1
P2
Pn
CSM
P1
CSM
P2
CSM
Pn
CSM
CSM
CSM
Q.9.
21
All local memories are private & accessible only by local processors. This
network presents point-to-point static connection among nodes. Inter node
communication is carried out by passing messages through the static
connection network.
Q.10. Explain SIMD Computers?
Ans. SIMD connotes single instruction stream and multiple data stream. These
computers are array processors. There are multiple processing elements
which are supervised under same control unit. Each processing element
receives same instruction but operate on different data from distinct module,
SIMD Machine Model
An operational model of an SIMD computer is specified by 5- Triple.
M = [ N, C, I, M, R]
Where
(1) N is the number of processing elements (PEs) in the machine.
(2) C is the set of instructions directly executed by control unit including
scalar and program flow control instructions.
22
(3) I is set of instructions broadcast by CPU to all PEs for parallel execution.
These include arithmetic, logic, data routing, masking and other local
operations executed by each active PE over data within that PE.
(4) M is the set of masking schemes, where each mask partitions the set of PEs
into enabled & disabled subsets.
(5) R is the set of data routing functions, specifying various patterns to be set
up in the inter connection network for inter PE communications.
Q.11. What are the Architectural development tracks?
Ans. Architecture of todays systems pursue development tracks. There are mainly
3 tracks. These tracks are illustrious by likeness in computational model &
technological bases.
1. Multiple Processor tracks: multiple processor system can be shared
memory or distributed memory.
CMU/
C.mmP
NYU/
Ultra Computer
IBM RP
BBN Butterfly
23
CUBE 2/6400
Cosmic Cuben
Inter iPscs
Mosaic
Intel paragon
MIT/J Machine
CDC 7600
Cray Y- mp
Cray/m PP
Cray 1
Fujitru, NEC, Hitachi Mode
The CDC 7600 was first vector dual processor system. There are 2 subtracks
derived from CDC-7600. The latest cray/mpp is a massively parallel system
with distributed shared memory.
24
Tera
CDC 600
HFP
MIT/Alenrife
25
arrangement I
I/O
Data & Instruction
Data bus
PE
CU
Memory
CU
PE
PEM
PEN
PEM
Interconnection Network
PEM
Control
26
arrangement II
I/O
CU Memory
Control
CU
PE0
PE1
PEn-1
Alignment Network
M0
M1
Mn-1
arrangement II (BSP)
Main differences in arrangement I and II is in 2 aspects. First the local
memories are attached to the PEs are replaced by parallel memory module
shared by all the PEs through an alignment network. Second, inter PE
network is replace by the inter PE memory alignment network, which is
controlled by CU.
Example of configuration II is Burrough Scientific processor (BSP). There are
N PEs and P memory modules in configuration II. These two numbers (N and
P) are not equal and are relatively prime. The alignment network is a path
switching network between PEs and parallel memories.
27
Chapter 2
Ans. Traditional computers are founded on control flow mechanism by which the
order of program execution is explicitly stated in the user program. Data flow
computers have high degree of parallelism at the fine grain instruction level
reduction computers are based on demand driven method which commence
operation based on the demand for its result by other computations.
Data flow & control flow computers : There are mainly two sort of
computers. Data flow computers are connectional computer based on Von
Neumamm machine. It carry out instructions under program flow control
whereas control flow computer, executes instructions under availability of
data.
Control flow Computers : Control Flow computers employ shared memory
to hold program instructions and data objects. Variables in shared memory
are updated by many instructions. The execution of one instruction may
produce side effects on other instructions since memory is shared. In many
cases, the side effects prevent parallel processing from taking place. In fact, a
uniprocessor computer is inherently sequential due to use of control driven
mechanism.
Data Flow Computers : In data flow computer, the running of an instruction
is determined by data availability instead of being guided by program
counter. In theory any instruction should be ready for execution whenever
operands become available. The instructions in data driven program are not
ordered in any way. Instead of being stored in shared memory, data are
directly held inside instructions. Computational results are passed directly
between instructions. The data generated by instruction will be duplicated
into many copies and forwarded directly to all needy instructions.
This data driven scheme requires no shared memory, no program counter
and no control sequencer. However it requires special method to detect data
availability, to match data tokens with needy instructions and to enable the
chain reaction of asynchronous instructions execution.
28
Q.2.
Ans. There are more than a few new data flow computer projects. Arvind and his
associates at MIT have developed a tagged token architecture for constructing
data flow computers.
Global path
PE'
PE2
PEn
29
Token
Match
Program
memory
1-Structure
Compute
Tag
ALU
Form Token
30
the memory. The time required for two processes to synchronize with each
other is called synchronization latency; computational granularity and
communication latency are closely related.
Q.4.
Ans. There exists a tradeoff among parallelism and scheduling overheads. The
time complexity entail both computation and communication overheads. The
program partitioning entail the algorithm designer, programmer, compiler,
operating system support etc.
The concept of grain packing is to apply five grain first in order to achieve a
higher degree of parallelism. Then one combines multiple fine grain nodes
into a coarse grain node if it can remove redundant communications delays
or lessen the overall scheduling overhead.
Usually, all five grain operations within a single coarse, grain node are given
to some processor for execution. Fine grain partition of a program often
demands more inter processor communication than that required in a coarse
grain partition. Thus grain pickings offers a tradeoff between parallelism and
scheduling. Internal delays amid fine grain operations within the same coarse
grain node are negligible because the communication delay is given chiefly
by inter processor delays rather than by delays within the same processor.
The selection of optimal grain size is meant to get the shortest schedule for
the nodes on a parallel system.
ppp
31
Chapter 3
Ans. When a specified network is cut into two identical halves, the minimum
number of edges along the cut is termed as channel bisection width b. In the
32
Ans. Data routing networks is used for inter PE data exchange. Data routing
network can be static or dynamic. In multicomputer network data routing is
achieved by message among multiple computer nodes. Routing network
reduces the time required for data exchange and thus system performance is
enhanced. Commonly used data routing functions are shifting, rotation,
permutations, broadcast, multicast, personalized communication, shuffle etc.
Some Data routing functions are described below:
(a) Permutations: Let there are n objects, and then there are nf permutations
by which n objects can be recorded. Set of all permutations form a
permutation group with respect to composition operation. Generally cycle
notation is used to specify permutation function. Cross can be used to
implement the permutation. Multi stage network can implement some of the
permutations in one or multiple passes through the network. Shifting and
broadcast operation are also used to implement permutation operation.
Permutation capability of a network is used to indicate the data routing
capacity. Permutation speed dominates the performance of data routing
network, when n is large.
(b) Hypercube routing function: Three dimensional cube is shown below:
Routing functions are defined by three bits in the node address. Bit order is
C2 C1 Co. Data can be exchanged among adjacent nodes which differs in the
least significant bit Co as shown below.
000
001
010
011
100
101
110
111
33
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Ans. Static interconnection networks have many topologies. These topologies are
classified according to the dimensions required for layout. Example one
dimension, 2 dimensional, 3- dimensional. One dimensional incorporated
linear array which is used for a number of pipelined architecture 2dimensional includes topology: ring, star, mesh and systolic array. 3
34
dimensional embrace completely connected chordal ring, 3-cube and 3cube connected cycle network.
One dimensional topology
Linear Array: In this N-nodes are connected by N-1 links in the
line.
In linear array, each internal node has degree equal to 2. Each external node
or terminal nodes have degree equal to 1. Diameter is N -1, which is long for
large value of N. The bisection width is b = 1. Linear arrays are actually
simplest connection topology. arrangement of linear assays is not symmetric.
So when N is large, then communication inefficiency is there.
0
0
1
0
2
0
3
0
7
0
6
0
5
0
4
0
8
0
9
0
10
0
11
0
15
0
14
0
13
0
12
0
35
O
O
10
11
O
12
O
0
O
O1
9O
O
O2
8O
O3
O
7
O
6
Star topology
O
4
O
5
Ring topology
Systolic array: For implementing fixed algorithm this type of pipelined array
architecture
is
used.
Figure
of systolic array
topology is
shown:
O
O
O
O
O
O
O
O
36
O
O
O
O
O
O
O
O
3- Cube
A 4- cube is made by interconnecting the corresponding nodes of
two 3-cubes. Node degree of n-cube is equal to n and so does the
network diameter. Nodes degree increases linearly with respect to the
dimensions, thus making hypercube difficult to use as a scalable architecture.
Cube-Connected Cycles
Improved architecture of hypercube is the cube connected cycles. 3- Cubes
are customized to form 3-cube connected cycles (CCC).
Thus, K-cube connected cycle can be made from the L-cube with n = 2x cycles
nodes. Each vertex of K-dimensional hyper cube is replaced by a ring of Knodes thus a k- cube is translated into a K-CCC with K x 2K nodes.
Q.5.
Ans. For multipurpose and general purpose application we always use dynamic
connections. Dynamic connection implements all common wrication patterns
based on program demands. Fixed connections with switches on arbiters are
used along the connecting path to provide the dynamic connectivity.
Basically there are 2 classes of dynamic interconnection network-single stage
and multistage network.
Single Stage Network: Single stage network is a switching network with Ninput selectors (Is) and N output selectors (Os). Each input selector is 1- to D
demultiplexer and each output selector is an m to -1 multiplexer where 1 =
D = N and 1 = m = N. Single stage network is called recirculating network.
Data items are recirculate through the single stage determines the number of
recirculations required. Crossbar switching network is a single stage network
with D = M = N. For establishing the desired path different control signals are
applied to all input selectors and output selectors.
37
IS
O
IS
O
IS
1
IS
1
IS
N-1
N-1
N-1
IS
N-1
38
a0
a1
b0
Switch box
b1
a0
>
b0
a1
>
b1
a0
b0
a1
b1
a0
b0
a1
b1
a0
b0
a1
b1
39
Chapter 4
Ans.
Properties
CISC
RISC
1. Number of instruction
data is used.
differ from 3 to 5
Vary from 8 to 24
reference instructions.
Directly employed in
hardware
hardware.
Execution competence
increased.
increased.
Micro programmed
used.
implementation
8. Execution efficiency
9. Control logic used
40
is employed.
12. Clock rate
Q.2.
35-50MHz
50-150 MHz
Ans. In a super scalar processor, multiple instructions are employed, this means
that multiple instructions are issued per cycle and multiple results are created
per cycle.
In simple scalar processor one instruction executes per cycle. Only one
instruction is employed per cycle and only one completion of instruction is
probable per cycle.
Super Scalar process are intended to utilize more instruction level parallelism.
Super scalar operate basically in parallel.
Super Scalar Architecture
It involves highly multipored register files. Their input parts are required for
each EU.
Super Scalar processors acknowledge a usual sequential stream of
instructions but can generate more than are instructions to the EUs in each
cycle. Super scalar processors do not presume dependency free code. They
cope with dependencies themselves using hardware. Super scalar processors
with the same degree of parallel execution are considerable more
multifaceted.
Cache
mimory
41
Fetch
unit
Decode
unit
Multiple instruction
EU
Instruction/Data
Data
EU : Execution unit
Q.3.
EU
EU
Register file
42
Main
memory
Register file
Load/
store
unit
F.P.
add
unit
Integer
ALU
Branch
unit
VLIW processor
VLIW processor expect dependency free code i.e. multi operation code. VLIW
processors are statically programmed. VLIW notion is taken from horizontal
micro coding. Different fields of the long instruction word carry the opcodes
to be send off to different functional units.
Cache
memory
43
Fetch
unit
Single multi operation interuction
EU
EU
EU
EU
Register file
Multioperation
instruction
Instruction control
Data
Eu : Execution unit
Characteristics
1. Knowledge
2. Common operation
3. Memory Requirements
4. Communication pattern
5. Properties of Algorithm
44
6. Input-Output Requirements
machine
7. Architecture features
Q.5. What is Virtual memory? In how many classes virtual memory system is
categorized?
Ans
Virtual memory is a notion used in some large system, that permits user to
make program as through large memory space were present, equal to the
totality of auxiliary memory. In memory ladder programs and data are first
stored in auxiliary memory. Portion of program and data are then brought
into main memory as they are needed by CPU. Each address referenced by
CPU goes through an address mapping from virtual address to physical
address in memory.
Hence virtual memory forever give an false impression that they have large
memory at their disposal, even through computer has relatively small
memory.
Virtual memory based system provides a mechanism for translating program
generated address into correct main memory locations. This all process is
done dynamically, when process are executing in main memory. The
translation a mapping is handled by automatically using hardware of
mapping table. The address used by programs are called virtual address as
such addresses set is called address space. An address in main memory is
called physical address set of such address is called memory space.
Virtual Memory System is grouped in 2 classes:(1) Those with fixed sized blocks called pages.
(2) Those with variable size block called segments.
Paging: It is a memory management method that allows the physical address
space of a method to be non-continuous.
45
t
CPU
P d
f0000
Page table
Physical
memory
CPU
Sigment table
s d
yes
L
Physical
memory
46
Various functional boards are plugged into slots on the backplane. Each slot
is given with one or more connectors for pop in the boards as shown by the
vertical arrows. For example one or two 96-pin connectors are used per slot
on the VME backplane.
CPU Board
Memory Board
Processor
and
Cache
Memory
Array
Functional
modules
Functional
Modules
System clock
driver, daisy
chain drives
Powder driver
Bus timer
Arbiter
Interface
Logic
Interface
Logic
Interface
Logic
Bus controller
Slot 1
47
Chapter 5
Pipelines Processors
Q.1.
48
Single task
i/p
Stage 1
Stage 2
Stage 3
O/P
Stage n
Q.2.
Ans. A linear Pipeline processor is a flow of processing stages which are linearly
connected to perform a fixed function over a stream of data flowing from one
end to other. In modern computers, linear pipelines are applied for
instruction execution, arithmetic computation, memory access operations.
A linear pipeline processor is built with the processing stages. External inputs
are inputted into the pipeline at the first stage S1 . The processed results are
passed from stage Si to stage Si+1 for all i = 1,2.K-1. The final result
appear from the pipeline at the last stage Sk. Depending on the control of
data flow along the pipeline, linear pipelines are formed in two group.
Asynchronous Model: Data flow amid adjacent stages in asynchronous
pipeline is controlled by handshaking protocol. When stage S1 is ready to
transmit, it sends a ready signal to Si + 1. After stage Si+1 receives the
incoming data, it returns an acknowledge signal to Si.
Input
Ready
Ack
S1
Ready
Ack
S2
Ready
Ack
Onput
Sk
Ready
Ack
49
L
Output
S2
S1
o
Sk
o
Clock
S2
Sk
Output
50
Stages
S1
S2
S3
S4
Stages
S1
S2
S1
S2
S3
S1
S3
S1
8
X
Processing sequence
S2
6
X
S3
S1
51
Fetch
F
Decode
D
Issue
I
Execute
E
Execute
E
Execute
E
Write
Back
52
the store of sum to memory location X must wait three cycles for the add
to finish due to flow dependence.
Q.7.
Ans
Pipeline arithmetic units are typically set up in very high speed computers.
They are used to apply floating point operation, multiplication of fixed point
numbers and similar computations encountered in scientific problems.
a Exponents b
A Mentissa B
Segment 2
Choose exponent
Allign mantissa
R
Segment 3
Segment 4
Add or subtract
Mantissa
Adjust exponent
Normalise Result
53
54
Case Studies
Case Study 1.
Cache Policies.
Consider two alternate caches, each with 4 sectors holding 1 block per sector and
one 32-bit word
per block. One cache is direct mapped and the other is fully associative with LRU
replacement
policy. The machine is byte addressed on word boundaries and uses write allocation
with write
back.
1a) What would the overall miss ratio be for the following address stream on the
direct
mapped cache? Assume the cache starts out completely invalidated.
read 0x00 M
read 0x04 M
write 0x08 M
read 0x10 M
read 0x08 H
write 0x00 M Miss ratio = 5/6 = 0.8333
55
LRU replacement
write back
byte addresses on word boundaries
2a) Sketch a block diagram of how the virtual address is mapped into the physical
address (assuming a TLB hit). Be sure to label exactly which/how many of the
address bits go
where. and how many bits are in each of the 3 fields in a TLB entry.
1 GB MEANS
30-BIT
VIRTUAL
ADDRESS
UNTRANSLATED
TLB
BITS 12-29
LOOKUP
18 bit
8 bits
14 bit
PAGE CONTROL
PAGE
NAME
ADDRESS
ASSOCIATIVE
You have a computer with two levels of cache memory and the following
specifications:
CPU Clock: 200 MHz Bus speed: 50 MHz
Processor: 32-bit RISC scalar CPU, single data address maximum per instruction
L1 cache on-chip, 1 CPU cycle access
block size = 32 bytes, 1 block/sector, split I & D cache
each single-ported with one block available for access, non-blocking
L2 cache off-chip, 3 CPU cycles transport time (L1 miss penalty)
56
57
Compute a measure of speed for each alternative and indicate which is the faster
solution. Assume
the performance statistics are
L2 cache local miss ratio = 0.19
Victim cache miss ratio = 0.26; and its transport time from L1 miss = 1 clock
Given fixed L1 cache performance, it is fair to compare these head-to-head (but the
comparison
might not stay the same if L1 were changed):
tea for L2 cache beyond the L1 access time is:
3 + 0.19 * (12+4+4+4) = 7.56 clocks in addition to L1 delay
tea for L2 cache beyond the L1 access time is:
1 + 0.26 * (12+4+4+4) = 7.24 clocks in addition to L1 delay
So, in this (contrived) case the victim cache is a slight win in speed, and a whole lot
cheaper.
Case Study 4.
Discuss about the advantage(s) and the disadvantages of the von Nuemann concept.
Solution:
The von Neumann concept is a computer design model that uses a single storage
model to hold both instructions and data.
Advantages:
Reprogramming was made easier
Programs are allowed to modify themselves
Programs can write Programs
General flexibility
Disadvantages:
Malfunctioning programs can damage other programs or the operating
system
von Neumann bottleneck - CPU must wait for Data to transfer to and from
memory
58
Case Study 5.
Define term delayed branch, its application, and its shortcomings.
Solution:
Advantage:
Allows for pipeline CPUs to reduce the clock cycles wasted due to pipeline
flushing during a branch or a jump operation
Disadvantage:
If the compiler cannot put instructions to execute after the branch due to
dependencies, then it must insert no-op instructions which increases the size
of program
Case Study 6.
CPU time (T) is defined as:
T = Ic* CPI *
Ic stands for the instruction count,
Solution:
Issues:
Memory Access: Any access to the memory can take longer than one
instruction
Branching: Program branches will flush instructions in a pipeline and cause it
to take longer then one instruction
Case Study 7. Loop fusion allows two or more loops that are executed the same
number of times and that use the same indices to be combined into one loop:
1. Within the scope of a RISC processor, why does it (Loop fusion) improve
performance (detail explanation)?
Solution:
59
60
Solution:
Solution:
In interleaved memory, the memory is divided into N banks of memory where
virtual address, i, would actually reside in memory bank i/N (ignoring the
remainder), logically addressed by i mod N.
Solution:
61
1.
2.
3.
Set-A
RISC stands for:
(a)
Register Instruction Set Computer
(b)
Reduced Instruction Set Computer
(c)
Reduced Instruction Set Clock
(d)
None of the above
( )
( )
( )
4.
........................is a term used to denote a large class of techniques that are used to provide
simultaneous data processing tasks
(a)
Shared memory
(b)
Parallel Processing
(c)
Memory hierarchy
(d)
None of the above
( )
5.
6.
7.
( )
62
(c)
(d)
8.
Instruction Register
Program Counter
( )
( )
9.
Many operating system are designed to enable the CPU to process a number of
independent program concurrently. This concept is called:
(a)
Cache Memory
(b)
Multiprogramming
(c)
Multiprocessor
(d)
None of the above
( )
10.
11.
12.
( )
( )
13.
Computers are interconnected with each other by means of communication lines to form
a:
(a)
Computer Network
(b)
Multiprocessor
(c)
Data Dependency
(d)
None of the above
( )
14.
15.
Loosely coupled system are more efficient when the interaction between task is:
( )
(a)
(c)
16.
17.
Maximum
Can not say
63
(b)
(d)
Minimum
None of the above
( )
( )
The memory connected to the common system bus is.......................by all processors.
(a)
Shared
(b)
Partitioned
(c)
Distributed
(d)
None of the above
( )
18.
19.
( )
( )
( )
( )
( )
20.
21.
22.
23.
24.
64
(c)
MIMD
(d)
( )
25.
26.
27.
28.
29.
30.
( )
( )
( )
( )
Router is a :
(a)
Data Transfer Protocol
(b)
Networking device
(c)
Modem
(d)
None of the above
( )
Answer
1. (b)
11. (b)
21. (c)
2. (b)
12. (d)
22. (a)
3. (c)
13. (a)
23. (c)
4. (b)
14. (b)
24. (b)
5. (a)
15. (b)
25. (a)
6. (c)
16. (c)
26. (a)
7. (d)
17. (a)
27. (a)
8. (a)
18. (a)
28. (a)
9. (b)
19. (d)
29. (d)
10. (c)
20. (a)
30. (b)
65
Set-B
1.
The channel width of a ..............network increases as we ascend from leaves to the root.
(a)
(b)
(c)
(d)
2.
3.
4.
5.
6.
7.
8.
( )
The time required for two processes to synchronize with each other is called:
(a)
Synchronization time
(b)
Synchronization Latency
(c)
Process Latency
(d)
Memory latency
( )
If the number of links is 2N, then this would be which kind of network?
(a)
Illiac mesh
(b)
2D Mesh
(c)
Both (a) and (b)
(d)
None of the above
( )
( )
Dynamic
None of the above
( )
SIMD is a :
(a)
Memory management scheme
(b)
Processor for multiple organization
(c)
Attachment array processor
(d)
Programming technique
( )
( )
66
(c)
(d)
9.
10.
11.
12.
13.
( )
( )
( )
( )
( )
( )
14.
.................is a shared memory system in which the access time varies with the location of
the memory word:
(a)
COMA
(b)
UMA
(c)
NUMA
(d)
All of the above
( )
15.
16.
( )
(a)
(b)
(c)
(d)
17.
18.
19.
20.
21.
22.
67
( )
( )
( )
( )
The process of assigning control of the data transfer bus to a requester is called:
(a)
Interleaving
(b)
Interruption
(c)
Synchronization
(d)
Arbitration
( )
( )
(b)
Dual of Parallelism
(d)
Degree of parallelism
( )
23.
Processors that use multiphase clock with a much increases clock rate ranging from 100 to
500 MHz.
(a)
RISC
(b)
VLIW
(c)
Both a and b
(d)
None of the above
( )
68
24.
25.
An/a .....................is a request from I/O or other devices to a processor for services or
attention:
(a)
Transaction
(b)
Arbitration
(c)
Interrupt
(d)
None of the above
( )
26.
( )
( )
The memory hierarchy developed was based on a program behaviour is known is:
(a)
Locality of reference
(b)
Locality of coherence
(c)
Coherence property
(d)
None of the above
( )
27.
28.
29.
30.
( )
Answer
1. (a)
11. (b)
21. (d)
2. (b)
12. (d)
22. (c)
3. (c)
13. (b)
23. (c)
4. (a)
14. (c)
24. (b)
5. (c)
15. (d)
25. (c)
6. (b)
16. (b)
26. (b)
7. (a)
17. (a)
27. (b)
8. (d)
18. (d)
28. (a)
9. (a)
19. (a)
29. (b)
10. (a)
20. (b)
30. (c)
1.
69
Set C
Cache memory is:
(a)
Temporary and costly
(b)
Primary
(c)
High speed memory
(d)
All of the above
( )
2.
..................instruction is used to store the contents of accumulator into the memory word
specified by the effective addresses:
(a)
LDA
(b)
BUN
(c)
STA
(d)
BSA
( )
3.
( )
4.
A computer system consists of a CPU, a memory and one or more specialized I/O
processor called:
(a)
Bandwidth
(b)
Data Channels
(c)
Interrupt
(d)
None of the above
( )
5.
6.
7.
( )
SIMM is a :
(a)
Single Instruction memory modular
(b)
Single in Line Memory Modular
(c)
Single Instruction Memory Manufacturer
(d)
Single in Line Micrograms Modular
( )
( )
70
8.
9.
10.
11.
12.
13.
14.
( )
( )
( )
( )
( )
RAID is:
(a)
A computer
(b)
Storage device
(c)
A type of input device
(d)
A type of output device
( )
( )
15.
16.
17.
18.
19.
20.
21.
22.
71
( )
A memory deices in which a bit is stored as a charge across the stray capacitance:
(a)
SRAM
(b)
EPROM
(c)
DRAM
(d)
Bubble Memory
( )
( )
( )
( )
( )
( )
Two or more CPU's present in a computer system which share some or all of the memory
called:
(a)
Paralled
(b)
Multipgramming
(c)
Multi tasking
(d)
Random File processing ( )
72
23.
Which mode transits data in both directions, but not at the same time:
(a)
Simplex mode
(b)
Half duplex mode
(c)
Full duplex
(d)
None
( )
24.
If a process does not have direct and unassisted access to data items these items are
said to be:
(a)
Off line
(b)
Time shared
(c)
On line
(d)
None
( )
25.
( )
( )
Pipelining is:
(a)
Programming technique
(b)
Decomposing of sequential process into sub operations
(c)
Hardware module
(d)
None
( )
( )
26.
27.
28.
29.
30.
( )
( )
73
Answer
1. (d)
11. (d)
21. (b)
2. (c)
12. (d)
22. (a)
3. (b)
13. (b)
23. (b)
4. (d)
14. (a)
24. (a)
5. (d)
15. (a)
25. (d)
6. (a)
16. (c)
26. (b)
7. (c)
17. (c)
27. (b)
8. (b)
18. (c)
28. (c)
9. (a)
19. (c)
29. (b)
10. (c)
20. (c)
30. (b)
74
Set D
1.
....................modules are used to select one out of n read or write requested for service:
(a)
Multiplexer
(b)
Demultiplexer
(c)
Crossbar
(d)
All of the above
( )
2.
3.
It manager the allocation and deal location of resources during the exeuction of user
programs:
(a)
CPU
(b)
OS
(c)
Monitor
(d)
Keyboard
( )
4.
( )
( )
( )
( )
5.
6.
7.
75
8.
9.
10.
11.
12.
( )
( )
( )
Which dynamic connection network has a low with limited bandwidth features?
(a)
Multistage interconnection
(b)
Crossbar switch
(c)
Bus system
(d)
All of the above
( )
13.
14.
( )
15.
...........................is a cascade of processing stage which are linearly connected to perform a
fixed function over a stream of data flowing from one end to the other:
(a)
Omega network
(b)
Tree Network
(c)
Linear Pipeline
(d)
Parallel Processor `
( )
16.
76
(b)
(c)
(d)
17.
Micro pipelining
Man pipelining
None of the above
( )
( )
18.
19.
The percentage of time that each pipeline stage is used over a sufficiently long series of
task initiation is the:
(a)
Pipeline throughout
(b)
Pipeline efficiency
(c)
Pipeline latency
(d)
Pipeline clock
( )
20.
21.
22.
23.
( )
( )
77
24.
25.
( )
( )
26.
27.
.....................is a pair of nodes that accounts for a disproportionately large portion of the
total network traffic.
(a)
Hit ration
(b)
Hot ratio
(c)
Hot spot
(d)
Hit spot
( )
28.
The memory hierarchy developed was based on a program behaviour is known as:
(a)
Coherence property
(b)
Locality of reference
(c)
Locality of coherence
(d)
None of the above
( )
Write through and write back are two strategies for maintaining:
(a)
Locality of reference
(b)
Collision
(c)
Coherence
(d)
All of the above
( )
( )
29.
30.
Answer
1. (a)
2. (b)
11. (b)
12. (c)
21. (d)
22. (c)
3. (b)
13. (a)
23. (b)
4. (d)
14. (b)
24. (a)
5. (b)
15. (c)
25. (b)
6. (c)
16. (b)
26. (c)
7. (d)
17. (a)
27. (c)
8. (a)
18. (a)
28. (b)
9. (a)
19. (c)
29. (d)
10. (a)
20. (b)
30. (b)
78
ADVANCED COMPUTER
ARCHITECTURE
OBJECTIVE PART- I
Year - 2011
Time allowed : One Hour
Maximum Marks : 20
The question paper contains 40 multiple choice questions with four choices and students
will have to pick the correct one. (Each carrying marks.).
1.
2.
3.
4.
()
( )
( )
(d)
5.
6.
7.
8.
9.
10.
11.
12.
79
( )
(b)
(d)
( )
Router is a :
(a)
Data transfer protocol
(b)
Networking device
(c)
Modem
(d)
None of the above
( )
( )
( )
SIMM is a :
(a)
Single Instruction Memory Modular
(b)
Single in-Line memory modular
(c)
Single instruction memory manufacturer
(d)
Single In-Line Micro programs Modular
The speed of microcomputer is measured in:
(a)
MIPS
(c)
Megahertz
(b)
(d)
( )
Picoseconds
Millihertz
( )
( )
( )
80
13.
14.
15.
16.
17.
18.
19.
20.
( )
are
( )
( )
( )
( )
( )
( )
(c)
(d)
21.
22.
23.
24.
25.
26.
27.
81
( )
( )
For a reservation table with n columns, the maximum forbidden latency (m) :
(a)
m n
(b)
m nn
(c)
m n
(d)
m n1
( )
( )
( )
( )
The T3D is a :
(a)
SIMD machine
(b)
MIMD machine
(c)
Both (a) and (b)
(d)
None of the above
( )
In future Bus + standard, the 64-bit address line are multiplexed with:
(a)
Lower order 64-bit data lines
(b)
High order 64-bit data lines
(c)
Lower order 32-bit data lines
(d)
Any one of the above
( )
82
28.
29.
30.
31.
32.
( )
Pipelining is:
(a)
Programming Techniques
(b)
Decomposing of sequential process into sub operations
(c)
Hardware module
(d)
None of the above
( )
( )
Bootstrap is:
(a)
A memory device
(c)
Error correction technique
(b)
(d)
A startup program
None of the above
( )
used
( )
33.
34.
( )
( )
35.
36.
37.
be
38.
39.
40.
83
( )
to
( )
( )
( )
( )
______________
84
DESCRIPTIVE PART-II
Year- 2011
Time allowed : 2 Hours
Maximum Marks : 30
Attempt any four descriptive types of questions out of the six. All questions carry 7 marks
each.
1.
2.
(a)
(b)
3.
(a)
(b)
4.
(a)
(b)
5.
(a)
(b)
6.
85
ADVANCED COMPUTER
ARCHITECTURE
OBJECTIVE PART- I
Year - 2010
Time allowed : One Hour
Maximum Marks : 20
The question paper contains 40 multiple choice questions with four choices and students
will have to pick the correct one. (Each carrying marks.).
1.
2.
3.
4.
( )
( )
( )
........................is a term used to denote a large class of techniques that are used to provide
simultaneous data processing tasks
(a)
Shared memory
(b)
Parallel Processing
(c)
Memory hierarchy
(d)
None of the above
( )
86
5.
6.
( )
( )
( )
7.
8.
9.
Many operating system are designed to enable the CPU to process a number of
independent program concurrently. This concept is called:
(a)
Cache Memory
(b)
Multiprogramming
(c)
Multiprocessor
(d)
None of the above
( )
10.
11.
12.
( )
( )
87
13.
Computers are interconnected with each other by means of communication lines to form
a:
(a)
Computer Network
(b)
Multiprocessor
(c)
Data Dependency
(d)
None of the above
( )
14.
( )
Loosely coupled system are more efficient when the interaction between task is:
(a)
Maximum
(b)
Minimum
(c)
Can not say
(d)
None of the above
( )
( )
The memory connected to the common system bus is.......................by all processors.
(a)
Shared
(b)
Partitioned
(c)
Distributed
(d)
None of the above
( )
15.
16.
17.
18.
19.
( )
( )
( )
20.
21.
22.
88
(a)
(b)
(c)
(d)
23.
( )
( )
24.
25.
26.
27.
28.
29.
30.
( )
( )
( )
( )
(c)
(d)
89
Modem
None of the above
( )
31.
Two or more CPUs present in a computer system which share some or all of the memory?
(a)
Parallel Processing
(b)
Multiprogramming
(c)
Random file processing
(d)
Multitasking
( )
32.
( )
( )
( )
( )
( )
( )
33.
34.
35.
36.
37.
38.
Static
None of the above
( )
90
39.
40.
( )
..........................is a concept used in some large computer systems that permit the user to
construct programs as thought a large memory space.
(a)
Cache memory
(b)
Random access memory
(c)
Virtual memory
(d)
None of the above
( )
Answer Key
1. (b)
2. (b)
3. (c)
4. (b)
5. (a)
6. (c)
7. (d)
8. (a)
9. (b)
10. (c)
11. (b)
12. (d)
13. (a)
14. (b)
15. (b)
16. (c)
17. (a)
18. (a)
19. (d)
20. (a)
21. (c)
22. (a)
23. (c)
24. (b)
25. (a)
26. (a)
27. (a)
28. (a)
29. (d)
30. (b)
31. (d)
32. (c)
33. (b)
34. (a)
35. (d)
36. (b)
37. (b)
38. (c)
39. (b)
40. (c)
___________
91
DESCRIPTIVE PART-II
Year- 2010
Time allowed : 2 Hours
Maximum Marks : 30
Attempt any four descriptive types of questions out of the six. All questions carry 7 marks
each.
Q.1
(a)
(b)
Q.2
Q.3
Q.4
(a)
(b)
Q.5
(a)
(b)
Q.6
Write
(a)
(b)
(c)
92
OBJECTIVE PART- I
Year - 2009
Time allowed : One Hour
Maximum Marks : 20
The question paper contains 40 multiple choice questions with four choices and student will have
to pick the correct one. (Each carrying marks.).
1.
The channel width of a ..............network increases as we ascend from leaves to the root.
(a)
(b)
(c)
(d)
2.
3.
4.
5.
6.
( )
The time required for two processes to synchronize with each other is called:
(a)
Synchronization time
(b)
Synchronization Latency
(c)
Process Latency
(d)
Memory latency
( )
If the number of links is 2N, then this would be which kind of network?
(a)
Illiac mesh
(b)
2D Mesh
(c)
Both (a) and (b)
(d)
None of the above
( )
( )
Dynamic
None of the above
( )
( )
7.
8.
9.
10.
11.
12.
13.
14.
93
( )
( )
( )
( )
( )
( )
( )
.................is a shared memory system in which the access time varies with the location of
the memory word:
(a)
COMA
(b)
UMA
94
(c)
(d)
15.
16.
17.
18.
19.
20.
21.
22.
NUMA
All of the above
( )
( )
( )
( )
( )
( )
The process of assigning control of the data transfer bus to a requester is called:
(a)
Interleaving
(b)
Interruption
(c)
Synchronization
(d)
Arbitration
( )
( )
(b)
Dual of Parallelism
(d)
Degree of parallelism
(c)
(d)
95
( )
23.
Processors that use multiphase clock with a much increases clock rate ranging from 100 to
500 MHz.
(a)
RISC
(b)
VLIW
(c)
Both a and b
(d)
None of the above
( )
24.
25.
An/a .....................is a request from I/O or other devices to a processor for services or
attention:
(a)
Transaction
(b)
Arbitration
(c)
Interrupt
(d)
None of the above
( )
26.
( )
( )
The memory hierarchy developed was based on a program behaviour is known is:
(a)
Locality of reference
(b)
Locality of coherence
(c)
Coherence property
(d)
None of the above
( )
27.
28.
29.
30.
96
(b)
(c)
(d)
31.
32.
( )
( )
( )
33.
......................is a pair of nodes that accounts for a disproportionately large portion of the
total network traffic.
(a)
Hot spot
(b)
Hit Spot
(c)
Hot ratio
(d)
Hit ratio
( )
34.
35.
36.
( )
(b)
(d)
Macro pipelining
None of the above
( )
( )
37.
Two or more CPUs present in a computer system which share some or all of the memory:
(a)
Parallel Processing
(b)
Multiprogramming
(c)
Random file processing
(d)
Multitasking
( )
38.
(a)
(b)
(c)
(d)
39.
40.
97
( )
( )
( )
Answer Key
1. (a)
2. (b)
3. (c)
4. (a)
5. (c)
6. (b)
7. (a)
8. (d)
9. (a)
10. (a)
11. (b)
12. (d)
13. (b)
14. (c)
15. (d)
16. (b)
17. (a)
18. (d)
19. (a)
20. (b)
21. (d)
22. (c)
23. (c)
24. (b)
25. (c)
26. (b)
27. (b)
28. (a)
29. (b)
30. (c)
31. (b)
32. (d)
33. (b)
34. (d)
35. (b)
36. (b)
37. (b)
38. (d)
39. (c)
40. (c)
_____________
98
DESCRIPTIVE PART - II
Year 2009
Time allowed : 2 Hours
Maximum Marks : 30
Attempt any four questions out of the six. All questions carry 7 marks each.
Q.1
(a)
(b)
Q.2
(a)
(b)
Q.3
Q.4
(a)
(b)
Discuss the terms data transfer bus (DTB) bus arbitration and control and
Financial modules related to backplane bus.
What do you mean by Backplane Bus system?
Q.5
(a)
(b)
Q.6
What is the basic difference between a linear pipeline processor and non-linear pipeline
processor? Discuss the asynchronous and synchronous models of linear pipeline
processor.
_______
99
OBJECTIVE PART- I
Year - 2008
Time allowed : One Hour
Maximum Marks : 20
The question paper contains 40 multiple choice questions with four choices and student will have
to pick the correct one. (Each carrying marks.).
1.
( )
2.
..................instruction is used to store the contents of accumulator into the memory word
specified by the effective addresses:
(a)
LDA
(b)
BUN
(c)
STA
(d)
BSA
( )
3.
( )
4.
A computer system consists of a CPU, a memory and one or more specialized I/O
processor called:
(a)
Bandwidth
(b)
Data Channels
(c)
Interrupt
(d)
None of the above
( )
5.
6.
SIMM is a :
(a)
Single Instruction memory modular
(b)
Single in Line Memory Modular
( )
100
(c)
(d)
7.
8.
9.
10.
11.
12.
13.
14.
( )
( )
( )
( )
( )
( )
( )
RAID is:
(a)
A computer
(b)
Storage device
(c)
A type of input device
(d)
A type of output device
( )
(a)
(b)
(c)
(d)
15.
16.
17.
18.
19.
20.
21.
CISC
SMP
RISC
All of the above
101
( )
( )
A memory deices in which a bit is stored as a charge across the stray capacitance:
(a)
SRAM
(b)
EPROM
(c)
DRAM
(d)
Bubble Memory
( )
( )
( )
( )
( )
( )
102
22.
Two or more CPU's present in a computer system which share some or all of the memory
called:
(a)
Paralled
(b)
Multipgramming
(c)
Multi tasking
(d)
Random File processing
( )
23.
Which mode transits data in both directions, but not at the same time:
(a)
Simplex mode
(b)
Half duplex mode
(c)
Full duplex
(d)
None
( )
24.
If a process does not have direct and unassisted access to data items these items are
said to be:
(a)
Off line
(b)
Time shared
(c)
On line
(d)
None
( )
25.
( )
( )
Pipelining is:
(a)
Programming technique
(b)
Decomposing of sequential process into sub operations
(c)
Hardware module
(d)
None
( )
( )
( )
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
103
SIMD is a :
(a)
Memory management scheme
(b)
Processor for multiple data organization
(c)
Attached array processor
(d)
Programming technique
( )
Multi-programming is:
(a)
A technique to perform more than one task in memory
(b)
Capability to keep more than one program
(c)
A technique to perform paralel processing
(d)
None of the above
( )
( )
Bootstrap is:
(a)
A memory device
(b)
a device to support the computer
(c)
A startup correction technique
(d)
an error correction technique
( )
( )
Router is a:
(a)
Networking device
(b)
Data transfer protocol
(c)
Modem
(d)
None
( )
Bus is a:
(a)
Logical Channel for transferring data
(b)
Electronic pathway for transferring data
(c)
Dedicated path
(d)
None
( )
104
(d)
38.
39.
40.
Microsoft
( )
( )
( )
(b)
(d)
Clock count
Instruction count
( )
Answer Key
1. (d)
11. (d)
21. (b)
31. (a)
2. (c)
12. (d)
22. (a)
32. (d)
3. (b)
13. (b)
23. (b)
33. (c)
4. (d)
14. (a)
24. (a)
34. (a)
5. (d)
15. (a)
25. (d)
35. (a)
6. (a)
16. (c)
26. (b)
36. (a)
_____________
7. (c)
17. (c)
27. (b)
37. (c)
8. (b)
18. (c)
28. (c)
38. (a)
9. (a)
19. (c)
29. (b)
39. (b)
10. (c)
20. (c)
30. (b)
40. (d)
105
DESCRIPTIVE PART - II
Year 2008
Time allowed : 2 Hours
: 30
Maximum Marks
Attempt any four questions out of the six. All questions carry 7 marks each.
Q.1
What do you understand with virtual memory? Describe the page replacement techniques
in virtual memory
Q.2
Q.3
Q.4
What do you understand with pipelining processor? Describe the arithmetic pipeli ne with
the help of example
Q.5
Describe:
(i)
Vector Processing principles
(ii)
Memory interleaving
Q.6
Differentiate between the RISC and CISC processors. Explain also the characteristics of
both.
_______
106
OBJECTIVE PART- I
Year - 2007
Time allowed : One Hour
Maximum Marks : 20
The question paper contains 40 multiple choice questions with four choices and student will have
to pick the correct one. (Each carrying marks.).
1.
....................modules are used to select one out of n read or write requested for service:
(a)
Multiplexer
(b)
Demultiplexer
(c)
Crossbar
(d)
All of the above
( )
2.
3.
It manager the allocation and deal location of resources during the exeuction of user
programs:
(a)
CPU
(b)
OS
(c)
Monitor
(d)
Keyboard
( )
4.
( )
( )
5.
6.
(b)
(c)
(d)
7.
COMA
UMA
All of the above
107
( )
( )
8.
9.
( )
( )
( )
Which dynamic connection network has a low with limited bandwidth features?
(a)
Multistage interconnection
(b)
Crossbar switch
(c)
Bus system
(d)
All of the above
( )
10.
11.
12.
13.
14.
108
(d)
Degree of processing
( )
15.
...........................is a cascade of processing stage which are linearly connected to perform a
fixed function over a stream of data flowing from one end to the other:
(a)
Omega network
(b)
Tree Network
(c)
Linear Pipeline
(d)
Parallel Processor `
( )
16.
17.
( )
( )
18.
19.
The percentage of time that each pipeline stage is used over a sufficiently long series of
task initiation is the:
(a)
Pipeline throughout
(b)
Pipeline efficiency
(c)
Pipeline latency
(d)
Pipeline clock
( )
20.
21.
22.
( )
(c)
(d)
Instruction Count
Clock Count
109
( )
23.
24.
( )
( )
( )
25.
26.
27.
.....................is a pair of nodes that accounts for a disproportionately large portion of the
total network traffic.
(a)
Hit ration
(b)
Hot ratio
(c)
Hot spot
(d)
Hit spot
( )
28.
The memory hierarchy developed was based on a program behaviour is known as:
(a)
Coherence property
(b)
Locality of reference
(c)
Locality of coherence
(d)
None of the above
( )
Write through and write back are two strategies for maintaining:
(a)
Locality of reference
(b)
Collision
(c)
Coherence
(d)
All of the above
( )
29.
30.
110
(d)
31.
32.
33.
34.
35.
(b)
(d)
( )
( )
( )
Broad call is :
(a)
Write operation
(c)
Both a and b
( )
(b)
Read Operation
(d)
Neither a nor b
For a reservation table with n columns, the maximum forbidden latency (m):
(a)
M n
(b)
n n1
(c)
M n
(d)
n n1
( )
( )
36.
.......................is a shared memory system in which the access time varies with the
location of the memory word.
(a)
UMA
(b)
COMA
(c)
NUMA
(d)
All of the above
( )
37.
38.
39.
( )
Dynamic
None of the above
( )
( )
40.
111
The portion of the operating system kernel which handles the allocation and deallocation
of main memory to executing processes is called:
(a)
Memory Swapper
(b)
Memory Manager
(c)
Process Swapper
(d)
Process Manager
( )
Answer Key
1. (a)
2. (b)
11. (b)
12. (c)
21. (d)
22. (c)
31. (b)
32. (c)
3. (b)
13. (a)
23. (b)
33. (b)
4. (d)
14. (b)
24. (a)
34. (a)
5. (b)
15. (c)
25. (b)
35. (c)
6. (c)
16. (b)
26. (c)
36. (c)
______________
7. (d)
17. (a)
27. (c)
37. (c)
8. (a)
18. (a)
28. (b)
38. (b)
9. (a)
19. (c)
29. (d)
39. (a)
10. (a)
20. (b)
30. (b)
40. (d)
112
DESCRIPTIVE PART - II
Year 2007
Time allowed : 2 Hours
Maximum Marks : 30
Attempt any four questions out of the six. All questions carry 7 marks each.
Q.1
Q.2
Q.3
Describe :
(i)
Generations of electronic computers.
(ii)
Elements of moderns computer
Q.4
Q.5
Q.6
Describe the following terms associated with program partitioning and scheduling:
(a)
Grain Sizes and latency
(b)
Grain packing and scheduling
_________
113
OBJECTIVE PART- I
Year - 2006
Time allowed : One Hour
Maximum Marks : 20
The question paper contains 40 multiple choice questions with four choices and student will have
to pick the correct one. (Each carrying marks.).
1.
2.
( )
( )
3.
In UMA multiprocessor model, all the processors have unequal access time to all
memory words:
(a)
True
(b)
False
( )
4.
5.
6.
7.
Node diameter
Network diameter
( )
( )
( )
O( )
O (n)
( )
114
8.
(b)
Mechanical
(d)
and
electron
( )
9.
10.
Barrel shiffer is a:
(a)
Static connection network
(b)
Dynamic connection network
(c)
Storage device
(d)
Switching device
11.
12.
13.
14.
15.
16.
( )
(b)
(d)
( )
( )
( )
( )
( )
(c)
Bounds on MAL
115
(d)
Delay Speed
( )
17.
Processors that use multiphase clocks with a muck increase clock rate ranging from 100 to
500 MHz are:
(a)
VLIW
(b)
RISC
(c)
Memory interleaving
(d)
Super view
( )
18.
19.
( )
( )
The T3D is a :
(a)
SIMD machine
(b)
MIMD machine
(c)
Both a and b
(d)
None of the above
( )
( )
( )
20.
21.
22.
23.
24.
(b)
Segmentation
(d)
None of the above
116
(d)
25.
26.
27.
28.
None is true
( )
( )
( )
In future Bus + standards, the 64 bit address lines are multiplexed with:
(a)
Lower order 64 - bit data lines
(b)
High order 64-bit data lines
(c)
Lower order 32 bit data lines
(d)
Any one
( )
The time in cycles required between the issuing of two adjacent instruction is:
(a)
Instruction issue rate
(b)
Instruction pipeline cycle
(c)
Instruction operations latency
(d)
Instruction issue latency
( )
29.
30.
31.
(b)
(d)
Greedy cycles
Hit ration
If the number of links is 2NB, then this would be which kind of network:
(a)
Illiac mesh
(b)
2D Mesh
(c)
Both a and b
(d)
None of the above
( )
( )
32.
33.
................uses high order bits as the module address and low order bits as the word
address within each module:
(a)
(c)
34.
117
(b)
(d)
( )
Printed circuit on which many connectors are used to plus in functional boards?
(a)
I/O Buses
(b)
Hierarchical Buses
(c)
Cache
(d)
Backplane Buses
( )
35.
...............................is an operation that fetches the non zero elements of sparse vector
from the memory using indicates:
(a)
Masking
(b)
Gather
(c)
Scatter
(d)
Reduction
( )
36.
( )
37.
38.
( )
( )
39.
40.
(b)
(d)
Omega
All of the above
( )
Answer Key
1. (c)
2. (c)
3. (b)
4. (a)
5. (b)
6. (c)
7. (b)
8. (b)
9. (c)
10. (a)
11. (a)
21. (c)
31. (b)
12. (b)
22. (c)
32. (c)
13. (a)
23. (c)
33. (b)
14. (a)
24. (c)
34. (a)
15. (c)
25. (b)
35. (a)
16. (a)
26. (d)
36. (b)
17. (c)
27. (d)
37. (d)
18. (a)
28. (d)
38. (b)
19. (c)
29. (b)
39. (c)
20. (c)
30. (c)
40. (d)
118
DESCRIPTIVE PART - II
Year 2006
Time allowed : 2 Hours
Maximum Marks : 30
Attempt any four questions out of the six. All questions carry 7 marks each.
Q.1
Q.2
Explain the following terms associated with program partitioning and scheduling:
(a)
Grain sizes and latency
(b)
Grain packing and scheduling
Q.3
Explain all the factors on which the performance of interconnected network depends.
Discuss the following dynamic connection networks.
(a)
Digital buses
(b)
Omega network
Q.4
Describe:
(a)
Locality of reference
(b)
Write back caches
(c)
Write through caches
Q.5
Q.6
119
Key Terms
A
Access Time
Accumulator
Address Bus
ALU
ASCII (American
Standard Code for
Information Interchange)
ASRAM (Asynchronous
RAM)
Assembler
Associative Memory
B
Binary Operator
Bit (Binary Digit)
Boolean Algebra
Buffer
Bus
Byte
C
Cache
COMA
Control Bus
Chipset
Clock
Combinational
(combinatorial) Circuit
120
Control Unit
CPU (Central Processing
Unit)
Computer Architecture
Computer
Organization
D
Data Bus
Decoder
Distributed Memory
DMA (Direct Memory
Access)
DRAM (Dynamic RAM)
E
EEPROM (Electronically
Erasable Programmable
Read-Only Memory)
Error-Correcting Code
Error-Detecting Code
Exclusive-OR Gate
(Function)
F
Fetch Cycle
Fixed-Point
Representation System
Flip-Flop
Floating-Point
Representation System
G
Gate
GB (Gigabyte)
H
Hexadecimal Numbers
Hit Ratio
Hz (Hertz)
I
IC (Integrated Circuit /
Chip)
Instruction Format
Instruction Set
Interrupt
Interrupt Handler
ISA (Instruction Set
Architecture)
K
K (Kilo)
L
L1 (Level 1) Cache
L2 (Level 2) Cache
LAN (Local Area
Network)
Latency
Link Editor (Linker)
Local Variable
Locality (of Reference)
Principle
LRU (Least Recently
Used) Scheme
M
M (Mega)
Mantissa
121
122
Micro program
MIMD (Multiple
Instruction stream,
Multiple-Data stream)
MIPS (Million
Instruction Per Second)
MISD
Miss Rate
Motherboard
Multiprocessor
Micro-operation
Microprocessor
Multiprogramming
N
Nonvolatile memory
NUMA
O
Opcode (Operation
Code)
Operand
Operating System
P
Page
Page Fault
Page Frame
Parity Bit
Peer-to-Peer Network
Pipeline
PRAM
123
even parity).
Two or more computers directly linked and directly share the
data and hardware resources.
R
Radix (Base)
Register
S
SCSI (Small Computer
System Interface)
Seek Time
Segmentation
Sequential Circuit
Sign-Magnitude
Representation
SIMD (SingleInstruction Stream /
Single-Data Stream)
SIMD (SingleInstruction stream,
Multiple-Data stream)
(Or "data parallel")
SIMM (Single-Inline
Memory Module)
SISD (Single-Inline,
Single-Data Stream)
Snooping Cache Memory
Spatial Locality
SRAM (Static RAM)
Stack
124
Sum-of-Product
Superscalar Pipelining
Superscalar Processor
Synchronous Timing
System Bus
T
Tag
TB (Terabytes)
TLB (Translation
Lookaside buffer
Transistor
Truth table
Throughput
U
Unary Operator
Underflow
UMA
V
Virtual Address
Virtual Memory
Volatile Memory
W
Write Back
Write Through
125
RAM.
A cache structural design in which data is only written to main
memory when it is enforced out of the cache. Contrary to writethrough.
A cache structural design in which data is written to main
memory at the similar time as it is cached.
126
Websites
http://williamstallings.com/COA5e.html
http://iiusatech.com/murdocca/CAO/
http://courses.soe.ucsc.edu/courses/cmpe202
http://www.randelshofer.ch/fhw/gri/float.html#chapterfloatapplet
http://courses.soe.ucsc.edu/courses/cmpe110
http://booksite.mkp.com/9780123838728/
http://inst.eecs.berkeley.edu/~cs152/sp12/
http://www.randelshofer.ch/fhw/gri/float.html
http://www.britannica.com/EBchecked/topic/163278/digital-computer
http://williamstallings.com/COA/COA7e.html
http://csg.csail.mit.edu/6.823/lecnotes.html
http://www.cs.berkeley.edu/~pattrsn/252S01/
http://gs.fanshawec.ca/tlc/math270/
http://courses.cs.vt.edu/~csonline/NumberSystems/Lessons/BinaryNumb
ers/index.html
http://www.math.grin.edu/~stone/courses/fundamentals/IEEEreals.html
http://www.randelshofer.ch/fhw/gri/doubleapplet.html
http://www.intel.com/products/processor (for Intel Itanium
Processor)
http://www.ibm.com/servers/eserver/pserieslhardware/whitepaper
s/power/ppc - arch.html
http://www . i bm .com! servers/ eserver/pserics/hard ware/wh
itepapers/power/ppc arch 2.html
127
Bibliography
1.
2.
3.
4.
5.
6.
7.
128
8.
9.
10.
11.