Efficient FPGA-based Implementation of A Novel Dual Mode Spectrum Sensing Technique
Efficient FPGA-based Implementation of A Novel Dual Mode Spectrum Sensing Technique
Tamer Khattab
I.
I NTRODUCTION
*&&&
120
Known P
Unknown P, known k
Unknown P, unknown k
100
80
gt
60
II.
40
i = 0, 1, ..., 1
i = , 1, ..., N
(1)
2
P + 2
(4)
To estimate the sup in (3), one has to solve for the P value
that maximizes f (P ) over the given P region. The authors
dened k as the sample where l(y) shows a consistent positive
20
0
20
0
50
100
Time (samples)
150
200
2
y
(N i) Pmax
+ 2 ,
Pmax ,
2
y
2
y
2
y
2
(N
i) Pmin
P =
N i
Pmax + 2
+ 2 ,
2
y
Pmin ,
(N i) Pmin +2 ,
(5)
N
where y = i=1 y 2 [i]. A simulation result for our method is
shown in Fig.1. Its shown that the simulation results for our
approach is in agreement with the known k approach. Since the
algorithm is applied sequentially, a declaration of the existence
of the PUs signal can be done after any sample inside the N
samples. In other words, we do not have to wait until the
end of the N samples to declare the existence of the PUs
signal in case it happened during any of the N samples. After
the end of the N samples or the declaration of the existence
of the PUs signal, gi+1 is reset to zero. In other words, our
quickest detection algorithm reduces to the cumulative sum test
where the estimation of the decision statistic gi+1 is executed
recursively through:
gi+1
=
=
max max
it
N +1
l(y[i])
+ l(y[i + 1]), 0
i=1
(6)
P
2(P + 2 ) 2
and k2 =
1
2
(7)
P
ln P +
2 , which with some
Pf
P r {l(y[i]) > h | H0 }
C
1 2Q
(8)
(9)
2
where C = hk
k1 . Likewise, the probability of detection can
be given by:
C
Pd = 1 2Q
(10)
P + 2
If l(y[i]) > 0, gi+1 in (6)
gi+1
(11)
2
FXv+2j
(hn )P r[J = j]
Resources
Energy detection
Slices
985
6848
Flip ops
1471
10184
LUTs
1327
9532
Multipliers
IV.
Quickest detection
SNR WALL F OR QD VS . ED
j=0
(13)
where v = v1 + v2 is the summation of the degrees of freedom
and J = J1 + J2 and the the probability mass function of J
can be estimated as a twofold convolution of the corresponding
mass function of N B(i , i ), where i = (ki 1)/ki and
i = vi /2. Likewise the probability of detection can be written
as:
2
FXv+2j
(hn )P r[J = j].
(14)
Pd = 1
j=0
III.
N
i=1
H1
y 2 [i]
(15)
H0
=
=
Pd
=
=
Qu ( 2, )
(16)
(17)
0.9
0.9
0.8
Probability of detection
Probability of detection
0.8
0.7
0.6
0.5
0.4
0.7
0.6
0.5
0.4
0.3
0.3
u=4
u=8
u = 128
0.2
u=1
u=2
u=4
0.2
0.1
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
energy
SN Rwall
(19)
0.9
Probability of detection Pd
0.8
0.7
0.6
0.5
0.4
0.3
SNR = 3 dB
SNR = 0 dB
SNR = 3 dB
SNR = 6 dB
0.2
0.1
50
100
150
200
250
300
Number of samples
[3]
[4]
[5]
N = 8 Samples
N = 16 Samples
0.8
0.8
0.6
0.6
[6]
[7]
Pd
0.4
0.4
SNR = 3 dB
SNR=0 dB
SNR = 3 dB
SNR = 6 dB
0.2
0
0.1
0.2
0.3
SNR = 3 dB
SNR = 0 dB
SNR = 3 dB
SNR = 6 dB
0.2
0
0.4
0.1
0.2
0.3
[8]
0.4
N = 32 Samples
[9]
N = 64 Samples
0.8
0.8
0.6
0.6
[10]
Pd
0.4
SNR = 3 dB
SNR = 0 dB
SNR = 3 dB
SNR = 6 dB
0.2
0
0.4
0.1
0.2
0.3
SNR = 3 dB
SNR = 0 dB
SNR = 3 dB
SNR = 6 dB
0.2
0
0.4
0.1
0.2
0.3
N = 128 Samples
N = 256 Samples
0.8
0.8
0.6
0.6
[12]
[13]
Pd
0.4
SNR = 3 dB
SNR = 0 dB
SNR = 3 dB
SNR = 6 dB
0.2
0
0.1
0.2
[11]
0.4
0.3
0.4
0.4
SNR = 3 dB
SNR = 0 dB
SNR = 3 dB
SNR = 6 dB
0.2
0
0.1
Pf
0.2
0.3
0.4
[14]
Pf
C ONCLUSION
Our quickest detection algorithm is a technique that minimizes the sensing time which allows for a higher spectrum
efciency. But, it has a higher implementation complexity
than the conventional ED approach. We rst derived a closed
form expression for the probability of false alarm as well
the probability of detection for our our quickest detection
algorithm. We then numerically computed its SNR wall. We
then presented a new technique that compromises speed and
complexity based on FPGA implementation results. Our dual
mode spectrum sensing system uses ED as long as the SNR is
higher than the EDs SNR wall, which in our case is 3dB.
Once the received SNR is dropped below the EDs SNR
wall, our technique automatically switches to the quickest
detection algorithm that can operate efciently all the way to
SN R = 6dB. We also found out from our FPGA design,
[15]
[16]
[17]
[18]
[19]
[20]
[21]
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