ADC0820

8-Bit High Speed P Compatible A/D Converter with

Track/Hold Function
General Description

Features

By using a half-flash conversion technique, the 8-bit

ADC0820 CMOS A/D offers a 1.5 s conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bit ADC and
a least significant 4-bit ADC.

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The input to the ADC0820 is tracked and held by the input

sampling circuitry eliminating the need for an external
sample-and-hold for signals moving at less than 100 mV/s.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or I/O port
without the need for external interfacing logic.

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Key Specifications
j Resolution

8 Bits

j Conversion Time

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2.5 s Max (RD Mode)

1.5 s Max (WR-RD Mode)

j Low Power

75 mW Max

j Total Unadjusted

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Built-in track-and-hold function

No missing codes
No external clocking
Single supply 5 VDC
Easy interface to all microprocessors, or operates
stand-alone
Latched TRI-STATE output
Logic inputs and outputs meet both MOS and T2L
voltage level specifications
Operates ratiometrically or with any reference value
equal to or less than VCC
0V to 5V analog input voltage range with single 5V
supply
No zero or full-scale adjust required
Overflow output available for cascading
0.3" standard width 20-pin DIP
20-pin molded chip carrier package
20-pin small outline package
20-pin shrink small outline package (SSOP)

12 LSB and 1 LSB

Error

Connection and Functional Diagrams

Dual-In-Line, Small Outline
and SSOP Packages

00550101

Molded Chip Carrier

Package

00550133

Top View

2004 National Semiconductor Corporation

DS005501

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ADC0820 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function

March 2004

ADC0820

Connection and Functional Diagrams

(Continued)

00550102

FIGURE 1.

Ordering Information
Part Number

Total

Package

Unadjusted Error
ADC0820BCV
ADC0820BCWM

Range
V20A Molded Chip Carrier

12 LSB

ADC0820BCN

Temperature
0C to +70C

M20B Wide Body Small Outline

0C to +70C

N20A Molded DIP

0C to +70C

ADC0820CCJ

J20A Cerdip

40C to +85C

ADC0820CCWM

M20B Wide Body Small Outline

0C to +70C

M20B Wide Body Small Outline

40C to +85C

N20A Molded DIP

0C to +70C

ADC0820CIWM
ADC0820CCN

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1 LSB

Dual-In-Line Package (ceramic)

Surface Mount Package

Supply Voltage (VCC)

300C

Vapor Phase (60 sec.)

215C

Infrared (15 sec.)

220C

10V

Logic Control Inputs

0.2V to VCC +0.2V

Voltage at Other Inputs and Output

0.2V to VCC +0.2V

Storage Temperature Range

Operating Ratings

(Notes 1, 2)

Temperature Range

65C to +150C

TMINTATMAX

ADC0820CCJ

40CTA+85C

1 mA

ADC0820CIWM

40CTA+85C

Package Input Current (Note 5)

4 mA

ADC0820BCN, ADC0820CCN

ESD Susceptability (Note 9)

900V

ADC0820BCV

0CTA70C

ADC0820BCWM, ADC0820CCWM

0CTA70C

Package Dissipation at TA = 25C

875 mW

Input Current at Any Pin (Note 5)

Lead Temp. (Soldering, 10 sec.)

Dual-In-Line Package (plastic)

0CTA70C

VCC Range

260C

4.5V to 8V

Converter Characteristics
The following specifications apply for RD mode (pin 7=0), VCC=5V, VREF(+)=5V,and VREF()=GND unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA=Tj=25C.
Parameter

Conditions

ADC0820BCN, ADC0820CCN
ADC0820CCJ

ADC0820BCV, ADC0820BCWM

Limit
Units

ADC0820CCWM, ADC0820CIWM
Typ

Tested

Design

Typ

Tested

(Note 6)

Limit

Limit

(Note 6)

Limit

Limit

(Note 7)

(Note 8)

(Note 7)

(Note 8)

Resolution

Total Unadjusted

ADC0820BCN, BCWM

Error

ADC0820CCJ

(Note 3)

ADC0820CCN, CCWM, CIWM

Bits

12

12

LSB

1
1

1
1

LSB

LSB

ADC0820CCMSA
Minimum Reference

Design

LSB

2.3

1.00

2.3

1.2

2.3

2.3

5.3

VCC

VCC

VCC

GND

GND

GND

VREF()

VREF()

VREF()

VREF(+)

VREF(+)

VREF(+)

VCC+0.1

VCC+0.1

VCC+0.1

GND0.1

GND0.1

GND0.1

Resistance
Maximum
Reference
Resistance
Maximum VREF(+)
Input Voltage
Minimum VREF()
Input Voltage
Minimum VREF(+)
Input Voltage
Maximum VREF()
Input Voltage
Maximum VIN Input
Voltage
Minimum VIN Input
Voltage
Maximum Analog

CS =VCC

Input Leakage

VIN=VCC

0.3

Current

VIN=GND

0.3

Power Supply
Sensitivity

VCC=5V 5%

14

14

LSB

1/16

14

1/16

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ADC0820

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

ADC0820

DC Electrical Characteristics
The following specifications apply for VCC=5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other
limits TA=TJ=25C.
Parameter

Conditions

ADC0820BCN, ADC0820CCN
ADC0820CCJ

Limit
Units

ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM

Typ

Tested

Design

Typ

Limit

Limit

(Note 6)

(Note 7)

(Note 8)

(Note 6)
VIN(1), Logical 1

VCC=5.25V

Input Voltage
VIN(0), Logical 0

VCC=4.75V

Input Voltage

Tested

Design

Limit

Limit

(Note 7)

(Note 8)

CS , WR , RD

2.0

2.0

2.0

Mode

3.5

3.5

3.5

CS , WR , RD

0.8

0.8

0.8

1.5

1.5

Mode

IIN(1), Logical 1

VIN(1)=5V; CS , RD

Input Current

VIN(1)=5V; WR
VIN(1)=5V; Mode

1.5
0.005

IIN(0), Logical 0

VIN(0)=0V; CS , RD , WR ,

Input Current

Mode

VOUT(1), Logical 1

VCC=4.75V, IOUT=360 A;

Output Voltage

DB0DB7, OFL , INT

0.005

0.1

0.1

0.3

50

200

50

170

200

0.005

0.005

VCC=4.75V, IOUT=10 A;

2.4

2.8

2.4

4.5

4.6

4.5

0.4

0.34

0.4

V
A

DB0DB7, OFL , INT

VOUT(0), Logical 0

VCC=4.75V, IOUT=1.6 mA;

Output Voltage

DB0DB7, OFL , INT , RDY

IOUT, TRI-STATE

VOUT=5V; DB0DB7, RDY

0.1

0.1

0.3

Output Current

VOUT=0V; DB0DB7, RDY

0.1

0.1

0.3

ISOURCE, Output

VOUT=0V; DB0DB7, OFL

12

12

7.2

mA

Source Current

INT

4.0

5.3

4.0

mA

ISINK, Output Sink

VOUT=5V; DB0DB7, OFL ,

14

14

8.4

mA

Current

INT , RDY

ICC, Supply Current

CS =WR =RD =0

7.5

15

7.5

13

15

mA

AC Electrical Characteristics
The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF()=0V and TA=25C unless otherwise specified.
Parameter

Conditions

Typ

Tested

(Note 6)

Limit

Design
Limit

(Note 7)

(Note 8)

Units

tCRD, Conversion Time for RD Mode

Pin 7 = 0, Figure 2

1.6

2.5

tACC0, Access Time (Delay from

Pin 7 = 0, Figure 2

tCRD+20

tCRD+50

ns

1.52

Falling Edge of RD to Output Valid)

tCWR-RD, Conversion Time for

Pin 7 = VCC; tWR = 600 ns,

WR-RD Mode

tRD=600 ns; Figures 3, 4

tWR, Write Time

tRD, Read Time

Min

Pin 7 = VCC; Figures 3, 4

Max

(Note 4) See Graph

Min

Pin 7 = VCC; Figures 3, 4

600

ns

50

s
600

ns

(Note 4) See Graph

tACC1, Access Time (Delay from

Pin 7 = VCC, tRD < tI; Figure 3

Falling Edge of RD to Output Valid)

CL=15 pF

190

280

ns

CL=100 pF

210

320

ns

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(Continued)
The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF()=0V and TA=25C unless otherwise specified.
Parameter

tACC2, Access Time (Delay from

Falling Edge of RD to Output Valid)

Conditions

Typ

Tested

(Note 6)

Limit

Design
Limit

(Note 7)

(Note 8)

Units

Pin 7 = VCC, tRD > tI; Figure 4

CL=15 pF

70

120

ns

CL=100 pF

90

150

ns

tACC3, Access Time (Delay from

Rising Edge of RDY to Output
Valid)

RPULLUP = 1k and CL = 15 pF

30

tI, Internal Comparison Time

Pin 7=VCC; Figures 4, 5

800

1300

ns

100

200

ns

tI

ns

ns

CL=50 pF
t1H, t0H, TRI-STATE Control

RL=1k, CL=10 pF

(Delay from Rising Edge of RD to

Hi-Z State)
tINTL, Delay from Rising Edge of

Pin 7 = VCC, CL= 50 pF

WR to Falling Edge of INT

tRD > tI; Figure 4

tRD < tI; Figure 3

tRD+200

tRD+290

ns

tINTH, Delay from Rising Edge of

Figures 2, 3, 4

125

225

ns

RD to Rising Edge of INT

CL=50 pFc

tINTHWR, Delay from Rising Edge of

Figure 5, CL=50 pF

175

270

ns
ns

WR to Rising Edge of INT

tRDY, Delay from CS to RDY

Figure 2, CL=50 pF, Pin 7 =0

50

100

tID, Delay from INT to Output Valid

Figure 5

20

50

ns

tRI, Delay from RD to INT

Pin 7=VCC, tRD < tI

200

290

ns

500

ns

Figure 3
tP, Delay from End of Conversion

Figures 2, 3, 4, 5

to Next Conversion

(Note 4) See Graph

Slew Rate, Tracking

0.1

CVIN, Analog Input Capacitance

45

V/s
pF

COUT, Logic Output Capacitance

pF

CIN, Logic Input Capacitance

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Accuracy vs. tWR and Accuracy vs. tRD graphs.
Note 5: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < Vor VIN > V+) the absolute value of current at that pin should be limited
to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.
Note 6: Typicals are at 25C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharged through a 1.5 k resistor.

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ADC0820

AC Electrical Characteristics

ADC0820

TRI-STATE Test Circuits and Waveforms

t1H

00550103
00550104

tr=20 ns

t0H

00550106

tr=20 ns
00550105

Timing Diagrams

00550107

Note: On power-up the state of INT can be high or low.

FIGURE 2. RD Mode (Pin 7 is Low)

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ADC0820

Timing Diagrams

(Continued)

00550108

FIGURE 3. WR-RD Mode (Pin 7 is High and tRD < tI)

00550109

FIGURE 4. WR-RD Mode (Pin 7 is High and tRD > tI)

00550110

FIGURE 5. WR-RD Mode (Pin 7 is High)

Stand-Alone Operation

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ADC0820

Typical Performance Characteristics

Logic Input Threshold Voltage vs. Supply Voltage

Conversion Time (RD Mode) vs. Temperature

00550134

00550135

Power Supply Current vs. Temperature

(not including reference ladder)

Accuracy vs. tWR

00550137

00550136

Accuracy vs. tRD

Accuracy vs. tp

00550139

00550138

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(Continued)

Accuracy vs. VREF [VREF=VREF(+)-VREF(-)]

tI, Internal Time Delay vs. Temperature

00550140

00550141

Output Current vs. Temperature

00550142

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ADC0820

Typical Performance Characteristics

ADC0820

Description of Pin Functions

Pin Name

Pin Name

Function

VIN

Analog input; range =GNDVINVCC

DB0

TRI-STATE data output bit 0 (LSB)

DB1

TRI-STATE data output bit 1

DB2

TRI-STATE data output bit 2

DB3

TRI-STATE data output bit 3

WR
/RDY

WR-RD Mode

INT

INT going low indicates that the

conversion is completed and the data
result is in the output latch. INT will go
low, 800 ns (the preset internal time out,
tI) after the rising edge of WR (see Figure
4 ); or INT will go low after the falling
edge of RD , if RD goes low prior to the
800 ns time out (see Figure 3). INT is
reset by the rising edge of RD or CS (see
Figures 3, 4 ).

WR: With CS low, the conversion is

started on the falling edge of WR.
Approximately 800 ns (the preset internal
time out, tI) after the WR rising edge, the
result of the conversion will be strobed
into the output latch, provided that RD
does not occur prior to this time out (see
Figures 3, 4 ).

RD Mode
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT is reset by
the rising edge of RD or CS (see Figure
2 ).

RD Mode
RDY: This is an open drain output (no
internal pull-up device). RDY will go low
after the falling edge of CS; RDY will go
TRI-STATE when the result of the
conversion is strobed into the output latch.
It is used to simplify the interface to a
microprocessor system (see Figure 2 ).
7

Mode

RD

10 GND

Ground

11 VREF()

The bottom of resistor ladder, voltage

range: GNDVREF()VREF(+) (Note 5)

12 VREF(+)

The top of resistor ladder, voltage range:

VREF()VREF(+)VCC (Note 5)

13 CS

Mode: Mode selection input it is

internally tied to GND through a 50 A
current source.

CS must be low in order for the RD or

WR to be recognized by the converter.

14 DB4

TRI-STATE data output bit 4

15 DB5

TRI-STATE data output bit 5

RD Mode: When mode is low

16 DB6

TRI-STATE data output bit 6

WR-RD Mode: When mode is high

17 DB7

TRI-STATE data output bit 7 (MSB)

WR-RD Mode

18 OFL

Overflow output If the analog input is

higher than the VREF(+), OFL will be low
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 10-bit). This output is always
active and does not go into TRI-STATE as
DB0DB7 do.

With CS low, the TRI-STATE data outputs

(DB0-DB7) will be activated when RD
goes low (see Figure 5 ). RD can also be
used to increase the speed of the
converter by reading data prior to the
preset internal time out (tI, 800 ns). If this
is done, the data result transferred to
output latch is latched after the falling
edge of the RD (see Figures 3, 4 ).
RD Mode

19 NC

No connection

20 VCC

Power supply voltage

1.0 Functional Description

With CS low, the conversion will start with

RD going low, also RD will enable the
TRI-STATE data outputs at the completion
of the conversion. RDY going TRI-STATE
and INT going low indicates the
completion of the conversion (see Figure
2 ).

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Function
WR-RD Mode

1.1 GENERAL OPERATION

The ADC0820 uses two 4-bit flash A/D converters to make
an 8-bit measurement (Figure 1 ). Each flash ADC is made
up of 15 comparators which compare the unknown input to a
reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the A/D as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
10

ADC0820

1.0 Functional Description

(Continued)

which most closely approximates the analog input. In addition, the sampled-data comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.
1.2 THE SAMPLED-DATA COMPARATOR
Each comparator in the ADC0820 consists of a CMOS inverter with a capacitively coupled input (Figures 6, 7 ). Analog switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverters input and output. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the comparator, and another for making the comparison.
In the first cycle, one input switch and the inverters feedback
switch (Figure 6 ) are closed. In this interval, C is charged to
the connected input (V1) less the inverters bias voltage (VB,
approximately 1.2V). In the second cycle (Figure 7 ), these
two switches are opened and the other (V2) inputs switch is
closed. The input capacitor now subtracts its stored voltage
from the second input and the difference is amplified by the
inverters open loop gain. The inverters input (VB') becomes

00550112

VO = VB
V on C = V1VB
CS = stray input node capacitor
VB = inverter input bias voltage

Zeroing Phase
FIGURE 6. Sampled-Data Comparator

00550113

and the output will go high or low depending on the sign of

VB'VB.
The actual circuitry used in the ADC0820 is a simple but
important expansion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (Figure 8 ), the scheme can be expanded to make dual differential comparisons. In this circuit,
the feedback switch and one input switch on each capacitor
(Z switches) are closed in the zeroing cycle. A comparison is
then made by connecting the second input on each capacitor
and opening all of the other switches (S switches). The
change in voltage at the inverters input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.

Compare Phase
FIGURE 7. Sampled-Data Comparator

00550145

00550114

FIGURE 8. ADC0820 Comparator (from MS Flash ADC)

input overrange. These two sets of comparators operate
alternately, with one group in its zeroing cycle while the other
is comparing.

1.3 ARCHITECTURE
In the ADC0820, one bank of 15 comparators is used in each
4-bit flash A/D converter (Figure 12 ). The MS (most significant) flash ADC also has one additional comparator to detect

When a typical conversion is started, the WR line is brought

low. At this instant the MS comparators go from zeroing to
11

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ADC0820

1.0 Functional Description

data which relate to interface timing. If an interrupt driven

scheme is desired, the user can wait for INT to go low before
reading the conversion result (Figure 10 ). INT will typically
go low 800 ns after WRs rising edge. However, if a shorter
conversion time is desired, the processor need not wait for
INT and can exercise a read after only 600 ns (Figure 9 ). If
this is done, INT will immediately go low and data will appear
at the outputs.

(Continued)

comparison mode (Figure 11 ). When WR is returned high

after at least 600 ns, the output from the first set of comparators (the first flash) is decoded and latched. At this point the
two 4-bit converters change modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600
ns later, the RD line may be pulled low to latch the lower 4
data bits and finish the 8-bit conversion. When RD goes low,
the flash A/Ds change state once again in preparation for the
next conversion.
Figure 11 also outlines how the converters interface timing
relates to its analog input (VIN). In WR-RD mode, VIN is
measured while WR is low. In RD mode, sampling occurs
during the first 800 ns of RD. Because of the input connections to the ADC0820s LS and MS comparators, the converter has the ability to sample VIN at one instant (Section
2.4), despite the fact that two separate 4-bit conversions are
being done. More specifically, when WR is low the MS flash
is in compare mode (connected to VIN), and the LS flash is in
zero mode (also connected to VIN). Therefore both flash
ADCs sample VIN at the same time.

00550117

1.4 DIGITAL INTERFACE

FIGURE 9. WR-RD Mode (Pin 7 is High and tRD < tI)

The ADC0820 has two basic interface modes which are

selected by strapping the MODE pin high or low.
RD Mode
With the MODE pin grounded, the converter is set to Read
mode. In this configuration, a complete conversion is done
by pulling RD low until output data appears. An INT line is
provided which goes low at the end of the conversion as well
as a RDY output which can be used to signal a processor
that the converter is busy or can also serve as a system
Transfer Acknowledge signal.
RD Mode (Pin 7 is Low)

00550118

FIGURE 10. WR-RD Mode (Pin 7 is High and tRD > tI)
Stand-Alone
For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WRs rising
edge.
WR-RD Mode (Pin 7 is High) Stand-Alone Operation
00550116

When in RD mode, the comparator phases are internally

triggered. At the falling edge of RD, the MS flash converter
goes from zero to compare mode and the LS ADCs comparators enter their zero cycle. After 800 ns, data from the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recovered.
WR then RD Mode
With the MODE pin tied high, the A/D will be set up for the
WR-RD mode. Here, a conversion is started with the WR
input; however, there are two options for reading the output

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00550119

12

ADC0820

1.0 Functional Description

(Continued)

00550120

Note: MS means most significant

LS means least significant

FIGURE 11. Operating Sequence (WR-RD Mode)

Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (tP, Figures 2, 3, 4, 5 ) is 500 ns.

OTHER INTERFACE CONSIDERATIONS

In order to maintain conversion accuracy, WR has a maximum width spec of 50 s. When the MS flash ADCs
sampled-data comparators (Section 1.2) are in comparison
mode (WR is low), the input capacitors (C, Figure 8 ) must
hold their charge. Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for too
long.

13

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ADC0820

Detailed Block Diagram

00550115

FIGURE 12.

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14

2.1 REFERENCE AND INPUT

The two VREF inputs of the ADC0820 are fully differential and
define the zero to full-scale input range of the A to D converter. This allows the designer to easily vary the span of the
analog input since this range will be equivalent to the voltage
difference between VIN(+) and VIN(). By reducing
VREF(VREF=VREF(+)VREF()) to less than 5V, the sensitivity
of the converter can be increased (i.e., if VREF=2V then 1
LSB=7.8 mV). The input/reference arrangement also facilitates ratiometric operation and in many cases the chip power
supply can be used for transducer power as well as the VREF
source.
This reference flexibility lets the input span not only be varied
but also offset from zero. The voltage at VREF() sets the
input level which produces a digital output of all zeroes.
Though VIN is not itself differential, the reference design
affords nearly differential-input capability for most measurement applications. Figure 13 shows some of the configurations that are possible.

The input capacitors must charge to the input voltage

through the on resistance of the analog switches (about 5 k
to 10 k). In addition, about 12 pF of input stray capacitance
must also be charged. For large source resistances, the
analog input can be modeled as an RC network as shown in
Figure 15. As RS increases, it will take longer for the input
capacitance to charge.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is the
time that WR is low. Since other factors force this time to be
at least 600 ns, input time constants of 100 ns can be
accommodated without special consideration. Typical total
input capacitance values of 45 pF allow RS to be 1.5 k
without lengthening WR to give VIN more time to settle.

2.2 INPUT CURRENT

Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The A/Ds sampled-data comparators take varying amounts of input current depending on
which cycle the conversion is in.

External Reference 2.5V Full-Scale

Power Supply as Reference

Input Not Referred to GND

00550122

00550121

00550123

FIGURE 13. Analog Input Options

15

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ADC0820

The equivalent input circuit of the ADC0820 is shown in

Figure 14. When a conversion starts (WR low, WR-RD
mode), all input switches close, connecting VIN to thirty-one
1 pF capacitors. Although the two 4-bit flash circuits are not
both in their compare cycle at the same time, VIN still sees all
input capacitors at once. This is because the MS flash
converter is connected to the input during its compare interval and the LS flash is connected to the input during its
zeroing phase (Section 1.3). In other words, the LS ADC
uses VIN as its zero-phase input.

2.0 Analog Considerations

ADC0820

2.0 Analog Considerations

occur. The comparators outputs are not latched while WR is

low, so at least 600 ns will be provided to charge the ADCs
input capacitance. It is therefore not necessary to filter out
these transients by putting an external cap on the VIN terminal.

(Continued)

2.4 INHERENT SAMPLE-HOLD

Another benefit of the ADC0820s input mechanism is its
ability to measure a variety of high speed signals without the
help of an external sample-and-hold. In a conventional SAR
type converter, regardless of its speed, the input must remain at least 12 LSB stable throughout the conversion process if full accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally
sampled, and held stationary during the conversion.
Sampled-data comparators, by nature of their input switching, already accomplish this function to a large degree (Section 1.2). Although the conversion time for the ADC0820 is
1.5 s, the time through which VIN must be 12 LSB stable is
much smaller. Since the MS flash ADC uses VIN as its
compare input and the LS ADC uses VIN as its zero input,
the ADC0820 only samples VIN when WR is low (Sections
1.3 and 2.2). Even though the two flashes are not done
simultaneously, the analog signal is measured at one instant.
The value of VIN approximately 100 ns after the rising edge
of WR (100 ns due to internal logic prop delay) will be the
measured value.

00550124

FIGURE 14.

Input signals with slew rates typically below 100 mV/s can
be converted without error. However, because of the input
time constants, and charge injection through the opened
comparator input switches, faster signals may cause errors.
Still, the ADC0820s loss in accuracy for a given increase in
signal slope is far less than what would be witnessed in a
conventional successive approximation device. An SAR type
converter with a conversion time as fast as 1 s would still
not be able to measure a 5V 1 kHz sine wave without the aid
of an external sample-and-hold. The ADC0820, with no such
help, can typically measure 5V, 7 kHz waveforms.

00550125

FIGURE 15.
2.3 INPUT FILTERING
It should be made clear that transients in the analog input
signal, caused by charging current flowing into VIN, will not
degrade the A/Ds performance in most cases. In effect the
ADC0820 does not look at the input when these transients

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16

ADC0820

3.0 Typical Applications

8-Bit Resolution Configuration

00550126

9-Bit Resolution Configuration

00550127

17

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ADC0820

3.0 Typical Applications

(Continued)

Multiple Input Channels

Telecom A/D Converter

00550129
00550128

VIN=3 kHz max 4VP

No track-and-hold needed
Low power consumption

8-Bit 2-Quadrant Analog Multiplier

00550130

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ADC0820

3.0 Typical Applications

(Continued)
Fast Infinite Sample-and-Hold

00550131

19

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ADC0820
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3.0 Typical Applications

(Continued)
Digital Waveform Recorde

20
00550132

ADC0820

Physical Dimensions

inches (millimeters) unless otherwise noted

Hermetic Dual-In-Line Package (J)

Order Number ADC0820CCJ
NS Package Number J20A

SO Package (M)
Order Number ADC0820BCWM, ADC0820CCWM or ADC0820CIWM
NS Package Number M20B

21

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ADC0820

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number ADC0820BCN or ADC0820CCN
NS Package Number N20A

Molded Chip Carrier Package (V)

Order Number ADC0820BCV
NS Package Number V20A

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22

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whose failure to perform when properly used in
accordance with instructions for use provided in the
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significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform
can be reasonably expected to cause the failure of
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ADC0820 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function

Notes