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(Pal) Programmable Array Logic

Programmable Array Logic (PAL) is a type of Programmable Logic Device (PLD) that consists of an AND gate array followed by an OR gate array. The AND gate array is programmable using fuses to determine the logic, while the OR gate array has a fixed logic. This makes PALs less flexible than Programmable Logic Arrays (PLAs) for programming, but also less expensive. A PAL has m inputs, p product terms from the AND gate array, and n outputs from the OR gate array to realize sum-of-products logic.

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849 views

(Pal) Programmable Array Logic

Programmable Array Logic (PAL) is a type of Programmable Logic Device (PLD) that consists of an AND gate array followed by an OR gate array. The AND gate array is programmable using fuses to determine the logic, while the OR gate array has a fixed logic. This makes PALs less flexible than Programmable Logic Arrays (PLAs) for programming, but also less expensive. A PAL has m inputs, p product terms from the AND gate array, and n outputs from the OR gate array to realize sum-of-products logic.

Uploaded by

anshu3012
Copyright
© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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Programmable Array Logic (PAL)

Programmable Array Logic (PAL) is a type of Programmable Logic


Device (PLD) used to realize a particular logical function. PALs
comprise of an AND gate array followed by an OR gate array as
shown by figure.

Function
It is to be noted that here only the AND gate array is
programmable unlike the OR gate array which has a fixed
logic.
This is because here the inputs are fed to the AND gates
through fuses, which act as programmable links.

Programmable-AND and fixed-OR structure of PALs make


them less flexible from programming point of view when
compared with Programmable Logic Arrays (PLAs).

However due to the same reason PALs are less expensive


than PLAs.

The second figure shows the internal structure of a PAL with


m inputs and n outputs.
Each of the input line is showed to pass through the buffers
and/or inverters. All of these inputs are connected each and
every AND gate present in the PAL.

Further this connection matrix is programmable which lets


the user to decide the connection between the input lines
and the AND gates.

Internal Diagram of the circuit


1. This means that one has to connect each and every input
line to either single or multiple AND gate(s), depending on
the logic.
2. Further the outputs of the AND gate array are fed as inputs
to the OR gates via hard-wired connections, which are fixed
and hence unalterable.
3. Moreover it is to be noted that the output of every AND gate
is
not
fed
to
everyORgate.

4. For example, OR gate 1 (O1) has multiple inputs including


the outputs of AND gate 1 (A 1), AND gate 2 (A2) and AND
gate n (An). However OR gate m (O m) has only two inputs
which are the outputs of AND gates A 1 and Ao. As these
connections are fixed, one has to pay attention while
establishing the connection to realize the logical 'or'
functionality of the product-terms obtained as outputs from
AND gate array.
5. Finally there are n output lines of the OR gate array resulting
in n output PAL realizing the required logic in sum-ofproducts (SOP) form. The PAL shown in Figure 2 can be
addressed as m-input, p-product-term, n-output PAL.
6. However it is to be noted that the number of inputs, AND
gates and OR gates present in the PAL are all independent
i.e. one PAL can have 3 inputs, 8 AND gates and 4 outputs
(and thus 4 OR gates).

Real Life Applications


Further device feeders and gang programmers can be used in order
to program more than one PAL.
Common programming languages in use include
1.PAL assembler (PALASM)
2. Compiler for Universal Programmable Logic (CUPL)
3. Advanced Boolean Expression Language (ABEL).

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