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Sequential Logic

This document discusses sequential logic and synchronous digital circuits. It begins by describing state-holding elements like latches and D flip-flops, including their operation and timing. Examples are given of sequential circuits like shift registers and counters built using these basic elements. The document emphasizes that synchronous digital design relies on a global clock to synchronize state updates in flip-flops. Timing considerations like setup, hold, propagation and clock skew must be accounted for in circuit design.

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jake
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© © All Rights Reserved
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44 views

Sequential Logic

This document discusses sequential logic and synchronous digital circuits. It begins by describing state-holding elements like latches and D flip-flops, including their operation and timing. Examples are given of sequential circuits like shift registers and counters built using these basic elements. The document emphasizes that synchronous digital design relies on a global clock to synchronize state updates in flip-flops. Timing considerations like setup, hold, propagation and clock skew must be accounted for in circuit design.

Uploaded by

jake
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 56

Fundamentals of Computer Systems

Sequential Logic

Martha A. Kim
Columbia University

1 / 22

State-Holding Elements
Latches
D Flip-Flop
Resets (Sync and Async)
The Synchronous Digital Logic Paradigm
Sequential Circuits
Shift Registers
Counters
Timing in Synchronous Circuits

2 / 22

Bistable Elements

Q
Q

Q
Q

Equivalent circuits; right is more traditional.


Two stable states:
0

3 / 22

RS Latch
R

Q
R Q
S Q
Q

0
0
1
1

0
1
0
1

4 / 22

RS Latch
0

Q
R Q
S Q

0
0
1
1

0
1
0
1

Set (Q = 1)

4 / 22

RS Latch
1

Q
R Q
S Q

0
0
1
1

0
1
0
1

1
0

0
1

Set (Q = 1)
Reset (Q = 0)

4 / 22

RS Latch
(0 + Q) = Q
0

Q
R Q
S Q

(0 + Q) = Q

0
0
1
1

0
1
0
1

Q
1
0

Q
0
1

Hold previous value


Set (Q = 1)
Reset (Q = 0)

4 / 22

RS Latch
1

Q
R Q
S Q

0
0
1
1

0
1
0
1

Q
1
0
0

Q
0
1
0

Hold previous value


Set (Q = 1)
Reset (Q = 0)
Bad. Do not use.

4 / 22

R S Latch
S

Q
S Q
R Q
Q

0
0
1
1

0
1
0
1

1
0
1
Q

1
1
0
Q

Bad. Do not use.


Reset (Q = 0)
Set (Q = 1)
Hold previous value

5 / 22

D Latch
D
Q
D Q
C
C Q
Q

0
1
1

X
0
1

Q
0
1

Q
1
0

6 / 22

A Challenge: Build a traffic light controller


Want the lights to cycle green-yellow-red.

D Q
C

D Q
C

D Q
C

Does this work?

7 / 22

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9 / 22

Positive-Edge-Triggered D Flip-Flop
Master
D
CM

D Q
C

Slave
D
CS

D Q
C

D Q

C
D
CM

transparent

D0
CS

opaque

10 / 22

Positive-Edge-Triggered D Flip-Flop
Master
D
CM

D Q
C

Slave
D
CS

D Q
C

D Q

C
D
CM

transparent

D0
CS

opaque

10 / 22

Positive-Edge-Triggered D Flip-Flop
Master
D
CM

D Q
C

Slave
D
CS

D Q
C

D Q

C
D
CM

transparent

opaque

D0
CS

opaque

transparent

10 / 22

Positive-Edge-Triggered D Flip-Flop
Master
D
CM

D Q
C

Slave
D
CS

D Q
C

D Q

C
D
CM

transparent

opaque

D0
CS

opaque

transparent

10 / 22

Positive-Edge-Triggered D Flip-Flop
Master
D
CM

D Q
C

Slave
D
CS

D Q
C

D Q

C
D
CM

transparent

opaque

transparent

transparent

opaque

D0
CS

opaque

10 / 22

Positive-Edge-Triggered D Flip-Flop
Master
D
CM

D Q
C

Slave
D
CS

D Q
C

D Q

C
D
CM

transparent

opaque

transparent

opaque

transparent

opaque

transparent

D0
CS

opaque

10 / 22

The Traffic Light Controller: A second try


Lets try this again with D flip-flops.

D Q

D Q

D Q

CLK

CLK
R
Y
G
11 / 22

The Traffic Light Controller: A second try


Lets try this again with D flip-flops.

D Q

D Q

D Q

CLK

CLK
R
Y
G
11 / 22

The Traffic Light Controller: A second try


Lets try this again with D flip-flops.

D Q

D Q

D Q

CLK

CLK
R
Y
G
11 / 22

The Traffic Light Controller: A second try


Lets try this again with D flip-flops.

D Q

D Q

D Q

CLK

CLK
R
Y
G
11 / 22

The Traffic Light Controller: A second try


Lets try this again with D flip-flops.

D Q

D Q

D Q

CLK

CLK
R
Y
G
11 / 22

The Traffic Light Controller with Reset

RESET

D Q

D Q

D Q

CLK

CLK
RESET
R
Y
G
12 / 22

The Traffic Light Controller with Reset

RESET

D Q

D Q

D Q

CLK

CLK
RESET
R
Y
G
12 / 22

The Traffic Light Controller with Reset

RESET

D Q

D Q

D Q

CLK

CLK
RESET
R
Y
G
12 / 22

The Traffic Light Controller with Reset

RESET

D Q

D Q

D Q

CLK

CLK
RESET
R
Y
G
12 / 22

The Traffic Light Controller with Reset

RESET

D Q

D Q

D Q

CLK

CLK
RESET
R
Y
G
12 / 22

The Traffic Light Controller with Reset

RESET

D Q

D Q

D Q

CLK

CLK
RESET
R
Y
G
12 / 22

D Flip-Flop with Enable

0
1

D Q

E
C

D
D Q

0
1

0
1
1
X
X

X
0
1
X
X

Q
0
1
Q
Q

E
C

Whats wrong with this


solution?

13 / 22

Asynchronous Preset/Clear

PRE
D Q
CLR

CLK
D
PRE
CLR
Q

14 / 22

The Traffic Light Controller w/ Async. Reset


RESET

PRE
D Q

CLK
CLR

PRE
D Q

CLR

PRE
D Q

CLR

15 / 22

The Synchronous Digital Logic Paradigm

Gates and D
flip-flops only
Each flip-flop
driven by the
same clock
Every cyclic
path contains
at least one
flip-flop

OUTPUTS

INPUTS

STATE

CL

CLOCK

NEXT STATE

16 / 22

Cool Sequential Circuits: Shift Registers


A
Q0
A

CLK

Q1

Q2
Q3

0
1
1
0
1
0
0
0
1
0

Q0 Q1 Q2 Q3
X
0
1
1
0
1
0
0
0
1

X
X
0
1
1
0
1
0
0
0

X
X
X
0
1
1
0
1
0
0

X
X
X
X
0
1
1
0
1
0

17 / 22

Universal Shift Register


L
D0

D1

D2

3
2
1
0

Q0

3
2
1
0

Q1

3
2
1
0

Q2

3
2
1
0

D3
R
S1

Q3

S1

S0

Q3

Q2

Q1

Q0

0
0
1
1

0
1
0
1

R
D3
Q3
Q2

Q3
D2
Q2
Q1

Q2
D1
Q1
Q0

Q1
D0
Q0
L

S1

S0

Operation

0
0
1
1

0
1
0
1

Shift right
Load
Hold
Shift left

CLK
S0
18 / 22

Cool Sequential Circuits: Counters

Cycle through sequences of numbers, e.g.,


00

01

10

11

19 / 22

Flip-Flop Timing
Setup Time: Time before
the clock edge after which
the data may not change
tsu
CLK
D
Q

20 / 22

Flip-Flop Timing
Setup Time: Time before
the clock edge after which
the data may not change
tsu

Hold Time: Time after the


clock edge after which
the data may change

th

CLK
D
Q

20 / 22

Flip-Flop Timing
Setup Time: Time before
the clock edge after which
the data may not change
tsu

Hold Time: Time after the


clock edge after which
the data may change

th

CLK
D
Q
Minimum Propagation
Delay: Time from
clock edge to when Q
might start changing

tp(min)

20 / 22

Flip-Flop Timing
Setup Time: Time before
the clock edge after which
the data may not change
tsu

Hold Time: Time after the


clock edge after which
the data may change

th

CLK
D
Q
Minimum Propagation
Delay: Time from
clock edge to when Q
might start changing

tp(min)
tp(max)

Maximum
Propagation Delay:
Time from clock edge
to when Q
guaranteed stable

20 / 22

Timing in Synchronous Circuits

CL

CLK

tc
CLK
Q
D

tc : Clock period. E.g., 10 ns for a 100 MHz clock


21 / 22

Timing in Synchronous Circuits

CL

CLK

Sufficient Hold Time?


tp(min,FF)

tp(min,CL)

CLK
Q
D

Hold time constraint: how soon after the clock edge is


D liable to start changing?
Min. FF delay + min. logic delay
21 / 22

Timing in Synchronous Circuits

CL

CLK

tp(max,FF)

Sufficient Setup Time?


tp(max,CL)

CLK
Q
D

Setup time constraint: when before the clock edge is D


guaranteed to have stabilized?
Max. FF delay + max. logic delay
21 / 22

Clock Skew: What Really Happens

Q
CLK1

CL

D
CLK2

CLK

Sufficient Hold Time?


tskew
CLK1
CLK2
Q
D
tp(min,FF)

tp(min,CL)

CLK2 arrives late, creating potential hold time violation


22 / 22

Clock Skew: What Really Happens

Q
CLK1

CL

CLK2

CLK

Sufficient Setup Time?


tskew
CLK1
CLK2
Q
D
tp(max,FF)

tp(max,CL)

CLK2 arrives early, creating potential setup time


violation
22 / 22

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