DATE: 1/08/16

EXP NO.: 1

LOGIC GATES
AIM: To design basic logic gates
TOOL USED: Xilinx Vivado, Digilent Nexys 4.
CODE:
module lab1_1basicgates(
input A,
input B,
output C,
output D,
output E,
output F,
output G,
output H
);
assign C=A&B;
assign D=A|B;
assign E=~(A&B);
assign F=~(A|B);
assign G=A^B;
assign H=~(A^B);
endmodule

TESTBENCH:
module lab1_1basicgates_tb( );
reg A,B;
wire C,D,E,F,G,H;
lab1_1basicgates dut(.A(A),.B(B),.C(C),.D(D),.E(E),.F(F),.G(G),.H(H));
initial
begin
A=0;B=0;
#10 A=0;B=1;
#10 A=1;B=0;
#10 A=1;B=1;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

DATE: 08/08/16
EXP NO.: 2

ADDERS
AIM: To design and realise the adders
TOOLS USED: Xilinx vivado , Digital Nexys 4.
2.1) HALF ADDER:
Code:
module adder(
input a,b,
output s,cout
);
assign s=a^b;
assign cout=a&b;
end module
TESTBENCH:
module HA_TB( );
reg a,b;
wire s,cout;
HA T1 (.a(a),.b(b),.s(s),.cout(cout));
initial
begin
a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION RESULT:

2.2) 1-BIT FULL ADDER:

Code:
module FA(
input a,b,ci,
output s,co
);
assign s=((a^b)^ci);
assign co=(((a&b)|(b&ci))|(a&ci));
endmodule

TESTBENCH:
module FA_TB( );
reg a,b,ci;
wire s,co;
FA T1 (.a(a),.b(b),.ci(ci),.s(s),.co(co));
initial
begin
a=0;b=0;ci=0;
#10 a=0;b=0;ci=1;
#10 a=0;b=1;ci=0;
#10 a=0;b=1;ci=1;
#10 a=1;b=0;ci=0;
#10 a=1;b=0;ci=1;
#10 a=1;b=1;ci=0;
#10 a=1;b=1;ci=1;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

2.3) 4-BIT FULL ADDER

Code:
module FA_4bit(
input [3:0] a,b,
output [3:0] s,
input ci,
output co );
wire c1,c2,c3;
FA_1bit FA0 (.a(a[0]),.b(b[0]),.ci(ci),.s(s[0]),.co(c1));
FA_1bit FA1 (.a(a[1]),.b(b[1]),.ci(c1),.s(s[1]),.co(c2));
FA_1bit FA2 (.a(a[2]),.b(b[2]),.ci(c2),.s(s[2]),.co(c3));
FA_1bit FA3 (.a(a[3]),.b(b[3]),.ci(c3),.s(s[3]),.co(co));
endmodule

TESTBENCH:
module FA_4bit_TB( );
reg [3:0]a,b;
reg ci;
wire [3:0] s;
wire co;
FA_4bit T1(.a(a),.b(b),.ci(ci),.s(s),.co(co));
initial
begin
a=4'b1100;b=4'b1101;ci=0;
#10 a=4'b1110;b=4'b0101;ci=0;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION RESULT:

DATE:

EXP NO.: 3

COMBINATIONAL CIRCUITS
3.1 ENCODER
AIM: To design 8 to 3 encoder
TOOL USED: Xilinx Vivado, Digilent Nexys 4
CODE:
module encoder_ifelse(
input [7:0] data,
output [2:0] code
);
reg [2:0] code;
always@(data)
begin
if(data==8'b00000001) code=3'b000;
else if(data==8'b00000010) code=3'b001;
else if(data==8'b00000100) code=3'b010;
else if(data==8'b00001000) code=3'b011;
else if(data==8'b00010000) code=3'b100;
else if(data==8'b00100000) code=3'b101;
else if(data==8'b01000000) code=3'b110;
else if(data==8'b10000000) code=3'b111;
else code=3'bxxx;
end
endmodule

TESTBENCH:
module encoder_tb( );
reg [7:0] data;
wire valid_data;
wire [2:0] code;
pencoder_casex dut (.data(data),.valid_data(valid_data),.code(code));
initial
begin
data=8'b01000000;
#10 data=8'b00000100;
#10 data=8'b10000000;
#10 data=8'b00000010;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

3.2 PRIORITY ENCODER:

AIM: To design 8 to 3 priority encoder
TOOL USED: Xilinx Vivado, Digilent Nexys 4

CODE:
module lab3_8to3pencoder(
input [7:0] data,
input enable,
output reg [2:0] code,
output valid_data
);
assign valid_data=|data;
always@(*)
begin
if(enable==1)
code=3'bz;
else
casex(data)
8'b1xxxxxxx:code=3'b111;
8'b01xxxxxx:code=3'b110;
8'b001xxxxx:code=3'b101;
8'b0001xxxx:code=3'b100;
8'b00001xxx:code=3'b011;
8'b000001xx:code=3'b010;
8'b0000001x:code=3'b001;
8'b00000001:code=3'b000;
default : code=3'bxxx;
endcase
end
endmodule

TESTBENCH:
module priority_encoder_tb();
reg [7:0] data;
reg enable;
wire valid_data;
wire [2:0] code;
lab3_8to3pencoder dut (.data(data),.valid_data(valid_data),.code(code));
initial
begin
data=8'b01000000; enable =1'b1;
#10 data=8'b00000100; enable =1'b0;
#10 data=8'b10000000; enable =1'b0;
#10 data=8'b00000010; enable =1'b0;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

3.3 MULTIPLEXER
AIM: To design 8 to 1 multiplexer
TOOL USED: Xilinx Vivado, Digilent Nexys 4.
CODE:
module mux(
input A,B,C,D,E,F,G,H,
input [2:0] SEL,
output reg MUX_OUT
);
always @(A,B,C,D,E,F,G,H,SEL)
begin
case(SEL)
3'd0:MUX_OUT=A;
3'd1:MUX_OUT=B;
3'd2:MUX_OUT=C;
3'd3:MUX_OUT=D;
3'd4:MUX_OUT=E;
3'd5:MUX_OUT=F;
3'd6:MUX_OUT=G;
3'd7:MUX_OUT=H;
default:;
endcase
end
endmodule

TESTBENCH:
module mux_tb( );
reg A,B,C,D,E,F,G,H;
reg [2:0] SEL;
wire MUX_OUT;
mux dut (.A(A),.B(B),.C(C),.D(D),.E(E),.F(F),.H(H),.SEL(SEL),.MUX_OUT(MUX_OUT));
initial
begin
A=1;B=0;C=1;D=1;E=0;F=1;G=0;H=1; SEL=3'b000;
#10 A=1;B=0;C=1;D=1;E=0;F=1;G=0;H=1; SEL=3'b001;
#10 A=1;B=0;C=1;D=1;E=0;F=1;G=0;H=1; SEL=3'b111;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

3.4 BINARY TO GRAY CONVERTER

AIM: To design binary to gray converter.
TOOLS USED: Xilinx Vivado, Digilent Nexys 4.
CODE:
module bintogray(
input w,x,y,z,
output a,b,c,d
);
wire w1,w2;
assign a=w;
assign b=w^x;
assign w1=b;
assign c=w1^y;
assign w2=c;
assign d=c^z;
endmodule
TESTBENCH:
module bintogray_tb();
wire a,b,c,d;
reg w,x,y,z;
bintogray t1(.a(a),.b(b),.c(c),.d(d),.w(w),.x(x),.y(y),.z(z));
initial
begin
w=1'b0;x=1'b0;y=1'b0;z=1'b0;
#10 w=1'b0;x=1'b0;y=1'b0;z=1'b1;
#10 w=1'b0;x=1'b0;y=1'b1;z=1'b0;
#10 w=1'b0;x=1'b0;y=1'b1;z=1'b1;
#10 w=1'b0;x=1'b1;y=1'b0;z=1'b0;
#10 w=1'b0;x=1'b1;y=1'b0;z=1'b1;
#10 w=1'b0;x=1'b1;y=1'b1;z=1'b0;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

3.5 2 BIT MAGNITUDE COMPARATOR

AIM: To design 2 bit magnitude comparator.
TOOLS USED: Xilinx Vivado, Digilent Nexys 4.
CODE:
module Mag_Comp_2bit(
input [1:0] A,
input [1:0] B,
output AgrtB,
output AequalB,
output AlessB
);
wire x0,x1;
assign x0=(A[0]^B[0]);
assign x1=(A[1]^B[1]);
assign AequalB = x0&x1;
assign AgrtB = (A[1]&(~(B[1])))|(x1&(A[0])&(~(B[0])));
assign AlessB = (~A[1])&(B[1])|((x1)&(~A[0])& (B[0]));
endmodule

TESTBENCH:
module mag_comp_tb( );
reg [1:0]A,B;
wire AgrtB,AequalB,AlessB;
Mag_Comp_2bit t1(.A(A),.B(B),.AgrtB(AgrtB),.AequalB(AequalB),.AlessB(AlessB));
initial
begin
A=2'b00;B=2'b00;
#10 A=2'b00;B=2'b10;
#10 A=2'b10;B=2'b00;
#10 A=2'b11;B=2'b11;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

DATE:

EXP NO.: 4

SEQUENTIAL CIRCUIT
4.1

S-R FLIP FLOP

AIM: To design SR Flip Flop.

TOOLS USED: Xilinx Vivado, Digilent Nexys 4.
CODE:
module SR_FF(
input s,r,
input clk,
input reset,
output reg q,qn
);
always @ (posedge (clk))
begin
if (reset)
begin
q <= 0;
qn <= 1;
end
else
begin
if (s!=r)
begin
q <= s;
qn <= r;
end
else if (s==1 && r==1)
begin
q <= 1'bZ;
qn <= 1'bZ;

end
end
end
endmodule

TESTBENCH:
module SR_TB( );
reg s,r,clk,reset;
wire q,qn;
SR_FF DUT (.s(s),.r(r),.clk(clk),.reset(reset),.q(q),.qn(qn));
initial
begin
clk=1;
end
always
begin
#10 clk=~clk;
end
initial
begin
s=1'b0;r=1'b0;reset=1'b1;
#10 s=1'b0;r=1'b1;reset=1'b0;
#10 s=1'b1;r=1'b0;reset=1'b0;
#10 s=1'b1;r=1'b1;reset=1'b0;
end
endmodule

RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION:

4.2 J-K FLIP FLOP

AIM: To design J-K Flip Flop.
TOOLS USED: Xilinx Vivado, Digilent Nexys 4.
CODE:
module JK_FF(
input j,k,clk,reset,
output reg q,qn
);
always @ (posedge clk)
begin
if (reset)
begin
q <= 0;
qn <= 1;
end
else begin
if (j!=k) begin
q <= j;
qn <= k;
end
else if (j==1 && k==1)
begin
q <= ~q;
qn <= ~qn;
end
end
end
endmodule

TESTBENCH:
module JK_TB( );

reg j,k,clk,reset;
wire q,qn;
JK_FF DUT (.j(j),.k(k),.clk(clk),.reset(reset),.q(q),.qn(qn));
initial
begin
clk=1;
end
always
begin
#10 clk=~clk;
end
initial
begin
j=1'b0;k=1'b0;reset=1'b1;
#10 j=1'b0;k=1'b1;reset=1'b0;
#10 j=1'b1;k=1'b0;reset=1'b0;
#10 j=1'b1;k=1'b1;reset=1'b0;
end
endmodule

RTL NETLIST:

SYNTHESIZED OUTPUT:

SIMULATION RESULT:

4.3 D FLIP FLOP

AIM: To design D flip flop.
TOOLS USED: Xilinx Vivado, Digilent Nexys 4.
CODE:
module D_ff(
input d,
input clk,
input rst,
output reg q,
output q_n
);
assign q_n=~q;
always@(posedge clk or posedge rst)
begin
if(rst==0)
q<=1'b0;
else if (d==0)
q<=1'b0;
else
q<=1'b1;
end
endmodule
TESTBENCH:
module d_fftb();
reg d,clk,rst;
wire q,q_n;
D_ff DUT (.d(d),.clk(clk),.rst(rst),.q(q),.q_n(q_n));
initial

begin
clk=1;
end
always
begin
#10 clk=~clk;
end
initial
begin
d=1'b1;rst=1'b0;
#10d=1'b1;rst=1'b1;
#10d=1'b1;rst=1'b1;
#10d=1'b0;rst=1'b1;
#10d=1'b1;rst=1'b1;
end
endmodule
RTL NETLIST:

SYNTHESISED DESIGN:

SIMULATION:

4.4 T FLIP FLOP

CODE:
module T_FF(
input t,
input clk,
input rst,
output reg q,
output q_n
);
assign q_n=~q;
always@(posedge clk or posedge rst)
begin
if(rst==0)
begin
q<=1'b0;
end
else if(t==1)
begin
q<=q_n;
end
else
begin
q<=~(q_n);
end
end
endmodule
TESTBENCH:
module T_FF_TB( );
reg t,clk,rst;
wire q,q_n;

T_FF DUT (.t(t),.clk(clk),.rst(rst),.q(q),.q_n(q_n));

initial
begin
clk=1;
end
always
begin
#10 clk=~clk;
end
initial
begin
t=1'b1;rst=1'b0;
#10 t=1'b1;rst=1'b1;
#10 t=1'b1;rst=1'b1;
#10 t=1'b0;rst=1'b1;
#10 t=1'b1;rst=1'b1;
end
endmodule
RTL NETLIST:

SYNTHESIZED DESIGN:

SIMULATION: