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Webinar 01 - Routing Basics CEF

This document provides an overview of routing and switching basics, packet forwarding process, routing table, routing protocols, layer 2 encapsulation, traffic types, CPU vs. ASIC, memory types, and switching methods including process-switching, fast-switching, and Cisco Express Forwarding (CEF). The key points are: 1. Routing finds the optimal path to a destination while switching moves packets between interfaces. Packet forwarding looks up the destination IP and routing table to find the next hop and outgoing interface. 2. The routing table contains IP prefixes, next hops, interfaces, and other data. CEF optimizes this into the Forwarding Information Base (FIB) table stored in TCAM

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95 views29 pages

Webinar 01 - Routing Basics CEF

This document provides an overview of routing and switching basics, packet forwarding process, routing table, routing protocols, layer 2 encapsulation, traffic types, CPU vs. ASIC, memory types, and switching methods including process-switching, fast-switching, and Cisco Express Forwarding (CEF). The key points are: 1. Routing finds the optimal path to a destination while switching moves packets between interfaces. Packet forwarding looks up the destination IP and routing table to find the next hop and outgoing interface. 2. The routing table contains IP prefixes, next hops, interfaces, and other data. CEF optimizes this into the Forwarding Information Base (FIB) table stored in TCAM

Uploaded by

Horia Călin
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We take content rights seriously. If you suspect this is your content, claim it here.
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Routing basics/CEF

Dmitry Figol, CCIE R&S #53592


Cisco TAC CATS (Architecture) team
2 November, 2016

Intro to routing and switching


Routing

Finding the optimal way towards destination

Switching

Moving packet between interfaces

Packet Forwarding
When the packet comes in, the router does the following:
0. Checks and removes L2 header, gets destination IP

1. Routing process
2. Switching process
3. L2 encapsulation

Routing Process

Finds the longest match based on destination IP in routing table


(RIB)

The goal is to find outgoing interface and Next Hop IP address


Decimal

Binary

Dest IP: 192.168.0.33

11000000.10101000.00000000.00100001

Prefix 1: 10.0.0.0/8

00001010.00000000.00000000.00000000

Prefix 2: 192.168.0.0/24

11000000.10101000.00000000.00000000

Prefix 3: 192.168.0.32/27

11000000.10101000.00000000.00100000

Routing table - example

Routing table (cont.)

Another name is RIB Routing Information Base

Recursive Lookup

Contains information useless for forwarding:

For example, Administrative Distance and Metric

Single lookup has linear complexity O(n)

Stored in RAM

Verification: show ip route [ip-address [mask]]

Routing table (cont.)


Metric (maximum is 232 - 1 = 4294967295):

Used to choose the best route within a single routing protocol


(*not always true)

Administrative distance (0..255):

Used to choose the best route between routing protocols

Routing table (cont.) - AD


Route Source

Value

Route Source

Value

Connected

RIP

120

Static

EGP

140

EIGRP summary

ODR

160

eBGP

20

EIGRP external

170

EIGRP internal

90

iBGP

200

IGRP

100

NHRP

250

OSPF

110

DHCP learned

254

IS-IS

115

Unknown* (Not installed) 255

Routing protocols

Static

Dynamic:

Interior Gateway Protocols (IGP):

Distance-vector (RIP, EIGRP)

Link-state (OSPF, IS-IS)

Exterior Gateway Protocols (EGP):

Path-vector (BGP)

L2 Encapsulation
Knowing outgoing interface and Next Hop address is not always
enough for packet rewrite

Point-to-point links no additional information required

Point-to-multipoint links L2 Destination Address is required


SRC IP

DST IP

IP Packet

DST MAC

SRC MAC

SRC IP

Encapsulated IP Packet

DST IP

Traffic types
Data plane traffic through the device
Control plane traffic to the device:

Routing protocols hello/updates

STP BPDU

FHRP and others

Management plane part of control plane:

SSH/Telnet

SNMP

source: networklessons.com

CPU vs ASIC

CPU

Central processing unit (CPU) is the brains of the network device

Handles control plane

Can do anything

Cant do packet forwarding with high throughput*

*Note: DPDK project enables x86 multi-core processors to forward 200+ Gbps

source: intel.com

ASIC

Application specific integrated circuit (ASIC) is circuit with transistors

Very fast, but dumb

Designed specifically to move packets

Expensive

Not possible to program new features

Responsible for data plane


source: wikipedia.org

Memory types

RAM
Random Access Memory (RAM) is the most common type of memory

Value is accessed by pointer (memory address)

Cheap

CAM
Content-addressable memory (CAM)

Value is accessed by a key, not a pointer

Key is presented using 0 and 1

Very fast

Expensive

High power consumption

O(1) constant time lookup

Used in switches for MAC address table

TCAM
Ternary Content-addressable memory (TCAM)

Value is accessed by a key

Key is presented using 0, 1 or x (dont care)

Very expensive

High power consumption

O(1) constant time lookup!

Used for next-hop lookup (CEF table), ACL (security and QoS)

Switching methods:
Process-switching
Fast-switching
CEF

Process-switching

Process-switching (cont.)

Recursive lookup is performed by CPU in RIB

There is special process responsible for process-switching IP Input

The following traffic is process-switched:

Control plane

Locally generated

No L2 adjacency information

ACL logging

Fast-switching

First packet for source-destination IP pair is process-switched

IP pair and corresponding encapsulation information is added to the


cache

Following packets are forwarding based on the entry in cache

Deprecated!

Cisco Express Forwarding (CEF)


RIB optimization

Resolves recursive lookup and gets rid of useless information

Adds pointer to pre-built L2 header in Adjacency table

FIB/CEF table:

Contains prefix, NH, outgoing interface, pointer to L2 header

Stored in DRAM and TCAM (if exists, lookup is much faster)

The lookup is done during the interrupt (process scheduling is not required)
Verification: show ip cef [ip-address [mask]] [detail] [internal]

CEF Adjacency table

CEF process takes information from all L3-to-L2 mappings and builds L2
header

Adjacency table contains NH, interface, associated L2 Header

Stored in RAM

Pitfall: CEF process does not allow adjacency to age out

(clear arp wont delete ARP entry if it can be revalidated)

Verification:
show adjacency [detail]

CEF on hardware-based platforms

CEF basically allows to forward traffic without CPU

Depending on platform there can be zero, one or more ASICs.

The same applies for TCAM

All L3 switches have TCAM, only some routers have it

Thats why generally speaking L3 switches forward traffic faster than routers

TCAM stores not only FIB, but ACL and QoS rules

CEF on hardware-based platforms (cont.)

CEF Load Balancing

Routing protocols can install several routes for the same prefix

How will CEF decide where to send packet?

CEF is doing load-balancing per-flow

By default, it takes source-destination IP pair, feeds it to the hashing


algorithm, which defines next-hop

Questions?

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