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Block Diagram of Binary Multiplier

The document describes a binary multiplier circuit with the following components: - A controller and datapath that includes registers to store the multiplicand, multiplier, partial products, and carry. - It operates in three states - idle, add, and shift - to sequentially add partial products and shift the multiplier. - When started, it loads the registers, sets an n-bit counter for the multiplier length, and begins adding and shifting depending on the multiplier bit to calculate the product over multiple cycles.

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Nithin Gopal
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488 views4 pages

Block Diagram of Binary Multiplier

The document describes a binary multiplier circuit with the following components: - A controller and datapath that includes registers to store the multiplicand, multiplier, partial products, and carry. - It operates in three states - idle, add, and shift - to sequentially add partial products and shift the multiplier. - When started, it loads the registers, sets an n-bit counter for the multiplier length, and begins adding and shifting depending on the multiplier bit to calculate the product over multiple cycles.

Uploaded by

Nithin Gopal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Block diagram of Binary multiplier

Controller and data path

Multiplicand-register B
Multiplier-reg Q
Counter-P
Carry storage-f/f C
Partial product-reg A
3 states- S _idle,S_add,S_shift
Data path width is 5 bits
When Start=0 ,then there is no actionie in S_idle state
When start =1multiplication process stars then S_idle move to S_add
--c=0 &A=0
--B&Q loaded with multiplicand and multiplier
--counter P set to n-ie no of bits in multiplier
Q[0] is checked-if 0 A and C hve no change
When Q[1]=1 then B+A and carry to C
-then P=P-1

//port declarations
module binary_multiplier(product,ready,multiplicant,multiplier,start,clk,reset_b);
//datapath
input [dp_width-1:0] multiplicant,multiplier;
input start,clk,reset_b;
output [2*dp_width-1:0] product;
output ready;
Parameter dp_width =5;
Parameter BC_size;
Parameter s_idle=3b001;
Parameter s_add=3b010;

Parameter s_shift=3b100;
//reg declaration
reg[2;0] state,next_state;
reg [dp_width-1:0] A,B,Q;
Reg C;
Reg BC_size[1:0] p;
Reg load_reg,decr_p,add_regs,shift_regs;
//combinational logic
Assign product={A,Q};
Wire Zero=(p==0);//counter zero
Wire ready=(state==S_idle);//contrl status
//control unit
always @ (posedge clk,negedge reset_b)
if(~reset_b)state<=s_idle;
Else state<=next_state;
always @ (state,start,Q[0],zero)
Begin
Next_state=S_idle;
Reg C;
Reg BC_size[1:0] p;
Reg load_reg=0;
decr_p=0;
add_regs=0;
shift_regs=0;
Case (state)
//datapath

always @ (posedge clk) begin


if(load_regs)begin
P<=dp_width;
A<=0;
C<=0;
B<=multiplicant;
Q<=multiplier;
end
If (Add_regs){C,A}<=A+B;
If (shift_regs){C,A,Q}<>= {C,A,Q}>>1;
If (decr_P)P>= P-1;
End
endmodule
Case (state)
S_idle:begin if(start)next_state=S_add;load_regs=1;end
S_add:begin next_state=S_shift; decr_P=1;if (Q[0]add_regs=1;end
S_shift:begin S_shift=1;if(zero)next_state=S_idle;
else next_state=S_add;end
default:next_state=S_idle;
Endcase
end

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