Analog Multiplier and PLL: Unit-Iii
Analog Multiplier and PLL: Unit-Iii
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Introduction
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Introduction
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MULTIPLIERS
A multiple produces an output V0 , which is
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Accuracy:
This specifies the derivation of the actual output from the ideal output, for any
combination of X and Y inputs falling within the permissible operating range of the
multiplier.
Linearity:
This defines the accuracy of the multiplier. It represents the maximum percentage
derivation from the ideal straight line output. An error surface is formed by plotting the
output for different combinations of X and Y inputs. The Linearity Error can be defined
as the maximum absolute derivation of the error surface. This linearity error imposes a
lower limit on the multiplier accuracy.
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..CONTD
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..CONTD
Bandwidth:
The Bandwidth indicates the operating capability of an analog
multiplier at higher frequency values. Small signal 3 dB
bandwidth defines the frequency f0 at which the output
reduces by 3dB from its low frequency value for a constant
input voltage. This is identified individually for the X and Y
input channels normally.
The transconductance bandwidth represents the frequency at
which the transconductance of the multiplier drops by 3dB of
its low frequency value. This characteristics defines the
application frequency ranges when used for phase detection
or AM detection.
Quadrant:
The quadrant defines the applicability of the circuit for
bipolar signals at its inputs. First quadrant device accepts
only positive input signals, the two quadrant device accepts
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signal and
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quadrant device accepts two bipolar signals.
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V z = K z T = K z At=Vx Vy/Kx Ky
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..CONTD
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Variable Transconductance
Technique:
V0 = gm RLVx = (Vy/VTRE)VxRL
=(Vx Vy RL/Vt Re
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Multiplier quadrants:
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Voltage Squarer:
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Frequency doubler
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Frequency doubler
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Voltage Divider
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PLL
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PLL
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PLL
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PLL
The phase detector is basically a multiplier and produces the sum (fs + fo)
and difference (fs - fo) components at its output. The high frequency
component (fs + fo) is removed by the low pass filter and the difference
frequency component is amplified then applied as control voltage vc to VCO.
The signal vc shifts the VCO frequency in a direction to reduce the frequency
difference between fs and fo. Once this action starts, we say that the signal is
in the capture range. The VCO continues to change frequency till its output
frequency is exactly the same as the input signal frequency. The circuit is then
said to be locked.
Once locked, the output frequency fo of VCO is identical to fs except for a
finite phase difference . This phase difference generates a corrective
control voltage vc to shift the VCO frequency from f0 to fs and thereby
maintain the lock. Once locked,PLL tracks the frequency changes of the input
signal.
Thus, a PLL goes through three stages (i)free running, (ii) capture and (iii)
locked or tracking.
Capture range: the range of frequencies over which the PLL can acquire lock
with an input signal is called the capture EC6404-LINEAR
range. This
parameter is also
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expressed as percentage of fo.
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Pull-in time: the total time taken by the PLL to establish lock is called pull-in
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Equations
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Block Diagram
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IC565
The signetics NE/SE 560 series is monolithic phase locked loops. The
SE/NE 560, 561,
562, 564, 565 & 567 differ mainly in operating frequency range, poser
supply requirements & frequency & bandwidth adjustment ranges.
The important electrical characteristics of the 565 PLL are,
Operating frequency range: 0.001Hz to 500 Khz.
Operating voltage range: 6 to 12v
Input level required for tracking: 10mv rms min to 3 Vpp max
Input impedance: 10 K ohms typically.
Output sink current: 1mA
Output source current: 10 mA
The center frequency of the PLL is determined by the free running
frequency of the VCO, which is given by
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IC565
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Applications of PLL-IC
1.Frequency Multiplier
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2.FSK Demodulator
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FSK Demodulator
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3.AM Demodulation
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4.Frequency
multiplication/division:
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5.Frequency Synthesizer
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