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Experiment 1 designs a CMOS inverter and obtains its schematic, simulations, and netlist. The schematic and netlist are provided. Simulations show the inverter's truth table with a 0 input giving a 1 output and vice versa. Experiment 2 implements a NOR logic using CMOS circuits, providing the schematic, netlist, and simulations, including the truth table. Experiment 3 similarly implements a NAND2 CMOS logic, providing the relevant design documents and truth table.

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Varun Sahani
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21 views17 pages

Microelectronics Files

Experiment 1 designs a CMOS inverter and obtains its schematic, simulations, and netlist. The schematic and netlist are provided. Simulations show the inverter's truth table with a 0 input giving a 1 output and vice versa. Experiment 2 implements a NOR logic using CMOS circuits, providing the schematic, netlist, and simulations, including the truth table. Experiment 3 similarly implements a NAND2 CMOS logic, providing the relevant design documents and truth table.

Uploaded by

Varun Sahani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment 1

To Design a CMOS inverter and obtain its schematic, simulations and net
list.
Schematic:

Netlist:
* source NOT
V_VA
N02340 0
+PULSE 0 5 0 0 0 0.1m 0.2m
V_V1
N03068 0 5Vdc
M_M13
VOUT N02340 0 0 MbreakN
M_M11
VOUT N02340 N03068 N03068MbreakP

VARUN SAHANI
04216412811

Simulations:

Truth Table:

VA (input)

Vout

VARUN SAHANI
04216412811

Experiment 2
To implement the NOR logic using CMOS circuits, and obtain it schematic,
simulations and netlist.
Schematic:

Netlist:
*source NOR
V_V3 VA 0
+PULSE 0V 05V 0 0 0 0.1m 0.2m
M_M4
N04577 VA N00074 MbreakP
V_V2 VB 0
+PULSE 0V 5V 0 0 0.05m 0.2m
M_M3
VO VB N04577 N04577MbreakP
V_V1
N00074 0 5Vdc
M_M1
VO VA 0 0 MbreakN
M_M2
VO VB 0 0 MbreakN

VARUN SAHANI
04216412811

Simulations:

Truth Table:
A (input)

B (input)

Vout

Experiment 3
VARUN SAHANI
04216412811

To implement a NAND2 CMOS Logic and obtain its schematic, simulations


and netlist.
Schematic:

Netlist:
*sourceNAND
M_M3
VOVAN00070N00070MbreakN
M_M4
N00070VB00MbreakN
V_V5
VA0
+PULSE0V 5V0000.1m0.2m
V_V4
VB0
+PULSE0V 5V0000.05m0.2m
M_M5
VOVAN00652N00652MbreakP
M_M6
VOVBN00652N00652MbreakP
V_V1
N006520 5Vdc

Simulations:

VARUN SAHANI
04216412811

Truth Table:
A (input)

B (input)

C(output)

Experiment 5

VARUN SAHANI
04216412811

To implement XNOR CMOS logic and obtain its schematic, simulations and
netlist.
Schematic:

Truth Table:
A (input)

B (input)

C(output)

Netlist:
VARUN SAHANI
04216412811

Simulations:

Experiment 4
To implement XOR Logic in CMOS and obtain its schematic, simulations and netilist.
VARUN SAHANI
04216412811

Schematic:

Truth Table:

VARUN SAHANI
04216412811

A (input)

B (input)

C(output)

Netlist:

Simulations:

VARUN SAHANI
04216412811

Experiment 6
To implement a Resistive Load inverter and obtain its voltage transfer characteristics.

VARUN SAHANI
04216412811

Schematic:

Net List:
* source VTCRL
V_V1
N00817 0 5v
M_M1
VOUT VIN 0 0 MbreakN
R_R1
VOUT N00817 100k
V_V2
VIN 0 0Vdc

Input/Output voltages with respect to time:

VARUN SAHANI
04216412811

Voltage Transfer Characteristics:

Experiment 7
VARUN SAHANI
04216412811

To implement N type Depletion Load Inverter and obtain its voltage transfer
characteristics.
Schematic:

Net List:
* source VTCNL
M_M2
N00817 VOUT VOUT 0 MbreakND
V_V1
N00817 0 5v
M_M1
VOUT VIN 0 0 MbreakN
V_V2
VIN 0 0Vdc

Input/Ouput voltages with respect to time:

VARUN SAHANI
04216412811

Voltage transfer characteristics:

Experiment 8
VARUN SAHANI
04216412811

Implement CMOS inverter and obtain its Voltage transfer characteristics.


Schematic:

Net List:
* source VTCMOS
V_V2
N00817 0 5v
M_M1
VOUT VIN 0 0 MbreakN
M_M2
VOUT VIN N00817 N00817MbreakP
V_V1
VIN 0 0Vdc

Input/Output voltage with respect to timing:

VARUN SAHANI
04216412811

Voltage Transfer Characteristics:

VARUN SAHANI
04216412811

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