Characterization of TTL
Characterization of TTL
This experiment includes characterization of TTL NAND gate and CMOS NAND gate.
This experiment enables a student to learn:
The principal objective of this experiment is to fully understand the function and input/output
electrical behaviour of TTL NAND gate and CMOS NAND gate
using IC 7400 and IC 4011
TTL NAND Gate:
Vi2
T1
T2 T3 T4 D V0
ON(for OF OF O O HIG
LOW LOW
)
F F N N H
HIG ON(for OF
H
)
F
HIG
ON(for OF
LOW
H
)
F
HIG HIG ON(rev OF
H
H
)
F
LOW
OF
F
OF
F
OF
F
O
N
O
N
O
N
O
N
O
N
O
N
HIG
H
HIG
H
HIG
H
Q3,Q4: NMOS
More complex logic functions such as those involving AND and OR gates require
manipulating the paths between gates to represent the logic. When a path consists of two
transistors in series, both transistors must have low resistance to the corresponding supply
voltage, modeling an AND. When a path consists of two transistors in parallel, either one or
both of the transistors must have low resistance to connect the supply voltage to the output,
modeling an OR. Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If
both of the A and B inputs are high, then both the NMOS transistors (bottom half of the
diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a
conductive path will be established between the output and Vss (ground), bringing the output
low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one
of the PMOS transistors will, and a conductive path will be established between the output
and Vdd (voltage source), bringing the output high.
1. At first change the input voltage. Then observe the corresponding voltage at each
node and also obseve the output voltage
2. At the time of changing the input voltage, when input voltage reaches 5 voltage
characteristic plot button will be appeared.
1. At first connect VCC and GND properly. Apply high voltage to VCC and apply low
voltage to GND.
2. Next, apply high voltage to one of the NAND gate inputs among four.
3. Next, Change the input voltage level. Then observe the corresponding output
voltage of that particular NAND gate.
4. If we apply high voltage to each NAND gate input we get coresponding output
voltage of each NAND gate.
1. When we change the input voltage the corresponding output voltage will be
appeared.
2. At the time of changing the input voltage, when it reaches 5 voltage characteristic
plot and transfer-characteristic buttons will be appeared.
5. Next, Click on the Transfer characteristic button. High to Low and Low to High
options will be appeared.
1. At first connect VCC and GND properly. Apply high voltage to VCC and apply low
voltage to GND.
2. Next, apply high voltage to one of the NAND gate inputs among four.
3. Change the input voltage level.Then observe the corresponding output voltage of
that particular NAND gate.
4. If we apply high voltage to each NAND gate input we get coresponding output
voltage of each NAND gate.
7. After clicking Transfer characteristic button two options, such as High to Low and
Low to High will be appeared.
8. Next click on High to Low and Low to High respectively.Corresponding plot will
be appeared. Then click on Exit button to go back to the experient.