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Floorplanning: An Optimal Floorplan, in Terms of Area

The document discusses floorplanning in VLSI design. It describes floorplanning as involving partitioning a chip area into rectangular regions to place blocks while minimizing area and wirelength. It outlines the inputs, objectives, and challenges of floorplanning. It also summarizes techniques for representing and generating floorplan solutions using normalized Polish expressions and simulated annealing to iteratively improve solutions.
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0% found this document useful (0 votes)
50 views27 pages

Floorplanning: An Optimal Floorplan, in Terms of Area

The document discusses floorplanning in VLSI design. It describes floorplanning as involving partitioning a chip area into rectangular regions to place blocks while minimizing area and wirelength. It outlines the inputs, objectives, and challenges of floorplanning. It also summarizes techniques for representing and generating floorplan solutions using normalized Polish expressions and simulated annealing to iteratively improve solutions.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 27

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Floorplanning
Inputs to the floorplanning problem:

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A set of blocks, fixed or flexible.

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ld

Pin locations of fixed blocks.

r
o
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A netlist.

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6

2
3

An optimal floorplan,
in terms of area

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u
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jn

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w

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Objectives: Minimize area, reduce wirelength for (critical) nets, maximize routability, determine shapes of flexible blocks

A nonoptimal floorplan
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Floorplan Design

w
w

Aspect ratio: r <= y/x <= s

Rotation:
Module connectivity
a

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b

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m
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y

Area: A=xy

Modules:

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3 6
d
5

f
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.
ld

u
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Floorplanning: Terminology
Rectangular dissection: Subdivision of a given rectangle by a finite #
of horizontal and vertical line segments into a finite # of non-overlapping
rectangles.

m
o
c

Slicing structure: a rectangular dissection that can be obtained by


repetitively subdividing rectangles horizontally or vertically.

r
o
w

Slicing tree: A binary tree, where each internal node represents a vertical
cut line or horizontal cut line, and each leaf a basic rectangle.
Skewed slicing tree: One in which no node and its right child are the
same.

1
2

4
6

w
w

.
w

4
2

1 H

6 7 4 5

Nonslicing floorplan

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1 V
6

H
7 V

4 5

A slicing tree (skewed) Another slicing tree


(nonskewed)

Slicing floorplan

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Related work

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Floorplan Design by Simulated Annealing

m
o
c

Wong & Liu, A new algorithm for floorplan design, DAC86.


Consider slicing floorplans.

r
o
w

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ld

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t
jn

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Wong & Liu, Floorplan design for rectangular and L-shaped modules, ICCAD87.
Also consider L-shaped modules.

.
w

w
w

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Wong, Leong, Liu, Simulated Annealing for VLSI Design, pp. 3171,
Kluwer academic Publishers, 1988.
Ingredients: solution space, neighborhood structure, cost function, annealing schedule?

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Solution Representation
An expression E = e1 e2 . . . e2n1 , where ei {1, 2, . . . , n, H, V }, 1 i
2n 1, is a Polish expression of length 2n 1 iff

m
o
c

1. every operand j, 1 j n, appears exactly once in E;


2. (the balloting property) for every subexpression Ei = e1 . . . ei, 1
i 2n 1, #operands > #operators.

.
ld

r
o
w

1 6 H 3 5 V 2 H V 7 4 H V
# of operands = 4 ....... = 7
# of operators = 2 ....... = 5

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T

u
t
jn

Polish expression Postorder traversal.


ijH: rectangle i on bottom of j; ijV : rectangle i on the left of j.

w
w

V
H

6
1

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J

.
w

2 7 5

6
E = 16H2V75VH34HV

E = 16+2*75*+34+*
Postorder traversal of a tree!
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Solution Representation (contd)


V

w
tu

Nonskewed
cases

w
w

....... HH ........

E = 123HV4V

U
T

nonskewed!

n
j
.
w

or

E = 123H4VV

.
ld

4
3

m
o
c

skewed!
V

N
J

3
1

....... VV ........

Question: How to eliminate ambiguous representation?


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Normalized Polish Expression


A Polish expression E = e1 e2 . . . e2n1 is called normalized iff E has no
consecutive operators of the same type (H or V ).

m
o
c

.
ld

Given a normalized Polish expression, we can construct a unique rectangular slicing structure.

w
w

H
3

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jn

.
w3

6
1

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o
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E = 16H2V75VH34HV
A normalized Polish expression

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Neighborhood Structure
Chain: HV HV H . . . or V HV HV . . .

m
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c

1 6 H 3 5 V 2 H V 7 4 H V

.
ld

r
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chain

u
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.
w

3 types of moves:

U
T

Adjacent: 1 and 6 are adjacent operands; 2 and 7 are adjacent operands;


5 and V are adjacent operand and operator.

w
w

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M 1 (Operand Swap): Swap two adjacent operands.


M 2 (Chain Invert): Complement some chain (V = H, H = V ).
M 3 (Operator/Operand Swap): Swap two adjacent operand and
operator.

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3

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Effects of Perturbation
3

.
ld

12V4H3V

M1

12V3H4V

M2

or

m
o
c
2

w
tu

M3

12H3H4V

4
3

12H34HV

U
T

Question: The balloting property holds during the moves?

n
j
.
w

M 1 and M 2 moves are OK.

Check the M 3 moves! Reject illegal M 3 moves.

N
J

w
w

Check M 3 moves: Assume that the M3 move swaps the operand ei


with the operator ei+1 , 1 i k 1. Then, the swap will not violate the
balloting property iff 2Ni+1 < i.
Nk : # of operators in the Polish expression E = e1 e2 . . . ek , 1 k 2n 1.

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Cost Function
= A + W .

A: area of the smallest rectangle


W : overall wiring length

.
ld

: user-specified parameter

W =

M1

.
w

w
w

ij cij dij .

M2

cij : # of connections between blocks i and j.

M3

2
1

4
3

A: 12H34HV

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4

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T

m
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dij : center-to-center distance between basic rectangles i and j.

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Cost Evaluation: Shape Curves


Shape curves correspond to different kinds of constraints where the
shaded areas are feasible regions.

hi

hi

hi

wi

y = six
Bounding
area

w
w

wi

u
t
n

y = six

j
.
w
y

r
o
w

y = ri x

corner
points

U
T

hi

.
ld

y = six

y = ri x

hi

wi

wi hi

y = six y = ri x y = 1
r x

N
J

wi

wi

feasible
region

m
o
c
y = s1 x
i

xi >= a, yi >= b, xi yi >= A


or
xi >= b, yi >= a, xi yi >= A

xi >= a, yi >= b

xi >= a, yi >= b
or
xi >= b, yi >= a

(a) rigid, fixed


orientation

(b) rigid, free (c) flexible, fixed (d) flexible, free


orientation
orientation
orientation

xi >= a, yi >= b
xi yi >= A

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Area Computation
2

{ (5,5) (9,4) }

{ (6,2) (3,3) }

{ (2,3) (3,2) } { (2,2) }

.
w

u2

u1
v

w
w
u1

u2
w

u
t
jn

max{u1, u2}

v+w
u2

4 { (1,2) (2,1) } { (2,2) }

{ (1,3) (3,1) } { (2,3) (3,2) }

.
ld

r
o
w

V { (3,2) }

m
o
c

{ (3,5) (6,,4) }

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U
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{ (2,5) (3,4) } H

u1+u2

u1

max{v, w}

Wiring cost?
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Incremental Computation of Cost Function


Each move leads to only a minor modification of the Polish expression.

m
o
c

At most two paths of the slicing tree need to be updated for each move.

u
t
jn

5
3

r
o
w

.
w

E = 12H34V56VHV

w
w

M1

H
V

2
3

E = 12H35V46VHV

N
J

U
T

.
ld
V

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Incremental Computation of Cost Function


(contd)

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E = 12H34V56VHV

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w

w
w
1

M3

.
ld
V

r
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m
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E = 12H34V56HVH
V

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M2

U
T

E = 12H34V56VHV

E = 123H4V56VHV
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Annealing Schedule
Initial solution: 12V 3V . . . nV .
1

m
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.
ld

r
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w

= 1, 2, 3, . . .; r = 0.85.

Ti =

riT0 , i

.
w

# of accepted moves < 5%,

temperature is low enough, or

w
w

run out of time.

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J

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t
jn

Terminate the annealing process if

U
T

At each temperature, try kn moves (k = 510).

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ld

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U
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Algorithm: Simulated Annealing Floorplanning(P, , r, k)


1 begin
2 E 12V 3V 4V . . . nV ; /* initial solution */
avg
; M M T uphill 0; N = kn;
3 Best E; T0 ln(P
)
4 repeat
5 M T uphill reject 0;
6 repeat
7
SelectMove(M );
8
Case M of
9
M1 : Select two adjacent operands ei and ej ; N E Swap(E, ei , ej );
10
M2 : Select a nonzero length chain C; N E Complement(E, C);
11
M3 : done F ALSE;
12
while not (done) do
13
Select two adjacent operand ei and operator ei+1 ;
14
if (ei1 6= ei+1 ) and (2Ni+1 < i) then done T RU E;
15
N E Swap(E, ei , ei+1 );
16
M T M T + 1; cost cost(N E) cost(E);
cost
17
if (cost 0) or (Random < e T )
18
then
19
if (cost > 0) then uphill uphill + 1;
20
E N E;
21
if cost(E) < cost(best) then best E;
22
else reject reject + 1;
23 until (uphill > N ) or (M T > 2N );
24 T = rT ; /* reduce temperature */
25 until ( reject
> 0.95) or (T < ) or OutOf T ime;
MT
26 end

.
w

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Floorplanning by Mathematical Programming


Sutanthavibul, Shragowitz, and Rosen, An analytical approach to floorplan design and optimization, 27th DAC, 1990.
Notation:

.
ld

r
o
w

wi, hi: width and height of module Mi.

m
o
c

u
t
jn

U
T

(xi, yi): coordinate of the lower left corner of module Mi.


ai wi/hi bi: aspect ratio wi/hi of module Mi. (Note: We defined
aspect ratio as hi/wi before.)

.
w

w
w

Linear constraints? Objective function?

N
J

Goal: Find a mixed integer linear programming (ILP) formulation for


the floorplan design.

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wi

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Area = hi * wi
Aspect ratio = wi / hi

.
ld

Mi

(xi, yi)

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o
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.
w

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Nonoverlap Constraints
Two modules Mi and Mj are nonoverlap, if at least one of the following linear constraints
is satisfied (cases encoded by pij and qij ):
pij
qij
Mi to the left of Mj :
xi + w i xj
0
0
Mi below Mj :
yi + h i y j
0
1
1
0
Mi to the right of Mj : xi wj xj
Mi above Mj :
yi h j yj
1
1

m
o
c

.
ld

r
o
w

Let W, H be upper bounds on the floorplan width and height, respectively.

u
t
jn

.
w

w
w

wi

xj + W (pij + qij )
yj + H(1 + pij qij )
xj W (1 pij + qij )
yj H(2 pij qij )

wj

wi

hj

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J

xi + w i
yi + h i
xi w j
yi h j

U
T

Introduce two 0, 1 variables pij and qij to denote that one of the above inequalities is
enforced; e.g., pij = 0, qij = 1 yi + hi yj is satisfied.

hi

(xj, yj)
(xi, yi)
xi + wi > xj

(xj, yj)
(xi, yi)
xi + wi <= xj

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Cost Function & Constraints


Minimize Area = xy, nonlinear! (x, y: width and height of the resulting
floorplan)
How to fix?

.
ld

Fix the width W and minimize the height y!

r
o
w

Four types of constraints:

m
o
c

u
t
jn

U
T

1. no two modules overlap (i, j : 1 i < j n);

.
w

3. xi 0, yi 0, 1 i n;

w
w

4. pij , qij {0, 1}.


wi, hi are known.

N
J

2. each module is enclosed within a rectangle of width W and height H


(xi + wi W, yi + hi H, 1 i n);

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Mixed ILP for Floorplanning


Mixed ILP for the floorplanning problem with rigid, fixed modules.
min

subject to

xi + wi W,
yi + hi y,
xi + wi xj + W (pij + qij ),
yi + hi yj + H(1 + pij qij ),
xi wj xj W (1 pij + qij ),
yi hj yj H(2 pij qij ),
xi , yi 0,
pij , qij {0, 1},

.
ld

w
w

Size of the mixed ILP: for n modules,

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

N
J

.
w

1in
1in
1i<jn
1i<jn
1i<jn
1i<jn
1in
1i<jn

U
T

r
o
w

u
t
jn

m
o
c

# continuous variables: O(n); # integer variables: O(n2 ); # linear constraints:


O(n2 ).
Unacceptably huge program for a large n! (How to cope with it?)
Popular LP software: LINDO, lp solve, etc.
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Mixed ILP for Floorplanning (contd)


Mixed ILP for the floorplanning problem: rigid, freely oriented modules.
min

.
ld

subject to
xi + ri hi + (1 ri )wi W,
yi + ri wi + (1 ri )hi y,
xi + ri hi + (1 ri )wi xj + M (pij + qij ),
yi + ri wi (1 ri )hi yj + M (1 + pij qij ),
xi rj hj + (1 rj )wj xj M (1 pij + qij ),
yi rj wj (1 rj )hj yj M (2 pij qij ),
xi , yi 0,
pij , qij {0, 1},

w
w

1in
1in
1i<jn
1i<jn
1i<jn
1i<jn
1in
1i<jn

(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)

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w

U
T

r
o
w

u
t
jn

m
o
c

For each module i with free orientation, associate a 0-1 variable ri :


ri = 0: 0 rotation for module i.
ri = 1: 90 rotation for module i.
M = max{W, H}.
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Flexible Modules
Assumptions: wi , hi are unknown; area lower bound: Ai .
Module size constraints: wi hi Ai ; ai
Hence, wmin =

Ai ai , wmax =

wi
hi

Ai bi , hmin =

Ai
,
bi

.
ld

hmax =

r
o
w

wi hi Ai nonlinear! How to fix?

m
o
c

bi .

Ai
.
ai

j
.
w

w
w

/ y = mx + c /
/ slope /
/ c = y0 mx0 /

N
J

u
t
n

h i = i w i + c i
hmax hmin
i =
wmin wmax
ci = hmax i wmin

U
T

Can apply a first-order approximation of the equation: a line passing through


(wmin , hmax ) and (wmax , hmin ).

Substitute i wi + ci for hi to form linear constraints (xi , yi , wi are unknown; i , j ,


ci , cj can be computed as above).

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h
Ai = wi * hi

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h max

hi =

i wi

+ ci

m
o
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h min

.
w

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T

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o
w

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t
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.
ld

wmax

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Reducing the Size of the Mixed ILP


Time complexity of a mixed ILP: exponential!

m
o
c

Recall the large size of the mixed ILP: # variables, # constraints: O(n2 ).
How to fix it?

.
ld

Key: Solve a partial problem at each step (successive augmentation)

r
o
w

Questions:

How to select next subgroup of modules? linear ordering based on connectivity.

u
t
jn

w
w

N
J

.
w

U
T

How to minimize the # of required variables?

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Next group
of modules

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J

w
w

U
T

.
w

.
ld

Partial
floorplan

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ld

u
t
jn

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Reducing the Size of the Mixed ILP (contd)


Size of each successive mixed ILP depends on (1) # of modules in the next group; (2)
size of the partially constructed floorplan.

m
o
c

Keys to deal with (2)

Minimize the problem size of the partial floorplan.

Replace the already placed modules by a set of covering rectangles.

r
o
w

# rectangles is usually much smaller than # placed modules.

.
w

w
w

Horizontal
cut edges

(a)

C3

C4
C2

(b)

R4

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Dead space

R5

R3

R2

C1

R1

(c)

(d)

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