Floorplanning: An Optimal Floorplan, in Terms of Area
Floorplanning: An Optimal Floorplan, in Terms of Area
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Floorplanning
Inputs to the floorplanning problem:
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A netlist.
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6
2
3
An optimal floorplan,
in terms of area
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Objectives: Minimize area, reduce wirelength for (critical) nets, maximize routability, determine shapes of flexible blocks
A nonoptimal floorplan
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Floorplan Design
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Rotation:
Module connectivity
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y
Area: A=xy
Modules:
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3 6
d
5
f
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Floorplanning: Terminology
Rectangular dissection: Subdivision of a given rectangle by a finite #
of horizontal and vertical line segments into a finite # of non-overlapping
rectangles.
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Slicing tree: A binary tree, where each internal node represents a vertical
cut line or horizontal cut line, and each leaf a basic rectangle.
Skewed slicing tree: One in which no node and its right child are the
same.
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1 H
6 7 4 5
Nonslicing floorplan
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1 V
6
H
7 V
4 5
Slicing floorplan
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Related work
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Wong & Liu, Floorplan design for rectangular and L-shaped modules, ICCAD87.
Also consider L-shaped modules.
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Wong, Leong, Liu, Simulated Annealing for VLSI Design, pp. 3171,
Kluwer academic Publishers, 1988.
Ingredients: solution space, neighborhood structure, cost function, annealing schedule?
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Solution Representation
An expression E = e1 e2 . . . e2n1 , where ei {1, 2, . . . , n, H, V }, 1 i
2n 1, is a Polish expression of length 2n 1 iff
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1 6 H 3 5 V 2 H V 7 4 H V
# of operands = 4 ....... = 7
# of operators = 2 ....... = 5
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2 7 5
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E = 16H2V75VH34HV
E = 16+2*75*+34+*
Postorder traversal of a tree!
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w
tu
Nonskewed
cases
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....... HH ........
E = 123HV4V
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nonskewed!
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or
E = 123H4VV
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4
3
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skewed!
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3
1
....... VV ........
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Given a normalized Polish expression, we can construct a unique rectangular slicing structure.
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E = 16H2V75VH34HV
A normalized Polish expression
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Neighborhood Structure
Chain: HV HV H . . . or V HV HV . . .
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1 6 H 3 5 V 2 H V 7 4 H V
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chain
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3 types of moves:
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Effects of Perturbation
3
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ld
12V4H3V
M1
12V3H4V
M2
or
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2
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tu
M3
12H3H4V
4
3
12H34HV
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Cost Function
= A + W .
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ld
: user-specified parameter
W =
M1
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ij cij dij .
M2
M3
2
1
4
3
A: 12H34HV
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hi
hi
hi
wi
y = six
Bounding
area
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y = six
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y
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y = ri x
corner
points
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hi
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y = six
y = ri x
hi
wi
wi hi
y = six y = ri x y = 1
r x
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wi
wi
feasible
region
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y = s1 x
i
xi >= a, yi >= b
xi >= a, yi >= b
or
xi >= b, yi >= a
xi >= a, yi >= b
xi yi >= A
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Area Computation
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{ (5,5) (9,4) }
{ (6,2) (3,3) }
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u2
u1
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u1
u2
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max{u1, u2}
v+w
u2
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V { (3,2) }
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{ (3,5) (6,,4) }
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{ (2,5) (3,4) } H
u1+u2
u1
max{v, w}
Wiring cost?
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At most two paths of the slicing tree need to be updated for each move.
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E = 12H34V56VHV
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M1
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2
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E = 12H35V46VHV
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V
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E = 12H34V56VHV
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M3
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E = 12H34V56HVH
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M2
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E = 12H34V56VHV
E = 123H4V56VHV
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Annealing Schedule
Initial solution: 12V 3V . . . nV .
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= 1, 2, 3, . . .; r = 0.85.
Ti =
riT0 , i
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wi
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Area = hi * wi
Aspect ratio = wi / hi
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Mi
(xi, yi)
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Nonoverlap Constraints
Two modules Mi and Mj are nonoverlap, if at least one of the following linear constraints
is satisfied (cases encoded by pij and qij ):
pij
qij
Mi to the left of Mj :
xi + w i xj
0
0
Mi below Mj :
yi + h i y j
0
1
1
0
Mi to the right of Mj : xi wj xj
Mi above Mj :
yi h j yj
1
1
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wi
xj + W (pij + qij )
yj + H(1 + pij qij )
xj W (1 pij + qij )
yj H(2 pij qij )
wj
wi
hj
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xi + w i
yi + h i
xi w j
yi h j
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Introduce two 0, 1 variables pij and qij to denote that one of the above inequalities is
enforced; e.g., pij = 0, qij = 1 yi + hi yj is satisfied.
hi
(xj, yj)
(xi, yi)
xi + wi > xj
(xj, yj)
(xi, yi)
xi + wi <= xj
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3. xi 0, yi 0, 1 i n;
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subject to
xi + wi W,
yi + hi y,
xi + wi xj + W (pij + qij ),
yi + hi yj + H(1 + pij qij ),
xi wj xj W (1 pij + qij ),
yi hj yj H(2 pij qij ),
xi , yi 0,
pij , qij {0, 1},
.
ld
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(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
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1in
1in
1i<jn
1i<jn
1i<jn
1i<jn
1in
1i<jn
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.
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subject to
xi + ri hi + (1 ri )wi W,
yi + ri wi + (1 ri )hi y,
xi + ri hi + (1 ri )wi xj + M (pij + qij ),
yi + ri wi (1 ri )hi yj + M (1 + pij qij ),
xi rj hj + (1 rj )wj xj M (1 pij + qij ),
yi rj wj (1 rj )hj yj M (2 pij qij ),
xi , yi 0,
pij , qij {0, 1},
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1in
1in
1i<jn
1i<jn
1i<jn
1i<jn
1in
1i<jn
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
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Flexible Modules
Assumptions: wi , hi are unknown; area lower bound: Ai .
Module size constraints: wi hi Ai ; ai
Hence, wmin =
Ai ai , wmax =
wi
hi
Ai bi , hmin =
Ai
,
bi
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hmax =
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c
bi .
Ai
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ai
j
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/ y = mx + c /
/ slope /
/ c = y0 mx0 /
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h i = i w i + c i
hmax hmin
i =
wmin wmax
ci = hmax i wmin
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h
Ai = wi * hi
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h max
hi =
i wi
+ ci
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h min
.
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wmax
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Recall the large size of the mixed ILP: # variables, # constraints: O(n2 ).
How to fix it?
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Questions:
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Next group
of modules
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Partial
floorplan
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Horizontal
cut edges
(a)
C3
C4
C2
(b)
R4
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Dead space
R5
R3
R2
C1
R1
(c)
(d)
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