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VHDL Code For 4 Bit Synchronous Counter

This document contains a VHDL code for a 4-bit synchronous counter, its circuit diagram, waveform, and synthesis report. The code defines a 4-bit synchronous up counter with a clock, reset, and up signal. The synthesis report shows the code was synthesized into a design using 4 slices, 4 flip flops, and 4 LUTs. The maximum frequency is 436.862MHz and timing requirements are met.

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Pawan Parihar
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339 views8 pages

VHDL Code For 4 Bit Synchronous Counter

This document contains a VHDL code for a 4-bit synchronous counter, its circuit diagram, waveform, and synthesis report. The code defines a 4-bit synchronous up counter with a clock, reset, and up signal. The synthesis report shows the code was synthesized into a design using 4 slices, 4 flip flops, and 4 LUTs. The maximum frequency is 436.862MHz and timing requirements are met.

Uploaded by

Pawan Parihar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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VHDL CODE FOR 4 BIT SYNCHRONOUS COUNTER =

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SYNCOUN is
Port ( CLK,RESET,UP : in STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
end SYNCOUN;
architecture Behavioral of CDCOUN is
SIGNAL TEMP : STD_LOGIC_VECTOR (3 DOWNTO 0);
begin
PROCESS(CLK,RESET,UP) IS
BEGIN
IF(RESET = '1') THEN
TEMP<= "0000";
ELSIF(RISING_EDGE(CLK)) THEN
IF(UP='1') THEN
IF(TEMP = "1111") THEN
TEMP<="0000";
ELSE
TEMP <= TEMP + 1;
END IF;
END IF;
END IF;
END PROCESS;
OUTPUT <= TEMP;

end Behavioral;

RTL=

CIRCUIT DIAGRAM

WAVE FORM=

SYNTHESIS REPORT =
================================================
=========================
*

Final Report

================================================
=========================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: CDCOUN
: NGC

Optimization Goal

: Speed

Keep Hierarchy

: NO

Design Statistics
# IOs

:7

Cell Usage :
# BELS

:4

INV

LUT3

:1

LUT4

:2

:1

# FlipFlops/Latches
#

FDCE

: CDCOUN.ngr

:4
:4

# Clock Buffers
#

:1

BUFGP

:1

# IO Buffers

:6

IBUF

OBUF

:2
:4

================================================
=========================

Device utilization summary:


---------------------------

Selected Device : 3s100ecp132-5

Number of Slices:

2 out of

960

0%

Number of Slice Flip Flops:

4 out of 1920

0%

Number of 4 input LUTs:

4 out of 1920

0%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

7
7 out of
1 out of

83
24

8%
4%

--------------------------Partition Resource Summary:


---------------------------

No Partitions were found in this design.

---------------------------

================================================
=========================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.


FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal

| Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
CLK

| BUFGP

|4

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:


--------------------------------------------------------------------------+------------------------+-------+
Control Signal

| Buffer(FF name)

| Load |

-----------------------------------+------------------------+-------+
RESET

| IBUF

|4

-----------------------------------+------------------------+-------+

Timing Summary:
--------------Speed Grade: -5

Minimum period: 2.289ns (Maximum Frequency: 436.862MHz)


Minimum input arrival time before clock: 2.088ns
Maximum output required time after clock: 4.221ns
Maximum combinational path delay: No path found

Timing Detail:
-------------All values displayed in nanoseconds (ns)

================================================
=========================
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 2.289ns (frequency: 436.862MHz)
Total number of paths / destination ports: 12 / 4
------------------------------------------------------------------------Delay:
Source:
Destination:
Source Clock:

2.289ns (Levels of Logic = 1)


TEMP_0 (FF)
TEMP_0 (FF)
CLK rising

Destination Clock: CLK rising

Data Path: TEMP_0 to TEMP_0


Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDCE:C->Q
INV:I->O
(Mcount_TEMP)
FDCE:D

5 0.514 0.538 TEMP_0 (TEMP_0)


1 0.612 0.357 Mcount_TEMP_xor<0>11_INV_0
0.268

TEMP_0

---------------------------------------Total

2.289ns (1.394ns logic, 0.895ns route)


(60.9% logic, 39.1% route)

================================================
=========================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Total number of paths / destination ports: 4 / 4

------------------------------------------------------------------------Offset:
Source:
Destination:

2.088ns (Levels of Logic = 1)


UP (PAD)
TEMP_0 (FF)

Destination Clock: CLK rising

Data Path: UP to TEMP_0


Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O
FDCE:CE

4 1.106 0.499 UP_IBUF (UP_IBUF)


0.483

TEMP_0

---------------------------------------Total

2.088ns (1.589ns logic, 0.499ns route)


(76.1% logic, 23.9% route)

================================================
=========================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 4 / 4
------------------------------------------------------------------------Offset:
Source:
Destination:
Source Clock:

4.221ns (Levels of Logic = 1)


TEMP_0 (FF)
OUTPUT<0> (PAD)
CLK rising

Data Path: TEMP_0 to OUTPUT<0>


Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDCE:C->Q

5 0.514 0.538 TEMP_0 (TEMP_0)

OBUF:I->O

3.169

OUTPUT_0_OBUF (OUTPUT<0>)

---------------------------------------Total

4.221ns (3.683ns logic, 0.538ns route)


(87.3% logic, 12.7% route)

================================================
=========================
CPU : 3.44 / 3.63 s | Elapsed : 3.00 / 3.00 s

-->

Total memory usage is 177420 kilobytes

Number of errors :
Number of warnings :
Number of infos

0 ( 0 filtered)
0 ( 0 filtered)
0 ( 0 filtered)

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