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EL3100 - Microprocessors Lab Experiment 3: Q D Q' Q D Q' Q D Q' Q D

This document describes an experiment to implement a 4-bit Johnson counter using Verilog. The key tasks are: 1. Simulate a 4-bit Johnson counter module in ISE using Verilog code provided. The code implements D flip-flops with reset to sequence through the counter states. 2. Synthesize and implement the 4-bit Johnson counter design on an FPGA board, using a clock divider and writing a UCF file to output the states on LEDs. 3. Design Verilog code to generate a 2.5MHz clock signal using a Johnson counter, based on the FPGA clock frequency. Connect the output to an oscilloscope.

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33 views2 pages

EL3100 - Microprocessors Lab Experiment 3: Q D Q' Q D Q' Q D Q' Q D

This document describes an experiment to implement a 4-bit Johnson counter using Verilog. The key tasks are: 1. Simulate a 4-bit Johnson counter module in ISE using Verilog code provided. The code implements D flip-flops with reset to sequence through the counter states. 2. Synthesize and implement the 4-bit Johnson counter design on an FPGA board, using a clock divider and writing a UCF file to output the states on LEDs. 3. Design Verilog code to generate a 2.5MHz clock signal using a Johnson counter, based on the FPGA clock frequency. Connect the output to an oscilloscope.

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josenit1787
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© © All Rights Reserved
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EL3100 - Microprocessors Lab

Experiment 3

Introduction

In this experiment, we will implement a Johnson counter. A 4-bit Johnson counter is shown in Figure 1. The
Johnson counter is like a ring counter, however, the inverted output of the last flip-flop is connected to the input
of the first flip-flop. A 3-bit Johnson counter will have states given by 000, 100, 110, 111, 011 and 001 and this
sequence repeats (Exercise: Identify the sequence for the 4-bit Johnson counter in Figure 1).

q3
q2
q1
q0
D3

D2

D1

D0

D Q

D Q

D Q

D Q

clk
reset
Figure 1: 4-bit Johnson counter

Tasks to be completed in this experiment

Task 1: Simulate a 4-bit Johnson counter in ISE. Complete the following Verilog programs for the simulation.
module johnson4bit(q3,q2,q1,q0,clk,rst);
input clk, rst;
output q0,q1,q2,q3;
wire q3bar, q2bar, q1bar, q0bar;
dflipflop_withreset D3(q3,q3bar,---,rst,clk);
dflipflop_withreset D2(q2,q2bar,---,rst,clk);
dflipflop_withreset D1(q1,q1bar,---,rst,clk);
dflipflop_withreset D0(q0,q0bar,q1,rst,clk);
endmodule
module dflipflop_withreset(q, qbar, d, rst, clk);
output q,qbar;
input d, rst, clk;
reg q,qbar;
always @ (posedge clk)
begin

if (~rst)
begin
q <= 1b0;
qbar <= 1b1;
end
else
begin
q <= ----; // complete the description of
qbar <= ----; // A Johnson counter transfers
end
// q to the data i/p of next f/f
end
// f/f whose i/p is qbar from the
endmodule

f/f
whatever is at
except for the leftmost
rightmost f/f

module stimulus_johnson;
wire q0,q1, q2,q3 ;
reg rst, clk;
johnson4bit j1(q3,q2,q1,q0,clk,rst);
initial
begin
rst = 1b0;
clk = 1b0;
#40 rst=1b1;
#200 $finish;
end
always #10 clk = ~clk;
initial $monitor($time, "q3 = %b, q2= %b, q1 = %b, q0 = %b", q3,q2,q1,q0);
endmodule
Task 2: Synthesize and implement the design for the 4-bit Johnson counter on the FPGA board. You need to
write a clock divider program and create an appropriate ucf file. The output for the Johnson counter should
appear on LEDs on the FPGA board.
Task 3: Design Verilog code for generating a 2.5 MHz clock signal using a Johnson counter (Hint: Find out the
frequency of the clock signal on the FPGA board and determine the number of bits you need for the Johnson
counter). You should connect the FPGA board suitably to an oscilloscope to show the output.

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