EL3100 - Microprocessors Laboratory

Introduction to Field Programmable Gate Arrays

Introduction

FPGAs are digital integrated circuits that contain configurable (programmable) blocks of logic plus configurable
interconnects between these blocks. Users can configure such devices to perform various tasks. Some FPGA
devices can be programmed just once while others (SRAM-based FPGAs that we will use) can be programmed
any number of times. Note that in either case, the FPGA is customized to a particular function.

1.1

Programming FPGAs and General-Purpose Microprocessors

General-purpose microprocessors (such as the Intel Pentium series or Motorola 68000) also contain digital logic
elements (gates). Users typically write programs in a high level language such as C or Java and input the same
to a compiler. The compiler may combine one or more edited files and build a logically correct sequence of bits
that are used to control the sequencing of the logic gates (typically, the bits dont directly control gates but need
to be connected to other bit patterns through a phase called linking taking the help of the operating system).
The gates allow writing data on to buses, latches, registers etc. but the gates have fixed relationships designed
to perform fixed functions.
For a Field Programmable Gate Array, a user may write a program in a hardware description language such
as Verilog or VHDL and have it compiled to generate register transfer logic (RTL) netlists. However, for an
FPGA, an additional synthesis procedure is also required to produce bits that will control the logic gates and fill
registers/memory on an FPGA.
Therefore, while the compiler (for a microprocessor) produces bits to control fixed-gate patterns (corresponding
to the microprocessors decoders, registers, ALU etc.), the synthesizer (for an FPGA) defines gate patterns based
on the logic prescribed in the (Verilog/VHDL) program. So, on an FPGA, program logic gets mapped into logical
gates and not into processor instructions that control existing gate structures.
Field programmable gate arrays can be used wherever microcontrollers (or general-purpose microprocessors)
are used. In other words, FPGAs can also be used to implement a microprocessor or even a microcontroller
with support for timers and other units.
FPGAs provide features beyond what most traditional microprocessors (or microcontrollers) do. In particular,
massive parallelism can be realized via an FPGA. One can have multiple copies of basic digital logic elements
such as comparators, adders, multiplexers etc. as demanded by an application (to meet a certain requirement on
the speed). The number of such elements one can have on an FPGA is determined by the capacity (measured
typically in terms of units called configurable logic blocks) of the FPGA.

1.2

Starter Kit for the Experiments

FPGAs were pioneered by Xilinx, Inc. In this laboratory, we will use a starter kit from Digilent, Inc. that has a
Spartan-3E series Xilinx FPGA. Details about the kit are available from my lab webpage http://www.ee.iitm.ac.in/
sridhara/el3100 lab. The starter kit has a number of peripherals besides an XC3S500E Spartan-3E FPGA device.
A datasheet on the FPGA is also available on the lab webpage (as a pdf file).

Sample Programs

We will write Verilog programs in the three experiments and synthesize them. A Verilog tutorial by Daniel Hyde
is on the lab webpage. The webpage also has some slides. A good book for Verilog is Samir Palnitkars Verilog
HDL published by Pearson Education (2003). Given below are two sample programs, one for a 1-bit full adder
and the other for finding the minimum of several numbers (using a binary-tree structured comparison approach).
// one bit adder
module fulladd(s, cout, a,b, cin);
1

input a;
input b;
input cin;
output s;
output cout;
wire s1, c1, c2;
xor (s1, a,b);
and (c1, a, b);
xor (s, s1, cin);
and (c2, s1, cin);
xor (cout, c2, c1);

endmodule

// Minimum finding in parallel

[15:0] min_val;

wire [15:0] n[0:31];

reg cmp_en0,cmp_en1,cmp_en2,cmp_en3,cmp_en4;
reg [2:0] state;
parameter st0=0,st1=1,st2=2,st3=3,st4=4,st5=5;
wire [15:0] min0,min1,min2,min3,min4,min5,min6,min7,min8,min9;
wire [15:0] min10,min11,min12,min13,min14,min15,min16,min17,min18,min19;
wire [15:0] min20,min21,min22,min23,min24,min25,min26,min27,min28,min29;

assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign

n[0] = 16hffff;
n[1] = 16hfeff;
n[2] = 16hfbff;
n[3] = 16hefff;
n[4] = 16heeff;
n[5] = 16hefff;
n[6] = 16hedff;
n[7] = 16hffff;
n[8] = 16hcdff;
n[9] = 16hcbff;
n[10] = 16hbbff;
n[11] = 16habff;
n[12] = 16h9bff;
n[13] = 16h8bff;
2

assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign

n[14]
n[15]
n[16]
n[17]
n[18]
n[19]
n[20]
n[21]
n[22]
n[23]
n[24]
n[25]
n[26]
n[27]
n[28]
n[29]
n[30]
n[31]

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

16h7bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h6bff;
16h4567;
16h53ff;
16h5bff;
16h5187;

//INSTANTIATION OF comparators
cmp c0(cmp_en0,n[0],n[1],min0);
cmp c1(cmp_en0,n[2],n[3],min1);
cmp c2(cmp_en0,n[4],n[5],min2);
cmp c3(cmp_en0,n[6],n[7],min3);
cmp c4(cmp_en0,n[8],n[9],min4);
cmp c5(cmp_en0,n[10],n[11],min5);
cmp c6(cmp_en0,n[12],n[13],min6);
cmp c7(cmp_en0,n[14],n[15],min7);
cmp c8(cmp_en0,n[16],n[17],min8);
cmp c9(cmp_en0,n[18],n[19],min9);
cmp c10(cmp_en0,n[20],n[21],min10);
cmp c11(cmp_en0,n[22],n[23],min11);
cmp c12(cmp_en0,n[24],n[25],min12);
cmp c13(cmp_en0,n[26],n[27],min13);
cmp c14(cmp_en0,n[28],n[29],min14);
cmp c15(cmp_en0,n[30],n[31],min15);
cmp
cmp
cmp
cmp
cmp
cmp
cmp
cmp

c16(cmp_en1,min0,min1,min16);
c17(cmp_en1,min2,min3,min17);
c18(cmp_en1,min4,min5,min18);
c19(cmp_en1,min6,min7,min19);
c20(cmp_en1,min8,min9,min20);
c21(cmp_en1,min10,min11,min21);
c22(cmp_en1,min12,min13,min22);
c23(cmp_en1,min14,min15,min23);

cmp
cmp
cmp
cmp

c24(cmp_en2,min16,min17,min24);
c25(cmp_en2,min18,min19,min25);
c26(cmp_en2,min20,min21,min26);
c27(cmp_en2,min22,min23,min27);

cmp c28(cmp_en3,min24,min25,min28);
cmp c29(cmp_en3,min26,min27,min29);
cmp c30(cmp_en4,min28,min29,min_val);

always @(posedge clk or negedge reset)

begin
if(!reset)
begin
cmp_en0 = 1b0;
cmp_en1 =1b0;
cmp_en2 = 1b0;
cmp_en3 = 1b0;
cmp_en4 = 1b0;
state = st0;
end
else
begin
case(state)
st0: begin
cmp_en0 = 1b1;
state = st1;
end
st1: begin
cmp_en0
cmp_en1
state =
end
st2: begin
cmp_en1
cmp_en2
state =
end
st3: begin
cmp_en2
cmp_en3
state =
end
st4: begin
cmp_en3
cmp_en4
state =
end

= 1b0;
= 1b1;
st2;

= 1b0;
= 1b1;
st3;

= 1b0;
= 1b1;
st4;

= 1b0;
= 1b1;
st4;

endcase
end
end
endmodule

Experiment-1

Task 1: Simulate the 1-bit full-adder program in Xilinx ISE. Also, write a .ucf file and get the full-adder program
running on the FPGA board.
Task 2: Write a comparator module in Verilog for comparing two numbers. Use this module along with the
Verilog module above for parallel binary-tree structured comparison to find the minimum of a set of 32 numbers.
Simulate the minimum finder.