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4 Bit Binary Full Adder

This experiment teaches students how binary addition works using 4-bit and 8-bit full adders built from 7483 integrated circuits, including cascading two 4-bit adders to create an 8-bit adder and using a 4-bit adder and XOR gates to implement a 4-bit adder/subtractor under 2's complement arithmetic. Students will learn the functionality of the 7483 chip by testing sample input patterns on a simulated virtual circuit and verifying the resulting sums and carries.

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Yellasiri Suresh
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1K views7 pages

4 Bit Binary Full Adder

This experiment teaches students how binary addition works using 4-bit and 8-bit full adders built from 7483 integrated circuits, including cascading two 4-bit adders to create an 8-bit adder and using a 4-bit adder and XOR gates to implement a 4-bit adder/subtractor under 2's complement arithmetic. Students will learn the functionality of the 7483 chip by testing sample input patterns on a simulated virtual circuit and verifying the resulting sums and carries.

Uploaded by

Yellasiri Suresh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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About the Experiment

This experiment enables a student to learn:

How to realize the functionality of IC 7483, a 4 bit binary full adder

How to realize the functionality of 8 bit full adder by carcading two 7483 chips(two 4
bit full adder)

how to implement a 4 bit adder/substractor.

Aim of the Experiment

The objective of part 1 of the experiment is to fully understand the functionality of 4 bit
binary full adder.
The objective of part 2 of the experiment is to fully understand the functionality of 8 bit full
adder by carcading to 7483 chips(two 4 bit full adder).
The objective of part 3 of the experiment is to fully understand the functiponality and
implementation of 4 bit adder/subtractor.

IC 7483 is 4-bit binary full adder which accepts two 4-bit binary words A3A2A1A0 and
B3B2B1B0 and a carry input (C0) as inputs and produces a 4-bit binary sum output S3S2S1S0
and a carry output C4.

Figure 1
The students of virtual DEC Laboratory can verify the functionality of the 7483
chip.Although in principle,there can be 29=512 input paterns possible,the students can verify
all zero,all one and some other patterns.

Part II
Cascading of two 7483 chips to achieve addition of two 8-bit numbers A =
A8A7A6A5A4A3A2A1 and B = B8B7B6B5B4B3B2B1 to produce Sum = S8S7S6S5S4S3S2S1 and
carry output C9 of the 217 input patterns possible , the students can test the 8bit adder for all
zeros , all ones and some other input patterns.

Figure 2
Part III
To implement a 4 bit adder/subtractor using 2's complement number system.Students learnt
the use of 7486 (qued 2-input Ex-OR gates)in experiment 3.Using a 7483(parallel adder) and
a 7486 chip one can realize 4 bit adder/subtractor.If ADD/SUB = "0" normal addition S = A +
B performed.On the other hand if ADD/SUB = "1" then S = A + [B] + 1 where [B] = 1's
complement of B. For example,if A = 0111(7) and B = 0101(5) then [B] = 1010 and S = 0010
or 2 neglecting carry out C4.If however A = 0101(5) and B = 0111(7) then B = 1000; or S =
1110 which represents -2 in 2's complement number system.

1. At first click on the Vcc switch that means Vcc = 1 and GND = 0 , show message
Vcc & GND properly connected.

2. Next, A0= 1, A1= 0, A2= 0, A3= 0 and B0= 1, B1= 0, B2= 0, B3= 0 now you can see
the output result of S0= 0, S1= 1, S2= 0, S3= 0 and C4= 0.

3. Next, A0= 0, A1= 0, A2= 0, A3= 0 and B0= 1, B1= 1, B2= 0, B3= 0 now you can see
the output result of S0= 1, S1= 1, S2= 0, S3= 0 and C4= 0.

4. Next, A0= 0, A1= 0, A2= 0, A3= 1 and B0= 0, B1= 0, B2= 0, B3= 1 now you can see
the output result of S0= 0, S1= 0, S2= 0, S3= 0 and C4= 1.

5. Next, A0= 1, A1= 1, A2= 1, A3= 1 and B0= 1, B1= 1, B2= 1, B3= 1 now you can see
the output result of S0= 0, S1= 1, S2= 1, S3= 1 and C4= 1.

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