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    C411 L07 Pass Tran Logic

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    ajayroy12
    This document discusses pass transistor logic and its advantages over static CMOS logic. It describes how pass transistor logic gates work using only NMOS or PMOS transistors instead of both. Issues with voltage swings and static power consumption in pass transistor logic are covered, along with solutions like level restoration, multiple threshold voltage transistors, and transmission gates.

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    C411 L07 Pass Tran Logic

    Uploaded by

    ajayroy12
    27 views28 pages
    This document discusses pass transistor logic and its advantages over static CMOS logic. It describes how pass transistor logic gates work using only NMOS or PMOS transistors instead of both. Issues with voltage swings and static power consumption in pass transistor logic are covered, along with solutions like level restoration, multiple threshold voltage transistors, and transmission gates.

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    C411L07PassTranLogic

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    This document discusses pass transistor logic and its advantages over static CMOS logic. It describes how pass transistor logic gates work using only NMOS or PMOS transistors instead of both. Issues with voltage swings and static power consumption in pass transistor logic are covered, along with solutions like level restoration, multiple threshold voltage transistors, and transmission gates.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    27 views28 pages

    C411 L07 Pass Tran Logic

    Uploaded by

    ajayroy12
    This document discusses pass transistor logic and its advantages over static CMOS logic. It describes how pass transistor logic gates work using only NMOS or PMOS transistors instead of both. Issues with voltage swings and static power consumption in pass transistor logic are covered, along with solutions like level restoration, multiple threshold voltage transistors, and transmission gates.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 28

    CMPEN 411

    VLSI Digital Circuits


    Spring 2011
    Lecture 07: Pass Transistor Logic

    [Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003


    J. Rabaey, A. Chandrakasan, B. Nikolic]

    Sp11 CMPEN 411 L07 S.1

    Heads up
    

    This lecture
    

    Pass transistor logic


    - Reading assignment Rabaey, et al, 6.2.3

    Next lecture
    

    MOS transistor dynamic behavior


    - Reading assignment Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

    Wiring capacitance
    - Reading assignment Rabaey, et al, 4.1-4.3.1

    Sp11 CMPEN 411 L07 S.2

    Review: Static Complementary CMOS


    

    High noise margins


    

    VDD
    In1
    In2

    In1
    In2
    InN

    Low output impedance, high


    input impedance

    No static power consumption

    PUN

    InN

    F(In1,In2,:InN)
    PDN

    PUN and PDN are dual logic networks

    Sp11 CMPEN 411 L07 S.3

    VOH and VOL are at VDD and


    GND, respectively

    Never a direct path between


    VDD and GND in steady state

    Delay a function of load


    capacitance and transistor on
    resistance
     Comparable rise and fall
    times (under the appropriate
    relative transistor sizing
    conditions)
    

    Review: Static Complementary CMOS


    

    VDD
    In1
    In2

    Why PUN use only PMOS and


    PDN use only NMOS?

    PUN

    InN
    In1
    In2
    InN

    Question:

    F(In1,In2,:InN)
    PDN

    PUN and PDN are dual logic networks

    ANSWER:
    NMOS transistors pass a
    ______ 0 but a _____ 1
    PMOS transistors pass a
    ______ 1 but a ______ 0

    Sp11 CMPEN 411 L07 S.4

    NMOS Transistors in Series/Parallel


    

    Primary inputs drive both gate and source/drain


    terminals

    NMOS switch closes when the gate input is ______


    A

    X = Y if ______

    X
    

    X = Y if _______
    Y

    Remember - NMOS transistors pass a ______ 0 but a


    ______1

    Sp11 CMPEN 411 L07 S.5

    PMOS Transistors in Series/Parallel


    

    Primary inputs drive both gate and source/drain


    terminals

    PMOS switch closes when the gate input is low


    A

    X = Y if _______________

    X = Y if ____________
    Y

    Remember - PMOS transistors pass a ______ 1 but a


    _____0

    Sp11 CMPEN 411 L07 S.6

    Pass Transistor (PT) Logic


    B

    B
    A
    0

    F = _____

    A
    B

    F = _____

    Gate is ______ a path exists to both supply rails under


    all circumstances
     ____ transistors instead of 2N (for CMOS)
     No static power consumption
     Ratioless
     Bidirectional (versus undirectional)
    

    Sp11 CMPEN 411 L07 S.7

    VTC of PT AND Gate


    B
    1.5/0.25

    Vout, V

    0.5/0.25

    B=VDD, A=0VDD
    1

    0.5/0.25

    B
    0

    0.5/0.25

    A=VDD, B=0VDD
    A=B=0VDD

    F= AB
    0
    0

    Pure PT logic is not regenerative - the signal


    gradually degrades after passing through a number
    of PTs (can fix with static CMOS inverter insertion)

    Sp11 CMPEN 411 L07 S.8

    Differential PT Logic (DPL/CPL)

    A
    A
    B
    B

    PT Network

    A
    A
    B
    B

    Inverse PT
    Network

    F=AB

    F=AB

    B
    AND/NAND
    Sp11 CMPEN 411 L07 S.9

    F=A+B

    B
    A

    F=AB

    F=A+B

    F=AB
    A

    OR/NOR

    Why NFET?

    XOR/XNOR

    CPL Properties
    

    Differential so complementary data inputs and outputs


    are always available (so dont need extra inverters)

    Still static, since the output defining nodes are always


    tied to VDD or GND through a low resistance path

    Design is _________; all gates use the same topology,


    only the inputs are permuted.

    Simple XOR makes it attractive for structures like ______

    Fast (assuming number of transistors in series is small)

    Additional routing overhead for complementary signals

    Sp11 CMPEN 411 L07 S.10

    CPL Full Adder


    B

    Cin

    Cin

    !Sum

    Sum
    B

    Cin

    A
    B

    !Cout
    Cin

    A
    B

    Sp11 CMPEN 411 L07 S.11

    Cin

    Cout
    Cin

    CPL Full Adder


    B

    Cin

    Cin

    !Sum

    Sum
    B

    Cin

    A
    B

    !Cout
    Cin

    A
    B

    Sp11 CMPEN 411 L07 S.12

    Cin

    Cout
    Cin

    NMOS Only PT Driving an Inverter


    Vx = ___
    In = VDD
    A = VDD

    VGS
    D

    M2

    S
    B

    M1

    Vx does not pull up to VDD, but _________

    Threshold voltage drop causes static power


    consumption (M2 may be weakly conducting forming a
    path from VDD to GND)

    Notice VTn increases for pass transistor due to body


    effect (VSB)

    Sp11 CMPEN 411 L07 S.13

    Voltage Swing of PT Driving an Inverter


    3

    In

    In = 0 VDD
    1.5/0.25

    Out

    0.5/0.25

    0.5/0.25

    Voltage, V

    VDD

    x = 1.8V

    Out
    0
    0

    0.5

    1.5

    Time, ns

    Body effect large VSB at x - when pulling high (B is


    tied to GND and S charged up close to VDD)

    So the voltage drop is even worse


    Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))

    Sp11 CMPEN 411 L07 S.14

    Cascaded NMOS Only PTs


    B = VDD

    B = VDD C = VDD

    A = VDD

    M1

    x = VDD - VTn1

    C = VDD

    M1

    M2

    Out

    M2

    Out

    Swing on y = VDD - VTn1 - VTn2

    A = VDD

    Swing on y = VDD - VTn1

    Pass transistor gates should never be cascaded as on


    the left
    Logic on the right suffers from static power dissipation
    and reduced noise margins

    Sp11 CMPEN 411 L07 S.15

    Solution 1: Level Restorer


    Level Restorer
    on
    Mr

    off

    B
    A=1
    A=0

    Mn

    x= 0
    1

    M2

    Out=0
    Out =1

    M1

    Full swing on x (due to Level Restorer) so no static


    power consumption by inverter

    No static backward current path through Level Restorer


    and PT since Restorer is only active when A is high

    For correct operation Mr must be sized correctly (ratioed)

    Sp11 CMPEN 411 L07 S.16

    Transient Level Restorer Circuit Response


    3

    W/L2=1.50/0.25
    W/Ln=0.50/0.25
    W/L1=0.50/0.25

    Voltage, V

    2
    W/Lr=1.75/0.25

    node x never goes below VM


    of inverter so output never
    switches

    W/Lr=1.50/0.25

    W/Lr=1.25/0.25
    W/Lr=1.0/0.25

    0
    0
    

    100

    200

    Time, ps

    300

    400

    500

    Restorer has speed and power impacts: increases the


    capacitance at x, slowing down the gate; increases tr (but
    decreases tf)

    Sp11 CMPEN 411 L07 S.17

    Solution 2: Multiple VT Transistors


    

    Technology solution: Use (near) zero VT devices for the


    NMOS PTs to eliminate most of the threshold drop (body
    effect still in force preventing full swing to VDD)
    low VT transistors
    In2 = 0V

    A = 2.5V

    on
    Out

    off but
    leaking

    In1 = 2.5V

    B = 0V

    sneak path

    Impacts static power consumption due to subthreshold


    currents flowing through the PTs (even if VGS is below VT)

    Sp11 CMPEN 411 L07 S.18

    Solution 3: Transmission Gates (TGs)


    

    Most widely used


    solution

    C
    A

    B
    C

    C
    C = GND
    A = VDD

    B
    C = VDD

    C = GND
    A = GND

    B
    C = VDD

    Full swing bidirectional switch controlled by the gate


    signal C, A = B if C = 1

    Sp11 CMPEN 411 L07 S.19

    Solution 3: Transmission Gates (TGs)


    

    Most widely used


    solution

    C
    A

    B
    C

    C
    C = GND
    A = VDD

    B
    C = VDD

    C = GND
    A = GND

    B
    C = VDD

    Full swing bidirectional switch controlled by the gate


    signal C, A = B if C = 1, minimum size (ratioless)

    Sp11 CMPEN 411 L07 S.20

    TG Multiplexer
    S

    S
    VDD

    In2
    S

    In1
    S
    F = !(In1 S + In2 S)

    GND
    In1

    Sp11 CMPEN 411 L07 S.21

    In2

    Transmission Gate XOR

    AB

    How many FETs for CMOS implementation? 10-12


    Sp11 CMPEN 411 L07 S.22

    Transmission Gate XOR

    on
    off
    A
    off
    on
    0
    B
    1

    Sp11 CMPEN 411 L07 S.23

    A !B
    AB
    B !A

    an inverter

    TG Full Adder

    Cin
    B

    Sum

    Cout

    How many transistors?


    Sp11 CMPEN 411 L07 S.24

    Differential TG Logic (DPL)


    B

    F=AB

    GND

    F=AB

    GND

    VDD

    F=AB

    VDD

    B
    AND/NAND

    Sp11 CMPEN 411 L07 S.25

    F=AB

    XOR/XNOR

    6-transistor SRAM Storage Cell


    WL

    M2
    M5

    M4
    Q

    M6

    !Q
    M1

    M3

    !BL

    Will cover how the cell works in detail later

    Sp11 CMPEN 411 L07 S.26

    BL

    MOS OR ROM Cell Array


    0

    BL(0)

    BL(1)

    BL(2)

    BL(3)

    WL(0)
    VDD

    0 1 WL(1)
    0

    on

    on

    WL(2)
    VDD

    WL(3)
    predischarge
    1 0

    Sp11 CMPEN 411 L07 S.27

    Next Lecture and Reminders


    

    Next lecture
    

    MOS transistor dynamic behavior


    - Reading assignment Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

    Wiring capacitance
    - Reading assignment Rabaey, et al, 4.1-4.3.1

    Sp11 CMPEN 411 L07 S.28

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