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This document contains an assignment for an ECE course covering topics in digital logic and Verilog HDL including: 1) Converting numbers between binary, hexadecimal, and decimal. 2) Identifying legal and illegal Verilog identifiers. 3) Describing the basic components of a Verilog module and which are mandatory. 4) Designing a logic circuit for a 1-bit full adder using only AND, OR, and NOT gates and writing the equivalent Verilog description. 5) Providing examples of Verilog gates, data types, modeling styles, system tasks and functions, compiler directives, and gate delays.

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100 views2 pages

Assignment 1

This document contains an assignment for an ECE course covering topics in digital logic and Verilog HDL including: 1) Converting numbers between binary, hexadecimal, and decimal. 2) Identifying legal and illegal Verilog identifiers. 3) Describing the basic components of a Verilog module and which are mandatory. 4) Designing a logic circuit for a 1-bit full adder using only AND, OR, and NOT gates and writing the equivalent Verilog description. 5) Providing examples of Verilog gates, data types, modeling styles, system tasks and functions, compiler directives, and gate delays.

Uploaded by

LakshminathSinganapudi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MUFFAKHAM JAH COLLEGE OF ENGINEERING TECHNOLOGY

ECE IV/IV-I SEMESTER

SECTION-A

2012-2013

ASSIGNMENT-1
1. Write the following numbers:

a. Decimal number 123 as a sized 8-bit number in binary. Use _ for readability.
b. A 16-bit hexadecimal unknown number with all x's.
c. A 4-bit negative 2 in decimal. Write the 2's complement form for this number.
d. An unsized hex number 1234.
2. Are these legal identifiers?
a. system1
b. 1reg
c. $latch
d. exec$
3. What are the basic components of a module? Which components are mandatory?
4. Does a module that does not interact with its environment have any I/O ports? Does it have a
port list in the module definition?
5. The 1-bit full adder described in the chapter can be expressed in a sum of products form.
sum = a.b.c_in + a'.b.c_in' + a'.b'.c_in + a.b'.c_in'
c_out = a.b + b.c_in + a.c_in
Assuming a, b, c_in are the inputs and sum and c_out are the outputs, design a logic circuit to
implement the 1-bit full adder, using only and, not, and or gates. Write the Verilog description
for the circuit. You may use up to 4-input Verilog primitive and and or gates. Write the
stimulus for the full adder and check the functionality for all input combinations.
6. Types of Verilog gates with their syntax.
7. A) Types of data types in Verilog HDL. B) Different modeling styles in Verilog HDL.

8. Write about System tasks and system function examples.


9. A) Compiler directive examples. B) Difference between simulation and synthesis.
10. Explain with an example about gate delays with output waveforms.

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