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Use If-Else Statement To Generate D-Latch With Reset Input, Also Verify The Result With RTL, Technology Schematic

This document outlines 9 Verilog design tasks including: 1) designing decoders and encoders, 2) designing a configurable full adder, 3) designing a shift register, 4) implementing a logic expression using gates, 5) designing a D-latch and flip-flop using if-else statements, 6) designing a 16:1 multiplexer using case statements, and 7) designing an 8:1 multiplexer using casez and casex statements. The tasks involve different modeling styles such as gate-level, dataflow, and behavioral modeling.

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senthil
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32 views1 page

Use If-Else Statement To Generate D-Latch With Reset Input, Also Verify The Result With RTL, Technology Schematic

This document outlines 9 Verilog design tasks including: 1) designing decoders and encoders, 2) designing a configurable full adder, 3) designing a shift register, 4) implementing a logic expression using gates, 5) designing a D-latch and flip-flop using if-else statements, 6) designing a 16:1 multiplexer using case statements, and 7) designing an 8:1 multiplexer using casez and casex statements. The tasks involve different modeling styles such as gate-level, dataflow, and behavioral modeling.

Uploaded by

senthil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab 2

1. Design Decoders with following specifications


a. 2:4 using gate level modeling.
b. 4:16 using shift operator.
2. Design 8:3 priority encoder using dataflow modeling.
3. Design configurable full adder using parameter construct (Test it for 8 bit and 16
bit full adder). Use $Strobe for Displaying result on transcript.
4. Design parallel in parallel out 8-bit rotational right shift register with a clock, load
input using
a. Blocking
b. Non-Blocking.
5. Implement Y= A|B|C + A.B.E + |B.C + C|D using delay value 3 for and gates, 2 for
or gates and 4 for not gates. Use two inputs and, or gates only. Use $Monitor for
displaying result on transcript ,also turn off display for 50 time units and then
continue displaying the results.
6. Use if-else statement to generate D-Latch with reset input, also verify the result with
RTL, Technology Schematic.

7. Design Flip-Flop using


a. D-latch of question 6 (Asynchronous Reset).
b. If-else Statement (synchronous reset).
8. Design 16: 1 Mux using case statement. Also display current state on the transcript.
9. Design and verify the functionality of a 8:1 Mux using
a. Casez Statement
b. Casex Statement

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