TMS320F2802x, 2803x Piccolo Enhanced

Capture (eCAP) Module

Reference Guide

Literature Number: SPRUFZ8A

May 2009 Revised October 2009

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Preface ....................................................................................................................................... 6
1
Introduction ........................................................................................................................ 8
2
Description ......................................................................................................................... 8
3
Capture and APWM Operating Mode ..................................................................................... 9
4
Capture Mode Description .................................................................................................. 10

........................................................................................................
4.2
Edge Polarity Select and Qualifier ...................................................................................
4.3
Continuous/One-Shot Control ........................................................................................
4.4
32-Bit Counter and Phase Control ...................................................................................
4.5
CAP1-CAP4 Registers ................................................................................................
4.6
Interrupt Control ........................................................................................................
4.7
Shadow Load and Lockout Control ..................................................................................
4.8
APWM Mode Operation ...............................................................................................
5
Capture Module - Control and Status Registers .....................................................................
6
Register Mapping ..............................................................................................................
7
Application of the ECAP Module .........................................................................................
7.1
Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger .............................................
7.2
Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ...............................
7.3
Example 3 - Time Difference (Delta) Operation Rising Edge Trigger ...........................................
7.4
Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger .............................
8
Application of the APWM Mode ...........................................................................................
8.1
Example 1 - Simple PWM Generation (Independent Channel/s) ................................................
Appendix A Revision History ......................................................................................................
4.1

Event Prescaler

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List of Figures
1

Capture and APWM Modes of Operation ................................................................................ 9

Capture Function Diagram ............................................................................................... 10

Event Prescale Control ................................................................................................... 11

Prescale Function Waveforms ........................................................................................... 11

Details of the Continuous/One-shot Block

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

.............................................................................
Details of the Counter and Synchronization Block ....................................................................
Interrupts in eCAP Module ...............................................................................................
PWM Waveform Details Of APWM Mode Operation .................................................................
Time-Stamp Counter Register (TSCTR) ...............................................................................
Counter Phase Control Register (CTRPHS) ..........................................................................
Capture-1 Register (CAP1) ..............................................................................................
Capture-2 Register (CAP2) ..............................................................................................
Capture-3 Register (CAP3) ..............................................................................................
Capture-4 Register (CAP4) ..............................................................................................
ECAP Control Register 1 (ECCTL1) ....................................................................................
ECAP Control Register 2 (ECCTL2) ....................................................................................
ECAP Interrupt Enable Register (ECEINT) ............................................................................
ECAP Interrupt Flag Register (ECFLG) ................................................................................
ECAP Interrupt Clear Register (ECCLR) ...............................................................................
ECAP Interrupt Forcing Register (ECFRC) ............................................................................
Capture Sequence for Absolute Time-stamp and Rising Edge Detect .............................................
Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect ..............................
Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect .........................................
Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect ..........................
PWM Waveform Details of APWM Mode Operation ..................................................................

List of Figures

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15
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22
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23
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29
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33

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List of Tables
1

Time-Stamp Counter Register (TSCTR) Field Descriptions ......................................................... 16

Counter Phase Control Register (CTRPHS) Field Descriptions..................................................... 16

Capture-1 Register (CAP1) Field Descriptions ........................................................................ 16

Capture-2 Register (CAP2) Field Descriptions ........................................................................ 16

Capture-3 Register (CAP3) Field Descriptions ........................................................................ 17

Capture-4 Register (CAP4) Field Descriptions ........................................................................ 17

ECAP Control Register 1 (ECCTL1) Field Descriptions .............................................................. 17

ECAP Control Register 2 (ECCTL2) Field Descriptions .............................................................. 19

ECAP Interrupt Enable Register (ECEINT) Field Descriptions ...................................................... 21

10

ECAP Interrupt Flag Register (ECFLG) Field Descriptions .......................................................... 22

11

ECAP Interrupt Clear Register (ECCLR) Field Descriptions

23

12

ECAP Interrupt Forcing Register (ECFRC) Field Descriptions

23

13
14

........................................................
.....................................................
Control and Status Register Set .........................................................................................
Changes Made in This Revision .........................................................................................

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34

Preface
SPRUFZ8A May 2009 Revised October 2009

Read This First

The enhanced capture (eCAP) module is used in systems where accurate timing of external events is
important. This guide describes the TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module
module and how to use it.
The eCAP module described in this reference guide is a Type 0 eCAP. See the TMS320C28xx, 28xxx
DSP Peripheral Reference Guide (SPRU566) for a list of all devices with a eCAP module of the same
type, to determine the differences between the types, and for a list of device-specific differences within a
type.

Related Documentation From Texas Instruments

The following documents describe the TMS320C2802x, 2803x Piccolo devices and related support tools
and can be downloaded from the TI website (www.ti.com):
Data Manuals
SPRS523 TMS320F28020, TMS320F28021, TMS320F28022, TMS320F28023, TMS320F28026,
TMS320F28027 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions,
as well as electrical and timing specifications for the 2802x devices.
SPRZ292 TMS320F28020, TMS320F28021, TMS320F28022, TMS320F28023, TMS320F28026,
TMS320F28027 Piccolo MCU Silicon Errata describes known advisories on silicon and provides
workarounds.
SPRS584 TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo
Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and
timing specifications for the 2803x devices.
SPRZ295 TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo MCU Silicon
Errata describes known advisories on silicon and provides workarounds.
CPU User's Guides
SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing
unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal
processors (DSPs). It also describes emulation features available on these DSPs.
Peripheral Guides
SPRUFN3 TMS320x2802x Piccolo System Control and Interrupts Reference Guide describes the
various interrupts and system control features of the 2802x microcontrollers (MCUs).
SPRUGL8 TMS320x2803x Piccolo System Control and Interrupts Reference Guide describes the
various interrupts and system control features of the 2803x microcontrollers (MCUs).
SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral
reference guides of the 28x digital signal processors (DSPs).
SPRUGO0 TMS320x2803x Piccolo Boot ROM Reference Guide describes the purpose and features
of the bootloader (factory-programmed boot-loading software) and provides examples of code. It
also describes other contents of the device on-chip boot ROM and identifies where all of the
information is located within that memory.

Preface

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Related Documentation From Texas Instruments

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SPRUFN6 TMS320x2802x Piccolo Boot ROM Reference Guide describes the purpose and features
of the bootloader (factory-programmed boot-loading software) and provides examples of code. It
also describes other contents of the device on-chip boot ROM and identifies where all of the
information is located within that memory.
SPRUGE6 TMS320x2803x Piccolo Control Law Accelerator (CLA) Reference Guide describes the
operation of the Control Law Accelerator (CLA).
SPRUGE2 TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guide
describes the operation of the Local Interconnect Network (LIN) Module.
SPRUFK8 TMS320x2803x Piccolo Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide
describes the operation of the Enhanced Quadrature Encoder Pulse (eQEP) module, which is used
for interfacing with a linear or rotary incremental encoder to get position, direction, and speed
information from a rotating machine in high performance motion and position control systems. It
includes the module description on registers.
SPRUGL7 TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN) Reference Guide
describes the operation of the Enhanced Controller Area Network (eCAN) which uses established
protocol to communicate serially with other controllers in electrically noisy environments.
SPRUGE5 TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator
Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit
pipelined ADC.
SPRUGE9 TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module
Reference Guide describes the main areas of the enhanced pulse width modulator that include
digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and
other forms of power conversion.
SPRUGE8 TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM)
describes the operation of the high-resolution extension to the pulse width modulator (HRPWM).
SPRUGH1 TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference
Guide describes how to use the SCI.
SPRUFZ8 TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guide
describes the enhanced capture module. It includes the module description and registers.
SPRUG71 TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide
describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit
stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmed bit-transfer rate.
SPRUFZ9 TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describes
the features and operation of the inter-integrated circuit (I2C) module.
Tools Guides
SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly
language tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the
TMS320C28x device.
SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the
TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and
produces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction
set of the C28x core.

Piccolo, TMS320C28x, C28x are trademarks of Texas Instruments.

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Reference Guide
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Enhanced Capture (eCAP) Module

The enhanced Capture (eCAP) module is essential in systems where accurate timing of external events is
important.
This reference guide is applicable for the eCAP found on the TMS320x2802x, 2803x Piccolo family of
processors. This includes all Flash-based, ROM-based, and RAM-based devices within the 2834x family .

Introduction
Uses for eCAP include:
Speed measurements of rotating machinery (e.g., toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module described in this guide includes the following features:
4-event time-stamp registers (each 32 bits)
Edge polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event time-stamps
Continuous mode capture of time-stamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All above resources dedicated to a single input pin
When not used in capture mode, the ECAP module can be configured as a single channel PWM output

Description
The eCAP module represents one complete capture channel that can be instantiated multiple times
depending on the target device. In the context of this guide, one eCAP channel has the following
independent key resources:
Dedicated input capture pin
32-bit time base (counter)
4 x 32-bit time-stamp capture registers (CAP1-CAP4)
4-stage sequencer (Modulo4 counter) that is synchronized to external events, ECAP pin rising/falling
edges.
Independent edge polarity (rising/falling edge) selection for all 4 events
Input capture signal prescaling (from 2-62)
One-shot compare register (2 bits) to freeze captures after 1 to 4 time-stamp events
Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4) scheme
Interrupt capabilities on any of the 4 capture events

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Capture and APWM Operating Mode

You can use the eCAP module resources to implement a single-channel PWM generator (with 32 bit
capabilities) when it is not being used for input captures. The counter operates in count-up mode,
providing a time-base for asymmetrical pulse width modulation (PWM) waveforms. The CAP1 and CAP2
registers become the active period and compare registers, respectively, while CAP3 and CAP4 registers
become the period and capture shadow registers, respectively. Figure 1 is a high-level view of both the
capture and auxiliary pulse-width modulator (APWM) modes of operation.
Figure 1. Capture and APWM Modes of Operation

SyncIn

Capture
mode

Counter (timer)
32

Note:
Same pin
depends on
operating
mode

CAP1 reg
CAP2 reg
CAP3 reg

Sequencing
Edge detection
Edge polarity
Prescale

ECAPx
pin

CAP4 reg
ECAPxINT

Interrupt I/F

Or

SyncIn

APWM
mode

Counter (timer)
32

Syncout

Period reg
(active) (CAP1)
Compare reg
(active) (CAP2)
Period reg
(shadow) (CAP3)

PWM
Compare logic

APWMx
pin

Compare reg
(shadow) (CAP4)
ECAPxINT

Interrupt I/F

A single pin is shared between CAP and APWM functions. In capture mode, it is an input; in APWM mode, it is an
output.

In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the corresponding
shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes
the shadow mode.

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Capture Mode Description

Figure 2 shows the various components that implement the capture function.
Figure 2. Capture Function Diagram
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]

SYNC

CTRPHS
(phase register32 bit)
SYNCIn

APWM mode
CTR_OVF

OVF
TSCTR
(counter32 bit)

SYNCOut

RST

CTR [031]

Deltamode

PRD [031]

PWM
compare
logic

CMP [031]
32
CTR=PRD

CTR [031]

CTR=CMP
32
PRD [031]
ECCTL1 [ CAPLDEN, CTRRSTx]

CAP1
(APRD active)
APRD
shadow

LD1

MODE SELECT

ECAPx
32

Polarity
select

LD

32
CMP [031]

32

32

CAP2
(ACMP active)

32

32

32

LD

LD2

Polarity
select
Event
qualifier

ACMP
shadow

CAP3
(APRD shadow)

LD

CAP4
(ACMP shadow)

LD

Event
Prescale

Polarity
select

LD3

LD4

ECCTL1[EVTPS]

Polarity
select

4
Capture events

Edge Polarity Select

ECCTL1[CAPxPOL]
4

CEVT[1:4]

to PIE

Interrupt
Trigger
and
Flag
control

CTR_OVF

Continuous /
Oneshot
Capture Control

CTR=PRD
CTR=CMP
ECCTL2 [ REARM, CONT/ONESHT, STOP_WRAP]

Registers: ECEINT, ECFLG, ECCLR, ECFRC

4.1

Event Prescaler

10

An input capture signal (pulse train) can be prescaled by N = 2-62 (in multiples of 2) or can bypass the
prescaler.
This is useful when very high frequency signals are used as inputs. Figure 3 shows a functional
diagram and Figure 4 shows the operation of the prescale function.

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Figure 3. Event Prescale Control

Event prescaler
0
PSout
1

Bypass

ECAPx pin
(from GPIO)

/n
5
ECCTL1[EVTPS]
prescaler [5 bits]
(counter)

When a prescale value of 1 is chosen (i.e. ECCTL1[13:9] = 0,0,0,0,0 ) the input capture signal by-passes the prescale
logic completely.

Figure 4. Prescale Function Waveforms

ECAPx

PSout
div 2

PSout
div 4
PSout
div 6
PSout
div 8
PSout
div 10

4.2

Edge Polarity Select and Qualifier

4.3

Four independent edge polarity (rising edge/falling edge) selection MUXes are used, one for each
capture event.
Each edge (up to 4) is event qualified by the Modulo4 sequencer.
The edge event is gated to its respective CAPx register by the Mod4 counter. The CAPx register is
loaded on the falling edge.

Continuous/One-Shot Control

The Mod4 (2 bit) counter is incremented via edge qualified events (CEVT1-CEVT4).
The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped.
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4
counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.

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The continuous/one-shot block controls the start/stop and reset (zero) functions of the Mod4 counter via a
mono-shot type of action that can be triggered by the stop-value comparator and re-armed via software
control.
Once armed, the eCAP module waits for 1-4 (defined by stop-value) capture events before freezing both
the Mod4 counter and contents of CAP1-4 registers (i.e., time-stamps).
Re-arming prepares the eCAP module for another capture sequence. Also re-arming clears (to zero) the
Mod4 counter and permits loading of CAP1-4 registers again, providing the CAPLDEN bit is set.
In continuous mode, the Mod4 counter continues to run (0->1->2->3->0, the one-shot action is ignored,
and capture values continue to be written to CAP1-4 in a circular buffer sequence.
Figure 5. Details of the Continuous/One-shot Block
0 1 2 3
2:4 MUX

CEVT1
CEVT2
CEVT3
CEVT4

CLK
Modulo 4
counter Stop
RST

Mod_eq

Oneshot
control logic

Stop value (2b)

ECCTL2[STOP_WRAP]

4.4

ECCTL2[REARM]
ECCTL2[CONT/ONESHT]

32-Bit Counter and Phase Control

This counter provides the time-base for event captures, and is clocked via the system clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software
forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time
difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4
signals.

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Figure 6. Details of the Counter and Synchronization Block

SYNC
ECCTL2[SWSYNC]

ECCTL2[SYNCOSEL]
SYNCI
CTR=PRD
Disable
Disable

ECCTL2[SYNCI_EN]

SYNCO
Sync out
select

CTRPHS

LD_CTRPHS

RST

Deltamode

TSCTR
(counter 32b)
SYSCLK

CLK

OVF

CTROVF

CTR[310]

4.5

CAP1-CAP4 Registers
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (i.e., capture a
time-stamp) when their respective LD inputs are strobed.
Loading of the capture registers can be inhibited via control bit CAPLDEN. During one-shot operation, this
bit is cleared (loading is inhibited) automatically when a stop condition occurs, i.e. StopValue = Mod4.
CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode.
CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and
CAP2 during APWM operation.

4.6

Interrupt Control
An Interrupt can be generated on capture events (CEVT1-CEVT4, CTROVF) or APWM events (CTR =
PRD, CTR = CMP).
A counter overflow event (FFFFFFFF->00000000) is also provided as an interrupt source (CTROVF).
The capture events are edge and sequencer qualified (i.e., ordered in time) by the polarity select and
Mod4 gating, respectively.
One of these events can be selected as the interrupt source (from the eCAPx module) going to the PIE.
Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, CTR=PRD, CTR=CMP) can be
generated. The interrupt enable register (ECEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (ECFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated to the PIE only if any of the interrupt
events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine must clear the
global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR) before any other
interrupt pulses are generated. You can force an interrupt event via the interrupt force register (ECFRC).
This is useful for test purposes.

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Note: The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode (ECCTL2[CAP/APWM
== 0]). The CTR=PRD, CTR=CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]).
CNTOVF flag is valid in both modes.
Figure 7. Interrupts in eCAP Module
ECFLG
Clear

ECCLR
ECFRC

Latch
ECEINT

Set

CEVT1

ECFLG
Clear

ECCLR
ECFRC

Latch
ECFLG
ECEINT

ECCLR

Set
ECFLG

Clear

Clear

Latch

ECEINT

Generate
interrupt
pulse when
input=1

ECCLR
ECFRC

Latch

Set

ECAPxINT

CEVT2

Set

CEVT3

ECFLG

Clear
0

ECCLR
ECFRC

Latch
ECEINT

Set

CEVT4

ECFLG
Clear

ECCLR
ECFRC

Latch

CTROVF

Set

ECEINT
ECFLG

Clear

ECCLR
ECFRC

Latch
ECEINT

PRDEQ

Set
ECFLG
Clear
Latch

ECEINT

4.7

Set

ECCLR
ECFRC
CMPEQ

Shadow Load and Lockout Control

In capture mode, this logic inhibits (locks out) any shadow loading of CAP1 or CAP2 from APRD and
ACMP registers, respectively.
In APWM mode, shadow loading is active and two choices are permitted:
Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value.
On period equal, i.e., CTR[31:0] = PRD[31:0]

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4.8

APWM Mode Operation

Main operating highlights of the APWM section:
The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators.
When CAP1/2 registers are not used in capture mode, their contents can be used as Period and
Compare values in APWM mode.
Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4). The shadow register
contents are transferred over to CAP1/2 registers either immediately upon a write, or on a CTR = PRD
trigger.
In APWM mode, writing to CAP1/CAP2 active registers will also write the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 will invoke the shadow mode.
During initialization, you must write to the active registers for both period and compare. This
automatically copies the initial values into the shadow values. For subsequent compare updates, i.e.,
during run-time, you only need to use the shadow registers.
Figure 8. PWM Waveform Details Of APWM Mode Operation
TSCTR
FFFFFFFF
APRD

1000h

500h
ACMP

300h

0000000C
APWMx
(o/p pin)

On
time

Offtime

Period

The behavior of APWM active high mode (APWMPOL == 0) is as follows:

CMP = 0x00000000, output low for duration of period (0% duty)
CMP = 0x00000001, output high 1 cycle
CMP = 0x00000002, output high 2 cycles
CMP = PERIOD, output high except for 1 cycle (<100% duty)
CMP = PERIOD+1, output high for complete period (100% duty)
CMP > PERIOD+1, output high for complete period

The behavior of APWM active low mode (APWMPOL == 1) is as follows:

CMP = 0x00000000, output high for duration of period (0% duty)
CMP = 0x00000001, output low 1 cycle
CMP = 0x00000002, output low 2 cycles
CMP = PERIOD, output low except for 1 cycle (<100% duty)
CMP = PERIOD+1, output low for complete period (100% duty)
CMP > PERIOD+1, output low for complete period

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Capture Module - Control and Status Registers

Figure 9. Time-Stamp Counter Register (TSCTR)

31

0
TSCTR
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1. Time-Stamp Counter Register (TSCTR) Field Descriptions

Bit(s)

Field

Description

31:0

TSCTR

Active 32-bit counter register that is used as the capture time-base

Figure 10. Counter Phase Control Register (CTRPHS)

31

0
CTRPHS
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2. Counter Phase Control Register (CTRPHS) Field Descriptions

Bit(s)

Field

Description

31:0

CTRPHS

Counter phase value register that can be programmed for phase lag/lead. This register shadows
TSCTR and is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used
to achieve phase control synchronization with respect to other eCAP and EPWM time-bases.

Figure 11. Capture-1 Register (CAP1)

31

0
CAP1
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3. Capture-1 Register (CAP1) Field Descriptions

Bit(s)

Field

Description

31:0

CAP1

This register can be loaded (written) by :) Time-Stamp (i.e., counter value TSCTR) during a capture
event) Software - may be useful for test purposes / initialization) APRD shadow register (i.e.,
CAP3) when used in APWM mode

Figure 12. Capture-2 Register (CAP2)

31

0
CAP2
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. Capture-2 Register (CAP2) Field Descriptions

16

Bit(s)

Field

Description

31:0

CAP2

This register can be loaded (written) by:

Time-Stamp (i.e., counter value) during a capture event
Software - may be useful for test purposes
APRD shadow register (i.e., CAP4) when used in APWM mode

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NOTE:

In APWM mode, writing to CAP1/CAP2 active registers also writes the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the
shadow registers CAP3/CAP4 invokes the shadow mode.

Figure 13. Capture-3 Register (CAP3)

31

0
CAP3
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. Capture-3 Register (CAP3) Field Descriptions

Bit(s)

Field

Description

31:0

CAP3

In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow
(APRD) register. You update the PWM period value through this register. In this mode, CAP3
(APRD) shadows CAP1.

Figure 14. Capture-4 Register (CAP4)

31

0
CAP4
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Capture-4 Register (CAP4) Field Descriptions

Bit(s)

Field

Description

31:0

CAP4

In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow
(ACMP) register. You update the PWM compare value via this register. In this mode, CAP4
(ACMP) shadows CAP2.

Figure 15. ECAP Control Register 1 (ECCTL1)

15

14

13

12

11

10

FREE/SOFT

PRESCALE

CAPLDEN

R/W-0

R/W-0

R/W-0

CTRRST4

CAP4POL

CTRRST3

CAP3POL

CTRRST2

CAP2POL

CTRRST1

CAP1POL

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. ECAP Control Register 1 (ECCTL1) Field Descriptions

Bit(s)

Field

15:14

FREE/SOFT

13:9

Value

Description
Emulation Control

00

TSCTR counter stops immediately on emulation suspend

01

TSCTR counter runs until = 0

1x

TSCTR counter is unaffected by emulation suspend (Run Free)

PRESCALE

Event Filter prescale select

00000

Divide by 1 (i.e,. no prescale, by-pass the prescaler)

00001

Divide by 2

00010

Divide by 4

00011

Divide by 6

00100

Divide by 8

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Table 7. ECAP Control Register 1 (ECCTL1) Field Descriptions (continued)

Bit(s)

Field

Value

Description

00101

Divide by 10

...

11110

Divide by 60

11111

Divide by 62

CAPLDEN

Enable Loading of CAP1-4 registers on a capture event

0

Disable CAP1-4 register loads at capture event time.

Enable CAP1-4 register loads at capture event time.

CTRRST4

Counter Reset on Capture Event 4

0

Do not reset counter on Capture Event 4 (absolute time stamp operation)

Reset counter after Capture Event 4 time-stamp has been captured

(used in difference mode operation)

CAP4POL

Capture Event 4 Polarity select

0

Capture Event 4 triggered on a rising edge (RE)

Capture Event 4 triggered on a falling edge (FE)

CTRRST3

Counter Reset on Capture Event 3

0

Do not reset counter on Capture Event 3 (absolute time stamp)

Reset counter after Event 3 time-stamp has been captured

(used in difference mode operation)

CAP3POL

Capture Event 3 Polarity select

0

Capture Event 3 triggered on a rising edge (RE)

Capture Event 3 triggered on a falling edge (FE)

CTRRST2

Counter Reset on Capture Event 2

0

Do not reset counter on Capture Event 2 (absolute time stamp)

Reset counter after Event 2 time-stamp has been captured

(used in difference mode operation)

CAP2POL

Capture Event 2 Polarity select

0

Capture Event 2 triggered on a rising edge (RE)

Capture Event 2 triggered on a falling edge (FE)

CTRRST1

Counter Reset on Capture Event 1

0

Do not reset counter on Capture Event 1 (absolute time stamp)

Reset counter after Event 1 time-stamp has been captured (used in difference mode
operation)

CAP1POL

Capture Event 1 Polarity select

0

Capture Event 1 triggered on a rising edge (RE)

Capture Event 1 triggered on a falling edge (FE)

Figure 16. ECAP Control Register 2 (ECCTL2)

15

11

10

Reserved

APWMPOL

CAP/APWM

SWSYNC

R-0

R/W-0

R/W-0

R/W-0

SYNCO_SEL

SYNCI_EN

TSCTRSTOP

REARM

R/W-0

R/W-0

R/W-0

R/W-0

STOP_WRAP
R/W-1

R/W-1

0
CONT/ONESH
T
R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 8. ECAP Control Register 2 (ECCTL2) Field Descriptions

Bit(s)

Field

Description

15:11

Reserved

Reserved

10

APWMPOL

APWM output polarity select. This is applicable only in APWM operating mode
0

Output is active high (i.e., Compare value defines high time)

Output is active low (i.e., Compare value defines low time)

CAP/APWM

CAP/APWM operating mode select

0

ECAP module operates in capture mode. This mode forces the following
configuration:
Inhibits TSCTR resets via CTR = PRD event
Inhibits shadow loads on CAP1 and 2 registers
Permits user to enable CAP1-4 register load
CAPx/APWMx pin operates as a capture input

ECAP module operates in APWM mode. This mode forces the following
configuration:
Resets TSCTR on CTR = PRD event (period boundary
Permits shadow loading on CAP1 and 2 registers
Disables loading of time-stamps into CAP1-4 registers
CAPx/APWMx pin operates as a APWM output

SWSYNC

Software-forced Counter (TSCTR) Synchronizing. This provides a convenient

software method to synchronize some or all ECAP time bases. In APWM mode,
the synchronizing can also be done via the CTR = PRD event.
0

Writing a zero has no effect. Reading always returns a zero

Writing a one forces a TSCTR shadow load of current ECAP module and any
ECAP modules down-stream providing the SYNCO_SEL bits are 0,0. After writing
a 1, this bit returns to a zero.
Note: Selection CTR = PRD is meaningful only in APWM mode; however, you can
choose it in CAP mode if you find doing so useful.

7:6

2:1

SYNCO_SEL

Sync-Out Select
00

Select sync-in event to be the sync-out signal (pass through)

01

Select CTR = PRD event to be the sync-out signal

10

Disable sync out signal

11

Disable sync out signal

SYNCI_EN

Counter (TSCTR) Sync-In select mode

0

Disable sync-in option

Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI
signal or a S/W force event.

TSCTRSTOP

Time Stamp (TSCTR) Counter Stop (freeze) Control

0

TSCTR stopped

TSCTR free-running

RE-ARM

One-Shot Re-Arming Control, i.e. wait for stop trigger. Note: The re-arm function is
valid in one shot or continuous mode.
0

Has no effect (reading always returns a 0)

Arms the one-shot sequence as follows:

1) Resets the Mod4 counter to zero
2) Unfreezes the Mod4 counter
3) Enables capture register loads

STOP_WRAP

Stop value for one-shot mode. This is the number (between 1-4) of captures
allowed to occur before the CAP(1-4) registers are frozen, i.e., capture sequence is
stopped.
Wrap value for continuous mode. This is the number (between 1-4) of the capture
register in which the circular buffer wraps around and starts again.
00

Stop after Capture Event 1 in one-shot mode

Wrap after Capture Event 1 in continuous mode.

01

Stop after Capture Event 2 in one-shot mode

Wrap after Capture Event 2 in continuous mode.

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Table 8. ECAP Control Register 2 (ECCTL2) Field Descriptions (continued)

Bit(s)

Field

Description
10

Stop after Capture Event 3 in one-shot mode

Wrap after Capture Event 3 in continuous mode.

11

Stop after Capture Event 4 in one-shot mode

Wrap after Capture Event 4 in continuous mode.
Notes: STOP_WRAP is compared to Mod4 counter and, when equal, 2 actions
occur:
Mod4 counter is stopped (frozen)
Capture register loads are inhibited
In one-shot mode, further interrupt events are blocked until re-armed.

20

CONT/ONESHT

Continuous or one-shot mode control (applicable only in capture mode)

0

Operate in continuous mode

Operate in one-Shot mode

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Figure 17. ECAP Interrupt Enable Register (ECEINT)

15

8
Reserved

CTR=CMP

CTR=PRD

CTROVF

CEVT4

CEVT3

CEVT2

CETV1

Reserved

R/W

R/W

R/W

R/W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. ECAP Interrupt Enable Register (ECEINT) Field Descriptions

Bits

Field

15:8

Reserved

CTR=CMP

Value

Description
Counter Equal Compare Interrupt Enable

Disable Compare Equal as an Interrupt source

Enable Compare Equal as an Interrupt source

CTR=PRD

Counter Equal Period Interrupt Enable

0

Disable Period Equal as an Interrupt source

Enable Period Equal as an Interrupt source

CTROVF

Counter Overflow Interrupt Enable

0

Disabled counter Overflow as an Interrupt source

Enable counter Overflow as an Interrupt source

CEVT4

Capture Event 4 Interrupt Enable

0

Disable Capture Event 4 as an Interrupt source

Capture Event 4 Interrupt Enable

CEVT3

Capture Event 3 Interrupt Enable

0

Disable Capture Event 3 as an Interrupt source

Enable Capture Event 3 as an Interrupt source

CEVT2

Capture Event 2 Interrupt Enable

0

Disable Capture Event 2 as an Interrupt source

Enable Capture Event 2 as an Interrupt source

CEVT1

Capture Event 1 Interrupt Enable

0

Disable Capture Event 1 as an Interrupt source

Enable Capture Event 1 as an Interrupt source

Reserved

The interrupt enable bits (CEVT1, ...) block any of the selected events from generating an interrupt.
Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the
ECFRC/ECCLR registers.
The proper procedure for configuring peripheral modes and interrupts is as follows:
Disable global interrupts
Stop eCAP counter
Disable eCAP interrupts
Configure peripheral registers
Clear spurious eCAP interrupt flags
Enable eCAP interrupts
Start eCAP counter
Enable global interrupts

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Figure 18. ECAP Interrupt Flag Register (ECFLG)

15

8
Reserved
R-0

CTR=CMP

CTR=PRD

CTROVF

CEVT4

CETV3

CEVT2

CETV1

INT

R-0

R-0

R-0

R-0

R-0

R-0

R-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. ECAP Interrupt Flag Register (ECFLG) Field Descriptions

Bits

Field

15:8

Reserved

CTR=CMP

Value

Description
Compare Equal Compare Status Flag. This flag is active only in APWM mode.

Indicates no event occurred

Indicates the counter (TSCTR) reached the compare register value (ACMP)

CTR=PRD

Counter Equal Period Status Flag. This flag is only active in APWM mode.
0

Indicates no event occurred

Indicates the counter (TSCTR) reached the period register value (APRD) and was reset.

CTROVF

Counter Overflow Status Flag. This flag is active in CAP and APWM mode.
0

Indicates no event occurred.

Indicates the counter (TSCTR) has made the transition from FFFFFFFF " 00000000

CEVT4

Capture Event 4 Status Flag This flag is only active in CAP mode.
0

Indicates no event occurred

Indicates the fourth event occurred at ECAPx pin

CEVT3

Capture Event 3 Status Flag. This flag is active only in CAP mode.
0

Indicates no event occurred.

Indicates the third event occurred at ECAPx pin.

CEVT2

Capture Event 2 Status Flag. This flag is only active in CAP mode.
0

Indicates no event occurred.

Indicates the second event occurred at ECAPx pin.

CEVT1

Capture Event 1 Status Flag. This flag is only active in CAP mode.
0

Indicates no event occurred.

Indicates the first event occurred at ECAPx pin.

INT

Global Interrupt Status Flag

0

Indicates no interrupt generated.

Indicates that an interrupt was generated.

Figure 19. ECAP Interrupt Clear Register (ECCLR)

15

8
Reserved
R-0

CTR=CMP

CTR=PRD

CTROVF

CEVT4

CETV3

CETV2

CETV1

INT

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 11. ECAP Interrupt Clear Register (ECCLR) Field Descriptions

Bits

Field

15:8

Reserved

CTR=CMP

Description
Counter Equal Compare Status Flag
0

Writing a 0 has no effect. Always reads back a 0

Writing a 1 clears the CTR=CMP flag condition

CTR=PRD

Counter Equal Period Status Flag

0

Writing a 0 has no effect. Always reads back a 0

Writing a 1 clears the CTR=PRD flag condition

CTROVF

Counter Overflow Status Flag

0

Writing a 0 has no effect. Always reads back a 0

Writing a 1 clears the CTROVF flag condition

CEVT4

Capture Event 4 Status Flag

0

Writing a 0 has no effect. Always reads back a 0.

Writing a 1 clears the CEVT4 flag condition.

CEVT3

Capture Event 3 Status Flag

0

Writing a 0 has no effect. Always reads back a 0.

Writing a 1 clears the CEVT3 flag condition.

CEVT2

Capture Event 2 Status Flag

0

Writing a 0 has no effect. Always reads back a 0.

Writing a 1 clears the CEVT2 flag condition.

CEVT1

Capture Event 1 Status Flag

0

Writing a 0 has no effect. Always reads back a 0.

Writing a 1 clears the CEVT1 flag condition.

INT

Global Interrupt Clear Flag

0

Writing a 0 has no effect. Always reads back a 0.

Writing a 1 clears the INT flag and enable further interrupts to be generated if any
of the event flags are set to 1.

Figure 20. ECAP Interrupt Forcing Register (ECFRC)

15

14

13

12

11

10

Reserved
R-0
7

CTR=CMP

CTR=PRD

CTROVF

CEVT4

CETV3

CETV2

CETV1

reserved

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions

Bits

Field

15:8

Reserved

CTR=CMP

Value

Description

0
Force Counter Equal Compare Interrupt
0

No effect. Always reads back a 0.

Writing a 1 sets the CTR=CMP flag bit.

CTR=PRD

Force Counter Equal Period Interrupt

0

No effect. Always reads back a 0.

Writing a 1 sets the CTR=PRD flag bit.

CTROVF

Force Counter Overflow

0

No effect. Always reads back a 0.

Writing a 1 to this bit sets the CTROVF flag bit.

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Table 12. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions (continued)
Bits
4

Field

Value

CEVT4

Force Capture Event 4

0

No effect. Always reads back a 0.

Writing a 1 sets the CEVT4 flag bit

CEVT3

Force Capture Event 3

0

No effect. Always reads back a 0.

Writing a 1 sets the CEVT3 flag bit

CEVT2

Force Capture Event 2

0

No effect. Always reads back a 0.

Writing a 1 sets the CEVT2 flag bit.

CEVT1

reserved

Description

Force Capture Event 1

0

No effect. Always reads back a 0.

Sets the CEVT1 flag bit.

Register Mapping
Table 13 shows the eCAP module control and status register set.
Table 13. Control and Status Register Set
Name

Offset

Size (x16)

Description

Time Base Module Registers

TSCTR

0x0000

Time-Stamp Counter

CTRPHS

0x0002

Counter Phase Offset Value Register

CAP1

0x0004

Capture 1 Register

CAP2

0x0006

Capture 2 Register

CAP3

0x0008

Capture 3 Register

CAP4

0x000A

Capture 4 Register

reserved

0x000C - 0x0013

ECCTL1

0x0014

Capture Control Register 1

ECCTL2

0x0015

Capture Control Register 2

ECEINT

0x0016

Capture Interrupt Enable Register

ECFLG

0x0017

Capture Interrupt Flag Register

ECCLR

0x0018

Capture Interrupt Clear Register

ECFRC

0x0019

Capture Interrupt Force Register

Reserved

0x001A - 0x001F

Application of the ECAP Module

The following sections will provide Applications examples and code snippets to show how to configure and
operate the eCAP module. For clarity and ease of use, the examples use the eCAP C header files.
Below are useful #defines which will help in the understanding of the examples.
// ECCTL1 ( ECAP Control Reg 1) //========================== // CAPxPOL bits #define EC_RISING
0x0 #define EC_FALLING 0x1 // CTRRSTx bits #define EC_ABS_MODE 0x0 #define EC_DELTA_MODE 0x1 //
PRESCALE bits #define EC_BYPASS 0x0 #define EC_DIV1 0x0 #define EC_DIV2 0x1 #define EC_DIV4 0x2
#define EC_DIV6 0x3 #define EC_DIV8 0x4 #define EC_DIV10 0x5 // ECCTL2 ( ECAP Control Reg 2)
//========================== // CONT/ONESHOT bit #define EC_CONTINUOUS 0x0 #define EC_ONESHOT 0x1
// STOPVALUE bit #define EC_EVENT1 0x0 #define EC_EVENT2 0x1 #define EC_EVENT3 0x2 #define
EC_EVENT4 0x3 // RE-ARM bit #define EC_ARM 0x1 // TSCTRSTOP bit #define EC_FREEZE 0x0 #define
EC_RUN 0x1 // SYNCO_SEL bit #define EC_SYNCIN 0x0 #define EC_CTR_PRD 0x1 #define EC_SYNCO_DIS 0x2
// CAP/APWM mode bit #define EC_CAP_MODE 0x0 #define EC_APWM_MODE 0x1 // APWMPOL bit #define
EC_ACTV_HI 0x0 #define EC_ACTV_LO 0x1 // Generic #define EC_DISABLE 0x0 #define EC_ENABLE 0x1
#define EC_FORCE 0x1

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7.1

Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger

Figure 21 shows an example of continuous capture operation (Mod4 counter wraps around). In this figure,
TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this gives
period (and frequency) information.
On an event, the TSCTR contents (i.e., time-stamp) is first captured, then Mod4 counter is incremented to
the next state. When the TSCTR reaches FFFFFFFF (i.e. maximum value), it wraps around to 00000000
(not shown in Figure 21), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if
enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured
Time-stamps are valid at the point indicated by the diagram, i.e. after the 4th event, hence event CEVT4
can conveniently be used to trigger an interrupt and the CPU can read data from the CAPx registers.
Figure 21. Capture Sequence for Absolute Time-stamp and Rising Edge Detect
CEVT1

CEVT2

CEVT3

CEVT4

CEVT1

CAPx pin
t5

t4

FFFFFFFF

t3
t2
t1

CTR[031]
00000000
MOD4
CTR
CAP1

CAP2

XX

t5

t1

XX

t2

XX

CAP3

t3

XX

CAP4

t4
t

Polarity selection
Capture registers [14]

All capture values valid

(can be read) at this time

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Code snippet for CAP mode Absolute Time, Rising Edge Trigger
// Code snippet for CAP mode Absolute Time, Rising edge trigger // Initialization Time
//======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_RISING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_ABS_MODE; ECap1Regs.ECCTL1.bit.CTRRST3 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_ABS_MODE; ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1; ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS; ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE; ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN; // Allow
TSCTR to run // Run Time ( e.g. CEVT4 triggered ISR call)
//========================================== TSt1 = ECap1Regs.CAP1; // Fetch Time-Stamp captured
at t1 TSt2 = ECap1Regs.CAP2; // Fetch Time-Stamp captured at t2 TSt3 = ECap1Regs.CAP3; // Fetch
Time-Stamp captured at t3 TSt4 = ECap1Regs.CAP4; // Fetch Time-Stamp captured at t4 Period1 =
TSt2-TSt1; // Calculate 1st period Period2 = TSt3-TSt2; // Calculate 2nd period Period3 = TSt4TSt3; // Calculate 3rd period

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7.2

Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger

In Figure 22 the eCAP operating mode is almost the same as in the previous section except capture
events are qualified as either rising or falling edge, this now gives both period and duty cycle information,
i.e: Period1 = t3 t1, Period2 = t5 t3, etc. Duty Cycle1 (on-time %) = (t2 t1) / Period1 x 100%, etc. Duty
Cycle1 (off-time %) = (t3 t2) / Period1 x 100%, etc.
Figure 22. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect
CEVT2

CEVT4

CEVT1

CEVT2

CEVT3

CEVT1

CEVT4
CEVT1
CEVT3

CAPx pin
FFFFFFFF
t6

t5
CTR[031]

t3

t9

t8

t7

t4

t2
t1
00000000
MOD4
CTR
CAP1

CAP2

CAP3

CAP4

XX

t1

XX

t5

t2

XX

t6

t3

XX

t7

t4

t8
tt

Polarity selection
Capture registers [14]

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Code snippet for CAP mode Absolute Time, Rising & Falling Edge Triggers
// Code snippet for CAP mode Absolute Time, Rising & Falling // edge triggers // Initialization
Time //======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_ABS_MODE; ECap1Regs.ECCTL1.bit.CTRRST3 = EC_ABS_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_ABS_MODE; ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1; ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS; ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE; ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN; // Allow
TSCTR to run // Run Time ( e.g. CEVT4 triggered ISR call)
//========================================== TSt1 = ECap1Regs.CAP1; // Fetch Time-Stamp captured
at t1 TSt2 = ECap1Regs.CAP2; // Fetch Time-Stamp captured at t2 TSt3 = ECap1Regs.CAP3; // Fetch
Time-Stamp captured at t3 TSt4 = ECap1Regs.CAP4; // Fetch Time-Stamp captured at t4 Period1 =
TSt3-TSt1; // Calculate 1st period DutyOnTime1 = TSt2-TSt1; // Calculate On time DutyOffTime1 =
TSt3-TSt2; // Calculate Off time

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Application of the ECAP Module

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7.3

Example 3 - Time Difference (Delta) Operation Rising Edge Trigger

This example Figure 23 shows how the eCAP module can be used to collect Delta timing data from pulse
train waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4 counter
wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event. Here
Capture events are qualified as Rising edge only. On an event, TSCTR contents (i.e. Time-Stamp) is
captured first, and then TSCTR is reset to Zero. The Mod4 counter then increments to the next state. If
TSCTR reaches FFFFFFFF (i.e. Max value), before the next event, it wraps around to 00000000 and
continues, a CNTOVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. The advantage
of Delta-time Mode is that the CAPx contents directly give timing data without the need for CPU
calculations, i.e. Period1 = T1, Period2 = T2,etc. As shown in the diagram, the CEVT1 event is a good
trigger point to read the timing data, T1, T2, T3, T4 are all valid here.
Figure 23. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect
CEVT1

CEVT3

CEVT2

CEVT4

CEVT1

CAPx pin
T1

FFFFFFFF

T3

T2

T4

CTR[031]

00000000
MOD4
CTR

CAP1

CAP2

XX

CTR value at CEVT1

t4

XX

t1

XX

CAP3

t2

XX

CAP4

t3
t

Polarity selection
Capture registers [14]

All capture values valid

(can be read) at this time

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Application of the ECAP Module

7.3.1

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Code snippet for CAP mode Delta Time, Rising Edge Trigger
// Code snippet for CAP mode Delta Time, Rising edge trigger // Initialization Time
//======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_RISING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_RISING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_DELTA_MODE; ECap1Regs.ECCTL1.bit.CTRRST3 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_DELTA_MODE; ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1; ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS; ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE; ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN; // Allow
TSCTR to run // Run Time ( e.g. CEVT1 triggered ISR call)
//========================================== // Note: here Time-stamp directly represents the
Period value. Period4 = ECap1Regs.CAP1; // Fetch Time-Stamp captured at T1 Period1 =
ECap1Regs.CAP2; // Fetch Time-Stamp captured at T2 Period2 = ECap1Regs.CAP3; // Fetch Time-Stamp
captured at T3 Period3 = ECap1Regs.CAP4; // Fetch Time-Stamp captured at T4

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Application of the ECAP Module

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7.4

Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger
In Figure 24 the eCAP operating mode is almost the same as in previous section except Capture events
are qualified as either Rising or Falling edge, this now gives both Period and Duty cycle information, i.e:
Period1 = T1+T2, Period2 = T3+T4, etc Duty Cycle1 (on-time %) = T1 / Period1 x 100%, etc Duty Cycle1
(off-time %) = T2 / Period1 x 100%, etc
Figure 24. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect
CEVT4

CEVT2

CEVT2

CEVT3

CEVT1

CEVT4
CEVT5
CEVT3

CEVT1

CAPx pin
T1

FFFFFFFF

T3

T5

T8

T2

T6
T4

T7

CTR[031]

00000000
MOD4
CTR
CAP1

CAP2

CAP3

CAP4

XX

t5

t1

XX

t2

XX

t4

CTR value at CEVT1

XX

t6

t3

t7
t

Polarity selection
Capture registers [14]

During initialization, you must write to the active registers for both period and compare. This will then
automatically copy the init values into the shadow values. For subsequent compare updates, i.e. during
run-time, only the shadow registers must be used.

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Application of the ECAP Module

7.4.1

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Code snippet for CAP mode Delta Time, Rising and Falling Edge Triggers
// Code snippet for CAP mode Delta Time, Rising and Falling // edge triggers // Initialization
Time //======================= // ECAP module 1 config ECap1Regs.ECCTL1.bit.CAP1POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP2POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CAP3POL = EC_RISING;
ECap1Regs.ECCTL1.bit.CAP4POL = EC_FALLING; ECap1Regs.ECCTL1.bit.CTRRST1 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST2 = EC_DELTA_MODE; ECap1Regs.ECCTL1.bit.CTRRST3 = EC_DELTA_MODE;
ECap1Regs.ECCTL1.bit.CTRRST4 = EC_DELTA_MODE; ECap1Regs.ECCTL1.bit.CAPLDEN = EC_ENABLE;
ECap1Regs.ECCTL1.bit.PRESCALE = EC_DIV1; ECap1Regs.ECCTL2.bit.CAP_APWM = EC_CAP_MODE;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = EC_CONTINUOUS; ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS;
ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE; ECap1Regs.ECCTL2.bit.TSCTRSTOP = EC_RUN; // Allow
TSCTR to run // Run Time ( e.g. CEVT1 triggered ISR call)
//========================================== // Note: here Time-stamp directly represents the
Duty cycle values. DutyOnTime1 = ECap1Regs.CAP2; // Fetch Time-Stamp captured at T2 DutyOffTime1
= ECap1Regs.CAP3; // Fetch Time-Stamp captured at T3 DutyOnTime2 = ECap1Regs.CAP4; // Fetch TimeStamp captured at T4 DutyOffTime2 = ECap1Regs.CAP1; // Fetch Time-Stamp captured at T1 Period1 =
DutyOnTime1 + DutyOffTime1; Period2 = DutyOnTime2 + DutyOffTime2;

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Application of the APWM Mode

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Application of the APWM Mode

In this example, the eCAP module is configured to operate as a PWM generator. Here a very simple
single channel PWM waveform is generated from output pin APWMx. The PWM polarity is active high,
which means that the compare value (CAP2 reg is now a compare register) represents the on-time (high
level) of the period. Alternatively, if the APWMPOL bit is configured for active low, then the compare value
represents the off-time. Note here values are in hexadecimal (h) notation.

8.1

Example 1 - Simple PWM Generation (Independent Channel/s)

Figure 25. PWM Waveform Details of APWM Mode Operation
TSCTR
FFFFFFFF
APRD

1000h

500h
ACMP

300h

0000000C
APWMx
(o/p pin)

On
time

Offtime

Period

Example 1. Code Snippet for APWM Mode

// Code snippet for APWM mode Example 1 // Initialization Time //======================= // ECAP
module 1 config ECap1Regs.CAP1 = 0x1000; // Set period value ECap1Regs.CTRPHS = 0x0; // make phase
zero ECap1Regs.ECCTL2.bit.CAP_APWM = EC_APWM_MODE; ECap1Regs.ECCTL2.bit.APWMPOL = EC_ACTV_HI; //
Active high ECap1Regs.ECCTL2.bit.SYNCI_EN = EC_DISABLE; // Synch not used
ECap1Regs.ECCTL2.bit.SYNCO_SEL = EC_SYNCO_DIS; // Synch not used ECap1Regs.ECCTL2.bit.TSCTRSTOP =
EC_RUN; // Allow TSCTR to run // Run Time (Instant 1, e.g. ISR call) //======================
ECap1Regs.CAP2 = 0x300; // Set Duty cycle i.e. compare value // Run Time (Instant 2, e.g. another ISR
call) //====================== ECap1Regs.CAP2 = 0x500; // Set Duty cycle i.e. compare value

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33

Appendix A

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Appendix A Revision History

The following technical change(s) were made to this document.
Table 14. Changes Made in This Revision

34

Location

Additions, Deletions, Changes

Global

Added the 2803x device.

Revision History

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