Stcomet: Smart Meter and Powerline Communication System-On-Chip

STCOMET
Smart meter and powerline communication system-on-chip

Datasheet - production data
Cortex-M4 Embedded Trace Macrocell

Up to 86 multiplexed GPIOs
11 timers
1 flexible CRC calculation unit
5 USARTs (ISO 7816 compliant), 5 SPI,
3 I2C
12-bit general purpose ADC with
6 channels
TQFP176 (20 x 20 x 1 mm)
Features
Integrated differential PLC analog front-end
PGA with automatic gain control and ADC
Current DAC with transmission predriver
Digital transmission level control
Zero crossing comparator
Up to 500 kHz PLC signal bandwidth
Integrated dual line driver
14 V p-p single ended, 28 V p-p differential
output range
Very high linearity for EMC compliance
Externally configurable amplifier topology
1 A rms max. current
Embedded overtemperature protection
Suitable for all PLC signals up to 500 kHz
Fully reprogrammable real-time engine (RTE)
modem for PLC standards up to 500 kHz
High accuracy metering front-end
3 independent 24-bit ADC channels
3.6 kHz bandwidth
Dedicated DSP for turnkey calculation of
metrology parameters
Direct access to 24-bit data
Integrated application core: ARM 32-bit
Cortex-M4F CPU
96 MHz maximum frequency
8-channel direct memory access controller
8-region memory protection unit
Serial wire and JTAG interfaces
September 2015
This is information on a product in full production.
Cryptographic engine
AES 128/192/256 engine
True random number generator
Memories
640 kB or 1 MB of embedded Flash
128 kB of embedded SRAM
8 kB of embedded shared RAM
Flexible static memory controller
Clock management
24 MHz external crystal for system clock
with internal QFS synthesizer
32.768 kHz external crystal for RTC
Power management
3.3 V and 8 - 18 V external supply voltages
1.2 V and 5 V integrated linear regulators
Normal and low power modes
Real-time clock (RTC)
VBAT supply with battery health monitoring
for RTC and backup registers
-40 C to +85 C operating temperature range
Applications
Smart metering, smart grid and Internet of
Things applications
Compliant with EN 50470-1, EN 50470-3, IEC
62053-21, IEC 62053-22 and IEC 62053-23
Compliant with CENELEC, FCC, ARIB
regulations
DocID028281 Rev 1
1/67
www.st.com
Contents
STCOMET
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2
Power line communication (PLC) sub-system . . . . . . . . . . . . . . . . . . . . . 10

1.2.1
Real-time engine (RTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.2
Digital front-end (DFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.3
Analog front-end (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.4
Line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3
Metrology sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.4
Application core sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5
1.4.1
ARM Cortex-M4F core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.2
Floating point unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.3
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13
1.4.4
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4.5
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.6
Debug and trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.7
General purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.8
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.9
Timers and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.10
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 19
1.4.11
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Cryptographic engine (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.5.1
True random number generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.2
Pseudo random number generator (PRNG) . . . . . . . . . . . . . . . . . . . . . 21
1.6
Interprocessor communication (IPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.8
1.7.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.7.2
One-time programmable (OTP) section . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.7.3
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.7.4
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 23
Reset, control, clock generation (RCC) and system controller

(SYS_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Contents
1.9
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.10
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.11
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 29
1.12
Temperature sensors and overtemperature protection . . . . . . . . . . . . . . 30
1.13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.14
System reprogrammability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.14.1
In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.14.2
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.1
Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2
GPIOs multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4
4.5
4.6
PLC analog front-end (AFE) and line driver characteristics . . . . . . . . . . . 51

4.4.1
Line driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.2
Line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4.3
AFE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Metrology characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5.1
Typical application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5.2
Typical application performance curves . . . . . . . . . . . . . . . . . . . . . . . . . 58
Embedded Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1
TQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DocID028281 Rev 1
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Contents
STCOMET
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Cortex-M4F core configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Interrupt definition and position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DMA channels muxing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Embedded Flash sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Boot mode and security level relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Boot modes and BOOT0/1 pin values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
GPIOs multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Absolute maximum ratings - voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute maximum ratings - current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Analog supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Digital supply characteristics - RTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Metrology power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Digital supply characteristics - Cortex-M4 fetching from RAM . . . . . . . . . . . . . . . . . . . . 49
Digital supply characteristics - Cortex-M4 fetching data from eFlash . . . . . . . . . . . . . . . 49
Digital supply characteristics - DOZE (sleep)/deepsleep mode . . . . . . . . . . . . . . . . . . . . . 50
Supply characteristics - QFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
24 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
32 kHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Digital supply characteristics - I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Digital supply characteristics - power consumption under battery . . . . . . . . . . . . . . . . . . . 51
Line driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Predriver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Receiver input referred noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PLC PGA characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Zero crossing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Energy measurement accuracy section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
On-chip reference voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Metrology reference application parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash memory current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TQFP176 (20 x 20 x 1 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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List of figures
STCOMET
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
6/67
STCOMET basic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STCOMET detailed architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset, clock and system controller interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STCOMET clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply scheme - digital and metrology sections . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power supply scheme - PLC AFE and line driver section. . . . . . . . . . . . . . . . . . . . . . . . . . 28
TQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Metrology reference application schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Active energy error vs. current at AI = 2x, T = 25 C,
load current phase phi = (0, 60, -60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Active energy error vs. current at AI = 16x, T = 25 C,
load current phase phi = (0, 60, -60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Active energy error vs. frequency at AI =2x, T = 25 C, power factor PF = 1 . . . . . . . . . . . 59
Active energy error vs. frequency at AI = 2x, T = 25 C, power factor PF = 0.8 . . . . . . . . . 59
Active energy error vs. frequency at AI = 2x, T = 25 C, power factor PF = 0.5 . . . . . . . . . 60
Reactive energy error vs. current at AI = 2x, T = 25 C,
load current phase phi = (90, -90, 60, -60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Reactive energy error vs. current at AI = 16x ,T = 25 C,
load current phase phi = (90, -90, 60, -60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
TQFP176 (20 x 20 x 1 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DocID028281 Rev 1
STCOMET
Description
Description
The STCOMET is a device that integrates a power line communication (PLC) modem,
a high-performance application core and metrology functions.
The PLC modem architecture has been designed to target EN50065, FCC, ARIB compliant
PLC applications. Together with the application core, it enables the STCOMET to support
the PRIME, G1, G3, IEEE 1901.2, METERS AND MORE and other narrow band PLC
protocol specifications.
The metrology sub-system is suitable for EN 50470-1, EN 50470-3, IEC 62053-21, IEC
62053-22 and IEC 62053-23 compliant class1, class0.5 and class0.2 AC metering
applications.
The STCOMET basic block diagram is shown in Figure 1.
Figure 1. STCOMET basic block diagram
DocID028281 Rev 1
7/67
67
Description
1.1
STCOMET
Device architecture
The architecture is composed of the following parts:
1.
PLC front-end including digital front-end and analog front-end
2.
PLC line driver
3.
Real-time engine: the digital core running the lower layers of the PLC protocol stack
and implementing modulation and demodulation
4.
Metrology sub-system including AFE and dedicated processing unit
5.
Protocol engine: the main digital core for running meter application, metrology
algorithm and the upper layers of the PLC protocol stack
6.
Wide range of peripherals logically divided into 4 blocks:
Basic peripherals
Com1 peripherals
Com2 peripherals
Crypto peripherals.
The STCOMET detailed architecture is shown in Figure 2.
8/67
DocID028281 Rev 1
STCOMET
Description
Figure 2. STCOMET detailed architecture
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DocID028281 Rev 1
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Description
1.2
STCOMET
Power line communication (PLC) sub-system

The STCOMET device embeds a full narrow band power line communication (NB-PLC)
sub-system, comprising the RTE, DFE, AFE and line driver.
The AFE and line driver have been designed for a differential power line interface; however,
single-ended operation is possible for simpler hardware application development.
The DC to 500 kHz signal bandwidth is supported, targeting a number of possible NB-PLC
solutions.
1.2.1
Real-time engine (RTE)

To match a performance required by emerging NB-PLC standards, the STCOMET embeds
a proprietary dedicated reprogrammable machine, the real-time engine. It is able to address
specific functionalities exploited by OFDM and the ones adopted in the current and future
NB- PLC standards in an efficient way.
1.2.2
Digital front-end (DFE)

Transmission and reception filter chains
The DFE includes programmable transmission/reception digital filter chains to fit the signal
bandwidth in different PLC modulation cases. The ADC and DAC clock frequencies are
controlled by the DFE to get the right sample rate fitting the filter chain configuration.
Automatic gain control (AGC)

The DFE implements the automatic gain control (AGC) block for the PGA, whose purpose is
to adapt the signal to the ADC dynamic.
Current control (CC)

The DFE includes also the current control (CC) block for the line driver to limit the maximum
output current.
1.2.3
Analog front-end (AFE)

Receiving chain
The STCOMET AFE features a programmable gain amplifier (PGA) and a dedicated
analog-to-digital converter (ADC) to achieve high RX sensitivity and a wide input range.
Transmission chain
The transmitted signal, generated in the digital domain, is fed into a dedicated digital-toanalog converter (DAC).
The DAC output is then fed into a predriver for buffering and applying an additional gain
before the line driver.
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Description
Zero crossing comparator

The mains line zero crossing can be detected by providing a mains synchronous bipolar
(AC) signal at the input of this comparator.
The zero crossing comparator provides positive and negative event information
(rising/falling edge or high/low level).
1.2.4
Line driver
The STCOMET is equipped with an integrated high-performance dual power line driver. It
has very low distortion, allowing the device to comply with EMC requirements.
When supplied at maximum voltage, the line driver is capable to provide 28 V p-p in
differential configuration or 14 V p-p in single-ended configuration.
The output current can reach 1 A rms in both differential and single-ended configurations, in
order to drive very low power line impedance.
Any overtemperature event will force the line driver to shut down, thus preventing the
STCOMET to get damaged.
1.3
Metrology sub-system
The STCOMET device embeds a metrology sub-system designed for high accuracy
measurement of single-phase and split phase power and energy using a Rogowski coil,
current transformer, or shunt current sensors.
This sub-system calculates instantaneous and RMS voltage and currents, active, active
fundamental, reactive and apparent power and energy. It also monitors when the SAG or
SWELL event on voltage and the SWELL event on the current are present in the input line.
The metrology sub-system consists of an analog and a digital section. The analog section
consists of two programmable gain low-noise low offset amplifiers (PGA) and three 24-bit
2nd order ADCs, bandgap voltage references with temperature compensation, a lowdrop voltage regulator and DC buffers. The digital section consists of a hardwired DSP and
DFE to the input modulators and an interconnection bus with the Cortex-M4 core.
The hardwired processing unit can be bypassed for direct access to the metrology samples
by the application core.
Key features of this block are:
Active and reactive power accuracy < 0.1% error over 1:5000 range
Active and reactive power accuracy < 0.5% error over 1:10000 range
Programmable energy and power calculation unit, that can be bypassed
0 - 3.6 kHz bandwidth at -3 dB, up to 72nd (60th) harmonic content at 50 Hz (60 Hz)
Primary and auxiliary current comparison for anti-tamper function on single-phase two
wires systems
SAG and SWELL detection on voltage channel with programmable thresholds
SWELL detection on current channels with programmable thresholds
The metrology sub-system is fully configurable and allows fast digital calibration in a single
point over the entire current dynamic range.
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Description
STCOMET
The metrology sub-system generates its high accuracy voltage reference for ADC,
externally available on METR_VREF for filtering purpose only.
A 100 nF capacitor between METR_VREF and METR_AGND is required.
The metrology voltage reference can be compensated vs. temperature by the dedicated
trimming register.
1.4
Application core sub-system
1.4.1
ARM Cortex-M4F core

The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage
pipeline Harvard architecture, making it ideal for demanding embedded applications. The
processor delivers exceptional power efficiency through an efficient instruction set and
extensively optimized design, providing high end processing hardware including IEEE754compliant single precision (32-bit) floating point computation, a range of a single cycle and
SIMD multiplication and multiply with accumulate capabilities, saturating arithmetic and
dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements
tightly coupled system components that reduce processor area while significantly improving
interrupt handling and system debug capabilities. The Cortex-M4 processor implements
a version of the Thumb instruction set based on Thumb-2 technology, ensuring high code
density and reduced program memory requirements. The Cortex-M4 instruction set
provides the exceptional performance expected of a modern 32-bit architecture, with the
high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M4 processor provides multiple interfaces using AMBA technology to
provide high-speed, low latency memory accesses. It supports unaligned data accesses
and implements atomic bit manipulation that enables faster peripheral controls, system
spinlocks and thread-safe Boolean data handling.
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Description
Table 1. Cortex-M4F core configuration
Component
Presence
Comment
JTAG
Yes
Full-featured debug access port (DAP), SWJ-DP and AHB access port
ETM
Yes
Embedded Trace Macrocell present
ITM
Yes
Instrumentation Trace Macrocell
TPIU
Yes
Trace port unit interface present
FPB
Yes
Flash patch breakpoint
DWT
Yes
Data watchpoint and trace
DEBUG level
N/A
Full debug with data matching for watchpoint generation
IRQ
N/A
80 IRQ source
Priority level
N/A
Set to 5:32 levels
MPU
Yes
Memory protection unit present. 8 regions implemented
FPU
Yes
Floating point unit present (single precision)
BB
Yes
Bit banding region present
RESET_ALL_REGS
Yes
Reset all synchronous state
CLKGATE
Yes
Possibility to minimize dynamic power dissipation by clock gating
WIC
Yes
10 lines: NMI, WWDG, RTC, metrology, GPIOs, IPC, DMA, GPT0, SPI0 and
USART0
1.4.2
Floating point unit (FPU)

The FPU fully supports single precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between the fixed
point and floating point data formats, and floating point constant instructions.
The FPU provides floating point operations that are compliant with the NSI/IEEE Std 7542008 A, IEEE Standard for Binary Floating-point Arithmetic, referred to as the IEEE 754
Standard.
The FPU contains 32 single precision extension registers, which can also be accessible as
16 double word registers for load, store, and move operations.
1.4.3
Nested vectored interrupt controller (NVIC)

The STCOMET embeds a NVIC able to handle 80 maskable interrupts. The software priority
level is configurable in the range of 0 - 31 for each interrupt. A higher level corresponds to
a lower priority, so the level 0 is the highest interrupt priority. In case two or more interrupt
lines share the same software priority level, the hardware priority level, which is described in
Table 2, is used.
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Table 2. Interrupt definition and position
Position Priority
Acronym
Description
-3
Reset
Reset
-2
NMI
Wake-up interrupt - non maskable interrupt - system error
-1
HardFault
All class of fault
MemManage
MPU mismatch
BusFault
Prefetch fault, memory access fault
UsageFault
Undefined instruction or illegal state
SVCall
System service call via SWI instruction
DebugMonitor
Debug monitor
PendSV
Pendable request for system service
SysTick
System tick timer
WDG_WIC
Wake-up interrupt - window watchdog
RTC_WIC
Wake-up interrupt - RTC interrupts
METR_V_WIC
Wake-up interrupt - metrology interrupt for voltage line
10
GPIO_WIC
Wake-up interrupt - GPIO interrupts
11
IPC_WIC
Wake-up interrupt - IPC interrupts
12
DMAC_WIC
Wake-up interrupt - DMAC interrupts
13
GPT0_WIC
Wake-up interrupt - GPT0 global interrupt
14
SPI0_WIC
Wake-up interrupt - SPI0 global interrupt
15
USART0_WIC
Wake-up interrupt - USART0 global interrupt
16
Reserved
10
17
TAMPER
Tamper pin interrupt
11
18
RTC
Real-time clock
12
19
FLASH_FATAL_ERROR
Flash interface
13
20
FLASH_ECC_RWW_ERROR
Flash interface
14
21
FLASH_ARY_DONE
Flash interface
15
22
IPC_MBOX
IPC mailbox
16
23
IPC_QUEUES
IPC queues
17
24
IPC_SHAREDRAM
IPC shared memory
18
25
DMA_Ch(1)
DMA global interrupt channel 1
19
26
DMA_Ch(2)
20
27
DMA_Ch(3)
21
28
DMA_Ch(4)
22
29
DMA_Ch(5)
23
30
DMA_Ch(6)
24
31
DMA_Ch(7)
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Description
Table 2. Interrupt definition and position (continued)
Position Priority
Acronym
Description
25
32
DMA_Ch(8)
26
33
ADC
ADC global interrupt
27
34
METR_C1
Metrology interrupt for primary current line
28
35
METR_C2
Metrology interrupt for secondary current line
29
36
FSMC_FILL_FIFO
FSMC interface
30
37
SPI1
SPI1 global interrupt
31
38
SPI2
32
39
SPI3
33
40
SPI4
34
41
I2C0_EVENT
I2C0 global event interrupt
35
42
I2C0_ERROR
I2C0 global error interrupt
36
43
I2C1_EVENT
37
44
I2C1_ERROR
38
45
I2C2_EVENT
39
46
I2C2_ERROR
40
47
AT0_BRK
Advanced timer 0 - BRK
41
48
AT0_UP
Advanced timer 0 - update
42
49
AT0_TRG_COM
Advanced timer 0 - trigger and commutation (COM)
43
50
AT0_CC
Advanced timer 0 - 4 CAPCOM
44
51
AT1_BRK
Advanced timer 1 - BRK
45
52
AT1_UP
Advanced timer 1 - update
46
53
AT1_TRG_COM
Advanced timer 1 - trigger and commutation (COM)
47
54
AT1_CC
Advanced timer 1 - 4 CAPCOM
48
55
GPT1
GPT1 - global interrupt
49
56
GPT2
50
57
GPT3
51
58
USART1
USART1 global interrupt
52
59
USART2
53
60
USART3
54
61
USART4
USART4global interrupt
55
62
CAN0
CAN0 global interrupt
56
63
CAN1
CAN1 global interrupt
57
64
AES
AES global interrupt
58
65
GPIO00
GPIO00 global interrupt
59
66
GPIO01
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STCOMET
Table 2. Interrupt definition and position (continued)
Position Priority
Acronym
Description
60
67
GPIO02
61
68
GPIO03
62
69
GPIO04
63
70
GPIO05
64
71
GPIO06
65
72
GPIO07
66
73
GPIO08
67
74
GPIO09
68
75
GPIO10
69
76
GPT4
70
77
GPT5
71
78
GPT6
72
79
GPT7
73
80
Reserved
74
81
Reserved
75
82
Reserved
76
83
Reserved
77
84
Reserved
78
85
Reserved
79
86
Reserved
1.4.4
DMA controller (DMA)

The STCOMET embeds 1 general purpose dual port DMA controller with 8 channels. It is
able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral
transfers. It features dedicated FIFOs for APB/AHB peripherals, a supports burst transfer
and is designed to provide the maximum peripheral bandwidth (AHB/APB).
The DMA controller supports circular buffer management, so that no specific code is needed
when the controller reaches the end of the buffer. It also has a double buffering feature,
which automates the use and switching of two memory buffers without requiring any special
code.
Each channel is connected to dedicated hardware DMA requests, with support for
a software trigger on each stream. Configuration is made by software and transfer sizes
between source and destination are independent.
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Description
Table 3. DMA channels muxing scheme
Peripheral
CH1
CH2
CH3
CH4
CH5
CH6
CH7
METR
ADC
CH8
METR
ADC
SPI0
SPI0_TX
SPI0_RX
SPI1
SPI2
SPI2_TX
SPI1_TX
SPI1_RX
SPI3_TX
SPI3_RX
SPI2_RX
SPI3
SPI4
USART0
USART0_TX
SPI4_TX
SPI4_RX
USART2_TX
USART2_RX
USART4_TX
USART4_RX
I2C2_TX
I2C2_RX
USART0_RX
USART1
USART1_TX USART1_RX
USART2
USART3
USART3_TX
USART3_RX
USART4
I2C0
I2C0_TX
I2C1
I2C1_TX
I2C0_RX
I2C1_RX
I2C2
AT0
AT0_CH1
AT0_CH2
AT0_CH4
AT0_TRIG
AT0_COM
AT0_UP
AT1
AT1_CH3
AT0_CH3
AT1_TRIG
AT1_COM
AT1_UP
AT1_CH1
AT1_CH2
AT1_CH4
GPT0_UP
GPT0
GPT1
GPT1_UP
GPT2
GPT2_UP
GPT3
GPT4
GPT5
GPT3_UP
GPT4_UP
GPT5_UP
GPT6
GPT7
GPT6_UP
GPT7_UP
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Description
1.4.5
STCOMET
Memory protection unit (MPU)

The MPU divides the memory map into up to 8 regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
Independent attribute settings for each region
Overlapping regions
Export of memory attributes to the system.
Background region
When memory regions overlap, memory access is affected by the attributes of the region
with the highest number.
The background region has the same memory access attributes as the default memory
map, but is accessible from privileged software only.
The MPU is useful to isolate and protect different parts of the firmware by giving different
levels of access privileges (for example: to implement separation of the metering-related
FW from the rest of the application FW). If a part of the firmware tries to access a memory
location that is prohibited by the MPU, the processor generates a fault. This causes a fault
exception that could be detected by the privileged firmware, which can take the appropriate
action.
The MPU is optional and can be bypassed for applications that do not need it.
1.4.6
Debug and trace

Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Embedded Trace Macrocell (ETM)

The ARM Embedded Trace Macrocell provides greater visibility of the instruction and data
flow inside the Cortex-M4 core by streaming compressed data at a very high rate from the
STCOMET device through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is then connected to a host in order to record and then
format the information for displaying and analysis.
1.4.7
General purpose input/outputs (GPIOs)

The STCOMET device has 11 GPIOs ports named from GPIO00 to GPIO10. Each port is
able to manage 8 pins, except the GPIO08 port that manages 6 pins. Each GPIO pin can be
individually configured by software as output (push-pull or open drain, with or without pull-up
or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral
alternate functions (with or without pull-up or pull-down). Each GPIO pin can also generate
interrupt depending on a level (low and high), or a transactional value of the pin (rising or
falling edge).
External interrupt
Each GPIOs port can generate interrupts. For each port one interrupt line is dedicated. The
pins of one port share the same interrupt line.
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1.4.8
Description
Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (Cortex-M4, DMA, and realtime engine) and the slaves (Flash memory, RAM, AHB and APB peripherals, metrology
and real-time engine) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
1.4.9
Timers and watchdog

The STCOMET embeds 8 general purpose timers, two advanced timers and one window
watchdog. The Cortex-M4 is also equipped with a SysTick timer.
General purpose timer (GPT)

The STCOMET device includes 8 full-featured general purpose timers based on a 16-bit
autoreload up/down counter and a 16-bit programmable prescaler.
Advanced timers (AT)

The STCOMET includes 2 advanced-control timers based on a 16-bit autoreload up/down
counter driven by a 16-bit programmable prescaler. They all feature 4 independent channels
for input capture, output compare, PWM generation or one pulse mode output.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with deadtime insertion).
Window watchdog (WWDG)

The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the
application program to abandon its normal sequence. The watchdog circuit generates
a device reset on expiry of a programmed time period, unless the program refreshes the
contents of the down counter register. A device reset is also generated if the down counter
value is refreshed before the down counter has reached the proper window register value.
This implies that the counter must be refreshed in a limited window.
The window watchdog is based on a 7-bit free-running down counter with two conditional
resets: the down counter is reloaded outside the window or the down counter value
becomes less than 0x40.
The window watchdog supports early wake-up interrupt trigged when the down counter is
equal to 0x40.
SysTick timer
The Cortex-M4 has a 24-bit system timer, SysTick, which counts down from the
programmable reload value to zero. It supports the autoreload and can generate
a maskable system interrupt when the counter reaches zero.
1.4.10
CRC (cyclic redundancy check) calculation unit

The cyclic redundancy check (CRC) is a widely used method for detecting errors. The CRC
calculation unit is used to get a CRC code in a flexible way using a configurable polynomial.
Output data size can be selected between 8, 16, 24 or 32 bits.
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STCOMET
Input data size can be configured between 1, 8, 16, 24 or 32 bits with selectable bit and byte
endianness.
The CRC unit allows the specification of the initial value (all zero, all one, or a generic value)
and the possibility to select an automatic XOR with all one when reading the data output.
1.4.11
Communication interfaces
Inter-integrated circuit interface (I2C)
The STCOMET embeds 3 I2C bus interfaces that can operate in multimaster and slave
modes. They can support the Standard and Fast modes. They support the 7/10-bit
addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
The I2C peripherals can be served by DMA and support SMBus 2.0/PMBus operations.
Universal synchronous/asynchronous receiver transmitters (USART)

The STCOMET embeds 5 universal synchronous/asynchronous receiver transmitters.
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
a multiprocessor communication mode, single-wire half-duplex communication mode and
have an LIN Master/Slave capability.
The peripherals also provide hardware management of the CTS and RTS signals,
a Smartcard mode (ISO 7816 compliant) and a SPI-like communication capability. All
interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)

The STCOMET embeds 5 SPIs in slave and master modes in full-duplex and simplex
communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame
is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic
SD Card/MMC modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in a TI mode for communications in
master mode and slave mode.
Controller area network (CAN)

The STCOMET embeds 2 CAN modules able to perform communication according to the
CAN protocol version 2.0 part A and B. The bitrate can be programmed to values up to
1 MBit/s. For communication on a CAN network, individual message objects are configured.
Each message object has its own identifier mask. The message objects and identifier masks
are stored in the 256 byte size message RAM with a programmable FIFO mode. All
functions concerning the handling of messages are implemented in the message handler.
Those functions are the acceptance filtering, the transfer of messages between the CAN
core and the message RAM, and the handling of transmission requests as well as the
generation of the module interrupt.
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Description
General purpose analog-to-digital converter (ADC)

One 12-bit SAR ADC working at a maximum conversion rate of 2 Msps is embedded in the
STCOMET. The ADC has 6 external available input channels performing conversion in
a single, continuous or scan mode. The core accesses to the peripheral through a 4x12-bit
FIFO interface.
The ADC can be served by the DMA controller. Additional 2 channels are internally used to
monitor the VBAT and the low power temperature sensor.
1.5
Cryptographic engine (CRYP)

The STCOMET embeds an advanced hardware AES peripheral which implements an
advanced standard cryptographic algorithm according to the NIST FIPS 197. The block
processes 128-bit data blocks using a key with the following possible sizes: 128, 192, 256
bits. The peripheral also supports the following modes: Electronic Code Book (ECB),
Cipher Block Chaining (CBC), Counter mode (CTR), Galois/Counter Mode (GCM),
GMAC and CCM modes.
The peripheral is able to encrypt and decrypt data. Interrupt can be generated when one
operation is finished.
1.5.1
True random number generator (TRNG)

The STCOMET embeds a TRNG processor based on a continuous analog noise that
provides a random 16-bit value. To avoid pseudo random sequences, two consecutive
accesses have to be performed when the ready bit in the status register is set to 1.
1.5.2
Pseudo random number generator (PRNG)

The STCOMET embeds a PRNG processor that provides a pseudo random 32-bit value.
Initial seed can be configured by software.
1.6
Interprocessor communication (IPC)

The Cortex-M4 core and the real-time engine communicate by means of an additional
8 kByte shared static RAM. This memory can be accessed by the two cores through an
interprocessor communication block that guarantees coherent and consistent read and
modify operations, to provide several functionalities to the system, among the others:
Configuration of real-time engine modes and functionalities during the normal working
operations
Data and information exchange between the Cortex-M4 and real-time engine in both
directions.
The Cortex-M4 wake up from a low power mode triggered by the real-time engine.
The real-time engine wakes up from a low power mode triggered by the Cortex-M4.
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1.7
Memories
1.7.1
Embedded Flash memory

The embedded Flash has the following features:
640 kB or 1 MB of size
128-bit wide data read
64-bit data write through a double 32-bit bus write
Sector erase with possibility to suspend erase procedure in case of read access to
other flash sectors
Multiple sector erase.

Table 4. Embedded Flash sectors
Block
Name
Number
Base address
Size
Main memory
B0F0
0x00000000
16 kB
B0F1
0x00004000
16 kB
B0F2
0x00008000
32 kB
B0F3
0x00010000
32 kB
B0F4
0x00018000
16 kB
B0F5
0x0001C000
16 kB
B0F6
0x00020000
64 kB
B0F7
0x00030000
64 kB
B0F8
0x00040000
128 kB
B0F9
0x00060000
128 kB
B0FA
10
0x00080000
128 kB
Not available in STCOMET05
B0FB
11
0x000A0000
128 kB
B0FC
12
0x000C0000
128 kB
B0FD
13
0x000E0000
128 kB
B0SH
14
0x00100000
16 kB
Shadow sector
Note
Shadow sector is accessible only in some security levels (see Section 1.13: Boot modes on
page 30).
1.7.2
One-time programmable (OTP) section

The STCOMET embeds a one-time programmable (OTP) section in the shadow sector of
the embedded Flash memory. During the manufacturing process, the EUI48 is stored in this
section. The user can also write its private key used during the boot process to verify and
authenticate the firmware image. This OTP section can be configured to avoid reads by
firmware in order to protect user confidential information (see Section 1.13).
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1.7.3
Description
Embedded SRAM
The STCOMET device has 128 kB of a static RAM. The Cortex-M4 can perform byte, half
word (16 bits) or full word (32 bits) access to the SRAM at maximum speed, with zero wait
states for both read and write operations. The SRAM start address is 0x20000000, the end
address is 0x20001FFFF.
The SRAM is split into two blocks of 64 kB with a capability for concurrent access by AHB
master sub-systems.
The Cortex-M4 can also execute a code from the RAM at a zero wait state.
1.7.4
Flexible static memory controller (FSMC)

The STCOMET embeds a FSMC peripheral able to interface external memory devices. The
types of memory supported are:
Asynchronous parallel NOR Flash with up to 21-bit address bus (no synchronous
parallel NOR supported)
Asynchronous SRAM memories
The data bus can be selected between 16 bits or 8 bits (reducing the total amount of
accessible memory), for little or big endian operation.
The FSMC peripheral can connect up to 2 memories with 2 independent chip select lines
(Ebar). The maximum size of each memory is 4 MB. Having 2 chip select lines, the
maximum external memory size is 8 MB.
1.8
Reset, control, clock generation (RCC) and system controller

(SYS_CTRL)
All the clock and reset configuration registers are located in the MISC and SYSCTRL
blocks. Figure 3 shows the interaction between these blocks.
Figure 3. Reset, clock and system controller interaction
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The system reset is generated by the RESETn pin (active low). Through the system
controller is also possible to assert a system software reset. The software reset to single
peripherals can be forced through MISC registers.
Clock management
Two external clock sources are required for the STCOMET:
1.
24 MHz frequency
2.
32.768 kHz frequency
Internal clocks are generated by a quadruple frequency synthesizer (QFS) that is fed by the
24 MHz source. Digital blocks can also use the external sources as clock reference.
The clock strategy is depicted in Figure 4.
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DocID028281 Rev 1
STCOMET
Description
Figure 4. STCOMET clock tree
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At a startup the 24 MHz oscillator clock is selected. This source must be always present to
allow the STCOMET starting correctly. 24 MHz can be provided by a quartz crystal or by any
other source. In this latter case, the clock must be provided through the MCLK_IN pin while
the MCLK_OUT pin must be tied to DGND. 32.768 KHz must be provided by a quartz
crystal.
APB peripherals can work up to 48 MHz. Each PCLK prescaler to the sub-systems should
be configured to respect this maximum frequency.
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67
Description
STCOMET
The general purpose ADC clock can run up to 33 MHz. The RTC core uses only the 32 KHz
external oscillator. The TRNG can work with the external 32 kHz or with the internal
cpu_hclk. If the internal clock is selected, the divisor should be configured to provide an
accurate 32 kHz clock in order to respect the requirements for a true random generation.
The metrology prescaler must be configured to provide a 24 MHz clock to the metrology
block.
Two master clock output lines can be enabled. The MCO1 is multiplexed with one general
purpose I/O and can take one of the QFS outputs with a configurable prescaler. The MCO2
is a 16 MHz clock output derived from the 24 MHz metrology sub-system clock and it can be
used to provide the same clock reference to additional external metrology devices.
1.9
Power management
The STCOMET should be powered with, at least, two external supply voltages:
3.3 V for I/Os, embedded Flash, QFS, DAC, OSC, ADC general purpose, 1.2 V
regulator and metrology
8 - 18 V for line driver
The device needs also two more supply voltages that can be generated internally:
1.2 V for digital cores and logic, embedded Flash, QFS and oscillator
5 V for the PLC AFE
1.2 V and 5 V can be provided by two internal linear regulators connected respectively to
DVDD_1V2 and AVDD_5V pins and supplied respectively by DVDD_3V3_REG and PVCC
pins. A bypass mode is available for the 1.2 V regulator in case an external source is used.
The device needs also 3 V for the metrology section, always generated internally by an LDO
regulator supplied by the AVDD_3 V3_M pin.
The power-on reset (POR) is conditioned by the level of DVDD_3 V3_IO and DVDD_1V2: at
power on, the whole STCOMET device is kept under reset until the two supply voltages are
above the respective turn-on thresholds named V(DVDD_3 V3_IO)_TH and
V(DVDD_1V2)_TH, while the device is turned off as soon as one of the voltages goes below
its turn-off thresholds, namely V(DVDD_3 V3_IO)_TL and V(DVDD_1V2)_TL.
An internal comparator checks the supply voltage on AVDD_5V_AFE as well, enabling the
use of the PLC AFE when the voltage is above V(AVDD_5V_AFE)_TH and disabling it when
the voltage goes below V(AVDD_5V_AFE)_TL.
Refer to Figure 5 and Figure 6 for the detailed power supply scheme.
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DocID028281 Rev 1
STCOMET
Description
Figure 5. Power supply scheme - digital and metrology sections
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DocID028281 Rev 1
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67
Description
STCOMET
Figure 6. Power supply scheme - PLC AFE and line driver section
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DocID028281 Rev 1
STCOMET
Description
VBAT operation
In case the RTC peripheral is used, the VBAT pin shall be supplied (2.0 V to 3.6 V) for the
RTC core operation and persistence of backup registers. An external battery or a similar
power source can be used.
The VBAT operation is activated, through an on-chip power switch, when the
DVDD_3V3_IO is not present. In this case the main core of the RTC and the backup
registers are under the VBAT domain.
The application can constantly monitor the health of the battery by reading the voltage level
present at the VBAT pin through the channel 7 of the general purpose 12-bit ADC.
A dedicated cutoff switch has been included to avoid continuous leakage from the battery
when the ADC is not sampling the line.
1.10
Low power modes

A clock gating is available for any peripheral in order to save all the dynamic power
contributes related the resources not used by the application.
The CPU is able to run at maximum frequency but, in case lower speed is sufficient to meet
the application requirements, also scaled values are allowed. The CPU could be in low
power modes waiting for wake-up events.
1.11
Real-time clock (RTC) and backup registers

The STCOMET embeds an integrated real-time clock (RTC). The RTC provides a hardware
calendar implementation, instead of a simple 32-bit free-running counter. The calendar can
be initialized to set the current time/date of the system and provide information on subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month),
month, and year.
Software can program the daylight saving compensation; it can control two programmable
alarms (with interrupt function) that can be triggered by any combination of the calendar
fields.
Synchronization can be done with an external clock using the sub-second shift feature.
RTC maskable interrupts/events are:
Alarms: two alarms are present
Timestamps: two timestamps are present
Tamper: two tamper detection inputs are present
The RTC is clocked with a 32.768 kHz external crystal and has coarse calibration (periodic
digital calibration), smooth calibration (0.954 ppm) and analog calibration functionalities.The
1 Hz /512 Hz internal reference clock is optionally available on RTC_TAMPB for calibration.
The RTC has also twenty 32-bit backup registers (80 bytes), available for user defined data
storage. The possibility that backup registers are reset when a tamper detection event
occurs is selectable by software.
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67
Description
1.12
STCOMET
Temperature sensors and overtemperature protection

The STCOMET embeds an overtemperature protection mechanism, with fixed temperature
threshold, preventing the device from overheating. This automatic protection acts by
shutting down the PLC line driver when overheating occurs during PLC transmission. The
normal operation of the line driver is restored automatically as the overtemperature event
has ended.
In addition to the overtemperature automatic protection, information from two temperature
sensors is provided:
The line driver temperature sensor
The low power temperature sensor
The first sensor monitors the line driver temperature and can be used by the RTE to prevent
the line driver to be shut down abruptly by the overtemperature protection. The way to use
this information may depend on the protocol and on the version of the RTE firmware, so its
usage (if any) will be described within the specific firmware documentation released by
STMicroelectronics.
The second sensor monitors the temperature of the low power section of the device. It is
internally connected to the channel 8 of the general purpose 12-bit ADC (see Section :
General purpose analog-to-digital converter (ADC) on page 21 for further details) and it can
be used by the application for its own purposes.
The accuracy of the sensors is guaranteed by design. In case a higher accuracy is required
on the low power temperature sensor, the user shall adopt its own calibration procedure
during the application manufacturing.
1.13
Boot modes
The STCOMET provides different security levels of protection:
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1.
Level 1: unsecure
The Cortex-M4 is accessible through the JTAG and it's possible to download the
firmware in the embedded Flash using debugger plug-in or to load it from the external
NVM using the system boot functionality. It's also possible to download customer OTP
data such as cryptography keys. The shadow sector is not accessible.
2.
Level 2: secure
The JTAG is blocked and it's not possible to access the embedded Flash for external
read or write operation. It's possible to load the ciphered firmware image from the
external NVM and upgrade the firmware thanks to the IAP functionality. Read access to
the embedded Flash is possible to the CortexTM-M4 code, including the shadow sector.
3.
Level 3: secure and locked

The JTAG is blocked and it's not possible to access the embedded Flash for external
read or write operation. Some embedded Flash sectors are locked (for instance the
metrology code ones). It's possible to upgrade the firmware thanks to the IAP
functionality unless the new image tries to change a locked area. Read access to the
embedded Flash is possible to the CortexTM-M4 code, including the shadow sector.
DocID028281 Rev 1
STCOMET
Description
4.
Level 4: secure for customer loader

The JTAG is blocked and it is not possible to access the embedded Flash for the
external read or write operation via the JTAG, while the read and write access is
allowed to the CortexTM-M4 code (with the exception of the shadow sector). With
respect to the Level 2, there is no load or upgrade of the firmware image from the
external NVM. The firmware image shall be already present in the embedded Flash
(loaded in Level 1) and a customer application (secondary bootloader) can manage
upgrades.
5.
Level 1*: secure erase and unlocking

The Cortex-M4 is accessible through the JTAG and it's possible to download
firmware in the embedded Flash. Before the unlocking, the embedded Flash is fully
erased including the customer OTP data. The shadow sector is not accessible.
In order to respect these security requirements, the STCOMET embeds a bootloader code.
The user can also configure the boot mode through the BOOT0/1 pins to select the proper
mode. The following boot modes are available:
1.
Normal mode: this is the standard way of booting the code and eventually load (or
restore) a new image version from the external NVM.
2.
Customer OTP write mode: in this mode the user can write its security keys and data
(e.g.: custom EUI48). After booting in this mode the security level is 2 (secure) or 4
(secure for customer loader) based on the selected option. In the security level 2 only
ciphered firmware can be loaded from an external memory while in the security level 4
the firmware upgrade is left to a customer bootloader.
3.
Unlocking mode: this is the boot mode that enables again all the debug feature.
4.
Low power mode: the minimal boot mode to guarantee low power operations. The
RTE is not enabled and the CortexTM-M4 code is executed as soon as possible at 24
MHz (the user can then scale the clock up or down).
The relationship between the security level and boot mode are shown in Table 5:
Table 5. Boot mode and security level relationship
Boot
mode
Normal
mode
Level 1
Yes
Customer
Yes go to level
OTP write
2 or 4
mode
Level 2
Level 3
Yes
Yes, but no update
If lock option
is performed on
selected for some
locked sector
area go to level 3
Level 4
Level 1*
Yes
(no update is
performed)
Yes
No
No
No
No
Unlocking
mode
Yes go to level
1*
Yes go to level
1*
Yes go to level
1*
Yes go to level
1*
Yes go to level
1*
Low power
mode
Yes
Yes
Yes
Yes
Yes
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67
Description
STCOMET
Table 6 shows the values of the boot pins for each boot mode.
Table 6. Boot modes and BOOT0/1 pin values
1.14
Boot mode
Boot mode value
BOOT1
BOOT0
Normal boot
0x2
Customer OTP write
0x0
Unlocking
0x1
Low power
0x3
System reprogrammability
The STCOMET supports both in-system and in-application programming (ISP and IAP)
modes through the use of the embedded Flash and an external non-volatile memory (NVM).
If the external NVM contains two firmware copies, it's also possible to roll back to the
previous firmware version in case of firmware malfunctioning. The change of firmware to
enable different functionalities will require a complete reset of the device if the customer
does not implement its own bootloader.
1.14.1
In-system programming (ISP)

The ISP mode allows the user to erase and program the embedded Flash through the JTAG
port. This mode can be inhibited to enhance the security level of the device.
1.14.2
In-application programming (IAP)

The IAP mode allows the application on board to store in an external non-volatile memory
the firmware to be downloaded into the internal embedded Flash. The firmware image in the
NVM is copied into the internal embedded Flash at the power-on. The boot code inside the
device takes care of the integrity check, embedded Flash erasure and programming. IAP
can be done using the power line or by the local upgrade port. The customer can also write
its dedicated bootloader to perform IAP with the activation of a specific security level.
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DocID028281 Rev 1
STCOMET
Pinout and pin description
2.1
Pin definition
Figure 7. TQFP176 pinout

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DocID028281 Rev 1
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67
STCOMET
Table 7. Pin description
Type(1) Dir.(2) RS(3)
Pin
Pin name
GPIO00_3
I/O
General purpose I/O, SPI1_MOSI, AT1_CH_1,

FSMC_PCAD_17
GPIO00_2
I/O
General purpose I/O, SPI1_SS, AT1_BKIN,

FSMC_PCAD_18, USART0_SCLK
GPIO00_1
I/O
General purpose I/O, USART0_CTS, FSMC_PCAD_19
DVDD_3 V3_IO
I/O 3.3 V supply
GPIO00_0
I/O
General purpose I/O, USART0_RTS, FSMC_PCAD_20
USART0_RXD
USART0_RXD
USART0_TXD
USART0_TXD
SPI0_SSn
OD
SPI0_SSn
SPI0_SCLK
SPI0_SCLK
10
SPI0_MISO
SPI0_MISO
11
SPI0_MOSI
SPI0_MOSI
12
DVDD_1V2_FLASH
Embedded Flash memory 1.2 V supply
13
DGND
Embedded Flash memory ground
14
DVDD_3 V3_FLASH
Embedded Flash memory 3.3 V supply
15
RESERVED
16
BOOT0
Boot mode selector pin 0
17
BOOT1
Boot mode selector pin 1
18
JTAG_TRSTn
JTAG test reset - active low
19
JTAG_TDI
JTAG test data input
20
JTAG_TMS
JTAG test mode select input, SWIO
21
JTAG_TCK
JTAG test clock input, SWCLK
22
JTAG_TDO
JTAG test data output, SWV
23
DVDD_1V2_ MCLK
24 MHz oscillator 1.2 V supply
24
DVDD_3 V3_IO
I/O 3.3 V supply
25
MCLK_IN
24 MHz oscillator input
26
MCLK_OUT
24 MHz oscillator output
27
DVDD_3 V3_REG
3.3 V input for the 1.2 V regulator
28
DVDD_1V2
I/O
I/O
1.2 V regulator output / external supply input
29
DVDD_1V2_QFS
QFS 1.2 V supply
30
DVDD_3 V3_QFS
QFS 3.3 V supply
31
DGND
QFS ground
32
AVDD_5V_PGA
PGA 5 V supply
33
RX_INN
PGA negative input
34/67
Description
Reserved, tie to DGND
DocID028281 Rev 1
STCOMET

Table 7. Pin description (continued)
Pin
Pin name
Description
34
RX_INP
PGA positive input
35
AGND
PGA ground
36
ZC_IN
Zero crossing comparator input
37
ZC_AGND_REF
Zero crossing comparator ground reference - connect to

AGND
38
AVDD_5V_AFE
PLC AFE 5 V supply + receiver ADC supply
39
PVCC
PA supply
40
PGND
PA ground
41
PA2_OUT
PA2 output
42
PA2_OUT
PA2 output
43
PA1_OUT
PA1 output
44
PA1_OUT
PA1 output
45
PGND
PA ground
46
PVCC
PA supply / 5 V regulator input voltage
47
PA1_INN
PA1 inverting input
48
PA1_INP
PA1 non-inverting input
49
PA2_INP
PA2 non-inverting input
50
PA2_INN
PA2 inverting input
51
AGND
5 V regulator ground
52
CSF
I/O
I/O
Current sense feedback
53
AVDD_5V
I/O
I/O
5 V regulator output / external supply input
54
RESERVED
Reserved - connect to AGND
55
AGND
Transmission predriver ground
56
TXDRV_OUTP
Transmission predriver positive output
57
TXDRV_OUTN
Transmission predriver negative output
58
AVDD_5V_TXDRV
Transmission predriver 5 V supply
59
AVDD_3 V3_DAC
Transmission DAC 3.3 V supply
60
AGND
Transmission DAC ground
61
DAC_OUTP
Transmission DAC positive output
62
DAC_OUTN
Transmission DAC negative output
63
DVDD_3 V3_IO
I/O 3.3 V supply
64
GPIO10_7
I/O
General purpose I/O, USART4_SCLK, AT0_BKIN,

SPI2_SSn, I2C2_SCL
65
GPIO10_6
I/O
General purpose I/O, USART4_TXD, AT0_CH_1,

SPI2_SCLK, I2C2_SDA
DocID028281 Rev 1
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67
STCOMET
Pin
Pin name
66
GPIO10_5
I/O
General purpose I/O, USART4_RXD, AT0_CH_2,

SPI2_MISO, I2C0_SCL
67
GPIO10_4
I/O
General purpose I/O, USART4_CTS, AT0_CH_3,

SPI2_MOSI, I2C0_SDA
68
GPIO10_3
I/O
General purpose I/O, USART4_RTS, AT0_CH_4,

USART3_CTS, I2C2_SMBA
69
GPIO10_2
I/O
General purpose I/O, AT0_CHN_1, USART3_RTS,

I2C0_SMBA
70
GPIO10_1
I/O
General purpose I/O, AT0_CHN_2, USART3_RXD
71
GPIO10_0
I/O
General purpose I/O, AT0_CHN_3, USART3_TXD
72
DVDD_3 V3_REG
73
DVDD_1V2
I/O
I/O
74
RESETn
I/OD
I/OD
Reset input, open drain output - active low
75
GPIO09_7
I/O
General purpose I/O, AT0_ETR, ETM_SWO, SPI4_SCLK
76
GPIO09_6
I/O
General purpose I/O, USART3_SCLK, ETM_DATA_3,

SPI4_MISO
77
GPIO09_5
I/O
General purpose I/O, METROLOGY_ZCOUT,

ETM_DATA_2, SPI4_MOSI
78
GPIO09_4
I/O
General purpose I/O, METROLOGY_LED_1,

ETM_DATA_1, SPI4_SSn
79
GPIO09_3
I/O
General purpose I/O, METROLOGY_LED_0,

ETM_DATA_0, USART2_CTS, MCO2
80
GPIO09_2
I/O
General purpose I/O, ETM_CLKOUT, USART2_RTS
81
GPIO09_1
I/O
General purpose I/O, CAN1_RX, USART2_RXD
82
GPIO09_0
I/O
General purpose I/O, CAN1_TX, USART2_TXD
83
DVDD_3 V3_IO
I/O 3.3 V supply
84
METR_AVDD_3 V3
Metrology 3.3 V supply / 3.0 V regulator input
85
METR_AGND_REG
Metrology 3.0 V regulator ground
86
METR_AVDD_3 V0
Metrology 3.0 V regulator output
87
METR_AGND
Metrology analog ground
88
METR_VREF
Metrology 1.2 V voltage reference output
89
METR_AP
Metrology auxiliary current channel positive input
90
METR_AN
Metrology auxiliary current channel negative input
91
METR_IP
Metrology current channel positive input
92
METR_IN
Metrology current channel negative input
93
METR_VN
Metrology voltage channel negative input
94
METR_VP
Metrology voltage channel positive input
95
METR_GND_ESD
Metrology ESD ring ground
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Description
DocID028281 Rev 1
STCOMET

Pin
Pin name
Description
96
RTC_TAMPB
I/O
Tamper input B, RTC clock output
97
RTC_TAMPA
Tamper input A
98
VBAT
2.0 to 3.6 V battery supply input
99
DVDD_3 V3_IO
I/O 3.3 V supply
100
OSC32_OUT
32 kHz oscillator output
101
OSC32_IN
32 kHz oscillator input
102
ADC_VREFN
General purpose ADC negative reference voltage input
103
ADC_VREFP
General purpose ADC positive reference voltage input
104
GPIO08_5
I/O
General purpose I/O, ADC_MUX_VIN_5, SPI3_SSn,

USART2_SCLK
105
GPIO08_4
I/O
General purpose I/O, ADC_MUX_VIN_4, SPI3_SCLK
106
GPIO08_3
I/O
General purpose I/O, ADC_MUX_VIN_3, USART1_CTS,

SPI3_MISO
107
GPIO08_2
I/O
General purpose I/O, ADC_MUX_VIN_2, USART1_RTS,

SPI3_MOSI
108
GPIO08_1
I/O
General purpose I/O, ADC_MUX_VIN_1, USART1_RXD,

I2C1_SCL
109
GPIO08_0
I/O
General purpose I/O, ADC_MUX_VIN_0, USART1_TXD,

I2C1_SDA, AT1_ETR
110
GPIO07_7
I/O
General purpose I/O, AT1_CHN_3, SPI1_SCLK
111
GPIO07_6
I/O
General purpose I/O, AT1_CHN_2, SPI1_MISO
112
GPIO07_5
I/O
General purpose I/O, AT1_CHN_1, SPI1_MOSI
113
GPIO07_4
I/O
General purpose I/O, AT1_CH_4, SPI1_SSn
114
GPIO07_3
I/O
General purpose I/O, AT1_CH_3
115
GPIO07_2
I/O
General purpose I/O, AT1_CH_2
116
GPIO07_1
I/O
General purpose I/O, AT1_CH_1, CAN0_RX
117
GPIO07_0
I/O
General purpose I/O, AT1_BKIN, CAN0_TX
118
GPIO06_7
I/O
General purpose I/O, SPI4_SSn, METROLOGY_ZCOUT,

ETM_SWO
119
GPIO06_6
I/O
General purpose I/O, SPI4_SCLK, METROLOGY_LED_1,

ETM_DATA_3
120
GPIO06_5
I/O
General purpose I/O, SPI4_MISO, METROLOGY_LED_0,

ETM_DATA_2
121
GPIO06_4
I/O
General purpose I/O, SPI4_MOSI, ETM_DATA_1
122
GPIO06_3
I/O
General purpose I/O, USART3_CTS, I2C1_SCL,

ETM_DATA_0
123
GPIO06_2
I/O
General purpose I/O, USART3_RTS, I2C1_SDA,

ETM_CLKOUT
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67
STCOMET
Pin
Pin name
124
GPIO06_1
I/O
General purpose I/O, USART3_RXD, I2C1_SMBA,

I2C2_SCL
125
GPIO06_0
I/O
General purpose I/O, USART3_TXD, I2C2_SDA
126
GPIO05_7
I/O
General purpose I/O, USART3_SCLK, I2C2_SMBA
127
GPIO05_6
I/O
General purpose I/O, USART0_CTS
128
GPIO05_5
I/O
General purpose I/O, USART0_RTS
129
GPIO05_4
I/O
General purpose I/O, MCO1
130
DVDD_3 V3_IO
I/O 3.3 V supply
131
GPIO05_3
I/O
General purpose I/O, FSMC_Ebar_1
132
GPIO05_2
I/O
General purpose I/O, USART2_SCLK, FSMC_Ebar_0
133
GPIO05_1
I/O
General purpose I/O, USART2_RXD, SPI2_SSn,

FSMC_BLn_0
134
GPIO05_0
I/O
General purpose I/O, USART2_TXD, SPI2_SCLK,

FSMC_BLn_1
135
DVDD_3 V3_IO
I/O 3.3 V supply
136
GPIO04_7
I/O
General purpose I/O, USART2_CTS, SPI2_MISO,

FSMC_PCDA_0
137
GPIO04_6
I/O
General purpose I/O, USART2_RTS, SPI2_MOSI,

FSMC_PCDA_1, MCO1
138
GPIO04_5
I/O
General purpose I/O, FSMC_PCDA_2
139
GPIO04_4
I/O
140
GPIO04_3
I/O
141
GPIO04_2
I/O
142
GPIO04_1
I/O
143
GPIO04_0
I/O
144
GPIO03_7
I/O
General purpose I/O, SPI3_SSn, FSMC_PCDA_8
145
GPIO03_6
I/O
General purpose I/O, SPI3_SCLK, FSMC_PCDA_9
146
GPIO03_5
I/O
General purpose I/O, SPI3_MISO, FSMC_PCDA_10
147
GPIO03_4
I/O
General purpose I/O, SPI3_MOSI, FSMC_PCDA_11,

USART3_SCLK
148
GPIO03_3
I/O
General purpose I/O, SPI2_SSn, USART3_CTS,

FSMC_PCDA_12
149
GPIO03_2
I/O
General purpose I/O, SPI2_SCLK, USART3_RTS,

FSMC_PCDA_13
150
GPIO03_1
I/O
General purpose I/O, SPI2_MISO, USART3_RXD,

FSMC_PCDA_14
151
GPIO03_0
I/O
General purpose I/O, SPI2_MOSI, USART3_TXD,

FSMC_PCDA_15
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Description
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STCOMET

Pin
Pin name
Description
152
DVDD_1V2
I/O
I/O
153
DVDD_3 V3_REG
154
DVDD_3 V3_IO
I/O 3.3 V supply
155
RESERVED
Reserved - connect to DGND
156
GPIO02_7
I/O
General purpose I/O, AT0_BKIN, FSMC_Lbar,

USART4_SCLK
157
GPIO02_6
I/O
General purpose I/O, AT0_CH_1, FSMC_PCWEn,

USART4_TXD
158
GPIO02_5
I/O
General purpose I/O, AT0_CHN_1, FSMC_PCOEn,

USART4_RXD
159
GPIO02_4
I/O
General purpose I/O, AT0_CH_2, FSMC_PCAD_0,

USART4_CTS
160
GPIO02_3
I/O
General purpose I/O, AT0_CHN_2, FSMC_PCAD_1,

USART4_RTS
161
GPIO02_2
I/O
General purpose I/O, AT0_CH_3, FSMC_PCAD_2
162
GPIO02_1
I/O
General purpose I/O, AT0_CHN_3, I2C2_SCL,

FSMC_PCAD_3
163
GPIO02_0
I/O
General purpose I/O, AT0_CH_4, I2C2_SDA,

FSMC_PCAD_4
164
GPIO01_7
I/O
General purpose I/O, AT0_ETR, I2C2_SMBA,

FSMC_PCAD_5, I2C1_SMBA
165
GPIO01_6
I/O
General purpose I/O, I2C1_SCL, CAN1_RX,

FSMC_PCAD_6
166
GPIO01_5
I/O
General purpose I/O, I2C1_SDA, CAN1_TX,

FSMC_PCAD_7
167
GPIO01_4
I/O
General purpose I/O, USART1_CTS, CAN0_RX,

FSMC_PCAD_8
168
GPIO01_3
I/O
General purpose I/O, USART1_RTS, CAN0_TX,

FSMC_PCAD_9
169
GPIO01_2
I/O
General purpose I/O, USART1_RXD, AT1_ETR,

FSMC_PCAD_10
170
GPIO01_1
I/O
General purpose I/O, USART1_TXD, AT1_CHN_3,

FSMC_PCAD_11
171
GPIO01_0
I/O
General purpose I/O, I2C0_SMBA, AT1_CHN_2,

FSMC_PCAD_12, USART1_SCLK
172
GPIO00_7
I/O
General purpose I/O, I2C0_SCL, AT1_CHN_1,

FSMC_PCAD_13
173
GPIO00_6
I/O
General purpose I/O, I2C0_SDA, AT1_CH_4,

FSMC_PCAD_14
174
GPIO00_5
I/O
General purpose I/O, SPI1_SCLK, AT1_CH_3,

FSMC_PCAD_15
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67
STCOMET
Pin
Pin name
Description
175
DVDD_3 V3_IO
I/O 3.3 V supply
176
GPIO00_4
I/O
General purpose I/O, SPI1_MISO, AT1_CH_2,

FSMC_PCAD_16
177
EXPAD
Exposed pad - DGND
1. Type: D = digital; A = analog; S = supply/ground.

2. Direction: I = input; O = output; I/O = input/output, OD = open drain.
3. Reset status: I = input, I/O = input/output, O = output.
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STCOMET
2.2
GPIOs multiplexing scheme

In the STCOMET, peripherals are connected to I/Os through a multiplexer. At a time one
single peripheral can control the I/Os. In this way, there is no conflict between peripherals
sharing the same I/O pins.
Thanks to a set of configuration registers, the user can select one of the 4 possible alternate
functions for each pin as described in Table 8.
Table 8. GPIOs multiplexing scheme
Pin name
Selection: 000
Selection: 001
Selection: 010
GPIO00_0
USART0_RTS
FSMC_PCAD_20
GPIO00_1
USART0_CTS
FSMC_PCAD_19
GPIO00_2
SPI1_SS
AT1_BKIN
FSMC_PCAD_18
GPIO00_3
SPI1_MOSI
AT1_CH_1
FSMC_PCAD_17
GPIO00_4
SPI1_MISO
AT1_CH_2
FSMC_PCAD_16
GPIO00_5
SPI1_SCLK
AT1_CH_3
FSMC_PCAD_15
GPIO00_6
I2C0_SDA
AT1_CH_4
FSMC_PCAD_14
GPIO00_7
I2C0_SCL
AT1_CHN_1
FSMC_PCAD_13
GPIO01_0
I2C0_SMBA
AT1_CHN_2
FSMC_PCAD_12
GPIO01_1
USART1_TXD
AT1_CHN_3
FSMC_PCAD_11
GPIO01_2
USART1_RXD
AT1_ETR
FSMC_PCAD_10
GPIO01_3
USART1_RTS
CAN0_TX
FSMC_PCAD_9
GPIO01_4
USART1_CTS
CAN0_RX
FSMC_PCAD_8
GPIO01_5
I2C1_SDA
CAN1_TX
FSMC_PCAD_7
GPIO01_6
I2C1_SCL
CAN1_RX
FSMC_PCAD_6
GPIO01_7
AT0_ETR
I2C2_SMBA
FSMC_PCAD_5
GPIO02_0
AT0_CH_4
I2C2_SDA
FSMC_PCAD_4
GPIO02_1
AT0_CHN_3
I2C2_SCL
FSMC_PCAD_3
GPIO02_2
AT0_CH_3
FSMC_PCAD_2
GPIO02_3
AT0_CHN_2
FSMC_PCAD_1
USART4_RTS
GPIO02_4
AT0_CH_2
FSMC_PCAD_0
USART4_CTS
GPIO02_5
AT0_CHN_1
FSMC_PCOEn
USART4_RXD
GPIO02_6
AT0_CH_1
FSMC_PCWEn
USART4_TXD
GPIO02_7
AT0_BKIN
FSMC_Lbar
USART4_SCLK
GPIO03_0
SPI2_MOSI
USART3_TXD
FSMC_PCDA_15
GPIO03_1
SPI2_MISO
USART3_RXD
FSMC_PCDA_14
GPIO03_2
SPI2_SCLK
USART3_RTS
FSMC_PCDA_13
GPIO03_3
SPI2_SS
USART3_CTS
FSMC_PCDA_12
GPIO03_4
SPI3_MOSI
FSMC_PCDA_11
DocID028281 Rev 1
Selection: 011
USART0_SCLK
USART1_SCLK
I2C1_SMBA
USART3_SCLK
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STCOMET
Table 8. GPIOs multiplexing scheme (continued)

Pin name
Selection: 000
Selection: 001
Selection: 010
GPIO03_5
SPI3_MISO
FSMC_PCDA_10
GPIO03_6
SPI3_SCLK
FSMC_PCDA_9
GPIO03_7
SPI3_SS
FSMC_PCDA_8
GPIO04_0
FSMC_PCDA_7
GPIO04_1
FSMC_PCDA_6
GPIO04_2
FSMC_PCDA_5
GPIO04_3
FSMC_PCDA_4
GPIO04_4
FSMC_PCDA_3
GPIO04_5
FSMC_PCDA_2
GPIO04_6
USART2_RTS
SPI2_MOSI
FSMC_PCDA_1
GPIO04_7
USART2_CTS
SPI2_MISO
FSMC_PCDA_0
GPIO05_0
USART2_TXD
SPI2_SCLK
FSMC_BLn_1
GPIO05_1
USART2_RXD
SPI2_SS
FSMC_BLn_0
GPIO05_2
USART2_SCLK
FSMC_Ebar_0
GPIO05_3
GPIO05_4
Selection: 011
FSMC_Ebar_1
MCO1
GPIO05_5
USART0_RTS
GPIO05_6
USART0_CTS
GPIO05_7
USART3_SCLK
I2C2_SMBA
GPIO06_0
USART3_TXD
I2C2_SDA
GPIO06_1
USART3_RXD
I2C1_SMBA
GPIO06_2
USART3_RTS
I2C1_SDA
ETM_CLKOUT
GPIO06_3
USART3_CTS
I2C1_SCL
ETM_DATA_0
GPIO06_4
SPI4_MOSI
GPIO06_5
SPI4_MISO
METROLOGY_LED_0
ETM_DATA_2
GPIO06_6
SPI4_SCLK
METROLOGY_LED_1
ETM_DATA_3
GPIO06_7
SPI4_SS
METROLOGY_ZCOUT
ETM_SWO
GPIO07_0
AT1_BKIN
CAN0_TX
GPIO07_1
AT1_CH_1
CAN0_RX
GPIO07_2
AT1_CH_2
GPIO07_3
AT1_CH_3
GPIO07_4
AT1_CH_4
SPI1_SS
GPIO07_5
AT1_CHN_1
SPI1_MOSI
GPIO07_6
AT1_CHN_2
SPI1_MISO
GPIO07_7
AT1_CHN_3
SPI1_SCLK
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I2C2_SCL
ETM_DATA_1
DocID028281 Rev 1
STCOMET

Table 8. GPIOs multiplexing scheme (continued)
Pin name
Selection: 000
Selection: 001
Selection: 010
Selection: 011
GPIO08_0
ADC_CH_0
USART1_TXD
I2C1_SDA
AT1_ETR
GPIO08_1
ADC_CH_1
USART1_RXD
I2C1_SCL
GPIO08_2
ADC_CH_2
USART1_RTS
SPI3_MOSI
GPIO08_3
ADC_CH_3
USART1_CTS
SPI3_MISO
GPIO08_4
ADC_CH_4
SPI3_SCLK
GPIO08_5
ADC_CH_5
SPI3_SS
USART2_SCLK
GPIO09_0
CAN1_TX
USART2_TXD
GPIO09_1
CAN1_RX
USART2_RXD
GPIO09_2
ETM_CLKOUT
USART2_RTS
METROLOGY_LED_0
ETM_DATA_0
USART2_CTS
GPIO09_4
METROLOGY_LED_1
ETM_DATA_1
SPI4_SS
GPIO09_5
METROLOGY_ZCOUT
ETM_DATA_2
SPI4_MOSI
GPIO09_6
USART3_SCLK
ETM_DATA_3
SPI4_MISO
GPIO09_7
AT0_ETR
ETM_SWO
SPI4_SCLK
GPIO10_0
AT0_CHN_3
USART3_TXD
GPIO10_1
AT0_CHN_2
USART3_RXD
GPIO10_2
AT0_CHN_1
USART3_RTS
I2C0_SMBA
GPIO09_3
MCO2
GPIO10_3
USART4_RTS
AT0_CH_4
USART3_CTS
I2C2_SMBA
GPIO10_4
USART4_CTS
AT0_CH_3
SPI2_MOSI
I2C0_SDA
GPIO10_5
USART4_RXD
AT0_CH_2
SPI2_MISO
I2C0_SCL
GPIO10_6
USART4_TXD
AT0_CH_1
SPI2_SCLK
I2C2_SDA
GPIO10_7
USART4_SCLK
AT0_BKIN
SPI2_SS
I2C2_SCL
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67
Memory map
STCOMET
Memory map
Figure 8. Memory map
0xFFFF.FFFF
Reserved
0x6800.0000
0x67FF.FFFF
FSMCBank1
FSMCBank0
Reserved
Com2
Reserved
Com1
Basic
Reserved
IPCregs
0x4000.5FFF
0x4000.4FFF
0x4000.3FFF
0x4000.2FFF
COM1APBGPIO2
0x4001.8FFF
0x4001.7FFF
0x4001.6FFF
0x4001.5FFF
COM1APBGPIO1
0x4001.4FFF
COM1APBGPIO0
0x4001.3FFF
COM1APBAT0
0x4001.2FFF
COM1APBSPI1
0x4001.1FFF
COM1APBSPI0
0x4001.0FFF
IPC(8K)
0x4000.1FFF
COM1APBI2C0
0x4000.0FFF
0x4000.0000
RAM64K
0x2000.0000
COM1APBCAN0
COM1APBUART1
COM1APBUART0
BasicAPBWWDOG
0x4004.FFFF
Reserved
0x4004.6000
BasicAPBRTC
0x4004.5FFF
CryptoAPBTRNG
0x4004.5000
0x4004.4FFF
0x4004.2FFF
0x4004.0FFF
0x4004.0000
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0x4002.7FFF
COM2APBADC
0x4002.6FFF
COM2APBSPI4
0x4002.5FFF
COM2APBSPI3
0x4002.4FFF
COM2APBSPI2
0x4002.3FFF
COM2APBI2C1
COM2APBCAN1
DocID028281 Rev 1
0x4002.1FFF
COM2APBUART3
0x4002.1000
0x4002.0FFF
0x4002.0000
CryptoAPBPRNG
CryptoAPBAES
CryptoAPBCRC
CryptoAPBUSART4
0x4004.1000
eFLASH
(Read/Write)
COM2APBAT1
0x4002.2000
0x4004.1FFF
0x0000.0000
0x4002.8FFF
0x4002.2FFF
0x4004.2000
0x002F.FFFF
COM2APBGPIO5
0x4002.3000
BasicAPBGPT0
0x4004.3FFF
0x0030.0000
0x4002.9FFF
0x4002.4000
0x4004.3000
COM2APBGPIO6
0x4002.5000
0x4004.4000
0x1FFF.FFFF
0x4002.AFFF
0x4002.6000
0x4001.0000
0x4000.1000
RAM64K
COM2APBGPIO7
0x4002.7000
0x4001.1000
BasicAPBGPT1
0x4002.BFFF
0x4002.8000
0x4001.2000
BasicAPBGPT2
COM2APBGPIO8
0x4002.9000
0x4001.3000
BasicAPBGPT3
0x4002.CFFF
0x4002.A000
0x4001.4000
BasicAPBGPT4
COM2APBGPIO9
0x4002.B000
0x4001.5000
BasicAPBGPT5
0x4002.DFFF
COM2APB
GPIO10
0x4002.C000
0x4000.2000
0x2001.0000
0x2000.FFFF
0x4000.6FFF
0x4001.9FFF
Reserved
0x4002.D000
0x4001.6000
0x4000.3000
0x2002.0000
0x2001.FFFF
BasicAPBGPT7
BasicAPBGPT6
0x4000.7FFF
COM1APBGPIO3
0x4001.7000
0x4000.4000
0x2002.2000
0x2002.1FFF
BasicAPBSYSCTRL
0x4000.5000
0x2002.3000
0x2002.2FFF
0x4000.8800
0x4001.AFFF
0x4002.EFFF
0x4002.E000
0x4001.8000
0x4000.6000
0x4000.0000
0x3FFF.FFFF
BasicAPBeFLASH
0x4000.7000
0x4001.0000
0x4000.FFFF
0x4000.9000
COM1APBGPIO4
0x4001.9000
0x4000.8000
0x4001.C000
0x4001.BFFF
BasicAPBMISC
0x4000.87FF
0x4002.0000
0x4001.FFFF
0x4000.A000
Reserved
0x4002.F000
0x4002.EFFF
0x4000.C000
0x4001.BFFF
0x4002.FFFF
0x4002.F000
0x4001.A000
0x4000.8FFF
Metrology
0x4003.0000
0x4002.FFFF
BasicAPBFSMC
0x4000.9FFF
Reserved
0x4003.1000
0x4003.0FFF
0x4000.DFFF
Reserved
0x4001.B000
0x4000.BFFF
Crypto
0x4004.0000
0x4003.FFFF
BasicAHBDMAC
0x4000.D000
0x4000.CFFF
0x4004.6000
0x4004.5FFF
0x4000.EFFF
0x4001.FFFF
0x4001.C000
0x4000.E000
0x6000.0000
0x5FFF.FFFF
BasicAHBATT
0x4000.F000
0x6400.0000
0x63FF.FFFF
0x4000.FFFF
CryptoAPBI2C2
COM2APBUART2
STCOMET
Electrical characteristics
4.1
Absolute maximum ratings

Table 9. Absolute maximum ratings - voltage
Symbol
Min.
Max.
Unit
Line driver supply voltage range
PGND -0.3
20
AVDD_5V
5 V internal regulator voltage range
AGND -0.3
Min. (5.5, PVCC +0.3)
AVDD_5V_AFE,
AVDD_5V_PGA,
AVDD_5V_TXDRV
5 V PLC AFE supply voltage range
AGND -0.3
Min. (5.5, PVCC +0.3)
AVDD_3 V3_DAC
3.3 V PLC AFE supply voltage range
AGND -0.3
5.2
M_GND_REG -0.3
5.2
GND-0.3
5.2
DGND -0.3
5.2
GND -0.3
2.4
1.2 V QFS supply voltage range
GND -0.3
2.4
ADC_VREFP
General purpose ADC positive reference

voltage range
GND -0.3
Min. (5.2,
DVDD_3V3_IO + 0.3)
ADC_VREFN
General purpose ADC negative

reference voltage range
GND -0.3
Min. (5.2,
DVDD_3V3_IO + 0.3)
VBAT voltage range
GND -0.3
5.2
GND -0.3
GND +0.3
AGND -0.3
AGND +0.3
GND -0.3
Min. (5.2,
DVDD_3V3_IO + 0.3)
PA output pins voltage range
PGND -0.3
Min. (20, PVCC +0.3)
PA_IN
PA input pins voltage range
AGND -0.3
Min. (20, PVCC +0.3)
RX_IN
RX_IN input pins voltage range
-5.5
ZC_IN
ZC_IN voltage range
-5.5
Min. (5.5,
AVDD_5V_ AFE +0.3)
DAC output pins voltage range
AGND -0.3
Min. (5.2,
AVDD_5V_ AFE +0.3)
TXDRV output voltage range
AGND -0.3
Min (. 5.5,
AVDD_5V_ AFE +0.3)
CSF pin voltage range
AGND-0.3
AVDD_5V +0.3
PVCC
METR_AVDD_3 V3
DVDD_3 V3_IO,
DVD_3 V3_REG
DVDD_3 V3_QFS
Parameter
3.3 V metrology analog supply voltage

range
I/O supply voltage range
3.3 V QFS supply voltage range
DVDD_1V2,
1.2 V digital supply voltage range
DVDD_1V2_FLASH
DVDD_1V2_QFS
VBAT
DGND, AGND,
METR_AGND,
Variations between different ground pins
METR_AGND_REG,
METR_GND_ESD
PGND
V(DIG_IN)
PA_OUT
DAC_OUT
TXDRV_OUT
CSF
Variations between different ground pins

Input voltage range
DocID028281 Rev 1
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67
STCOMET
Table 9. Absolute maximum ratings - voltage (continued)

Symbol
Parameter
Min.
Max.
Unit
V(METR_ INPUT)
Metrology ADC input pins voltage range
METR_GND_ESD
-0.3
METR_GND_ESD
+0.3
V(MCLK)
24 MHz oscillator pins voltage range
GND-0.3
Min. (5.2,
DVDD_3 V3_IO+0.3)
V(OSC32)
32 kHz oscillator pins voltage range
GND-0.3
Min. (5.2,
DVDD_3V3_IO + 0.3)
-2
+2
kV
Max.
Unit
1.5
A rms
V(ESD)
Maximum withstanding voltage range

Test condition:
ANSI-ESDA-JEDEC_JS-001 human
body model acceptance criteria: normal
performance
Table 10. Absolute maximum ratings - current

Symbol
I(PA_OUT)
4.2
Parameter
Min.
PA repetitive RMS current
Thermal characteristics
Table 11. Thermal characteristics
Symbol
T(J)
46/67
Parameter
Conditions
Min.
Junction temperature
Max.
Unit
125
T(AMB)
Operating ambient temperature
-40
85
T(STG)
Storage temperature
-50
150
DocID028281 Rev 1
STCOMET
4.3
Operating conditions
T(AMB) = -40 to +85 C, T(J) < 125 C, PVCC = 18 V unless otherwise specified.
All typical values are referred to T(AMB) = 25 C.
Power supply characteristics

Table 12. Analog supply characteristics
Symbol
Parameter(1)
V(PVCC)
Line driver supply voltage
I(PVCC)_RX
Line driver supply current

Rx mode
I(PVCC)_TX
Line driver supply current

Tx mode, no load
Conditions
Min.
Typ.
15
Max. Unit
18
No load on AVDD_5V
500
No load on AVDD_5V
Dual power amplifier
configuration
40
mA
No load on AVDD_5V
Single power amplifier
configuration
20
mA
V(PVCC)_TH

turn-on threshold
V(PVCC)_TL

turn-off threshold
6.5
V(PVCC)_HYST

hysteresis
0.5
V(AVDD_5V)
5 V regulator output
voltage , no load
4.5
5.5
V(AVDD_5V_AFE)_TH
5 V PLC AFE supply

voltage turn-on threshold
4.33
V(AVDD_5V_AFE)_TL
5 V PLC AFE supply

voltage turn-off threshold
4.26
60
mV
V(AVDD_5V_AFE)_HYST
I(5V)_RX
I(5V)_TX
5 V PLC AFE supply

voltage hysteresis
5 V PLC AFE supply
current Rx mode
See(2)
PGA maximum gain
54
mA
5 V PLC AFE supply

current Rx active mode
See(2)
PGA maximum gain
Rx in progress
61
mA
5 V PLC AFE supply

current Tx mode, no load
See(2)
mA
1.6
mA
mA
I(AVDD_3V3_DAC)
RX
3.3 V PLC AFE supply

current Rx mode
I(AVDD_3V3_DAC)
TX
3.3 V PLC AFE supply

current Tx mode
DAC full scale current = 4 mA

Sine wave output f = 100 kHz
DocID028281 Rev 1
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67
STCOMET
Table 12. Analog supply characteristics (continued)

Parameter(1)
Symbol
Conditions
Min.
Typ.
3.0
3.3
Max. Unit
V(DVDD_3V3_IO)
Digital I/O supply voltage
V(DVDD_3V3_IO)_TH

turn-on threshold
2.82
V(DVDD_3V3_IO)_TL

turn-off threshold
2.7
V(DVDD_3V3_IO)_HYST

hysteresis
0.1
1.2 V regulator input

voltage
3.3
V(DVDD_3V3_REG)
3.6
V(DVDD_1V2)
1.2 V regulator output

voltage
Low power mode
1.233
High power mode
1.285
I(DVDD_1V2)
1.2 V regulator output

current
Low power mode
15
mA
High power mode
300
mA
V(DVDD_1V2)_TH
1.2 V supply voltage

turn-on threshold
Low and high power modes
1.11
V(DVDD_1V2)_TL

turn-off threshold
Low and high power modes
1.025
V(DVDD_1V2)_HYST

hysteresis
Low power mode
86
mV
High power mode
86
mV
METR_AVDD_3V3
Operating supply voltage
V(METR_AVDD_3V3)_TH
3.3 V metrology supply

voltage turn-on threshold
METR_AVDD_3V0
Regulated supply voltage
2.95
METR_AVDD_3V3 = 3.3 V;
CL = 100 nF; no loads
3.3
3.65
2.5
3.08
1. Based on characterization, not tested in production.

2. I(5 V) = I(AVDD_5V_AFE) + I(AVDD_5V_PGA) + I(AVDD_5V_TXDRV).
Table 13. Digital supply characteristics - RTE

Symbol
I(DVDD_1V2)
I(DVDD_1V2)
Parameter(1)
Conditions
1.2 V digital supply current RTE frequency = 48 MHz see(2)

1.2 V digital supply current
RTE frequency = 120 MHz see(2)
Min.
Typ.
Max. Unit
29
mA
68
mA

2. The tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG, QFS. Cortex frequency equals to 48 MHz and Cortex fetching by RAM. The value is calculated by measuring
the difference in the supply current with and without RTE enabled and running.
48/67
DocID028281 Rev 1
STCOMET
Table 14. Metrology power consumption
Symbol
Parameter
I(DVDD_1V2)
Conditions
I(METR_AVDD_3V3)
3.3 V metrology supply current
Typ.
Max. Unit
See(1)
0.4
mA
(1)
2.7
mA
See
Min.
TRNG, QFS. Cortex frequency equals to 96 MHz and Cortex fetching by RAM. The values are calculated by measuring
the difference in the supply current with and without metrology enabled and running.
Table 15. Digital supply characteristics - Cortex-M4 fetching from RAM

Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
see(1)
9.6
mA
I(DVDD_1V2)
Cortex frequency = 24 MHz
I(DVDD_3V3)
Cortex frequency = 24 MHz see(1)
0.9
mA
see(1)
I(DVDD_1V2)
I(DVDD_3V3)
Cortex frequency = 48 MHz
16.4
mA
(1)
0.9
mA
(1)
23.8
mA
Cortex frequency = 48 MHz see
I(DVDD_1V2)
I(DVDD_3V3)
0.9
mA
(1)
30.9
mA
(1)
0.9
I(DVDD_1V2)
I(DVDD_3V3)
mA
2
1. All the tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I C, AES,
TRNG, QFS.
Table 16. Digital supply characteristics - Cortex-M4 fetching data from eFlash
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
I(DVDD_1V2)
11.2
mA
I(DVDD_3V3)
3.5
mA
I(DVDD_1V2)
17.6
mA
(1)
3.6
mA
(1)
I(DVDD_3V3)
I(DVDD_1V2)
24.2
mA
I(DVDD_3V3)
3.7
mA
I(DVDD_1V2)
30.6
mA
(1)
I(DVDD_3V3)
3.8
mA
2
1. All the tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I C, AES,
TRNG, QFS.
DocID028281 Rev 1
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67
STCOMET
Table 17. Digital supply characteristics - DOZE (sleep)/deepsleep mode

Symbol
I(DVDD_1V2)
I(DVDD_3V3)
Parameter
Conditions
Min.
Cortex in DOZE mode see(1)
(1)
Cortex in DOZE mode see
Typ.
Max. Unit
6.5
mA
0.9
mA
(1)
6.5
mA
0.9
I(DVDD_1V2)
Cortex in deepsleep mode see
I(DVDD_3V3)
Cortex in deepsleep mode see(1)
mA
2
1. The test is performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I C, AES,
TRNG.
Table 18. Supply characteristics - QFS

Symbol
Parameter
Conditions
Min. Typ. Max. Unit
I(DVDD_1V2_QFS)
QFS power consumption from 1.2 V

Master clock = 24 MHz see(1)
power supply
5.1
mA
I(DVDD_3V3_QFS)
QFS power consumption from 3.3 V

Master clock = 24 MHz see(1)
power supply
1.1
mA
1. The test is performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG. The value is calculated by measuring the difference in the supply current with and without QFS enabled and running.
Table 19. 24 MHz oscillator

Symbol
f(MCLK)
C0
ESR
CL
Parameter
Conditions
Min.
Crystal oscillator frequency
Typ. Max. Unit

24
External quartz crystal

Shunt capacitance
External quartz crystal ESR value
See(1)
MCLK_IN , MCLK_OUT load

capacitance
See(1)
10
MHz
3.5
pF
60
15
pF
1. Guaranteed by design, not tested in production.
Table 20. 32 kHz oscillator

Symbol
f(OSC32)
C0
ESR
CL
Parameter
Conditions
Crystal oscillator frequency

External quartz crystal
Shunt capacitance
Typ.
External quartz crystal load

capacitance
See(1)
DocID028281 Rev 1
Max. Unit
32.768
kHz
0.9
pF
External quartz crystal ESR value See(1)
50/67
Min.
60
12.5
k
pF
STCOMET
Table 21. Digital supply characteristics - I/O
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
I(DVDD_3V3_IO)
3.3 V I/O digital

8 GPIO toggling at 0.5 MHz with Cext ~= 50 pF see(1)
supply current
23.0
mA
I(DVDD_3V3_IO)
3.3 V I/O digital

8 GPIO toggling at 1 MHz with Cext ~= 50 pF see(1)
supply current
24.9
mA
I(DVDD_3V3_IO)
3.3 V I/O digital

8 GPIO toggling at 8 MHz with Cext ~= 50 pF see(1)
supply current
49.4
mA
TRNG, QFS. Cortex frequency equals to 96 MHz and Cortex fetching by RAM. The values are calculated by measuring
the difference in the supply current with and without 8 GPIOs enabled and toggling at the given frequency.
Table 22. I/O characteristics

Parameter(1)
Symbol
Conditions
Output current sunk by any I/Os and control pin
I (I/O)
Output current source by any I/Os and control pin
Min. Typ. Max. Unit
See(1)
(1)
See
mA
Table 23. Digital supply characteristics - power consumption under battery

Symbol
Parameter
Conditions
I(DVDD_VBAT)
Digital supply current under VBAT
Min.
Typ.
Max.
Unit
A
1.3
4.4
PLC analog front-end (AFE) and line driver characteristics
4.4.1
Line driver characteristics

Table 24. Line driver characteristics
Symbol
V(PAx_OUT)
BIAS
Parameter
Conditions
Power amplifier output

Bias voltage
- Rx mode
GBWP
Power amplifier
Gain-bandwidth product
I(PAx_OUT)
MAX
Power amplifier
Maximum output current
V(PAx_OUT)
HD2

2nd harmonic distortion
V(PAx_OUT)
HD3

3rd harmonic distortion
V(PAx_OUT)
THD

Total harmonic distortion
Min.
Typ.
Max.
PVCC/2
149
MHz
1000
VCC = 18 V,
V(PA_OUT) = 13 Vpp,
Rload = 50 ,
f = 100 kHz
V(PA_OUT) DC = PVCC/2
DocID028281 Rev 1
Unit
mA rms
-64
dBc
-67
dBc
-61
dB
51/67
67
STCOMET
Table 24. Line driver characteristics (continued)

Symbol
Parameter
Conditions
V(PAx_OUT)
HD2

2nd harmonic distortion
V(PAx_OUT)
HD3

3rd harmonic distortion
V(PAx_OUT)
THD

Total harmonic distortion
C(PAx_INP),
C(PAx_INN)
Power amplifier Input

capacitance
Power supply rejection ratio
CSF_RATIO
Ratio between PA_OUT and

CSF output current
Typ.
Max.
Unit
VCC = 18 V,
V(PA_OUT) = 13 Vpp,
Rload = 50 ,
f = 500 kHz
V(PA_OUT) DC = PVCC/2
-57
dBc
-58
dBc
-54
dB
PA_IN+ vs. VSS (see(1))
10
pF
10
pF
50 Hz
-100
dB
1 kHz
-88
dB
PA_IN- vs. VSS
PSRR
Min.
(see(1)
106
1. Not tested in production, guaranteed by design.
4.4.2
Line driver test circuit

Figure 9. Line driver test circuit
5
5
9&&

5

&
Q)
3$[ B,11
&
3$[ B287
&
6,*1$/,1
3$[ B,13
Q)

5B/2$'
5

$0
52/67
DocID028281 Rev 1
STCOMET
4.4.3
AFE characteristics
Transmission path characteristics
Table 25. DAC characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I(DAC_OUT)
CURRENT
DAC output current
Rx mode, current measured on both

outputs
mA
I(DAC_OUT)
CURRENT
DAC output current
Tx mode, current measured on both

outputs
mA
V(DAC_OUT)
Tx mode, differential
Rload = 120 1%
Vpp
-76
dBc
-83
dBc
-74
dBc
-74
dBc
-82
dBc
-73
dBc
2nd
V(DAC_OUT)
HD2
DAC output
harmonic distortion
V(DAC_OUT)
HD3
DAC output 3rd

harmonic distortion
V(DAC_OUT)
THD
DAC output total

harmonic distortion
V(DAC_OUT)
HD2
DAC output 2nd

harmonic distortion
V(DAC_OUT)
HD3
DAC output 3rd

harmonic distortion
V(DAC_OUT)
THD
DAC output total

harmonic distortion
R(DAC_OUT) = 120
Fclk = 20 MHz
Fout = 100 kHz
R(DAC_OUT) = 120
Fclk = 20 MHz
Fout = 500 kHz
Table 26. Predriver characteristics

Symbol
V(TX_OUT) BIAS
Parameter
Transmitter output bias
voltage
Predriver load impedance
V(TX_OUT) HD2
Transmitter output 2nd

harmonic distortion - see(1)
V(TX_OUT) HD3
Transmitter output 3rd

harmonic distortion see(1)
V(TX_OUT) THD
Conditions
Min.
Rx mode
Typ.
AVDD_5V_TXDRV/2
Max.
Unit
V
k
-76
dBc
-83
dBc
Transmitter output total

-74
dB
V(TX_OUT) HD2
Transmitter output 2nd

harmonic distortion - see(1)
-74
dBc
V(TX_OUT) HD3
Transmitter output 3rd

-82
dBc
V(TX_OUT) THD
Transmitter output total

-73
dB
V(TX_OUT) = 4.7 V
pk-pk, no load,
Fout = 100 KHz
V(TX_OUT) = 4.7 V
pk-pk, no load,
Fout = 500 KHz
1. DAC + predriver chain distortion.
DocID028281 Rev 1
53/67
67
STCOMET
Reception path characteristics

Table 27. Receiver input referred noise
Symbol
V(RX_INP RX_INN)
Parameter
Conditions
Min.
Typ. Max.
Unit
CENELEC-A (35 kHz to 95 kHz)
16
dBV
CENELEC -B (95 kHz to 125 kHz)
12
dBV
CENELEC -C (125 kHz to 140 kHz)
dBV
Receiver input referred noise CENELEC -D (140 kHz to 148 kHz)
dBV
ARIB STD-T84 (35 kHz to 400 kHz)
22
dBV
FCC-LOW (35 kHz to 125 kHz)
17
dBV
G3-FCC (150 kHz to 490 kHz)
21
dBV
Table 28. PLC PGA characteristics

Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V(RX_INP),
V(RX_INN)
Receiver input maximum voltage
Single-ended mode
10
V p-p
V(RX_INPRX_INN)
Receiver input maximum voltage
Differential mode
20
V p-p
Receiver input bias voltage
AVDDD_5
V_PGA/2
Receiver input impedance
5.2
PLC PGA minimum gain
-12
dB
PLC PGA maximum gain
42
dB
dB
GPGA(PLC)
GPGA(PLC)_Step PLC PGA gain step
Table 29. ADC characteristics

Parameter
ADC input range
Conditions
Differential mode
Resolution
54/67
DocID028281 Rev 1
Min.
Typ.
Max.
Unit
V p-p
12
bit
STCOMET
Zero crossing comparator characteristics

Table 30. Zero crossing characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
10
V p-p
V(ZC_IN)
MAX
Zero crossing
Detection input
Voltage range
V(ZC_IN)
TL
Zero crossing
Detection input
Low threshold
-6
mV
V(ZC_IN)
TH
Zero crossing
Detection input
High threshold
+6
mV
ZC_IN
d.c.
Zero crossing
Input duty cycle
50
5.8
ZC_IN delay Mains zero crossing to detection delay time
4.5
Metrology characteristics
Table 31. General section
Symbol
OSF
Fs
Parameter
Conditions
Min.
Typ.
Oversampling frequency
Sampling frequency after decimation
Max.
Unit
MHz
7.8125
kHz
Table 32. Energy measurement accuracy section

Symbol
AW
Parameter
Conditions
Min.
Primary and secondary channel over dynamic

Active energy wide range 1:5000, PGA = 2 to 16, integrator off
band
range 1:10000, PGA = 2 to 16, integrator off
Typ. Max.
Unit
0.1
0.5
RW
Reactive energy

range 2000, PGA = 2 to 16, integrator off
0.1
RMS
Voltage RMS
Over dynamic range 1:200
0.5
Current RMS
Over dynamic range 1:500
0.5
fBW
Effective bandwidth -3 dB
3.6
PSSR(DC)
Power supply DC
rejection
Voltage signal: 200 mVrms/50 Hz,

METR_AVDD_3V3 = 3.3 V 10%
current signal: 10, mVrms/50 Hz
90
dB
PSSR(AC)
Power supply AC
rejection
Voltage signal: 200 mVrms/50 Hz,

METR_AVDD_3V3 = 3.3 V 10%
current signal: 10, mVrms/50 Hz
120
dB
DocID028281 Rev 1
kHz
55/67
67
STCOMET
Table 33. Analog inputs
Symbol
Parameter
GPGA(METR)
GPGA(METR)_Step
Conditions
Max.
Unit
dB
Metrology PGA
maximum gain
24
dB
Metrology PGA gain

step
dB
Maximum input
signal levels
Voff
Input referred offset
ZIP
METR_VP,
METR_VN
Impedance
ZIN
Typ.
Metrology PGA
minimum gain
METR_VP-METR_VN channel
VMAX
Min.
METR_IP,
METR_IN,
METR_AP,
METR_AN
impedance
GERR
Current channels
gain error
IILV
Voltage channel
input current
IILI
Current channel
input current
-0.3
+0.3
METR_IP-METR_IN /
METR_AP-METR_AN channels
Gain 2 x
-0.3
Gain 4 x
-0.15
Gain 8 x
-0.075
Gain 16 x
-0.0375
Over the total operating voltage

range
Over the total operating voltage
range
Gain 2x
Gain 4x
Gain 8x
Gain 16x
+0.3
+0.15
+0.075
+0.0375
250
90
170
300
510
-10
+10
VCC = 3.3 V channel disabled
-1
VCC = 3.3 V channel disabled
-1
Table 34. On-chip reference voltage section

Symbol
M_VREF
M_VREF(TC)
Parameter
Conditions
Reference voltage
Typ.
Max.
1.17
After calibration default
condition(1)
Temperature coefficient
56/67
Min.
DocID028281 Rev 1
30
Unit
V
50
ppm/C
STCOMET
4.5.1
Typical application description

Figure 10. Metrology reference application schematics
1(875$/
5
5
5
&
Q)

&
Q)
5

&
Q)
5
/,1(B/2$'

0(75B,3
0(75B,1
0(75B93
0(75B91 0(75B$3
0(75B$1
&
Q)

5
5B6+817
P

/,1(

/,1(
5

5

&
Q)
&855(1775$16)250(5
5
$0
Table 35. Metrology reference application parameters

Symbol
Parameter
Value (typ.)
Unit
43000
pulse/kWh
CP
Pulse constant
INOM
Nominal load current
A rms
Imin
Minimum load current
0.1
A rms
Imax
Maximum load current
100
A rms
KV = R4/(R1 + R2 + R3 + R4)
Line voltage transducting ratio for nominal line voltage =

230 V
1650:1 4%
V/V
Load current transducting ratio - shunt
0.3 5%
mA/V
Load current transducting ratio - current transformer
2.4 5%
mA/V
50
ppm/C
KS
TC
Temperature coefficient for all transducers
Measurement error
The power measurement error is defined by the following equation:
e% = (measured power - true power) / true power
All measurements come from the comparison with a higher class (0.02% error) power meter
reference.
DocID028281 Rev 1
57/67
67
4.5.2
STCOMET
Typical application performance curves

Figure 11. Active energy error vs. current at AI = 2x, T = 25 C,
load current phase phi = (0, 60, -60)
Figure 12. Active energy error vs. current at AI = 16x, T = 25 C,

load current phase phi = (0, 60, -60)
58/67
DocID028281 Rev 1
STCOMET
Figure 13. Active energy error vs. frequency at AI =2x, T = 25 C, power factor PF = 1
Figure 14. Active energy error vs. frequency at AI = 2x, T = 25 C, power factor PF = 0.8
DocID028281 Rev 1
59/67
67
STCOMET
Figure 15. Active energy error vs. frequency at AI = 2x, T = 25 C, power factor PF = 0.5
Figure 16. Reactive energy error vs. current at AI = 2x, T = 25 C,

load current phase phi = (90, -90, 60, -60)
60/67
DocID028281 Rev 1
STCOMET
Figure 17. Reactive energy error vs. current at AI = 16x ,T = 25 C,
load current phase phi = (90, -90, 60, -60)
DocID028281 Rev 1
61/67
67
4.6
STCOMET
Embedded Flash characteristics

Table 36. Flash memory characteristics
Parameter(1)
Symbol
Conditions
Min. Typ.(2) Max.(3) Max.(4) Unit
Not including SW overhead
18
50
500
Module program (512 kB)
1.3
1.65
33
tBKPRG Bank program (1056 KB)
2.6
6.6
66
tDWPRG Double word program

tMPRG
tER16K
Sector pre-program and erase

(16 KB)
0.2
0.5
5.0
tER32K

(32 KB)
0.3
0.6
5.0
tER64K

(64 KB)
0.4
0.9
5.0
tER128K

(128 KB)
0.6
1.3
5.0
tMKER
Module erase (512 KB)
4.8
7.6
55
tBKER
Bank erase (1056 KB)
12.6
91
tPABT
Program abort latency
10
10
tEABT
Erase abort latency
30
30
tESUS
Erase suspend latency
30
30
tESRT
Erase suspend request rate
ms
Typ.
Max.
20

2. Assuming nominal supply values and operation at 25 C, 0 cycles.
3. Assuming nominal supply values and operation at 25 C, 100 cycles.
4. Assuming nominal supply values and operation at 125 C, 100 Kcycles.
Symbol
NEND
Table 37. Flash memory endurance and data retention

Parameter
Endurance
Min.(1)
Conditions
TA = -40 to +85 C
(2)
tRET
Data retention
1 kcycle at TA = +85 C
(2)
1 kcycles
at TA = +55 C

2. Cycling performed over the whole temperature range.
62/67
DocID028281 Rev 1
(see(2))
Unit
1K
Cycles
15
Years
30
Years
STCOMET
Table 38. Flash memory current consumption
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
I(Flash_VDD3V3)
Current consumption from 3.3 V

supply source
During the erase of all the

sectors - see(1)
1.6
mA
I(Flash_VDD1V2)
Current consumption from 1.2 V

supply source
During the erase of all the

sectors(1)
12.3
mA
1. During characterization, not tested in production. The values exclude the consumption from other pins.
DocID028281 Rev 1
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67
Package information
STCOMET
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
5.1
TQFP176 package information

Figure 18. TQFP176 (20 x 20 x 1 mm) package outline
74)3
64/67
DocID028281 Rev 1
STCOMET
Package information
Table 39. TQFP176 (20 x 20 x 1 mm) package mechanical data
Dimensions (millimeters)
Symbol
Min.
Typ.
1.20
A1
0.05
A2
0.95
1.00
1.05
0.13
0.18
0.23
0.09
21.80
22.00
22.20
D1
19.80
20.00
20.20
0.127
0.20
D2
8.70
D3
17.20
21.80
22.00
22.20
E1
19.80
20.00
20.20
E2
8.70
E3
17.20
0.40
0.45
0.60
L1
0.75
1.00
3.5
ccc
5.2
Max.
7
0.08
Thermal data
Table 40. Thermal data
Symbol
RthJA
Parameter
Conditions
Mounted on a 2s2p PCB, with a dissipating

Maximum thermal resistance junction
surface, connected through vias, on the bottom
ambient steady state
side of the PCB.
DocID028281 Rev 1
Typ.
value
Unit
34
C/W
65/67
67
Ordering information
STCOMET
Ordering information
Table 41. Ordering information
Order code
Package
Packing
eFlash size
STCOMET10
TQFP176 (20 x 20 x 1 mm)
Tray
1 MB
STCOMET05
TQFP176 (20 x 20 x 1 mm)
Tray
640 kB
Revision history
Table 42. Document revision history
66/67
Date
Revision
01-Sep-2015
Changes
Initial release.
DocID028281 Rev 1
STCOMET
IMPORTANT NOTICE PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (ST) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to STs terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
2015 STMicroelectronics All rights reserved
DocID028281 Rev 1
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STCOMET

Smart meter and powerline communication system-on-chip

Cortex-M4 Embedded Trace Macrocell

TQFP176 (20 x 20 x 1 mm)

Power line communication (PLC) sub-system . . . . . . . . . . . . . . . . . . . . . 10

Real-time engine (RTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Digital front-end (DFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Analog front-end (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Metrology sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Application core sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ARM Cortex-M4F core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Floating point unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13

DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Debug and trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

General purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 18

Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Timers and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 19

Cryptographic engine (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

True random number generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . 21

Pseudo random number generator (PRNG) . . . . . . . . . . . . . . . . . . . . . 21

Interprocessor communication (IPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

One-time programmable (OTP) section . . . . . . . . . . . . . . . . . . . . . . . . . 22

Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 23

Reset, control, clock generation (RCC) and system controller

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 29

Temperature sensors and overtemperature protection . . . . . . . . . . . . . . 30

In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

GPIOs multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PLC analog front-end (AFE) and line driver characteristics . . . . . . . . . . . 51

Line driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Typical application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Typical application performance curves . . . . . . . . . . . . . . . . . . . . . . . . . 58

Embedded Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

TQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Cortex-M4F core configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

STCOMET basic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PLC front-end including digital front-end and analog front-end

PLC line driver

Metrology sub-system including AFE and dedicated processing unit

Wide range of peripherals logically divided into 4 blocks:

The STCOMET detailed architecture is shown in Figure 2.

Power line communication (PLC) sub-system

Real-time engine (RTE)

Digital front-end (DFE)

Automatic gain control (AGC)

Current control (CC)

Analog front-end (AFE)

Zero crossing comparator

Programmable energy and power calculation unit, that can be bypassed

SAG and SWELL detection on voltage channel with programmable thresholds