B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

Transistor-Characteristics
AIM: To draw the input and output characteristics of given N-P-N transistor in the Common Emitter
configuration and hence to determine the input resistance, output resistance and current gain

and

APPARATUS: N-P-N transistor, Variable DC power supplies, Digital voltmeter, DC Microammeter, DC

Milliammeter, 100 KW Resistor and 100W Resistor.
PRINCIPLE: Transistor is a three terminal, two junction semiconductor device. The three terminals are
Emitter, Base and Collector. In an N-P-N transistor, a P-type semiconductor is sandwiched between two Ntype materials. Here Emitter is heavily doped, the Base is lightly doped and the Collector is intermediately
doped. Common Emitter configuration is most effective because of its high current gain, high voltage and
power gain. In Common Emitter configuration, Emitter terminal is made common to both input and output
circuits. Input junction (Base-Emitter) is forward biased and output junction (Collector-Emitter) is reverse
biased so that the input junction is having low resistance (since it is forward biased) and output junction high
resistance (since it is reverse biased).
Input characteristics of a transistor is a curve showing the variation of input (Base) current IB as a function of
input (Base-Emitter) voltage VBE, when the output (Collector-Emitter) voltage VCE is kept constant.
Output characteristics of a transistor is a curve showing variations of output current IC as a function of output
voltage VCE, when the input current IB is kept constant.

Current gain

IC
=
IB

PROCEDURE: The circuit connections are made as shown in figure.

(a) Input characteristics: Power supply VCC is switched on and VCE(say 2, 4 volts) is adjusted to a desired value
by varying VCC. Base-Emitter voltage (VBE) is varied in steps of 0.1volt and corresponding base current (IB) is
noted down. The readings are plotted with VBE along X-axis and IB along Y-axis. Slope of the graph will input
resistance.
M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

2

(b) Output characteristics: By varying C, IB is adjusted to a desired value (say 25, 50 75 A . Now VCE is
varied in steps of 1.0volts and corresponding value of IC is noted down. The readings are plotted with VCE
along X-axis and IC along Y-axis. Another set of observation is taken for different IB value and the graph is
plotted. Slope of the graph will give output resistance.
(c) Current gain: Keeping VCE constant, collector current IC is noted for different values of base current IB. The
experiment is repeated for various constant values of VCE and readings are tabulated. A graph is drawn with IB
along X-axis and IC along Y-axis. Slope of the graph will give current gain .
OBERVATIONS:
VCE =2.0(volt) VCE =
VBE(vo
lt)

IB

4.0(volt)
VBE(vo IB
A lt)

0.1
0.1
0.2
0.2
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
0.7
0.7
0.8
0.8
0.9
0.9
1.0
1.0
(10) Input characteristics

(b)Output characteristics

M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

3

VCE =2.0(volt)
IB
IC
A

VCE =4.0(volt)
IB
IC

mA

mA

VCE =6.0(volt)
IB
IC
A

mA

10
10
10
20
20
20
30
30
30
40
40
40
50
50
50
60
60
60
70
70
70
80
80
80
90
90
90
100
100
100
(c) Current gain or Transfer characteristics
CALCULATIONS:
V BE
IB =

(1) Slope of the VBE - IB graph (Input resistance Ri) =

(2) Slope of the VCE - IC graph (Output resistance Ro) =

(3) Slope of the IB - IC graph (Current gain

)=

V CE
IC =

IC
IB =

RESULTS:
(1) The input and output characteristics are drawn.
(2) Input resistance Ri=
(3) Output resistance Ro =
(4) Current gain

INVERSE SQUARE LAW: Gamma Rays

PURPOSE:
The Inverse Square Law is an important concept to be understood. It states that intensity of gamma radiation
falls
M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

4

inversely as a square of the distance.

EQUIPMENT:
G.M. Counter,G.M Detector with connecting cable, gamma source G.M. stand / holder and source
arrangement
PROCEDURE:
1) Make detector-source arrangement as shown in the (Fig.) and power up the unit.
2) Withoutsource measure background counts Nb(about 5 times)and take an average background counts
for a pre-set-time of 50 second
3) Place a gamma source in the source holder and adjust the distance (d) from the detector to 2 cm
4) Set the HV to Operating Voltage (say 350 V), program 'preset time' to 50 sec and press 'START' button
to start the counting.
5) Increases the Distance (d) in steps of 0.5cm (5mm) and for each time observes the counts Na and
tabulates the data.It is repeated till you reach a distance about 5cms.
6) Subtract the background counts Nbfrom the recorded counts Nawhich results in corrected counts (N)
N
R=
in 50sec. From this obtain Net Count Rate (R) per sec by relation
100
7) Find out log d and log R values and plot a graph of log R v/s log d as shown. Draw a straight line and
find the slope if it is 2 then the inverse square law is verified.
Diagram

Nature of graph
Log R
A

C
Log d

Tabular column:
(a) Measurement of back ground counts (Nb) without source
Nb=

N 1 + N 2 + N 3 + N 4+ N 5
5
(b) Measurement of log R and log d
T.N

Distance Observed
d in cm counts Na

Collected counts
N=Na-Nb

Count rate
N
R=
100

Log d

Log R

sec

M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

5

Zener Diode
Aim: To draw the characteristics of a Zener Diode and hence to determine the streak own voltage and the
forward resistance of the given Zener Diode.
Apparatus: Zener Diode, rheostat, voltmeter (0 to 10v), milliammeter (0-10mA), battery etc.
Circuit Diagram:

Procedure:
1. Electrical connections are made as shown in the fig.
2. Input (I/P) voltage (0-4v), v is kept by turning the knob of the battery eliminator.
3. The input voltage is gradually increased in a regular step of 0.1v and each time diode current in
milliammeter is measured.
4. The graph of I VS V is plotted to obtain forward biased Zener diode characteristics.
5. The zener diode is connected in the reverse bias. The reverse biased voltage is gradually increased in
regular steps of 0.5v and at each step diode current is measured.
6. The graph of I VS V is plotted to obtain reverse bias diode characteristics.
Tabular Column:
Sl no

Current in
mA

Voltage
in volts

M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

6

Graph:

REGULATED POWER SUPPLY

AIM: Construction of zener diode voltage regulator and study of variation of output voltage with load
resistance and input voltage.
APPARATUS: step down transformer, bridge rectifier, -section filter (L-R-C filter) potentiometer, load
resistors, digital multimeter, connecting wires etc.
BRIEF EXPLANATION: zener diode voltage regulator is one of the regulated power supplies. The purpose
of all regulated power supplies is to provide constant D.C output voltage irrespective of variation in input
voltage or load resistance. For proper functioning of the regulator, zener diode should be operated in zener
breakdown voltage.
Input voltage being kept constant any increase or decrease in the load resistance produce proportionate
decrease or increase in the load current. Hence the output voltage remains always constant and is independent
of variation in the load resistance. In addition any increases or decreases the voltage drop across the series
resistance Rs, thereby maintaining constant voltage across the zener diode.
Load resistance being kept constant, any increase or decrease in the input voltage in turn increases or
decreases the voltage across the series resistance Rs thereby maintaining constant voltage across zener diode.
In addition, any increase or decrease in the input voltage produces proportionate increase or decrease in the
zener current thereby maintaining constant current through the load resistance. Hence, output voltage always
remains constant and is independent of variation in the input voltage.
Part-A
Procedure:
VARIATION OF OUTPUT VOLATAGE WITH LOAD RESISTANCE
Circuit connections are made as shown in the figure. A constant D.C input voltage, say 4 volts, is set between
points A and B using potentiometer. The load resistance RL is varied in steps of 500upto10k and the
corresponding voltage is noted in each step using digital multimeter(DMM).
The experiment is repeated for different input voltages and readings are recorded in the tabular column 1
The graph of output voltage v/s load resistance for different input voltages is drawn as shown in figure 1
PART-B
VARIATION OF OUTPUT VOLTAGE WITH INPUT VOLTAGE

M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

7

Keeping the load resistance constant, say 5k the D.C input voltage between points A and B is varied in equal
steps using potentiometer. The output voltage is noted in each step using DMM
The experiment is repeated for different load resistances and readings are recorded in tabular column 2
The graph of output voltage v/s input voltage for different load resistances is drawn as shown in figure 2
Circuit diagram:
Tabular column 1
V in =4v
RL
0.5k
1k
1.5k

vout

V in =6v
RL

vout

V in =8v
RL

vout

Vout

RL=10k
Vin

vout

10k

Tabular column 2
RL=5k
Vin
4v
4.5v
5v

Vout

RL=7k
Vin

10v
Result: a) inut voltage remaining constant, output voltage remains constant above the load resistance-b) Load resistance remaining constant, output voltage remains constant above the input voltage-TRANSISTOR CHARACTERISTICS COMMON-EMITTORCONFIGURATION
Aim: Determination of input resistance, output resistance, and current gains of common-emitter configuration
of transistor.
Diagram:
M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

8

Procedure:
Case 1:The electrical connections are made as shown in the fig.
A: The voltage between collector and emitter is kept constant at 0v. The voltage between base and emitter is
gradually increased in regular steps, each time IB is measured. The graph of
IB->VBEis plotted. The experiment is repeated for different values of VCE.
Case 2:
B: The base current IBis kept constant. The voltage between collector and emitter is gradually in regular steps
at each step, collector current IC is measured. The graph of IC->VCE is plotted. From graph r1, r0, and are
determined using formulae. The experiment is repeated for different values of IB.
Input characteristics:

VCE= const
Vdt
VBE

Base current
IB

VCE=const
Vdt
VBE

Base current
IB

Output characteristics
IB=20a

IB=40a

IB=60a

M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

9

VCE in volt
B/w C and E

IC
Collector
current

Volt b/w C
and E

Collector
current Ic

Volt b/w C
and E

Collector
current IC

.
CHARACTERISTICS OF A TRANSISTOR
Aim: - To draw the input and out put characteristics of the given NPN transistor and hence to determine its
constants , and knee voltage for silicon.

Apparatus: - Transistor SL-100, variable power supply, DC micro ammeter (0 to 200 A), DC milliammeter
(0 to 500 mA), digital voltmeter, patch cards.

Procedure: 1. The circuit is connected as shown in the circuit diagram.

2. All the power supply knobs are turned to the minimum position.
Input Characteristics:
1. The collector emitter voltage VCE is set to 2 volts by varying VCC.
2. The base emitter voltage VBE i.e., the input voltage is increased from 0 to 0.8 V in steps of 0.1 V and the
corresponding values of the base current IB are noted from the microammeter.
Output Characteristics:
1. The input current IB is set to 30 A by varying VBB.
2. VCE is varied from 0 to 7V in steps of 1V by varying V CC and the corresponding readings of collector
current ICare recorded.
3. The above procedure is repeated by setting IB = 60 A.
Graph:
A graph is plotted for input current IB in mA versus input voltage VBE. The portion of the curve that could be
approximated to a straight line is extrapolated downward to X-axis at K and the value of V BE at K known as
knee voltage VK is noted. Similarly a graph of output voltage V CE verses output current IC is plotted for input
current IB for 30 A and 60 A as shown in the diagram. From the graph, the current amplification factor is
M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

10

calculated as = IC / IB. This is calculated for different values of I C and IB and an average value is found
out. The value of is calculated using the formula.

Result: The input and output characteristics for the given NPN transistor have been studied
1.

The knee voltage VK =______________ V

2.

The value of

= ______________

3.

The value of

= ______________

b) Circuit diagram

c)
d)

e)
f)
g) Formula

h) The current amplification factor

i) Where is current gain given by;

I C
I B

I C 2 I C1
I B 2 I B1
=

M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

B Sc Physics Laboratory Manual /Fifth Semester/ Paper -5

11

M N Ravikantha, Assistant Professor of Physics, HPPC Government First Grade College Challakere 577 522.

j)
k) Input Characteristics:
l) Dependence of IB on VBE for constant VCE
m)
o) V
C
E

n) V

B
E

(
v
o
l
t
s
)

2
V
q) I
B

A
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r)

s)

t)

u)

v)

w)

x)

y)

z)

aa)

ab)

ac)

ad)

ae)

af)

ag)

ah)
ai)
aj)
ak) Output Characteristics:
al) Dependence of IC on VCE for constant IB
am)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

ao) I

ap) I

3
0

6
0

an) V
C
E

(
v
o
l
t
s
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ar) I

as) I

m
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A

at)

au)

av)

aw)

ax)

ay)

az)

ba)

bb)

bc)

bd)

be)

bf)

bg)

bh)

bi)

bj)

bk)

bm)

bn)

bo)

bp)

bq)

br)

bs)

bt)

bl)

bu)
bv)
bw)

Experiment No:____________
Date:_______________
bx)
by) GM COUNTER DETERMINATION OF HALF-LIFE

bz)
ca) Aim: To determine the half-life of the given radioactive source using GM Counter.
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

cb)
cc) Apparatus: GM Counting system, GM tube (End window type), radioactive source
(Cs137/ K-40), GM tube holder and source stand.
cd)
ce) Principle: The activity (number of disintegrations per second) of a radioactive
sampledecreases with time. Keeping GM tube at its operating voltage, the number of
counts (N) as a function of time is recorded by placing the source at a fixed distancefrom
the GM tube window. The graph of log (N-N o) againsttime is plotted and its slope is
determined which gives the value of decay constant. By knowing the decay constant,
half-life of the sample can be determined.
cf)
cg) Formula:
ch) The Half-life of the given radioactive sample
ci)

T 1=
2

0 . 693

cj) Where is the decay constant of the given radioactive sample

ck)
cl) Figure:

cm)

cn)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

co)

cp)
cq) Procedure:
cr)

GM tube is mounted on the stand and its electrodes are connected to H. T. supply of
the GM Counting system (scalar) taking care of its polarities. HT supply is turned ON.
Gradually supply voltage is increased to 450 V and the system is left for stabilization
about 10 minutes.

cs)

After the system is stabilized, the counting system is reset to read 0. Without the
source placed, counter is turned on and the background counts (B) are recorded for 5
minutes.

ct)

Now the radioactive source (tubular form) is placed coaxial with the GM tube at a
convenient distance (say 2 cm) and the counter is reset to read 0. Counter is turned on and
the counts (NS) are recorded as a function of time (say intervals of 5 minutes).

cu)

A graph of log (N) against time is plotted and its slope is determinedwhich gives the
value of decay constant. By knowing the decay constant, half-life of the sample can be
determined.

cv)
cw)

Tabular Column:

cx) Operating voltage of the GM tube = ______ V

cy) Background counts for 5
minutes =
db)

dc) B2 =_______
de) Background counts per
minute=

dh)
di)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

B1 B 2
2

cz) B1 =_______

df) NB=NB/5=

da) NB=
=____________
dg)

dj) Ti
m
e
dk) T
dl) (i
n
m
in
)

dm)
Obser
ve
d
C
o
u
nt
s
N
S

dn) C
o
u
nt
s
pe
r
m
in
do) NS
=
N
S /
T

dp) C
or
re
ct
ed
C
o
u
nt
s
pe
r
m
in

dr) lo
g
N

dq) N
=
NS

N
B

ds) 5

dt)

dx) 10

dy)

dz)

ea)

eb)

ec) 15

ed)

ee)

ef)

eg)

eh) 20

ei)

ej)

ek)

el)

em)
25

en)

eo)

ep)

eq)

er) 30

es)

et)

eu)

ev)

ew)35

ex)

ey)

ez)

fa)

fb) 40

fc)

fd)

fe)

ff)

fg) 45

fh)

fi)

fj)

fk)

fl) 50

fm)

fn)

fo)

fp)

fq) 55

fr)

fs)

ft)

fu)

fv) 60

fw)

fx)

fy)

fz)

ga)
gb)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

du)

dv)

dw)

gc)
gd)
ge) Result:
gf)
1. The decay constant of the given radioactive sample () =______
T1
2. The Half-life of the given radioactive sample ( 2 ) = _________years
gg) Experiment No:____________
Date:_______________
gh)
gi) Experiment No:____________
Date:_______________
gj)
gk) THERMO EMF
gl)
gm)

Aim: To measure the emf of thermocouple using a potentiometer.

gn)
go) Apparatus: Leclanche Cell, Thermocouple, Ballistic Galvanometer, Potentiometer,
Resistance Box, Thermometers, Beakers, Sliding contact etc
gp)
gq) Formula :

e
gr)

Elr
100(R r )

The emf of thermocouple is given by

gs) Where E - emf of the cell, l - balancing length, r resistance of the potentiometer wire
and R -resistance unplugged from the resistance box
gt)
gu) Procedure:
gv) Connections are made as shown in the circuit. a suitable resistance R is unplugged from
the resistance box RB . One of the given thermocouple is immersed in cold water in a
beaker and the other junction is immersed in hot water in the other beaker. The lead of the
positive junction of the thermocouple is connected to positive end of the potentiometer &
the other lead is connected to sliding contact through a suspended coil galvanometer G.
The position of the sliding contact on the potentiometer wire is adjusted such that the spot
of light obtained on the scale by reflection at the mirror of the galvanometer is not
deflected. The balancing length l (in cm) & the corresponding temp of the hot junction
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

are noted. The experiment is repeated for different temperature of the hot junction as it
cools in steps of 50C. The thermo emf is calculated using relation.
gw) A graph of e versus
junction1.

2 1

is plotted, where

is the temperature of the cold

gx)
gy)
gz)
ha)
hb)
hc)
hd)
he)
hf) Result: The emf of given thermocouple =e= ___________V

hg)

1Inference: as the temp difference increases thermo emf also increases.

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

hh) Observations:
hi)
1. Resistance of the potentiometer wire, r=_____________ohm
2. Resistance unplugged in the resistance box, R=_______ohm
3. Emf of storage cell, E=_____ volt
1
4. Temperature of cold junction, =_______0C
hj)
hk)
T
ri
al
N
o
hu)
1
hz)
2
ie)
3
ij)
4
io)
5
it)
6
iy)
7
jd)
8

hl)
hm) in
0
C

hn)

2 1
ho)

in
C

hv)

hw)

hp)Bala
ncin
g
lengt
hl
hq) (in
cm)
hx)

hr) emf
hs) e
ht) (in
V)

hy)

ia)

ib)

ic)

id)

if)

ig)

ih)

ii)

ik)

il)

im)

in)

ip)

iq)

ir)

is)

iu)

iv)

iw)

ix)

iz)

ja)

jb)

jc)

je)

jf)

jg)

jh)

ji)
jj)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

jk) Experiment No:____________

Date:_______________
jl)
jm)
PHOTO DIODE AND ZENER DIODE
jn)
jo) Aim: To study the I-V Characteristics of a photo diode and Zener diode.
jp)
jq) Apparatus:Photo diode ,Zener diode, DC Power supply, Ammeter, Voltmeter.
jr) Procedure:
js)
jt) Reverse Characteristics of Photo Diode:
ju)
1. Check the circuit assembled (Fig-1) and switch ON the supply to the board.
2. Place the board under a table lamp so that the light falls directly on the photodiode fitted on the
panel.
3. Vary the voltage from 0-10 for different trials and note down the corresponding values of diode
current.
4. Plot a graph of voltage applied versus diode current.
5. Now place a piece of translucent paper (a tracing Sheet) on the photo diode in order to reduce the
light intensity falling on the photo diode.
6. Again take readings of applied voltage and corresponding diode current & plot on the same
graph. The graph will be similar to the one shown in fig-2.
jv)
jw) Reverse Characteristics of Zener Diode:
jx)
jy)
jz)
ka) Result:
kb) Experimentally it is found that characteristics of photodiode is as shown in Fig
kc)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

kd)Circuit diagram:

ke)
kf)
kg)
kh)
ki) Tabular column:
kj)
kk)
kl) km)
Volta
T
ge in V
ri
al
N
o
ko)
kp)

kn)
Curren
t in A

kq)

kr)

ks)

ku)

kv)

kx)

ky)

kz)

la)

lb)

lc)

ld)

le)

lf)

lg)

lh)

li)

lj)

lk)

ll)

lm)
ln)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

kt)
kw)

lo) Experiment No:____________

Date:_______________
lp)
lq) FIELD EFFECT TRANSISTOR
lr)
ls) Aim: To study transfer and output characteristics of a given Field Effect Transistor and
hence to determine its parameters.
lt)
lu) Apparatus: FET (BFW 10), Milliammeter, Voltmeters, regulated power supply, rheostats
and resistance box.
lv)
lw) Formula:
lx) The characteristic parameters of a FET are given by
VDS

ID VGS

rd

1. Drain resistance

in

ID

VGS VDS

gm

2. Trans conductance

in mho (1)

VDS
rd gm

VGS ID

3. Amplification factor
ly) Where
VDS is the drain-source voltage
lz) VGS is the gate-source voltage and
ma)

ID is the drain current.

mb)
mc)

Circuit:

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

md)
me)

mf)
mg) Procedure: Electrical connections are made as shown in the circuit diagram by using
a n-channel FET BFW 10.
mh)
mi) Transfer characteristics: The voltage between the drain and source (VDS) is kept constant
at 1 V. the voltage between the gate and source (VGS) is gradually increased in regular
steps of 0.5V and the drain current ID is measured. The experiment is repeated by fixing
the VDS at 2V. Transfer characteristic curve is obtained by plotting a graph of ID verses VGS
at constant VDS.
mj)
mk) Drain characteristics: The Voltage between gate and source (VGS) is kept constant
at 1V. The voltage between drain and source (VDS) is gradually increased is regular
steps of 0.5V and thedrain current ID is measured. The procedure is repeated for
another value of VGS say at 2V. Drain characteristic curve is obtained by plotting a
graph of ID verses VDS at constant VGS.
ml)
mm) The constants of FETDrain resistance,Transconductance and Amplification factor
are
determined from the characteristic curves.
mn)
mo)

Tabular column:

mp)

Transfer characteristics:

mq)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

RD = 1000

mr)VDS =
1V

ms)

VDS
= 2V

mt)
V

mu)
I

mv)
V

mw)
I

mx)

my)

mz)

na)

nb)

nc)

nd)

ne)

nf)

ng)

nh)

ni)

nj)

nk)

nl)

nm)

nn)

no)

np)

nq)

nr)

ns)

nt)

nu)

nv)

nw)

nx)

ny)

nz)

oa)

ob)

oc)

od)

oe)

of)

og)

oh)

oi)

oj)

ok)

ol)

om)

on)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

oo)

oq)

op)
or)
os) Output characteristics:

RD=1000

ot)
ou) VGS =
1V

qt)

ov) VGS =
2V

ow)
V

ox)
I

oy)
V

oz)
I

pa)
0

pb)

pc)
0

pd)

pe)
0

pf)

pg)
0

ph)

pi)
1

pj)

pk)
1

pl)

pm)
1

pn)

po)
1

pp)

pq)
2

pr)

ps)
2

pt)

pu)
2

pv)

pw)
2

px)

py)
3

pz)

qa)
3

qb)

qc)
3

qd)

qe)
3

qf)

qg)
4

qh)

qi)
4

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

qj)

qk)
4

ql)

qm)
4

qn)

qo)
5

qp)

qq)
5

qr)

qs)
qu)
qv)
qw)

Results: The characteristic parameters of the given FET are .

1. Drain resistance rd = __________________
2. Transconductancegm
= __________________1
3. Amplification factor = __________________
qx) Experiment No:____________
Date:_______________
qy)
qz) RC PHASE SHIFT OSCILLATOR

ra)
rb)

Aim: To Construct a phase shift oscillator using transistor and verify the frequencies for
different values of capacitor.

rc)
rd) Apparatus:Transistor (BC 547), Resistors, Capacitors, regulated Power supply and CRO.
re)
rf) Formula:
rg)

The frequency of oscillation of RC Phase Shift Oscillator is given by

f
rh)
ri)

Where f

2RC 6

frequency in hertz (Hz),

rj)

R resistance in ohm () and

rk)

C capacitance in farad (F)

rl)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

0.065
RC

in Hz

rm)
rn) Circuit:

ro)
rp)
rq) Procedure: Rig up the RC Phase Shift Oscillator circuit on the breadboard as shown in
the circuit diagram. Switch on the power supply and adjust the supply voltage to 15V. Set
the capacitors C1=C2=C3= C to a convenient value (say 0.01 F) and Adjust the time base
of the CRO to get a sharp sinusoidal wave signal generated by the RC Phase Shift
Oscillator. Measure the width of one sinusoidal wave pulse (i.e., number of divisions, a)
on the Time scale axis (x-axis) and note down the time/ division (b). The product of a and
b gives the time period (T) of the generated sinusoidal wave signal. The reciprocal of T
gives its frequency.
rr)
rs)
The experiment is repeated for various values of C1=C2=C3 =C and the
frequency the generated square wave signal is determined is each case and is compared with
the theoretical frequencies which are calculated using the given formula.
rt)
ru)
rv)
rw)
rx) Tabular Column:
ry)
rz) Capacitor
sa) C1=C2=C3 =C

sb)
N

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

se)
Ti

sg)
Pe

sj) Fre
que

sk) Theo
retica
l

sm)
Ca
sn)
Co

so) C
a
p
a
ci
t
a
n
c
e
v
a
l
u
e
(i
n
n
F
)

su)
22

sv) 2
2
0

tb)
10

tc) 1
0
0

ti)
40
tp)
0.
tw)
10

sc)
x
sd)
(a

sf)
(

sh)
T
si)
(in

sw)

sx)

sy)

td)

te)

tf)

tj) 4
0

tk)

tl)

tm)

tq) 2
2

tr)

ts)

tt)

tx) 1
0

ty)

tz)

ua)

uf)

ug)

uh)

um)

un)

uo)

ud)
68

ue) 6
.
8

uk)
56

ul) 5
.

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

ncy
f

1
(in kHz)
T

frequ
ency
sl)
f

0.065
in Hz
RC

sz)

ta)

tg)

th)

tn)

to)

tu)

tv)

ub)

uc)

ui)

uj)

up)

uq)

6
ur)
33

us) 3
.
3

ut)

uu)

uv)

uw)

ux)

uy)
uz)
va)
vb)
vc)
vd)
ve)
vf)
vg)
vh)
vi)
vj)
vk)
vl)
vm)
vn)
vo)
vp) Result:
vq)

The RC Phase Shift Oscillator is constructed and the frequency of the sinusoidal wave
generated is determined for different values of capacitor and found to be in agreement
with the respective theoretical value.
vr) Experiment No:____________
Date:_______________
vs)
vt) PHOTO DIODE IV Characteristics

vu)
vv) Aim: To study the I-V Characteristics of a photo diode.
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

vw)
vx) Apparatus:Photo diode, Zener diode, DC Power supply, Ammeter, Voltmeter.
vy)
vz) Theory:
wa)
PHOTO DIODE : A photo diode is a P-N junction which is reverse biased in normal
operation and whose junction is exposed to the radiant energy source through a window
in its encapsulation.Both germanium and silicon have been used in photodiodes, but
germanium has largely been supplanted by silicon since the former material has a higher
value of dark current. This is the leakage current that flows when the incident radiation
is zero. The dark current associated with a germanium device may be high as 10mA and
this for a silicon device may be as low as 20nA. An increase in illumination results in an
increase in the number of electron hole pairs generated in the semiconductor, and the
minority charge carrier, which are generated close to the junction are swept across it. The
carriers that cross the junction in this way constitute flow of photocurrent through the
diode. When illuminate, the diode current under reverse biased conditions is the sum of
leakage current and photocurrent.
wb)
wc)

Procedure:

wd)
we)

Reverse Characteristics of Photo Diode:

wf)
wg) Check the circuit assembled and switch ON the supply to the board. Place the board
under a table lamp so that the light falls directly on the photodiode fitted on the panel. Vary
the voltage from 0-10 for different trials and note down the corresponding values of diode
current. Plot a graph of voltage applied versus diode current. Repeat the experiment for
different intensities and plot the graph is each case.
wh)
wi)
wj)
wk)
wl)
wm)
wn)
wo)
wp)

Result:

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

wq) Reverse Characteristics of the given photo diodeis studied experimentally and is found to
be in agreement with the theory.
wr)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

ws)Circuit diagram:
wu)

wt)

wv)
ww)
wx)

Tabular column:

wy)
wz)
xa) xb)
Intensity
I1
xe)
xf)
xh)
V
C
ol
u
ta
rr
g
e
e
nt
xg)
xi)
in
in
V

A
xr)
xs)
xt)

xc)
I2

Intensity
xj)
V
ol
ta
g
e
xk)
in
V

xd)
I3

Intensity
xn)
V
ol
ta
g
e
xo)
in
V

xu)

xl)
C
u
rr
e
nt
xm)
in

A
xv)

xw)

xp)
C
u
rr
e
nt
xq)
in

A
xx)

xy)

xz)

ya)

yb)

yc)

yd)

ye)

yf)

yg)

yh)

yi)

yj)

yk)

yl)

ym)

yn)

yo)

yp)

yq)

yr)

ys)

yt)

yu)

yv)

yw)

yx)

yy)

yz)

za)

zb)

zc)

zd)

ze)

zf)

zg)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

zh)

zi)

zj)

zk)

zl)

zm)

zn)

zo)

zp)

zq)

zr)

zs)

zt)

zu)

zv)

zw)

zx)

zy)

zz)

aaa)

aab)

aac)

aad)

aae)

aaf)

aag)

aah)

aai)

aaj)
aak)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

aal)

Experiment No:____________
Date:_______________
aam)
aan)
NAND GATE as A Universal Logic Gate

aao)
aap)
aaq)
aar)

Aim : To verify NAND gate as universal logic gate using IC-7400.

Apparatus: power supply, IC-7400, Bread board, connecting wires etc..

aas) Theory: A logic gate is an electrical circuit within or more inputs but a single output.
It performs logical operations on input digital signals. They are primarily implementing using
diodes or transistors acting as electronic switches.
aat)
An integrated circuit or monolithic integrated circuit (also referred to as IC, a chip or
a microchip) is a set of electronic circuits on small plate (chip) of semiconducting
material , normally silicon .ICs can be made very compact ,having up to several billion
transistors and other electronic components within a size of tens of nanometre as per recent
advancements. In digital electronics, a NAND gate (Negated AND of NOT AND ) is a logic
gate which produces an output that is false only if all its inputs are true i.e. output
complement to that of AND gate. By using a combination of NAND gates, we can
implement any Boolean function this property is called as functional completeness. It can be
used to implement all other logic gates hence it is called a universal logic gate.
aau)
aav)
1.
2.
3.
4.
5.
6.

Procedure:

Mount the IC on bread board

Connect +5 to pin 14 and ground to pin7 in IC
Make the connections as per circuit diagram
Give the logic level input according to truth table shown for each gate
Note down the output logic level.
Put logic 1 for ON state of LED & logic 0 for state of LED on the observations table.
aaw)

aax) Result:
aay) The different logic gates are constructed using IC 7400 and verified with their
corresponding truth tables.
aaz)
aba)
abb)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

abc) Circuit diagram: pin configuration

abd)
abe) Verification of Truth Table for different Logic gates:
abf)
abg) G
ATE

abh)

Circuit Using NAND Gate

abk)
abj)

A
ND
Gate

abi)
abl)
A
abq)
0
abv)
0
aca)
1
acf)
1

TRUTH
TABLE
abm)
abn)
B =A.B
abr)
abs)
0
abw)
abx)
1
acb)
acc)
0
acg)
ach)
1

Y
0
0
0
1

aci)
ack)
acj)

O
R
Gate

acl)
A

acm)
acn)
Y
B =A+B
acq) acr)
acs)
0
0
0
acv) acw)
acx)
0
1
1
ada) adb)
adc)
1
0
1
adf) adg)
adh)
1
1
1

adi)

N
OT
Gate

adm)
adl)
A

adj)

adz)

adr)
adq)
0
adw)
adv)
1

adk)

N
OR

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

ady)
aea)

aeb)
A

adn)
Y=
A
ads)
1
adx)
0

aec)
aed)
Y

B
= A +B

Gate

aeg)
0
ael)
0
aeq)
1
aev)
1

aeh)
0
aem)
1
aer)
0
aew)
1

aei)
1
aen)
0
aes)
0
aex)
0

afb)
A

afc)
B

afg)
0
afl)
1
afq)
0
afv)
1

afh)
0
afm)
0
afr)
1
afw)
1

afd)
Y=
A

B
afi) 0

aey)
aez) X
-OR
Gate

afy)
afz)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

afa)

afn)
1
afs)
1
afx)
0

aga)

Experiment No:____________
Date:_______________
AGB)
agc) OPERATIONAL AMPLIFIER

agd)
age) Aim: to study the performance of an operational amplifier (OP-AMP) in inverting and
noninverting modes and hence to determine its gain for different feedback resistances.
agf)
agg) Apparatus: OP-AMP (IC741), AF oscillator, resistor, resistance box and
multimeter/ digital voltmeter.
agh)
agi)

Formula:
AV

1. The gain of the operational amplifier in inverting mode is

V0 R f

Vi
Ri

AV

Rf
V0
1
Vi
Ri

2. The gain of the operational amplifier in non-inverting mode is

agj)
Where Viand Vo Input and output voltages respectively (in V)
agk)

Rf Feedback resistance (in )

agl)

Ri series input resistance (in )

agm)
agn)

Circuit:
agp)

ago)

agq)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

agr)
ags)

Procedure:
Inverting mode:

agt) The op-amp circuit in the inverting mode is rigged up on the breadboard. The
input signal from the AF oscillator is set at a convenient value (say 0.1 V @ 1 kHz) with a
series resistance Ri =1 k. The value of feedback resistance Rfis varied in steps of 0.5 k
from 1 k and the out put voltage is measured in each case. The voltage gain is calculated
both experimentally and theoretically and the values are compared.
agu)
agv)

Non Inverting mode:

agw) The op-amp circuit in the noninverting mode is rigged up on the breadboard.
The input signal from the AF oscillator is set at a convenient value (say 0.1 V @ 1 kHz) with
a series resistance Ri =1 k. The value of feedback resistance Rfis varied in steps of 0.5 k
from 1 k and the out put voltage is measured in each case. The voltage gain is calculated
both experimentally and theoretically and the values are compared.
agx)
agy)

ahb)

Observations:
agz)

Input voltage = Vi = ____0.1____V

aha)

Series input resistance = Ri =__1000_

Inverting mode:

ahc)
ahi)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

Voltage Gain

ahd)
Feedb
ac
k
res
ist
an
ce

ahf)
Outpu
t

ahl)
Experi
me
nt
al
ahm)

ahn)
Theor
eti
cal

ahe)
Rf (in
k
)

ahh)
V0 (in
V)

AV

AV

ahp)
1.0

ahq)

ahr)

aht)
1.5

ahu)

ahv)

ahx)
2.0

ahy)

ahz)

aia)

aib)
2.5

aic)

aid)

aie)

aig)

aih)

aii)

aik)

ail)

aim)

aio)

aip)

aiq)

ais)

ait)

aiu)

aiw)

aix)

aiy)

aif) 3.0
aij) 3.5
ain)
4.0
air) 4.5
aiv)
5.0

ahg)
Volta
ge

V0
Vi

aho)

Rf

Ri

ahs)
ahw)

aiz)
aja)

Non Inverting mode:

ajg)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

Voltage Gain

ajb)
Feedb
ac
k
res
ist
an
ce

ajd)
Outpu
t
aje)
Volta
ge

ajl) Th
eor
eti
cal
ajm)

V
AV 0
Vi

AV 1

ajq)

ajc)
Rf (in
k
)

ajf)V0
(in
V)

ajn)
1.0

ajo)

ajp)

ajs)

ajt)

ajv)
2.0

ajw)

ajx)

ajy)

ajz)
2.5

aka)

akb)

akc)

akd)
3.0

ake)

akf)

akg)

akh)
3.5

aki)

akj)

akk)

akl)
4.0

akm)

akn)

ako)

akp)
4.5

akq)

akr)

aks)

akt)
5.0

aku)

akv)

akw)

ajr) 1.5

akx)
aky)
akz)
ala)
alb)

ajj) Ex
pe
ri
me
nt
al
ajk)

Result:

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

Rf

Ri

aju)

alc)

The voltage gain of the given operational amplifier (IC741) is determined in

inverting and noninverting determined modes for different feedback resistances and is
found to be in agreement with the respective theoretical value.
ald)
ale)

Experiment No:____________
Date:_______________
alf)
alg)
RS FLIP-FLOP USING IC-7400

alh)
ali) Aim: To Construct RS flip-flop using IC-7400(NAND)and hence verify its truth table.
alj)
alk) Apparatus: GM Counting system, GM tube (End window type), radioactive source
(Cs137/ K-40), GM tube holder and source stand.
all)
alm) Apparatus: IC-7400(NAND), Bread board, power supply +5V DC, Connecting
wires, Switches.
aln)
alo) Theory: A flip-flop is a binary storage device i.e., it can store binary bit either 0 or 1.
It has two stable states HIGH and LOW, i.e. 1 and 0 .it has the property to remain in one
state indefinitely until it is directed by an input signal to switch over to other state. It is
also called bistable multivibrator. it is basic memory element.
alp) A flip-flop circuit has two outputs one for normal value and one for the compliment
value of the bit stored in it. Binary information can enter a flip-flop on variety of ways, a
fact which give raise to different types of flip-flop. The various types of flip-flop are RS
flip-flop, JK flip-flop, D flip-flop, T flip-flop, master slave flip-flop.
alq)
alr) The output of a flip-flop in low voltage or high voltage. So that it has two states 0 or
1. The input S is known as she set (or) present input and the input R as the reset or clear
input. The flip-flop is called RS flip-flop. Since the information is locked in place, this
flip-flop is also termed as latch. It is very useful to add clock to RS flip-flop to control
precisely the time at which the flip-flop changes the state of its output. The clock, a
square wave using AND gate as shown in fig(3) . When clock is low the state of flip-flop
is not changes because zero inputs are applied to the flip-flop via AND gate. Flip-flop can
change its output only when the clock is high.
als)
alt) Operation of RS flip-flop:
alu)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

Input R=S=0 i.e. in the absence of any trigger input, the output state is undetermined i.e. Q may
be either 0 or 1.
If R=0, S=1 gate-1 is enabled and gate -2 is disabled. Therefore, Q=1 and Q=0. The Flip-flop is
now SET.
If R=1, S=0 gate-1 is disabled and gate -2 is enabled. Therefore=0 and Q=1. The Flip=flop is
now RESET.
If R=S=1 the Flip-flop will not change its state and will remain in LAST STATE. Hence, it is
called no change (NC) condition.

alv)
alw) Procedure:
alx) Set up the circuit as shown in the figure. Connect pin 14 to +5 V and pin 7 to ground.
Pin 13 and 1 are interconnected, pin 4 is connected to 8 and pin 10 connected to 6. The
pin 8 gives the output Q and pin gives the Q. Pin 13 and 1 are interconnected and pin 13
or 1 is connected to clock. Observe that in this circuit the input will effective only when
clock pulse is present. Give logic inputs according to the truth table. For different values
of S and R the output is obtained and verify the truth table.
aly)
alz)
ama) Logic symbol for RS Flip-flop:

amb) Pin configuration:

amd)

amc)

ame) Circuit diagram:

amf)
amg)
amh) Truth table:
ami)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

aml)
Lo amm)
Log
amj)
gical inputs
ical outputs
Clock
ams)
input amp)
amq) amr)
Q
amk)
R
S
Q
amu)
1
ana)
1
ang)
1
anm)
1

amv)
0
anb)
0
anh)
1
ann)
1

amw)
0
anc)
1
ani)
0
ano)
1

amx)
and)
1
anj)
0
anp)
1

amn)

Comments
amt)

amy)
amz)
Last state
ane)
anf)
SET
0
ank)
anl)
RESET
1
anq)
anr)
Forbidden state
1

ans)
ant)
anu)
anv)
anw)
anx)
any)

Result:

RS lip-flop is constructed and hence its truth table is verified.

anz)
aoa)

Experiment No:_____
aob)

Date:__________

ASTABLE MULTIVIBRATOR USING IC-555

aoc) Aim: To construct Astablemultivibrator using IC-555 and to determine its duty cycle.
aod) Apparatus: IC- 555, CRO, Regulated Power supply, resistors, capacitors Bread board
etc
aoe) Theory: the 55 timer is an IC that can be used as a Astable or
monostablemultivibrator and for other application normally threshold voltage V =2/3 V
and triggering voltage V =1/3 V those events can
aof) th
CC
er
cc be altered with external connection to the control
voltage terminal (5) . When the V goes above the threshold level the latch is RESET and
aog) er
aoh) output foes low. When the RESET is low. The latch is RESET causing the output goes
low. This turn in it providing a low impedance path from the discharge terminal to
ground.
aoi) An Astable multivibrator often called a free-running multivibrator is a rectangular
wave generating circuit unlike the monostablemultivibrator . this circuit dies not requires
any external trigger to change the state of the output hence the name free running before
going to make the circuit, make sure your IC-555 is working for that go through the
article. How to test 555-IC for working an Astable multivibrator can be produced by
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

adding resistors and a capacitor to the basic timer IC, as illustrated in fig. the timing
during which the output is either high or low is determined by the externally connected
two resistors and a capacitor. The details of the Astable multivibrator circuit are given
below.
aoj)

Circuit diagram:

aok)

aol)
aom)

aon)

Output wave form:

aoo)
aop) Operation:
aoq) For explaining the operation of the timer 555 as an asatblemultivibrator , necessary
internal circuitry with external connections are shown in Fig. qhen
aor)

Q is low or output voltage (V )is high the discharging transistor is cut off
aos)

resistance R and Rbecause

outand the capacitor C begins charging toward V

aot) cc
charging timeconstant is (R + R ) C . eventually the threshold
aou)
aov)

B of the is the

A B

voltage exceeds +2/3 V .

aow)

aox)

cc

The time during which the capacitor C charges from 1/3V to 2/3 V is

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

aoy)
ccequal to the time the output is high and is given as t or T =0.693/(R + R )
apa)
apb)

aoz)
H Hig
A
C,
This is proved below. Voltage across the capacitor at any instant during charging

period is given
apc)

cc
B

The duty cycle the ratio of the time t during which the output is high to the
apd)

ape)

total time period T is given.

apf)

% duty cycle

apg)
aph) From the above equation it is obvious that square wave (50% duty cycle) output
cannot be obtained unless R is made zero. However there is a
api)
apj)

danger in shorting resistance R to zero with R =0 terminal is directly

apk) A
discharging of capacitor through R and the

Aconnected to V

during the

apl) CC
B
apm) time . However a symmetrical square wave can be obtained.The capacitor charges
through R and diode D approximately +2/3 V and discharge
A cc
apn)

through resistors R and terminal until the capacitor voltage drops to 1/3V

B cc
apo) .
app) Then the cycle is repeated to obtain a square wave output must be combination of a
fixed resistor.
apq) Procedure:
apr) The circuit connections are made shown in the figure .the output wave form is
obtained on the screen of CRO as shown in Fig. the period or the wave and time for
which the output is high ( T and t )are measured. The frequency of
aps)
H the Astable multivibrator and
the duty cycle are calculated. They are verified with the theoretical formulae. The experiment is
repeated for different values of C are tabulated.

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

apt) Observations:
apv)apy) aqb)
Fr
aqc)
t
equency
aqd)
apz)
inHz
apw)
H
T in
aqa)
in
apx)
in
aqe)
Hz
ses
sec

aqf)
Duty
cycle
aqg)
D= t /T
aqh)
t

aqk)

aql)

aqm) aqn)

aqo)

H
aqp)

aqq)

aqr)

aqs)

aqt)

aqu)

aqv)

aqw)

aqx)

aqy)

aqz)

ara)

arb)

arc)

ard)

are)

arf)

arg)

arh)

ari)

arj)

ark)

arl)

arm)

arn)

aro)

arp)

arq)

arr)

ars)

art)

aru)

arv)

arw)

arx)

ary)

arz)

apu)
Cap
acitance c in

aqi)
Ca
lculated
duty
aqj)

asa)
asb) The fig shows the circuit diagram of the free running or Astablemultivibrator the
trigger input and the threshold input are connected together. The capacitor charges
through
discharge through , therefore frequency and duty cycle can be set by
choosing proper and value of
. The fallowing can be used for Astable operation.
1. Frequency
2. Time for which output is high
3. Time for which output is low
4. Period of output wave form
5. Duty cycle
asc)
asd)
Result:
ase)
Frequency and duty cycle of Astablemultivibrator using IC-555 is verified
experimentally.
asf)
asg)
ash)
asi)Experiment No:____
Date:__________
asj)
ask) CAPACITY OF CONDENSER BY ABSOLUTE METHOD
asl)Aim: To determine the capacity of condenser using balastic galvanometer.
asm) Apparatus: BG condenser, tapping key, charge- discharge key, Resistance boxes
etc
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

asn)

Circuit diagram:
aso)

asp) Procedure:
1) With s=0 & R +R =1000 ( or a suitable high value ) close the plug
asq)
1
2 key K & note the steady deflection . Now
increase the value of S
asr) 2
ass) so that the deflection reduces to /2. This particular value of s
ast)

asu) gives galvanometer resistance G.

2) Determine the times for N free torsional oscillation of the coil. Calculate the period T=t/N.
3) unplug the suitable value in R adjust R so that R +R =1000(or a
1 2
1
2 suitable high
value ) keep S=0 close key k note down steady
2 deflection
keeping k open,
charge the condenser C & discharge
asv) 2
asw) it through .B.G using the charge & discharge key. Note the first throw &
second throw
the formula.

on the same side of zero. Calculate the capacity of condenser using

asx)
asy)

Repeat the experiment for different values of R and R keeping

asz)1

ata)

R +R =1000 (or a suitable high value).

atb)

2
1.

atd)

1
ate)

atc)
Observation:
S=0 , r=0.1 , R +R =1000( a high value) the steady deflection

2
=________

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

atf)

The value of S to reduce the deflection to

atg)

The galvanometer resistance G=___________

2. Time for N torsional oscillation =t seconds

ath)
ati)
Trial
atj)
No

atk)
R
atl)
1
atm)
In

/2 is G =____________

Periods T=t/N=_______seconds
atn)
R
ato)
2
atp)
in

atq)
Ste
ady
deflection
atr)

ats)
rst
att)
row

Fi

atv)
econd
th throw
atw)
atu)

S atx)

Capacity
aty)

aua)

aub)

auc)

aud)

aue)

auf)

atz)
aug)

auh)

aui)

auj)

auk)

aul)

aum)

aun)

auo)

aup)

auq)

aur)

aus)

aut)

auu)

auv)

auw)

aux)

auy)

auz)

ava)

avb)

avc)

avd)

ave)

avf)

avg)

avh)

avi)

avj)

avk)

avl)

avm)

avn)

avo)

avp)

avq)

Mean
C=____________

avr)
avs)
avt)
avu)
avv)
avw)
avx)
avy)
Result :
avz)The capacitance of the given capacitor by absolute method is =______
No:___ _____
Date:__________
awa)

Experiment

LOGIC GATES

awb) Aim: To construct basic logic gates and to verify their truth tables.
awc) Apparatus: power supply , diodes, transistors, resistors, LED or voltmeter.
awd) Basic information: A basic logic gate is a circuit where the output is logically related
to the input i.e it is a circuit which make logic decision. The output signal appears only
for certain combinations of input signal. In these circuits the numbers 1 and 0 are used to
represent two voltage levels, a high voltage say +5V and low voltage say 0V, they are also
referred to as TRUE or FALSE.
awe) Procedure:
1. OR Gate: it is a gate to provide an output of 1 when either of inputs A or B or both are The
circuit to realize an OR gate is shown in the fig. The electrical connections are made as
shown the fig to feed high input , the input terminal is connected to +5V of the power supply.
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

To feed the low input, the input terminal is connected to ground terminal of the supply. The
output is considered as high if the measured output voltage is close to the supply voltage
(+5V) or if LED glows. It is low if the measured output voltage is 0V or if LED does not
glow. When both inputs A and B are 0 that means connected to ground the LED does not
glow which is equal to 0. When the input A is 0 and B is +5V the diode D is forward
awf)2 biased
and hence conducts. The LED glows, that means the output logic 1, when the input A is
at+5V and B is 0V the output logic is 1. When both inputs A and B are at +5V, both diodes
D1and D2 conduct and hence the LED glows therefore the logic output logic is 1.
2. AND Gate: it is a gate which provides an output 1 when all its inputs are present that means
only if each input is 1. The circuit connections are mad as shown in the fig. when the inputs
are at logic 0. The diode D1 and
awg)D2 forward biased &V is almost at ground potential, LED does not glow
awh) 0
awi) (logic0). When the input A is at logic 0 & B is at logic 1,D1 is forward biased &V is at
ground potential .LED does not glow(logic 0) ,when the
awj) 0 input A is at logi1 & B is at logic 0, D2 is forward biased & V is at
ground
awk) 0
awl) potential LED does not glow (logic0) . When both the inputs A& B are at logic 1,
both D1 adnD2 are reverse biased & they do not conduct & hence V is at logic 1 & LED
glows.
awm)
0
3. NOT Gate: it is the gate which inverse the input & hence it is also called the inverter. the
circuit connections are made as shown in figure, when the input A is at logic 0, the transistor
is turned OFF & hence the output will be at +5V , thence the LED will glow (logic1) when
the input A is at logi1 , the transistor is turned ON since maximum collector current flows
awn). Therefore V is 0 & LED is OFF (logic0).
awo)
0
4. NOR Gate: it is combination of NOT & NOR gate. The circuit connections are made as
sown in the fig. the input conditions are kept as in OR gate& the output are NOT.
5. NAND Gate: it is a combination of MOT & AND gate. The circuit connections are made as
shown in the fig. the input conditions are kept as in AND gate & the output conditions are NOT.
awp)
awq) Circuit diagram and truth table:
p)q)
awr)
AB

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

a)b)

c)

AB

d)e)

f)

00

g)h)

i)

01

j) k)

l)

10

m)
n)

o)

11

r)

s)t)

00

v)w)

01

y)z)

10

ab)
ac)

11

aws)

awt)

awu)
awv)
aww)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

awx)
awy) The logic gates are
corresponding truth tables.
awz)
axa)
axb)
axc)
axd)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

ae)

af)
ag)

BY=

ah)

ai)
aj)

01

ak)

al)
am)

11

an)

ao)
ap)

01

aq)

ar)
as)

10

az)

ba)

bb)

bc)

bd)

be)

bf)

bg)

bh)

bi)

bj)

bk)

bl)

bm)

bn)

constructed and verified the

at)

au

av)

aw

ax)

ay

axe)
axf)
axg)
axh)
axi)
axj)
axk)
axl)
axm)
axn)
axo)
axp)
axq)
axr)
axs)
axt)
axu)
axv)
axw)
axx)
axy)
axz)
aya)
ayb) Experiment No:_____
Date:__________
ayc)
ayd)
TRANSISTOR LOAD LINE ANALYSIS
aye)
ayf) Aim : to construct a D.C load line in a CE amplifier and verify the predicted
operating
conditions of the amplifier and construct a maximum dissipation curve .
Result:
ayg) Apparatus: transistor BC548, regulated power supply, miliammeter, voltmeter.
ayh) Circuit diagram:

ayi)
ayj)
Theory : transistor amplifier must be operated over the linear portion
of their characteristic when it is necessary to reproduce the input signal without
distortion . Therefore it is necessary to choose the operating points and the associated
circuit components.
ayk)
The fig. shows characteristics curves for a transistor in CE mode .
ayl) These curves show the behaviour of the transistor over a range of IC and V
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

aym)
C

efor special values of base currents I . However there is a restriction, relating

ayn)

ayo) to maximum collector dissipation permissible. foreg. For 2N649 transistor

ayp) P =100mWi.e V x IC =100mW. The transistor must be operated to the left
ayq) max
Ceof this
curve.
ayr)
The performance of a transistor amplifier can be predicted graphically
by means of a load line, the load line may be drawn by joining two limiting points on I
-V characteristics. The limiting points are.
ays) C
CE
i) V =0, I = V /R (saturation point)
ayt)
Ce
C
ii) I =0, V = V ( cut point)
ayu)
C
Ce
ayv)
ayw)

CC

CC

ayx) Procedure:
ayy)
The circuit connections are made as shown in the figure. A suitable value of
I (say10A) is selected . V varied in steps of 1V, form 0V and the
aza)

ayz) C
Ce is
corresponding values of I are noted. Those values are tabulated. The

family of I - V

curves are

azb) C experiment is repeated for other values of I .a

azc)

Ce

azd) drawn.

azf) I =
azg)
B
azh) A
azo)
V
azp)
C
E
azq)
azs)
In
v
o
l
t

aze) Observation:Tabular column:

azi)
I=
azl)
I=
azj)
B
azm)
B
azk) A
azn) A
azr)
azt)
azw)
azy)
bab)
I in
V
I in
V
I in
m azu)
C
m azz)
C
m
A E
A E
A
azv)
baa)
c
azx)
c
bac)
c
In
In
v
v
o
o
l
l
t
t

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bad)

bae)

baf)

bag)

bah)

bai)

baj)
bak) Nature of graph:

bal)
bam) Result:
ban)
D.C load line in CE amplifier circuit is constructed and verified the predicted
operating condition of the amplifier.
bao)
bap)

No:_____
Date:__________

bar)

baq)
FERMI ENERGY OF COPPER

bas)
bat)
bau) AIM: To determine the Fermi energy of copper using meter bridge.
bav) PRINCIPLE: Metals have positive temperature co efficient of resistance. When
the temperature of a metal increase its resistance also increases. By noting the change in
resistance with temperature for copper metal and knowing the number of free electrons
per unit volume, Debye temperature and atomic weight of copper, its Fermi energy can
be calculated.
baw) Formula:
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bax)
Ef
Where, E = Fermi energy of copper (eV)
baz) f
bba)
N= Number of free electrons per unit volume (m-3)
bbb)
W Atomic weight of the copper (g)
bbc)
=
bbd)
A= Area of cross section (m2)
bbe)
L = Length of the copper wire (m)
bay)

bbg)

bbf)
S = Slope
Circuit diagram:
bbh)

bbi)

PROCEDURE:
bbj)
The given copper coil is kept in a calorie meter and its ends are
connected to the left gap of a meter bridge. A standard resistance box is connected in the
right gap of the meter bridge. A battery, plug key and sliding contact are connected as
shown in the figure.. Suitable resistance of the order 2 is unplugged from the standard
resistance box. The plug key is closed and the battery is switched on. A suitable voltage
of the order 1V is applied from the battery. The sliding contact is checked for opposite
deflection in the galvanometer by pressing the wire at either side.
bbk)
Boiling water is poured into the calorimeter. The copper coil at a high
temperature of the order 80C, the sliding contact is moved on the wire till the deflection
in the galvanometer becomes zero. The corresponding balancing length is noted. Repeat
the experiment for every 5 C decrease in temperature. The readings are tabulated and the
value of resistance is calculated. Then graph of R versus T is plotted and its slope is
calculated.
bbl) Tabular column:
bbm) Te
mperatur
e t in C
bbn)
bbo)

bbp) T
empe
ratur
e

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bbt)
length

Balancing
bbu)

bbv)
bbw) R=

bbq)

in
K

bbx)
bby)
bbz)
bca)
bcb)
bcc)
bcd)

bbr) (
T=t+
273)
bbs)
bce)

bcf)

bcg)

bch)
bci) CALCULATION:
bcj)
bck) RESULT: Fermi energy of Copper is found to be .eV
bcl)
bcm) Experiment No:_____
Date:__________

bco)

bcn)
PHASE SHIFT OSCILLATOR

bcp)
bcq)
bcr)
bcs)

Aim: To determine the frequency of oscillation of phase shift oscillator.

Apparatus: Resistors, Capacitors, Power supply, Transistor, CRO etc.
Circuit diagram:

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bct)

bcu)
bcv)
bcw)

Procedure:
The connections are made as shown in the circuit diagram in a bread board.
Resistors R and R provide the potential divider bias for the circuit .
bcx)
1
2
bcy) The output of the amplifier goes to a feedback network. The feedback network
consists of three identical RC sections. Each RC section provides a phase of 600C.
Thus a total of 600 X 3=1800 phase shift is provided by the network.
bcz)
Phase shift network is connected between output and input. By this positive
feedback is achieved &Barkhausen criterion (AB=1) holds good. Therefore the circuit
starts oscillating and produces self-sustained conditions sinusoidal signal. By changing
the value capacitor different frequencies are generated.
bda)
bdb)
bdc)
bdd)

The frequency of oscillation is given by

Observations:
bde)
Tri

bdo)
1

bdf)

R
in
K

bdp)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bdg)
C in

bdq)

bdh)
Pe bdi)
Fr
riod T in sec equency
bdj)
in
bdk)
Hertz
bdr)

bds)

bdl)

The
oretica
l value
bdm)

bdn)
bdt)

in
Hz

bdu)
2
bea)
3
beg)
4
bem)
5
bes)
6
bey)
bez)
bfa)
bfb)
bfc)
bfd)

bdv)

bdw)

bdx)

bdy)

bdz)

beb)

bec)

bed)

bee)

bef)

beh)

bei)

bej)

bek)

bel)

ben)

beo)

bep)

beq)

ber)

bet)

beu)

bev)

bew)

bex)

Result:

1) Experimental frequency
bfe)
bff)
bfg)
2) Theoretical frequency
bfh)
bfi)
bfj)
bfk)

Experiment No:____________
Date:_______________
bfl)ASTABLE MULTIVIBRATOR USING IC-555

bfm)
bfn)

Aim: To construct an astable multivibrator using IC-555 and to measure and verify the
frequencies of the square wave generated by it for different values of capacitor.

bfo)
bfp) Apparatus: IC-555, DC power supply (+5V), Resistors, Capacitors, Cathode ray
oscilloscope, Bread board, etc
bfq)
bfr)

Formula:

bfs) The frequency (f) of the square wave generated by an astable multivibrator circuit is
given by
f

bft)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

1.443
(R1 2R2 ) C2

in Hz

bfu)

Where f

= frequency in hertz (Hz),

bfv)

R1 & R2 = resistance in ohm () and

bfw)

C1, C2 = capacitance in farad (F)

bfx)
bfy)

Circuit:

bfz)

bga)

bgb)
bgc) Procedure: Rig up the astable multivibrator circuit on the breadboard as shown in the
circuit diagram. Switch on the power supply and adjust the supply voltage to 5V. It
generates square wave of its own without any external triggering pulse. Set the variable
capacitor C2 to a convenient value (say 0.1 F) and Adjust the time base of the CRO to
get a sharp square wave signal generated by the astable multivibrator. Measure the width
of one square wave pulse (i.e., number of divisions, a) on the Time scale axis (x-axis) and
note down the time/ division (b). The product of a and b gives the time period (T) of the
generated square wave signal. The reciprocal of T gives its frequency.
bgd) The experiment is repeated for various values of C 2 and the frequency the
generated square wave signal is determined is each case and is compared with the theoretical
frequencies which are calculated using the given formula.
bge)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bgf)

Tabular column:

bgg)

bgh)
Capa
ci
to
r
bgi)

C
2

bgj)
(in

F
)

bgk)
Num
b
e
r
o
f
d
i
v
is
i
o
n
s
o
n
bgl)
x
a
x
is

bgn)
Time
/
d
i
v
bgo)
(b in
m
s)

bgp)
Peri
o
d
bgq)
T=
a

bgs)
Frequ
e
n
c
y
in
f

bgu) Theoretic
al frequency
bgv)
1
T

b
bgr)
(in
m
s
)

bgt)
(in
k
H
z)

1.443
(R1 2R2 ) C2

bgw) (in kHz)

bgm)
(a in
d
i
v
)
bgx)
0.1

bgy)

bgz)

bha)

bhb)

bhc)

bhd)
0.2

bhe)

bhf)

bhg)

bhh)

bhi)

bhj)
0.3

bhk)

bhl)

bhm)

bhn)

bho)

bhp)
0.4

bhq)

bhr)

bhs)

bht)

bhu)

bhv)

bhw)

bhx)

bhy)

bhz)

bia)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

0.5
bib)
0.6

bic)

bid)

bie)

bif)

big)

bih)
0.7

bii)

bij)

bik)

bil)

bim)

bin)
0.8

bio)

bip)

biq)

bir)

bis)

bit) 0.
9

biu)

biv)

biw)

bix)

biy)

biz)
1.0

bja)

bjb)

bjc)

bjd)

bje)

bjf)
bjg)
bjh)
bji)
bjj)
bjk)
bjl)
bjm)
bjn)
bjo)
bjp)
bjq)
bjr)
bjs)
bjt)
bju)
bjv)
bjw)
bjx)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bjy)
bjz) Result: The Astable multivibrator is constructed using IC555 and the frequency of
the square wave generated is determined for different values of capacitor and found to be
in agreement with the respective theoretical value.
bka)
bkb)
bkc) Experiment No:____________
Date:_______________
bkd) FIELD EFFECT TRANSISTOR
bke)
bkf) Aim: To study transfer and output characteristics of a given Field Effect Transistor
and hence to determine its parameters.
bkg)
bkh) Apparatus: FET (BFW 10), Milliammeter, Voltmeters, regulated power supply,
rheostats and resistance box.
bki)
bkj)
bkk)

Formula:
The characteristic parameters of a FET are given by
VDS

ID VGS

rd

4. Drain resistance

in

ID

VGS VDS

gm

5. Trans conductance

in mho (1)

VDS
rd gm

VGS ID

bkl)

6. Amplification factor
Where VDS is the drain-source voltage

bkm)

VGS is the gate-source voltage and

bkn)

ID is the drain current.

bko)
bkp) Circuit:

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bkq)
bkr)

bks)
bkt) Procedure: Electrical connections are made as shown in the circuit diagram by using
a n-channel FET BFW 10.
bku)
bkv) Transfer characteristics: The voltage between the drain and source (VDS) is kept
constant at 1 V. the voltage between the gate and source (VGS) is gradually increased in
regular steps of 0.5V and the drain current ID is measured. The experiment is repeated
by fixing the VDS at 2V. Transfer characteristic curve is obtained by plotting a graph of
ID verses VGS at constant VDS.
bkw)
bkx) Drain characteristics: The Voltage between gate and source (VGS) is kept constant at
1V. The voltage between drain and source (VDS) is gradually increased is regular steps
of 0.5V and the drain current ID is measured. The procedure is repeated for another
value of VGS say at 2V. Drain characteristic curve is obtained by plotting a graph of ID
verses VDS at constant VGS.
bky)
bkz) The constants of FETDrain resistance, Transconductance and Amplification factor
are
determined from the characteristic curves.
bla)

Tabular column:

blb)

Transfer characteristics:

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

RD = 1000

blc)

VDS
= 1V

bld)

VDS
= 2V

ble)
V

blf)
I

blg)
V

blh)
I

bli)

blj)

blk)

bll)

blm)

bln)

blo)

blp)

blq)

blr)

bls)

blt)

blu)

blv)

blw)

blx)

bly)

blz)

bma)

bmb)

bmc)

bmd)

bme)

bmf)

bmg)

bmh)

bmi)

bmj)

bmk)

bml)

bmm)

bmn)

bmo)

bmp)

bmq)

bmr)

bms)

bmt)

bmu)

bmv)

bmw)

bmx)

bmy)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bmz)

bnb)

bna)
bnc)
RD=1000

bnd) Output characteristics:

bne) VGS
= 1V

bnf)

VGS
= 2V

bng)
V

bnh)
I

bni)
V

bnj)
I

bnk)
0

bnl)

bnm)
0

bnn)

bno)
0

bnp)

bnq)
0

bnr)
bpd)

bns)
1

bnt)

bnu)
1

bnv)

bnw)
1

bnx)

bny)
1

bnz)

boa)
2

bob)

boc)
2

bod)

boe)
2

bof)

bog)
2

boh)

boi)
3

boj)

bok)
3

bol)

bom)
3

bon)

boo)
3

bop)

boq)
4

bor)

bos)
4

bot)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bou)
4

bov)

bow)
4

box)

boy)
5

boz)

bpa)
5

bpb)

bpc)
bpe)
bpf)
bpg)
bph)
bpi)

Results: The characteristic parameters of the given FET are .

4. Drain resistance rd
5. Transconductance gm
6. Amplification factor

= __________________
= __________________1
= __________________

bpj)
bpk) Note: The Transfer characteristic curves are also known as mutual Characteristic or
Transconductance curve and the Drain characteristic curves are also known as output or
common source drain characteristic curves.
bpl)
bpm)
Code

bpn)
Typ
e

bpo)

M
ax.
VDS

bpr)
BFW
1
0
bpw)
BFW
1
1

bpp)
Max.
ID

bpq) Appl
ication

bpu)
20mA

bps)
NF
E
T

bqb)
BFW
1
2

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bpt)

3
0V

bpz)
10mA

bqe)
5mA

bpv)

Ampl
ifier

bqg)

Experiment No:____________
Date:_______________
bqh) FULL WAVE RECTIFIER

bqi)
bqj) Aim: To construct a full wave rectifier by soldering the circuit and hence to study the
effect of load and effect of different filters on its ripple factor.
bqk)
bql) Apparatus: Semiconductor diodes, resistance box, Inductor. Capacitor, Stepdown
transformer.
bqm)
bqn) Principle: Rectification the process of converting ac signal into dc signal. In a Full
wave rectifier the complete cycle of input ac signal converted into dc signal. The ripple
factor is defined as the ratio of rms value of ac components to the value of dc component.
The ripple factor for full wave rectifier without filter is 0.482.
bqo)
bqp) Formula:

bqq)
bqr)

The ripple factor for full wave rectifier is given by

Where Vac rms value of voltage for ac components
Vdc

bqs)
bqt)
bqu) Circuit:

bqv)
bqw)
bqx)

Vac
Vdc

Procedure:

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

value of voltage for dc components

bqy)
The full wave rectifier circuit is constructed as shown in the circuit by
soldering. Adjust the value of load resistance RL = 100 and measure the AC and DC
voltages it. The experiment is repeated for by increasing the load resistance in steps of
100 and the ripple factor is calculated in each case.
bqz)
Now the rectifier output is fed to the capacitor input filter and varying the load
resistance in steps of 100 , the variations in the AC and DC voltages across the load are
observed and readings are tabulated. Finally ripple factor is calculated.
bra) The experiment is repeated by feeding rectifier output to L section and section
filters.
brb)
brc)

Tabular Column:

brd)

Inductance of the Inductor L = __1_____H

bre)

Capacitance of the Capacitor C = __100____ F

brf)

Capacitance of the Capacitor C = ____47___ F

brg)
brh)
bri)
brj)
brk)

brl)
F

brm) Circ
uit

brn) L
oad
Resi
stan
ce
bro) (
in
)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

brp)
AC
V
o
l
t
a
g
e

brr)
DC
V
o
l
t
a
g
e

brq)
Vac
(
i
n

brs)
Vdc
(
i
n

V
)

V
)

brt)

Rippl
e Factor

Vac
Vdc

brw)

brx)

bry)

bsd)

bse)

bsj)

bsk)

bsp)

bsq)

bsv)

bsw)

btb)

btc)

bth)

btn)

00

bru)
Series Inductor

brv)

bsc)
50
bsi)
00
bso)
50
bsu)
00
bta)
00

bsz)

btg)

bsy)
Shunt Capacitor

50
btm)

bti)
bto)

00
bts)

2
50

bty)

btt)

btu)

btz)

bua)

buf)

bug)

bul)

bum)

bur)

bus)

buw) 2
50

bux)

buy)

bvc)

bvd)

bve)

bvj)

bvk)

bvp)

bvq)

00
bue)
00

buc)
L- Section

bud)

buk)
50
buq)
00

bvg)
- Section

00
bvi)
00
bvo)
50

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

brz)
bsf)
bsl)
bsr)
bsx)
btd)
btj)
btp)
btv)
bub)
buh)
bun)
but)
buz)
bvf)
bvl)
bvr)

bvu)

bvv)

bvw)

bwa) 2
50

bwb)

bwc)

bwg) 3
00

bwh)

bwi)

00

bvh)

bvx)
bwd)
bwj)

bwk)
bwl)

bwm)
bwn)
bwo)
bwp)
bwq)
bwr)
bws)

Result:

bwt)
The full wave rectifier circuit is constructed and the effect of load and effect of
different filters on its ripple factor is studied.
bwu)
bwv)
bww) Note: For series inductor filter, choose the value of L such that X L >> RL and for
Shunt capacitor filter, choose the value of C such that XC << RL
bwx)
bwy) Experiment No:____________
Date:_______________
bwz) HALF WAVE RECTIFIER
bxa)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

bxb) Aim: To construct a half wave rectifier by soldering the circuit and hence to study the
effect of load and effect of different filters on its ripple factor.
bxc)
bxd) Apparatus: Semiconductor diodes, resistance box, Inductor. Capacitor, Stepdown
transformer.
bxe)
bxf) Principle: Rectification the process of converting ac signal into dc signal. In a half
wave rectifier only the half cycle of input ac signal converted into dc signal. The ripple
factor is defined as the ratio of rms value of ac components to the value of dc component.
The ripple factor for half wave rectifier without filter is 1.21.
bxg)
bxh)

Formula:

bxi)
bxj)

The ripple factor for half wave rectifier is given by

Vac
Vdc

Where Vac rms value of voltage for ac components

Vdc

bxk)
bxl)
bxm) Circuit:

bxn)

bxo)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

value of voltage for dc components

bxp)

Procedure:

bxq)
The half wave rectifier circuit is constructed as shown in the circuit by
soldering. Adjust the value of load resistance RL = 100 and measure the AC and DC
voltages it. The experiment is repeated for by increasing the load resistance in steps of
100 and the ripple factor is calculated in each case.
bxr)
Now the rectifier output is fed to the capacitor input filter and varying the load
resistance in steps of 100 , the variations in the AC and DC voltages across the load are
observed and readings are tabulated. Finally ripple factor is calculated.
bxs) The experiment is repeated by feeding rectifier output to L section and section
filters.
bxt)
bxu)

Tabular Column:

bxv)

Inductance of the Inductor L = __1_____H

bxw) Capacitance of the Capacitor C = __100_____ F

bxx)

Capacitance of the Capacitor C = ____4.7___ F

bxy)
bxz)
bya)
byb)

byc)
F

byd)

Circ
uit

bye) L
oad
Resi
stan
ce
byf) (
in
)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

byg)
AC
V
o
l
t
a
g
e

byi)
DC
V
o
l
t
a
g
e

byh)
Vac
(
i
n

byj)
Vdc
(
i
n

V
)

V
)

byk) Rippl
e Factor

Vac
Vdc

byn)

byo)

byp)

byu)

byv)

bza)

bzb)

bzg)

bzh)

bzm)

bzn)

bzs)

bzt)

bzy)

bzz)

cae)

caf)

cak)

cal)

caq)

car)

caw)

cax)

cbc)

cbd)

cbi)

cbj)

cbo)

cbp)

cbu)

cbv)

cca)

ccb)

ccg)

cch)

00

byl)
Series Inductor

bym)

byt)
50
byz)
00
bzf)
50
bzl)
00
bzr)
00

bzq)

bzx)

bzp)
Shunt Capacitor

50
cad)
00
caj)
50
cap)
00
cav)
00
cau)

cbb)

cat)
L- Section

50
cbh)
00
cbn)
50
cbt)
cbx)
- Section

00
cbz)
00
ccf)
50

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

byq)
byw)
bzc)
bzi)
bzo)
bzu)
caa)
cag)
cam)
cas)
cay)
cbe)
cbk)
cbq)
cbw)
ccc)
cci)

ccl)

ccm)

ccn)

ccs)

cct)

ccy)

ccz)

00
ccr)
50

cby)
ccx)

00

cco)
ccu)
cda)

cdb)
cdc)
cdd)
cde)
cdf)
cdg)
cdh)
cdi)
cdj)
cdk)
cdl)
cdm)
cdn)
cdo)
cdp)
cdq)
cdr)
cds)
cdt)
cdu)

Result:

cdv)
The half wave rectifier circuit is constructed and the effect of load and effect
of different filters on its ripple factor is studied.

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

cdw)

Experiment No:____________
Date:_______________
cdx) RC PHASE SHIFT OSCILLATOR

cdy)
cdz)

Aim: To Construct a phase shift oscillator using transistor and verify the frequencies for
different values of capacitor.

cea)
ceb) Apparatus: Semiconductor diodes, resistance box, Inductor. Capacitor, Stepdown
transformer.
cec)
ced) Theory: An oscillator is a circuit, which generates ac output signal without giving
any input ac signal. This circuit is usually applied for audio frequencies only. The basic
requirement for an oscillator is positive feedback. The operation of the RC Phase Shift
Oscillator can be explained as follows. The starting voltage is provided by noise, which is
produced due to random motion of electrons in resistors used in the circuit. The noise
voltage contains almost all the sinusoidal frequencies. This low amplitude noise voltage
gets amplified and appears at the output terminals. The amplified noise drives the
feedback network, which is the phase shift network. Because of this the feedback voltage
is maximum at a particular frequency, which in turn represents the frequency of
oscillation. Furthermore, the phase shift required for positive feedback is correct at this
frequency only. The voltage gain of the amplifier with positive feedback is given by
Af

A
1 A

.
A 1

Af

cee) From the above equation we can see that if

then
. The gain
becomes infinity means that there is output without any input. i.e. the amplifier becomes an
A 1

oscillator. This condition

is known as the Barkhausen criterion of oscillation.
cef)
Thus the output contains only a single sinusoidal frequency. In the beginning,
as the oscillator is switched on, the loop gain A is greater than unity. The oscillations
build up. Once a suitable level is reached the gain of the amplifier decreases, and the value of
the loop gain decreases to unity. So the constant level oscillations are maintained. Satisfying
the above conditions of oscillation the value of R and C for the phase shift network is selected
such that each RC combination produces a phase shift of 60. Thus the total phase shift
produced by the three RC networks is 180. Therefore at the specific frequency fo the total
phase shift from the base of the transistor around the circuit and back to the base is 360
thereby satisfying Barkhausen criterion. We select R1= R2=R3 =R and C1 =C2 =C3 = C
ceg) The frequency of oscillation of RC Phase Shift Oscillator is given by
f

2RC 6

0.065
RC

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

ceh)
cei)

At this frequency, the feedback factor of the network is

1
29

A 1

In order that
operation.

it is required that the amplifier gain

A 29

for oscillator

cej)
cek)

Formula:
cel)

The frequency of oscillation of RC Phase Shift Oscillator is given by

f

cem)
cen)

Where f

1
2RC 6

0.065
RC

in Hz

frequency in hertz (Hz),

ceo)

R resistance in ohm () and

cep)

C capacitance in farad (F)

ceq)
cer)
ces)

Circuit:

cet)
ceu) Procedure: Rig up the RC Phase Shift Oscillator circuit on the breadboard as shown
in the circuit diagram. Switch on the power supply and adjust the supply voltage to 15V.
Set the capacitors C1=C2=C3= C to a convenient value (say 0.01 F) and Adjust the time
base of the CRO to get a sharp sinusoidal wave signal generated by the RC Phase Shift
Oscillator. Measure the width of one sinusoidal wave pulse (i.e., number of divisions, a)
on the Time scale axis (x-axis) and note down the time/ division (b). The product of a and
b gives the time period (T) of the generated sinusoidal wave signal. The reciprocal of T
gives its frequency.
cev)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

cew) The experiment is repeated for various values of C1=C2=C3 =C and the
frequency the generated square wave signal is determined is each case and is compared with
the theoretical frequencies which are calculated using the given formula.
cex)
cey)

Tabular Column:

cez)
cfa)

Capacitor

cfb)

C1=C2=C3
=C

cfn)
Ca
cfo)
Co

cfv)
22
cgc)
10
cgj)
40
cgq)
0.

cfp)
Cap
a
ci
t
a
n
c
e
v
a
l
u
e
(i
n
n
F
)
cfw)
220
cgd)
100
cgk)
40
cgr)

cfc)
N
cfd)
x
cfe)
(a

cfh)
Pe
cff)
Ti

cfi)
T

cfg)
(

cfk)

F
req
uen
cy
f

cfj)
(in

cfl) Theor
etical
frequ
ency
cfm)

1
(in kHz)
0.065
T
f
in Hz
RC

cfx)

cfy)

cfz)

cga)

cgb)

cge)

cgf)

cgg)

cgh)

cgi)

cgl)

cgm)

cgn)

cgo)

cgp)

cgs)

cgt)

cgu)

cgv)

cgw)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

cgx)
10
che)
68
chl)
56
chs)
33

cgy)
10
chf)
6.8
chm)
5.6
cht)
3.3

cgz)

cha)

chb)

chc)

chd)

chg)

chh)

chi)

chj)

chk)

chn)

cho)

chp)

chq)

chr)

chu)

chv)

chw)

chx)

chy)

chz)
cia)
cib)
cic)

Result:

cid)
The RC Phase Shift Oscillator is constructed and the frequency of the
sinusoidal wave generated is determined for different values of capacitor and found to be
in agreement with the respective theoretical value.
cie)
Experiment No:____________
Date:_______________
cif) OPERATIONAL AMPLIFIER
cig)
cih) Aim: to study the performance of an operational amplifier (OP-AMP) in inverting and
noninverting modes and hence to determine its gain for different feedback resistances.
cii)
cij) Apparatus: OP-AMP (IC741), AF oscillator, resistor, resistance box and multimeter/
digital voltmeter.
cik)
cil) Formula:
AV

3. The gain of the operational amplifier in inverting mode is

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

Rf
V0

Vi
Ri

AV

Rf
V0
1
Vi
Ri

4. The gain of the operational amplifier in non-inverting mode is

cim)
Where Vi and Vo Input and output voltages respectively (in V)
cin)

Rf Feedback resistance (in )

cio)

Ri series input resistance (in )

cip)

Circuit:
cir)

ciq)

cis)

cit)

ciu)
ciw)
cix)
ciy)

Procedure:
Inverting mode:

ciz)
The op-amp circuit in the inverting mode is rigged up on the breadboard. The
input signal from the AF oscillator is set at a convenient value (say 0.1 V @ 1 kHz) with a
series resistance Ri =1 k. The value of feedback resistance Rf is varied in steps of 0.5 k
from 1 k and the out put voltage is measured in each case. The voltage gain is calculated
both experimentally and theoretically and the values are compared.
cja)
cjb)

Non Inverting mode:

cjc)
The op-amp circuit in the noninverting mode is rigged up on the breadboard.
The input signal from the AF oscillator is set at a convenient value (say 0.1 V @ 1 kHz) with
a series resistance Ri =1 k. The value of feedback resistance Rf is varied in steps of 0.5 k
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

from 1 k and the out put voltage is measured in each case. The voltage gain is calculated
both experimentally and theoretically and the values are compared.
cjd)
cje)

cjh)

Observations:
cjf)

Input voltage = Vi = ____0.1____V

cjg)

Series input resistance = Ri =__1000_

Inverting mode:

cji)
cjj) Fe
ed
ba
ck
res
ist
an
ce

cjl) Ou
tp
ut
cjm)
Volta
ge

cjk)
Rf (in
k
)

cjn)
V0 (in
V)

cjv)
1.0

cjo)
cjr)Ex
pe
ri
me
nta
l
cjs)

Voltage Gain
cjt) Th
eor
eti
cal
cju)

V
AV 0
Vi

AV

cjw)

cjx)

cjy)

cjz)
1.5

cka)

ckb)

ckd)
2.0

cke)

ckf)

ckg)

ckh)
2.5

cki)

ckj)

ckk)

ckl)
3.0

ckm)

ckn)

cko)

ckp)
3.5

ckq)

ckr)

cks)

ckt)
4.0

cku)

ckv)

ckw)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

Rf

Ri

ckc)

ckx)
4.5

cky)

ckz)

cla)

clb)
5.0

clc)

cld)

cle)

clf)
clg)

Non Inverting mode:

clh)
Feedb
ac
k
res
ist
an
ce
cli) Rf
(in
k
)

clm)
clj) Ou
tp
ut
clk)
Volta
ge
cll) V0
(in
V)

clp)
Experi
me
nta
l
clq)
AV

V0
Vi

Voltage Gain

clr) Th
eor
eti
cal
cls)
AV 1

clu)

clv)

clx)
1.5

cly)

clz)

cmb)
2.0

cmc)

cmd)

cme)

cmf)
2.5

cmg)

cmh)

cmi)

cmj)
3.0

cmk)

cml)

cmm)

cmn)
3.5

cmo)

cmp)

cmq)

cmr)
4.0

cms)

cmt)

cmu)

cmv)
4.5

cmw)

cmx)

cmy)

clt) 1.0

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

Rf

Ri

clw)
cma)

cmz)
5.0

cna)

cnb)

cnc)

cnd)
cne)
cnf)

Result:

cng) The voltage gain of the given operational amplifier (IC741) is determined in
inverting and noninverting determined modes for different feedback resistances and is
found to be in agreement with the respective theoretical value.

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

cnh)

I V CHARACTERISTICS OF A ZENER DIODE

cni) Aim: - To draw the I-V characteristics of a Zener diode and to determine the knee
voltage and Zener voltage.
cnj) Apparatus: -Zener diode, 0 to 20 V DC power supply, digital voltmeter (DVM),
digital DC milliammeter (DCM), resistor and patch cards.
cnk)
cnl) Principle: - A Zener diode is basically an ordinary p-n junction diode with heavily
doped p and n regions. A forward biased Zener diode conducts like an ordinary p-n
junction diode, when the biasing voltage exceeds the junction barrier potential. When
reverse biased, the reverse saturation current is very small of the order of A until the
breakdown voltage is reached. At breakdown the resistance of the diode becomes very
low and the reverse current increases abruptly. Since the voltage across the diode is
almost a constant as long as it is conducting, it is used as a voltage regulator.
cnm)
cnn) Procedure: - The circuit is connected as shown in the diagram (i). Power supply
knob is turned to minimum position.
cno)

Forward Bias:

1. Connect positive terminal of the battery to the P-section of the zener diode and negative terminal
of the battery to n-section of the zener diode.
2. The applied voltage VF is increased from zero (in steps of 0.1 V) to a value where there is a sign
of increase in current. After observing a small increase in current, now the voltage is varied in
steps of 0.04 volt up to a value where there a steep rise in the current IF.
cnp) Reverse Bias:
1. The power supply knobs turned to minimum.
2. The Zener diode is reverse biased by connecting n-section of the zener diode to positive of the
battery terminal and p section to the negative of the battery terminal.
3. The voltage VR is varied from zero (in steps of 1 V) to a value where there is a sign of increase in
current. After observing a small increase in current, now the voltage is varied in steps of 0.1 volt
up to a value where there a steep rise in the reverse current IR.
cnq)
cnr)

Graph:

cns) A graph of current versus voltage for both forward bias and reverse bias of zener
diode is plotted. From the forward bias characteristic curve, the portion of the curve that
could be approximated to a straight line is extrapolated downward to meet the X-axis.
This voltage value is known as knee voltage VK. Similarly in the reverse bias
characteristic curve, the portion of curve that forms a straight line is extrapolated upward
to meet at X-axis. The value of corresponding voltage is known as breakdown voltage or
zener voltage VZ.
cnt)
DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

cnu)
cnv)
cnw) Result: cnx) The knee voltage VK of the given zener diode
cny)

The zener breakdown voltage VZ of the given zener diode =____________ V

cnz)
coa)

=____________ V

Circuit diagram
cob)

coc)
cod)
coe)

DEPARTMENT OF PHYSICS, BNMIT, BANGALORE 70

cof)

Forward bias characteristics:

cog)
coh)
VF
(i
n
V
)

coi)
IF

coj)

cok)

col)

com)

con)

coo)

cop)

coq)

cor)

cos)

cot)

cou)

cov)

cow)

cox)

coy)

coz)

cpa)

cpb)

cpc)

cpd)

cpe)

cpf)

cpg)

cph)

cpi)

cpj)

cpk)

(
m
A
)

cpl)
cpm) Reverse
bias
characteristics
:
cpn)

cpo)
VR
(i
n
V
)

cpp)

cpq)

cpr)

cps)

cpt)

cpu)

cpv)

cpw)

cpx)

cpy)

cpz)

cqa)

cqb)

cqc)

cqd)

cqe)

cqf)

cqg)

cqh)

cqi)

cqj)

cqk)

cql)

cqm)

cqn)

cqo)

cqp)

cqq)

cqr)

I
R

(mA
)

cqs)
cqt)
cqu)

Capacitance of a capacitor Using BG by absolute method

Aim: Determination of Capacitance of a capacitor Using BG by absolute method

cqv)

cqw)

Apparatus: capacitor, plug key, ballistic galvanometer, battery, resistance box etc.

cqx) Procedure: If a quality of charge Q passes through a BG it produces a first throw 1

of the coil which have the relationship
cqy)

Q=T/2 i/01 (1/2)1/4

cqz)
Where 0 is the steady deflection for current I and T is the free period of oscillation of
the coil. If a charged condenser is discharged through BG, then we have
cra)
crb) the lamp and scale are arranged in front of leveled BG and free period of oscillation is
determined electrical connections are made as in fig1 .the condenser is charged by
pressing the charge and discharge key and it is discharged through the BG by setting it to
touch up terminal. The shunting key of BG should be unplugged while discharging the
first and third throws 01 and 03 are noted.
crc)

Electrical connections are as shown in fig2 R and S are resistance boxes of 0-5000 ohms
and a resistance of 0.1 respectively resistance of R about 2000 ohm is unplugged in R
and the shunt key is unplugged. A steady deflection is observed on the scale nothing the
deflection in resistance in the box S is adjusted till the deflection is about half of its
originalvalue. The resistance unplugged in the box S given the resistance of the BG coil
G.

crd) Deflection 0 is noted for their different values of S and average value of Er/(R+1)
(G+S)0 is calculated the capacitance of condenser is given by
cre)

C= T/2 (i/) 1 (1/2)1/4F

crf)

OBSERVATION:

crg)

Time taken for 10 oscillation=t=

crh)

sec.

Period of free oscillations=T=t/10= sec.

cri) Value of resistance unplugged in R = .

crj) Deflection when S is zero== m.
crk)

TABULAR COLUMN

crl) deflection 1 cm

crm)
3 cm

deflection

crn)

(1/2)1/4

cro)

crp)

crq)

crr)

crs)

crt)

cru)

crv)

crw)

crx)

Mean=

cry)
Resis
ta
n
ce
r

crz)
Resis
ta
n
ce
R

csa)
shunt
re
si
st
a
n
ce
S

csb)
Stead
y
d
ef
le
ct
io
n

csc)
Galva
no
m
et
er
re
sis
ta
nc
e
G

csd) i/s
=Er/R
(G+S)
1/

csg)

csh)

csi)

csj)

csk)

csl)

csm)

csn)

cso)

csp)

csq)

csr)

css)

cst)

csu)

csv)

csw)

csx)

csy)

csz)

cta)

ctb)

ctc)

ctd)

cte)

ctf)

ctg)

cth)

cti)

ctj)

cse)
csf)

ctk)

(i/) mean=

ctl) RESULT: The capacitance of the condenser by absolute method is=

ctm)
ctn)
cto)
ctp)

5. RS FLIP-FLOP USING IC-7400

Construct and working of RS flip-flop i=using IC-7400(NAND). Apparatus:

IC-7400(NAND),circuit board, power supply +5V DC,

ctq)

Connecting wires, switch (S , S ).

ctr) 1

cts)
Theory:
ctt)
A flip-flop is a binary storage device i.e. , it can store binary bit either 0 or 1.
It has two stable states HIGH and LOW, i.e. 1 and 0 .it has the property to remain in one state

indefinitely until it is directed by an input signal to switch over to other state . it is also called
bistablemultivibrator . it is basic memory element .
ctu)
The various types of flip-flop are RS flip-flop ,JK flip-flop, D flip-flop, T flipflop, master slave flip-flop.
ctv)
A flip-flop circuit has two outputs one for normal value and one for the compliment
value of the bit stored in it. Binary information can enter a flipflop on variety of ways, a fact
which give raise to different types of flip-flop .
ctw)

The output of a flip-flop in low voltage or high voltage.

ctx)

So that it has two states 0 or 1.

cty)

ctz)
The input S is known as she set (or) present input and the input R as the reset
or clear input. The flip-flop is called RS flip-flop. Since the information is locked in place, this
flip-flop is also termed as latch.
cua)
It is very useful to add clock to RS flip-flop to control precisely the time at
which the flip-flop changes the state of its output. The clock, a square wave using AND gate as
shown in fig(3) . When clock is low the state of flip-flop is not changes because zero inputs are
applied to the flip-flop via AND gate. Flip-flop can change its output only when the clock is
high. Operation of RS flip-flop:
cub)
1. Input R=S=0 i.e. in the absence of any trigger input, the output state is undetermined i.e. Q may be
either 0 or 1.
2. If R=0, S=1 gate-1 is enabled and gate -2 is disabled. Therefore, Q=1 and Q=0. The Flip-flop is now
SET.
3. If R=1, S=0 gate-1 is disabled and gate -2 is enabled. Therefore=0 and Q=1. The Flip=flop is now
RESET.
4. If R=S=1 the Flip-flop will not change its state and will remain in LAST STATE. Hence, it is called
no change (NC) condition.
cuc)
cud)
cue)

Logic symbol for RS Flip-flop:

cuf)
cug) Procedure:
1) Set up the circuit as shown in fig(3)

pin configuration:

2) Connect pin 14 to _5 V V and pin 7 to ground.

cuh)
cc
3) Pin 13 and 1 are interconnected, pin 4 is connected to 8 and pin 10 connected to
6.
4) The pin 8 gives the output Q and pin gives the Q.
5) Pin 13 and 1 are interconnected and pin 13 or 1 is connected to clock.
6) Observe that in this circuit the input will effective only when clock pulse is
present.
7) Give logic inputs according to the truth table.
8) For different values of S and R the output is obtained and verify the truth table.
cui)
cuj)

Circuit diagram:

cuk)
cul)
cum)

Truth table:

bo)

bq)

br)

Clock
input
bp)

Lo
gical inputs

Log bs)
C
ical outputs
omments

bu)

bv)

bw)

bx)
by)

bz)

ca)

cb)

cc)

cd)
ce)
st state

La

1
cf)

cg)

ch)

ci)

cj)ck)

0 ET

cl)

cm)

cn)

co)

cp)
cq)

1 ESET

cr)

cs)

ct)

cu)

cv)
cw)

Fo
1 rbidden state

cun)
cuo)
cup)
cuq)
cur)
cus)

Result:

RS lip-flop is constructed and hence truth table is verified.

cut) CAPACITY OF CONDENSER BY ABSOLUTE METHOD

cuu)

Aim: To determine the capacity of condenser using balastic galvanometer.

cuv) Apparatus: BG condenser, tapping key, charge- discharge key, Resistance boxes
etc
cuw) Circuit diagram:
cux)

cuy) Procedure:
4) With s=0 & R +R =1000 ( or a suitable high value ) close the plug
cuz)
1
2 key K & note the steady deflection . Now
increase the value of S
cva) 2
cvb) so that the deflection reduces to /2. This particular value of s
cvc)

cvd) gives galvanometer resistance G.

5) Determine the times for N free torsional oscillation of the coil. Calculate the period T=t/N.
6) unplug the suitable value in R adjust R so that R +R =1000(or a
3 2
1
2 suitable high value )
keep S=0 close key k note down steady
4 deflection
keeping k open, charge the
condenser C & discharge
cve) 2
cvf) it through .B.G using the charge & discharge key. Note the first throw &
second throw
the formula.

on the same side of zero. Calculate the capacity of condenser using

cvg)

cvh)

Repeat the experiment for different values of R and R keeping

cvi) 1

cvj)

R +R =1000 (or a suitable high value).

cvk)

2
3.

cvm) 1
cvn)

cvl)
Observation:
S=0 , r=0.1 , R +R =1000( a high value) the steady deflection

2
=________

cvo)

The value of S to reduce the deflection to

cvp)

The galvanometer resistance G=___________

4.

cvq)
cvr)
Trial
cvs)
No

cvt)
R
cvu)
1

/2 is G =____________

Time for N torsional oscillation =t seconds

Periods T=t/N=_______seconds
cvw)
R
cvx)
2

cvz)
Ste cwb)
ady
rst
deflection
cwc)
row
cwa)

Fi
th

cwe)
econd
throw

S cwg)

cwf)
cwd)

cvy)
in

cwj)

cwk)

cwl)

cwm)

cwn)

cwo)

cwp)

cwq)

cwr)

cws)

cwt)

cwu)

cwv)

cww)

cwx)

cwy)

cwz)

cxa)

cxb)

cxc)

cxd)

cxe)

cxf)

cxg)

cxh)

cxi)

cxj)

cxk)

cxl)

cxm)

cxn)

cxo)

cxp)

cxq)

cxr)

cxs)

cxt)

cxu)

cxv)

cxw)

cxx)

cxy)

cwi)

cxz)

Mean
C=____________

cyb)
cyc)
cyd)
cye)
cyf)
cyg)

Capacity
cwh)

cvv)
In

cya)

cyh)
Result :
cyi) The capacitance of the given capacitor by absolute method is =______
No:___ _____
Date:__________
cyj)

Experiment

LOGIC GATES

cyk)

Aim: To construct basic logic gates and to verify their truth tables.

cyl)

Apparatus: power supply , diodes, transistors, resistors, LED or voltmeter.

cym) Basic information: A basic logic gate is a circuit where the output is logically related
to the input i.e it is a circuit which make logic decision. The output signal appears only
for certain combinations of input signal. In these circuits the numbers 1 and 0 are used to
represent two voltage levels, a high voltage say +5V and low voltage say 0V, they are also
referred to as TRUE or FALSE.
cyn) Procedure:
6. OR Gate: it is a gate to provide an output of 1 when either of inputs A or B or both are The circuit
to realize an OR gate is shown in the fig. The electrical connections are made as shown the fig to
feed high input , the input terminal is connected to +5V of the power supply. To feed the low input,
the input terminal is connected to ground terminal of the supply. The output is considered as high if
the measured output voltage is close to the supply voltage (+5V) or if LED glows. It is low if the
measured output voltage is 0V or if LED does not glow. When both inputs A and B are 0 that means
connected to ground the LED does not glow which is equal to 0. When the input A is 0 and B is +5V
the diode D is forward
cyo)2 biased
and hence conducts. The LED glows, that means the output logic 1, when the input A is
at+5V and B is 0V the output logic is 1. When both inputs A and B are at +5V, both diodes
D1and D2 conduct and hence the LED glows therefore the logic output logic is 1.
7. AND Gate: it is a gate which provides an output 1 when all its inputs are present that means only if
each input is 1. The circuit connections are mad as shown in the fig. when the inputs are at logic 0.
The diode D1 and
cyp) D2 forward biased &V is almost at ground potential, LED does not glow
cyq) 0
cyr) (logic0). When the input A is at logic 0 & B is at logic 1,D1 is forward biased &V is at
ground potential .LED does not glow(logic 0) ,when the
ground

cys)

0 input A is at logi1 & B is at logic 0, D2 is forward biased & V is at

cyt) 0
cyu) potential LED does not glow (logic0) . When both the inputs A& B are at logic 1,
both D1 adnD2 are reverse biased & they do not conduct & hence V is at logic 1 & LED
glows.
cyv) 0
8. NOT Gate: it is the gate which inverse the input & hence it is also called the inverter. the circuit
connections are made as shown in figure, when the input A is at logic 0, the transistor is turned OFF

& hence the output will be at +5V , thence the LED will glow (logic1) when the input A is at logi1 ,
the transistor is turned ON since maximum collector current flows
cyw) . Therefore V is 0 & LED is OFF (logic0).
cyx)
0
9. NOR Gate: it is combination of NOT & NOR gate. The circuit connections are made as sown in the
fig. the input conditions are kept as in OR gate & the output are NOT.
10. NAND Gate: it is a combination of MOT & AND gate. The circuit connections are made as
shown in the fig. the input conditions are kept as in AND gate & the output conditions are NOT.
cyy)
cyz)

Circuit diagram and truth table:

cza)

cx)
cy)

cz)

czb)

AB

da)
db)

dc)

00

dd)
de)

df)

01

dg)
dh)

di)

10

dj)
dk)

dl)

11

1
dm)
dn)

AB

dp)
dq)

00

ds)
dt)

01

dv)
dw)

10

dy)
dz)

11

czc)

czd)
cze)
czf)

ew)

ex)

ey)

ez)

fa)

fb)

fc)

fd)

fe)

ff)

fg)

fh)

fi)

fj)

fk)

eq)

eb)

ec)
ed)

BY=

ee)

ef)
eg)

01

eh)

ei)
ej)

11

ek)

el)
em)

czj)

01

czk)

en)

eo)
ep)

10

czg)
czh) The logic gates are
corresponding truth tables.
czi)

constructed and verified the

er

es)

et)

eu)

ev

czl)
czm)
czn)
czo)
czp)
czq)
czr)
czs)
czt)
czu)
czv)
czw)
czx)
czy)
czz)
daa)
dab)
dac)
dad)
dae)
daf)
dag)
dah)
dai)
daj)
dak)
dal)

TRANSISTOR LOAD LINE ANALYSIS

dam)
Result:

dan) Aim : to construct a D.C load line in a CE amplifier and verify the predicted
operating conditions of the amplifier and construct a maximum dissipation curve .
dao) Apparatus: transistor BC548, regulated power supply, miliammeter, voltmeter.

dap) Circuit diagram:

daq)
dar)
Theory : transistor amplifier must be operated over the linear portion
of their characteristic when it is necessary to reproduce the input signal without
distortion . Therefore it is necessary to choose the operating points and the associated
circuit components.
das)
dat)

The fig. shows characteristics curves for a transistor in CE mode .

These curves show the behaviour of the transistor over a range of IC and V

efor special values of base currents I . However there is a restriction, relating

dav)

dau)
C

daw) to maximum collector dissipation permissible. foreg. For 2N649 transistor

dax) P =100mWi.e V x IC =100mW. The transistor must be operated to the left
day) max
Ceof this
curve.
daz)
The performance of a transistor amplifier can be predicted graphically
by means of a load line, the load line may be drawn by joining two limiting points on I
-V characteristics. The limiting points are.
dba) C

CE

iii) V =0, I = V /R (saturation point)

dbb)
Ce
iv) I =0, V = V ( cut point)
dbc)
C

CC

Ce

CC

dbd)
dbe)
dbf) Procedure:
dbg)
The circuit connections are made as shown in the figure. A suitable value of
I (say10A) is selected . V varied in steps of 1V, form 0V and the

dbi)

dbh) C
Ce is
corresponding values of I are noted. Those values are tabulated. The

family of I - V

dbj)

curves are

C experiment is repeated for other values of I .a

dbk)

dbl)

dbx)
E

Ce

drawn.
dbm) Observation:Tabular column:
dbq) I =
dbt) I =

dbn) I =
dbo)

dbr)

dbp)

dbw)
V

dbz)
dcb)
I in
V
m
C
A dcc)
E

C
dby) dca)
In
v
o
l
t
s
dcl)

dcr)

dbs)

dcm)

dcd) dcf)
In
v
o
l
t
s
dcn)

dbu)
A

B
dbv)

dce)
dcg)
I in
V
m
C
A dch)
E
c

dco)

dci) dck)
In
v
o
l
t
s
dcp)

A
dcj)
I in
m
A
c

dcq)

dcs) Nature of graph:

dct)
dcu) Result:
dcv)
D.C load line in CE amplifier circuit is constructed and verified the predicted
operating condition of the amplifier.
dcw) Experiment No:_____

Date:__________

dcx)

dcy) Study of V-I & power curves of solar cells and find
maximum power point & efficiency.
dcz)
dda)