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06CS33 May - June 2010

This document contains the exam questions for the Third Semester B.E. Degree Examination in Logic Design. It is divided into two parts, with Part A covering topics like Boolean algebra, K-maps, and Quine-McCluskey method. Part B focuses on sequential circuits including shift registers, counters, finite state machines, and synchronous/asynchronous circuit design. It also includes questions on analog to digital and digital to analog conversion techniques. Students must answer 5 out of the 8 questions, selecting at least 2 from each part.

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Rafael Barrios
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40 views2 pages

06CS33 May - June 2010

This document contains the exam questions for the Third Semester B.E. Degree Examination in Logic Design. It is divided into two parts, with Part A covering topics like Boolean algebra, K-maps, and Quine-McCluskey method. Part B focuses on sequential circuits including shift registers, counters, finite state machines, and synchronous/asynchronous circuit design. It also includes questions on analog to digital and digital to analog conversion techniques. Students must answer 5 out of the 8 questions, selecting at least 2 from each part.

Uploaded by

Rafael Barrios
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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06CS33

USN

Third Semester B.E. Degree Examination,


Logic Design

May/June2010

Time: 3 hrs.

Max. Marks:lOO
Note: Answer any FlVEful1 questiQns, selecting
at least TWO questionsfrom each part.

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a. Define decoder, Draw logic diagram of3:8 decoder with enable input.
b. Implement the given Boolean function by using 8:1 multiplexer.
f(A, B, C, D) = L(O,1,j,~,7, 11,12,13,14)
c. With a neat diagram, explain the decimal to BCD encoder.
a,

(06 Marks)

(06Marks)
(08Marks)

What are the three different models for writing a module body in verilog HDL? Give
exampleforanyone model.
.
(06Marks)

b. With truth table and a neat logic diagram, explain full adder implementation.
c. Explain how IC 7483 can be.used as 4 bit adderlsubtractor.

-;;;.~
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.

PART-A
a. Simplify the given Boolean function by using K-map method and express it in SOP form.
Realise logic circuit by using NAND gates only.
(06Marks)
f(A,B,C,D)=L(m(7,
9, 10, 11, 12, 13, 14,15
b. Simplify following Boolean function by using K-map method in P~S form:
(06 Marks)
f(A, B, C, D) = :Lm(O, 1,2, 3,4,5,7)
c. Find prime implicants for the Boolean expression by using Quine McClusky method.
(08 Marks)
f(A, B, C, D) = L(l, 3, 6, 7, 8,9, 10,12, 14,15)+d(11, 13)

(06Marks)
(08Marks)

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PART-B
5 a. Explain any two types of shift register with waveforms. How Johnson counter is obtained
from shift register?
(10Marks)
b. Design Mod-6 synchronous counter by using J-K flip-flop. Give excitation table of J-K
flip-flop, state diagram and state transition table.
(10Marks)

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a. With transfer characteristic, explain how Schmitt trigger converts a random waveform into a
rectangular waveform.
(06 Marks)
b. Explain basic S.R flip-t1opby using NOR gate. What is the drawback of S-R t1ip-flop?How
J-K flip-flop is obtained from S-R flip-flop?
(08Marks)
c. Find out characteristic equations of J-K flip-flop and D flip-flop.
(06Marks)

a. Differentiate between Moore and Mealy model of synchronous sequential circuit. (04Marks)
b. Reduce the state transition diagram of Mealy model by row elimination method and
implication table method.
(16Marks)
State transition diagram.
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Fig. Q6 (b)
lof2

06CS33
7

a. Explain with neat diagram, R-2R ladder type 4 bit D to A converter. Find out analog output
if input is 1100 and '1'= +5 volts. For 10bit DAC if full scale output is 10.24 volts, what is
resolution?
(10Marks)
b. Explain with a neat diagram, successive approximation type DAC.
(10Marks)

a. With a neat circuit diagram, explain the operation of a two input TTL NAND gate with
tolem pole output.
(08Marks)
b. Explain with a neat diagram, CMOS inverter.
(06Marks)
c. Explain CMOS characteristics.
(06 Marks)

*****

20f2

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