IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO.

3, AUGUST 2015

213

Analysis of Temperature Distribution in Stacked IC

With On-Chip Sensing Device Arrays
Toshihiro Matsuda, Member, IEEE, Keita Yamada, Haruka Demachi, Hideyuki Iwata,
Tomoyuki Hatakeyama, Member, IEEE, Masaru Ishizuka, Member, IEEE,
and Takashi Ohzone

AbstractTemperature distributions in 3-D integrated circuits (ICs) are analyzed with a test structure, which has a top-tier
chip attached on a bottom dummy chip with adhesive layer. The
devices with four kinds of top-tier chip thickness tSi of 50410 m
were fabricated by a standard 0.18 m CMOS process. The test
structure consists of 24 sensor blocks, each of which has sensor p-n diodes, an on-chip heater resistor, and selector switches.
The temperature distributions of the top-tier test chip under
the constant and pulsed heater power were analyzed by both
measurements and thermal simulations. Temperature T, which
decreases with the distance L, is proportional to the reciprocal of L (1/L). Stacking effects on the temperature distributions
become clear for the device with thinner tSi , and tSi = 50 m
device has a different proportional constant for the region of
larger L. Thermal simulations with an entire chip model show
similar temperature distributions and the effects of bonding
pads. Thermal transient phenomena in stacked ICs were analyzed under the pulsed heating and compared with simulation
results. T rises abruptly after the heating pulse input and then
gradually increases, and the thermal simulation reproduces the
similar results. The test structure and the simulation modeling
can provide an effective way for analysis of thermal conduction
in stacked ICs.
Index TermsIntegrated circuit (IC) thermal factors, IC
design, IC measurements, temperature measurement, three
dimensional (3-D) ICs.

I. I NTRODUCTION
ITH advance of CMOS device and packaging technology, device density in LSI systems increases the
power consumption and the temperature in a chip greatly [1].
Not only the larger power raises the mean temperature of
the chip, but the temporal and spatial distribution of power
causes hot spots of the temperature. The temperature-related
effects have an impact on not only performance but reliability of LSI circuits such as electromigration, time dependent

Manuscript received October 10, 2014; accepted February 11, 2015. Date
of publication March 3, 2015; date of current version July 31, 2015. This work
was supported in part by the VLSI Design and Education Center, and in part by
the University of Tokyo in collaboration with Cadence Design Systems, Inc.,
Mentor Graphics, Inc., Rohm Corporation, and Toppan Printing Corporation.
T. Matsuda, K. Yamada, H. Demachi, and H. Iwata are with the
Department of Information Systems Engineering, Toyama Prefectural
University, Toyama 939-0398, Japan (e-mail: [email protected]).
T. Hatakeyama and M. Ishizuka are with the Department of Mechanical
Systems Engineering, Toyama Prefectural University, Toyama 939-0398, Japan.
T. Ohzone is with Dawn Enterprise, Nagoya 467-0808, Japan.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TSM.2015.2408434

dielectric breakdown (TDDB) and negative bias temperature

instability (NBTI). Consequently, analysis of hot spots and
temperature distributions in CMOS LSI become important
issue for advanced LSI design [2][7].
In addition, three dimensional (3D) IC technology is
a promising solution for emerging More than Moore products with higher performance and lower cost. Stacked structure
of multiple chips has higher integration density with smaller
foot print and flexibility in a combination of various ICs even
fabricated in different processes. The poor thermal conductivity of adhesive layers for chip stacking, however, causes
higher temperature and affects the temporal and spatial uniformity of temperature distribution in LSI chips. Therefore,
the thermal management is one of the major challenges for
3D integration technology [8][11]. A number of thermal simulation results for non-stacking single chip and stacked ICs
have been reported so far [12][16]. Actual temperature distributions of stacked ICs have scarcely been measured with
the spatial resolution of tens of micrometers. Though thermal
simulators are widely used as powerful LSI design tools, verification of simulation results with experimental measurements
is essential to accurate analysis.
We have proposed a test structure for analysis of temperature distribution in stacked ICs with on chip sensor arrays and
fundamental thermal properties of LSI chip are measured and
discussed [17][20]. In this paper, we will extend our thermal
simulation to the entire stacked ICs and transient phenomena and compare the results of experiments. The stacked IC
consists of a top tier chip, which has the test structure with
24 sensor blocks, and a 410 m thick bottom dummy chip.
Each sensor block has an on-chip heater, a temperature sensor array and selector switches. The test chips were fabricated
by a standard 0.18 m CMOS process and assembled into
ceramic 80 QFPs. Stacking effects on temperature distributions
and thermal transient phenomena with pulse heating were analyzed and compared with thermal simulation results. The test
structure can provide effective means for analysis of thermal
properties of 3D ICs packaged in various ways.
II. E XPERIMENTS
A. Test Structure
Fig. 1(a) shows a schematic of a sensing block for
the measurement and the definition of the distance L,
and (b) a photograph of a sensor block [17][20]. Each block,

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Fig. 1.
(a) Schematic of a sensing block for the measurement and the
definition of the distance L. (b) Photograph of a sensor block [17][20].

Fig. 3.
Cross sections of a (a) single chip, (b) stacked IC structure,
and (c) photograph of a device assembled into ceramic 80-pin QFP.

Fig. 2. Test structure chip floor plan, which has 24 blocks (four rows by
six columns) of 1.23 1.23 mm2 in size.

of which size is 260 x 60 m2 , has a resistor of about 500 

as an on-chip heater, 32 p-n diodes for temperature sensing
and sensor selector switches. The p type diffusion resistor
and the p type polysilicon resistor are used for the heaters.
Fig. 2 shows a chip floor plan of 24 blocks with 4 rows
by 6 columns arranged in the die area of 1.23 x 1.23 mm2 .
According to the addressing signals from X and Y decoders,
one of the sensor diodes in these blocks is selected. The
selected transmission gate switches connect force and sense
lines to one of the 32 sensor diodes. The Kelvin connection
scheme with the force and sense lines shorted at the anode
electrode of the diode are used for accurate I V measurements, and thus precise temperature extraction [17][20].
Fig. 3 shows a schematic cross sections of (a) a single chip,
(b) a stacked IC structure, and (c) a photograph of a device
assembled into ceramic 80 pin quad flat package (QFP) [19],

[20]. The stacked IC consists of a top tier chip, which has the
test structure with sensor arrays, and a 410 m thick bottom
dummy chip. The thickness of the top tier chips tSi are 50,
100, 200 m, which were thinned by polishing, and 410 m
without thinning. The top tier chips were glued on the bottom dummy chips by the die adhesive (Henkel QMI536). The
device of non-stacking single chip structure is also fabricated
as a reference. Both top tier chips and bottom dummy chips
were fabricated by a standard 0.18 m CMOS process.
B. Temperature Measurement Procedure
Since the sensor temperature T is proportional to the diode
voltage V D at the constant current of 10 A, T can be determined by the T VD curves obtained for every diode in
advance as described in [19]. The power of the heater resistor
was set to 50, 70, 90, and 110 mW with appropriate DC supply voltages for steady state analysis. A measurement set up
for the transient analysis under the pulsed heating is shown
in Fig. 4. A constant current source of 10 A was composed
of discrete components for high speed measurements [7]. The
rise and fall time of the input pulse was 5 s. The ambient
temperature T A of the devices were kept 293 K in a constant
temperature chamber, and the wait time for the measurements
was 20 min for the stable thermal environment.

MATSUDA et al.: ANALYSIS OF TEMPERATURE DISTRIBUTION IN STACKED IC

215

Fig. 6. Distance L dependences of the temperature T for the different tSi at

the dissipated power PR = 110 mW.

Fig. 4. Measurement setup for the transient analysis under the pulsed heating
conditions. The rise and fall time of the input pulse was 5 s.

Fig. 7. Distance L dependences of the temperature T for the different PR in

the device of tSi = 50 m.

Fig. 5. Time-dependent temperature changes of the sensor diode adjacent to

the heater for the top-tier chips with the different thicknesses tSi .

III. E XPERIMENTAL R ESULTS

A. Steady-State Analysis Under Constant Power Heating
Fig. 5 shows time dependent temperature changes of the
sensor diode adjacent to the heater for the top tier chips
with the different thicknesses tSi . The sensor temperature rises
rapidly just after the start of on-chip heating and becomes
saturated independently of tSi . Since the temperature change
becomes saturated after 200 300 s, the temperatures T for
the steady state was measured at 400 s. Fig. 6 shows a distance L dependences of T for the different tSi at the dissipated
power PR = 110 mW. T decreases with L rapidly, and saturates around 100 m. Although the devices of the single chip
and tSi = 200, 410 m give nearly the same characteristics,
the temperature of the thinner device (tSi = 50 and 100 m)
becomes higher. Fig. 7 shows L dependences of T for the different PR in the device of tSi = 50 m. The increase of T
becomes larger with PR , but the L dependences of T are similar regardless of PR . The top tier thickness tSi dependence of
T at the different L is shown in Fig. 8. The stacking effects
on the temperature distributions become clear for the devices
of tSi = 50 and 100 m, while the other thicker tSi and single
chip devices show almost the same temperature distributions.

Fig. 8. Top-tier thickness tSi dependence of the temperature T at the different

distance L.

Fig. 9 shows proportional relation between the reciprocal of L and the temperature T for (a) a diffusion resistor and (b) a polysilicon resistor as heaters, respectively.
Regardless of tSi , an empirical equation can be expressed as:
T = T0 + 1 (1/L),

(1)

where T 0 and 1 are the temperature at L = and a constant,

respectively. Note that the tSi = 50 m device has a different
proportional constant 2 for the region of larger L, for both
kinds of heaters. Larger value of 2 indicates a rapid decrease

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Fig. 10. T versus (1/L) for the tSi = 50 m device. T at larger L shows
similar characteristics regardless of PR .

Fig. 9.
T versus (1/L) for the various tSi with an empirical equation.
T = T0 + (1/L) for (a) diffusion resistor and (b) polysilicon resistor as
heaters, respectively.

of T for the distant region of the thinner devices. Fig. 10 also

shows (1/L) dependence of T at the different PR for the
tSi = 50 m device, which has two proportional constants
regardless of PR . Since 1 and 2 are also proportional to the
heater power PR as given in Fig. 11, T can be rewritten in the
form of
T = T0 + PR (1/L),

(2)

where is a constant of 1.28 (1.77) and 2.0 (2.0) (Km)/mW

for 1 and 2 , of the diffusion (polysilicon) resistor heaters,
respectively. Our test devices show nearly the same for 1
independently of tSi and single chip structure.
B. Transient Analysis Under Pulse Power Heating
For a high speed analysis of thermal transient phenomena in
stacked ICs, the voltage pulse was applied to the heater resistor
just once and V D changes of p-n diode sensors were measured
under the constant current condition of 10 A. Fig. 12 shows
a time dependent temperature change under the pulsed heating
of (a) the diffusion and (b) the polysilicon resistors in the time
range of -1 to 3 ms for the various tSi at L = 14.6 and 11.6 m,
respectively. T rises abruptly after the heating pulse input
within 10 s, which is the limit of time resolution in our
measurement set up, and then gradually increases. T of the
thinner devices (tSi = 50 and 100 m) becomes higher same

Fig. 11. Heater power PR dependence of proportional constant 1 and 2

for the diffusion (polysilicon) resistor heaters.

as the results of DC heating. Fig. 13 shows tSi dependences

of the maximum temperature T max during the pulsed heating
at the same sensor diode positions in Fig. 12. T max with the
polysilicon resistor becomes a little higher than the diffusion
resistor heating. A time dependent temperature change under
the pulsed heating of the diffusion resistor at the various L
is shown in Fig. 14. Although the amount of the first abrupt
change decreases with L, the slopes of the gradual increase
of T are nearly the same. The result of the pulsed heating
suggests that the thermal transient phenomena comprise fast
(less than 10 s) component and relatively slow processes.
C. Thermal Simulation Analysis
Temperature distributions and thermal properties of the
stacked ICs were simulated by Ansys Icepak ver. 14.0 [21] and
compared with measured results. Fig. 15 shows a simulation
model of the entire test structure chip of 2.5 x 2.5 mm2 , including a sensor block of 260 x 60 m2 . The bonded 80 metal
pads are put on the surface of the peripheral region of the
chip and their temperature is fixed to 293 K, because they are
connected to the lead frame and the package pins, which are
exposed to the chamber ambient. Fig. 16 shows a schematic
cross section of the simulation model. The top tier chip with
about 8.6 m thick interlayer and surface passivation oxide is
stacked on the bottom dummy chip. The junction depth of the
on chip p type diffusion heater is 0.15 m. For the thermal

MATSUDA et al.: ANALYSIS OF TEMPERATURE DISTRIBUTION IN STACKED IC

217

Fig. 14. Time-dependent temperature change under the pulsed heating of

the diffusion resistor at the various L.

Fig. 12.
Time-dependent temperature change under the pulsed heating
of (a) diffusion and (b) polysilicon resistors in the time range of 1 to 3 ms
for the various tSi at L = 14.6 and 11.6 m, respectively.

Fig. 15. Top view of a thermal simulation model of the entire test structure
chip of 2.5 2.5 mm2 .

Fig. 13. Top-tier thickness tSi dependences of the maximum temperature

T max during the pulsed heating at the same sensor diode positions in Fig. 12.

boundaries, the bottom of the adhesive layer under the dummy

chip is set at constant temperature of 293 K. At the rests of
the chip boundary, heat is removed by natural convective cooling of ambient air. For the flow boundary, no-slip condition
is applied to the chip surface. Radiation is not considered in
this simulation. The assumed constant thermal conductivities
of materials are indicated in Fig. 16 [22].
Fig. 17 shows temperature distributions of (a) tSi = 50
and (b) 410 m devices with 110 mW heating of p-diffusion
resistor, respectively. Although the entire regions of both top
tier chip and bottom dummy chip were modeled in the thermal
simulation, the sensor block was extracted from the simulated

Fig. 16.
Schematic cross section of the simulation model with thermal
conductivities.

regions and shown here. The simulated temperature distribution indicates that the adhesive layer prevents the heat transfer.
The cross section of the top tier chip shows that the temperature profile along the depth direction becomes uniform at the

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Fig. 19. T versus (1/L) for simulated and measured data of tSi = 410 and
50 m at PR 110 mW.

Fig. 17.
Simulated temperature distributions of (a) tSi = 50 m and
(b) tSi = 410 m devices with 110 mW heating, which is modeling the
entire chip regions.

Fig. 20. Comparison of measured and simulated transient analysis under the
pulsed heating (a) for the different tSi devices at the adjacent to the heater
and (b) at the different L for tSi = 50 m device, respectively.
Fig. 18.
Simulated temperature distributions of the entire chip surface
of (a) tSi = 410 m and (b) tSi = 50 m device, respectively. The color
scale of the temperature is the same as Fig. 17.

distance L gets large. Temperature distribution of the bottom

dummy chip is almost uniform regardless of tSi . Fig. 18 shows
temperature distributions of the entire chip surface of (a) tSi =
410 m and (b) tSi = 50 m devices simulated with the same
condition as Fig. 17, respectively. The higher temperature
region spreads out concentrically within about 100 m radius
from the heater for the tSi = 410 m device, and the temperature distribution becomes relatively uniform. Contrastingly,
the surface and the body of tSi = 50 m device has larger

temperature gradient, because the thinner thickness of the top

tier chip enhances the effects of the peripheral bonding pads.
Fig. 19 shows T versus (1/L) for simulated and measured
data of tSi = 410 and 50 m at PR 110 mW. T is proportional to 1/L in the simulation same as the measured
data except for the lower temperature of about 7 K. Although
tSi = 410 m device has a single proportional coefficient 1
only, tSi = 50 m device has two proportional constants of
1 and 2 as observed in the measurements. Proportional constants of 1 and 2 extracted from simulated and measured
results are considerably similar as summarized in Table I.
2 for the region of larger L (1/L = 1.6 x 102 1/m or less)

MATSUDA et al.: ANALYSIS OF TEMPERATURE DISTRIBUTION IN STACKED IC

TABLE I
P ROPORTIONAL C ONSTANTS OF 1 AND 2 IN THE P ROPOSED E MPIRICAL
E QUATION E XTRACTED F ROM S IMULATED AND M EASURED R ESULTS

of tSi = 50 m device corresponds to the effects of bonding

pads as shown in Fig. 18.
Fig. 20 shows a comparison of measured and simulated transient analysis under the pulsed heating (a) for the different tSi
devices at the adjacent to the heater, and (b) at the different
L for tSi = 50 m device, respectively. Since the simulation time range is from 0 to 2 ms, the falling edge of the
pulse is not simulated. Both results of simulations are very
similar to the measured data except for slightly lower temperature. Although the entire chip models can produce temperature
dependences similar to the measured results, detailed models
including a ceramic package and wiring layer will be needed
to improve our simulation accuracy.
IV. C ONCLUSION
The temperature distributions and transient phenomena in
stacked IC have been analyzed with the proposed test structure,
which has a top tier chip attached on a bottom dummy chip
with adhesive layer. The thermal simulation results with the
entire chip model are compared with the measured data and
discussed.
The test structure in the top tier chip consists of 24 blocks,
which has 32 temperature sensor devices and a p-type diffusion or polysilicon resistor heater each. The test chips were
fabricated by a standard 0.18 m CMOS process, and were
thinned to four kinds of thickness tSi of 50-410 m.
The sensor temperature T decreases with distance L rapidly,
and saturates around 100 m regardless of the heater
power PR . Although the devices of the single chip and
tSi = 200, 410 m give nearly the same temperature distribution as the single chip device, T of the thinner device
(tSi = 50 and 100 m) becomes higher. The temperature T is
proportional to the reciprocal of L regardless of tSi and PR .
The tSi = 50 m device has a different proportional constant
for the region of larger L, where T decreases more rapidly
than the thicker devices. These proportional constants are also
proportional to PR .
High speed thermal transient phenomena were analyzed
with the voltage pulses applied to the heaters. T rises abruptly
after the heating pulse input, and then gradually increases. It
suggests that the thermal transient phenomena comprise fast
(less than 10 s) component and relatively slow processes,
and requires the further analysis with higher time resolution.
Temperature distributions and thermal properties of the
stacked ICs were simulated by Ansys Icepak with a model
of the entire test structure chip including 80 bonding metal
pads on the surface. The simulated temperature distribution is

219

similar to the measured result except for the lower temperature of about 7 K. The cross section shows that the adhesive
layer prevents the heat transfer and the bottom dummy chip
has almost uniform temperature distribution regardless of tSi .
Although the higher temperature region spreads out concentrically near the heater for the tSi = 410 m device, tSi = 50 m
device has larger temperature gradient due to the effects of
the peripheral bonding pads. T is proportional to 1/L in the
simulation, and tSi = 50 m device has two proportional constants of 1 and 2 as observed in the measurements. The
results of transient simulations are very similar to the measured data except for slightly lower temperature. An improved
models including a ceramic package and wiring layer will be
needed for the more accurate simulation.

ACKNOWLEDGMENT
The authors would like to thank Prof. M. Pfost of Reutlingen
University for his valuable advice about high-speed current
source circuits.

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Toshihiro Matsuda (M99) received the B.E. degree

from Kyoto University, the M.S. degree in electrical engineering from the University of Michigan,
and the Ph.D. degree from Toyama Prefectural
University, in 1978, 1985, and 1999, respectively.
From 1978 to 1990, he was involved in CMOS and
Bi-CMOS LSI design at Hitachi Ltd. He is currently
a Professor with Toyama Prefectural University. His
research interests include CMOS device technology, light emitting devices, and very large-scale
integration design.

Keita Yamada was born in Fukui, Japan, in 1991.

He received the B.E. degree in electrical information
engineering from Toyama Prefectural University,
Toyama, Japan, in 2014, where he is currently
pursuing the M.S. degree in electrical information
engineering. His current research interests include
optical communication technology.

Haruka Demachi was born in Toyama, Japan,

in 1992. She received the B.E. degree in electrical
information engineering from Toyama Prefectural
University, Toyama, in 2015, where he is currently
pursuing the M.S. degree in electrical information
engineering. Her current research interests include
analysis of temperature distribution in 3-D ICs.

Hideyuki Iwata received the B.S. and M.S.

degrees in mathematics from Keio University, Japan,
and the Dr.Eng. degree in electronic engineering from Nagoya University, Japan. He joined the
Semiconductor Research Center, Matsushita Electric
Company Ltd., Osaka, where he was engaged in
the development of dynamic random access memorys and the numerical modeling and simulation of
MOS devices. He later joined Toyama Prefectural
University, Toyama, Japan, where he is currently
an Associate Professor. His current research interests include physics, modeling and simulation of advanced MOSFETs, and
quantum effect devices.

Tomoyuki Hatakeyama (M11) received the B.E.,

M.E., and Ph.D. degrees from the Tokyo Institute
of Technology, Japan, in 2003, 2005, and 2008,
respectively. He is an Assistant Professor with the
Department of Mechanical Systems Engineering,
Toyama Prefectural University, Japan. His research
interests are cooling technology of electrical equipment, thermal design of electronics, and micro-scale
heat transfer phenomena.

Masaru Ishizuka (M02) received the B.S., M.S.,

and Ph.D. degrees from the University of Tokyo,
Japan, in 1975, 1977, and 1981, respectively. From
1981 to 2000, he worked at Toshiba Corporation,
Kawasaki, Japan, where he has been involved
in the research and development of the cooling technology of electronic equipment. From
2000 to 2003, he was an Associate Professor and
from 2003 to 2013, he was a Professor at the
Department of Mechanical Systems Engineering,
Toyama Prefectural University, Japan. He is currently the President of Toyama Prefectural University. He is a fellow
of American Society of Mechanical Engineers and the Japan Society of
Mechanical Engineers.

Takashi Ohzone received the B.S. and M.S. degrees

in electrical engineering from Nagoya University,
Japan, in 1966 and 1968, respectively, and
the Ph.D. degree in engineering science from
Osaka University, Japan, in 1981. In 1968,
he joined the Semiconductor Research Center,
Matsushita Electric Industrial Company, Ltd., Japan,
where he had been working on the research and
development of MOS integrated circuits, chargecoupled devices, static RAMs, and dynamic RAMs.
In 1990, he joined the Department of Electronics and
Informatics, Toyama Prefectural University, as a Professor. He moved to the
Department of Communication Engineering, Okayama Prefectural University,
in 2002. Since 2007, he has been at Dawn Enterprise Company, Ltd., Japan.
His current research interests are MOS devices, light emitting devices, and
superconductor materials.