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Notes 326 Set12 PDF

This document discusses timing considerations for synchronous sequential circuits. It defines key timing parameters such as maximum clock frequency, maximum allowable clock skew, and global setup and hold times. It explains how these parameters are derived from the timing of flip-flops and gates. The document discusses why gating the clock signal to control register loading is a poor design practice, as it can cause unintended triggering of flip-flops. Finally, it describes better ways to add load control signals to registers.

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Eswaran Samy
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98 views17 pages

Notes 326 Set12 PDF

This document discusses timing considerations for synchronous sequential circuits. It defines key timing parameters such as maximum clock frequency, maximum allowable clock skew, and global setup and hold times. It explains how these parameters are derived from the timing of flip-flops and gates. The document discusses why gating the clock signal to control register loading is a poor design practice, as it can cause unintended triggering of flip-flops. Finally, it describes better ways to add load control signals to registers.

Uploaded by

Eswaran Samy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 17

Sequential Circuit Timing

Objectives
This section covers several timing considerations encountered
in the design of synchronous sequential circuits. It has the
following objectives:
Define the following global timing parameters and show
how they can be derived from the basic timing parameters
of flip-flops and gates.
Maximum Clock Frequency
Maximum allowable clock skew
Global Setup and Hold Times
Discuss

ways to control the loading of data into registers


and show why gating the clock signal to do this is a poor
design practice.

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Sequential Circuit Timing

Reading Assignment

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Sections 3.5 and 3.6. Please also see .ppt slides


posted on the web - the animation helps a lot!

Sequential Circuit Timing

13.1. Maximum Clock Frequency


The clock frequency for a synchronous sequential
circuit is limited by the timing parameters of its flipflops and gates. This limit is called the maximum
clock frequency for the circuit. The minimum clock
period is the reciprocal of this frequency.
Relevant timing parameters

Gates:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL

Flip-Flops:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
Setup time: tsu
Hold time: th

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Sequential Circuit Timing

Example
D Q

CK

TW max tPFF + tsu

For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns
TW max (max tPLH + tsu, max tPHL + tsu)
TW max (25+20, 40+20) = 60

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Sequential Circuit Timing

Example
Q

D Q

CK

TW max tPFF + max tPINV + tsu

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Sequential Circuit Timing

Example
D Q

Q0

MUX

D Q

Q1

1
Q

CK

TW max tPFF + max tPMUX + tsu

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Sequential Circuit Timing

Example

Paths from Q1 to Q1: None


Paths from Q1 to Q2: TW max tPDFF +tJKsu = 20 +10 = 30 ns
TW max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns
Paths from Q2 to Q1: TW max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns
Paths from Q2 to Q2: TW max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns

TW 47 ns
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Sequential Circuit Timing

Clock Skew

If a clock edge does not arrive at different flip-flops at


exactly the same time, then the clock is said to be skewed
between these flip-flops. The difference between the times
of arrival at the flip-flops is said to be the amount of clock
skew.
Clock skew is due to different delays on different paths
from the clock generator to the various flip-flops.
Different length wires (wires have delay)
Gates (buffers) on the paths
Flip-Flops that clock on different edges (need to invert clock for

some flip-flops)

Gating the clock to control loading of registers (a very bad idea)

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Sequential Circuit Timing

Example (Effect of clock skew on clock rate)

Clock C2 skewed after C1


D Q

C1

D2

Q1

D Q

C2

Q2

CK

TW max TPFF + max tOR + tsu


(if clock not skewed, i.e., tINV = 0)

TW max TPFF + max tOR + tsu - min tINV


(if clock skewed, i.e., tINV > 0)

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Sequential Circuit Timing

Clock C1 skewed after C2


D Q

C1

Q1

D2
C2

D Q

Q2

CK

TW max TPFF + max tOR + tsu


(if clock not skewed, i.e., tINV = 0)
TW max TPFF + max tOR + tsu + max tINV
(if clock skewed, i.e., tINV > 0)

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Sequential Circuit Timing

Summary of maximum clock frequency calculations


D Q

Q1

D2
Logic
Network

C1

D Q

C2

TW

TW

C1

C1

tSK = tINV

tSK = tINV

C2

C2

Q1

Q1

D2

D2
tPFF

tOR

tPFF

tsu

tOR
tsu

C2 skewed after C1: TW max TPFF + max tNET + tsu - min tINV
C2 skewed before C1: TW max TPFF + max tNET + tsu + max tINV
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Sequential Circuit Timing

Example

tXY = Network delay from X to Y


tXD = Network delay from X to D
tQY = Network delay from Q to Y
tQD = Network delay from Q to D

For each of the following two connections find


The minimum clock period
The maximum and minimum delay from CLK to YOUT

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Sequential Circuit Timing

Circuit 1:
n2

tXY = Network delay from X to Y


tXD = Network delay from X to D
tQY = Network delay from Q to Y
tQD = Network delay from Q to D

Minimum Clock Period:


Tw max tPFF + max tQY + (n-2) max tXY +max tXD + tsu

TW

Tw max tPFF + max tQD + tsu


Maximum Delay:
TCY max tPFF + max tQY + (n-1) max tXY
Minimum Delay:
TCY min tPFF + min tQY
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Sequential Circuit Timing

Circuit 2:
n2

tXY = Network delay from X to Y


tXD = Network delay from X to D
tQY = Network delay from Q to Y
tQD = Network delay from Q to D

Minimum Clock Period:


Tw max tPFF + max tXD + tsu
Tw max tPFF + max tQD + tsu
Maximum Delay:
TCY max tPFF + max (max tXY, max tQY)
Minimum Delay:
TCY min tPFF + min (min tXY, min tQY)
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Sequential Circuit Timing

2. Maximum Allowable Clock Skew


How much skew between C1 and C2 can be tolerated
in the following circuit?
D Q

Q1

D2

D Q

C1

C2

Case 1: C2 delayed after C1


tPFF > th + tSK
tSK < min tPFF - th

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Sequential Circuit Timing

Case 2: C1 delayed from C2


D Q

Q1

D2

C1

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D Q

C2

16

Sequential Circuit Timing

How does additional delay between the flip-flops


affect the skew calculations?

tSK min tPFF - th


tsk min tPFF + min tMUX - th

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Sequential Circuit Timing

Summary of allowable clock skew calculations

tSK + th tPFF + tNET


tSK min tPFF + min tNET - th
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Sequential Circuit Timing

Example: What is the minimum clock period for the


following circuit under the assumption that the clock
C2 is skewed after C1 (i.e., C2 is delayed from C1)?
N2
D1
D Q

Q1

D2

N1

D Q

Q2

C1

C2

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Sequential Circuit Timing

N2
D1
D Q

Q1

D2

N1

Q2

C1

D Q

C2

First calculate the maximum allowable clock skew.


tSK < min tPFF + min tN1 - th
Next calculate the minimum clock period due to the path
from Q1 to D2.
TW > max tPFF + max tN1 + tsu - min tSK
Finally calculate the minimum clock period due to the path
from Q2 to D1
TW > max tPFF + max tN2 + tsu + max tSK
TW > max tPFF + max tN2 + tsu + (min tPFF + min tN1 - th)
TW > max tPFF + min tPFF + max tN2 + min tN1 + tsu - th

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Sequential Circuit Timing

10

3. Global Setup Time, Hold Time and


Propagation Delay
Global setup and hold times (data delayed)
X

NET

D Q

CK

CLK

TSU = tsu + max tNET


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TH = th - min tNET

21

Sequential Circuit Timing

Global setup & hold time (clock delayed)


D

D Q

CK

CLK

TSU = tsu - min tC

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TH = th + max tC
22

Sequential Circuit Timing

11

Global setup & hold time (data & clock delayed)


X

NET

D Q

CK

CLK

TSU = tsu + max tNET - min tC


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TH = th - min tNET + max tC


23

Sequential Circuit Timing

Global propagation delay


D Q

CLK

CK

Q
NET

TP = tC + tFF + tNET
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Sequential Circuit Timing

12

Summary of global timing parameters

TSU = tsu + max tPN - min tPC tsu + max tPN


TH = th + max tPC - min tPN th + max tPC
TP = tPFF + tPN + tPC
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Sequential Circuit Timing

Example
LD

D Q

D
CLK

CK

Find TSU and TH for input signal LD relative to CLK.


TSU = tsu +max tNET - min tC
= tsu + max tINV + max tNAND + max tNAND - min tINV
TH = th - min tNET + max tC
= th - min tNAND - min tNAND + max TINV

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Sequential Circuit Timing

13

4. Register load control (gating the clock)


A very bad way to add a load control signal LD to a
register that does not have one is shown below
D Q

D
LD

CK

CLK

The reason this is such a bad idea is illustrated by the


following timing diagram.

The flip-flop sees two rising edges and will trigger


twice. The only one we want is the second one.
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Sequential Circuit Timing

If LD was constrained to only change when the clock was low,


then the only problem would be the clock skew.

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Sequential Circuit Timing

14

If gating the clock is the only way to control the


loading of registers, then use the following approach:
D

D Q

CLK

LD

There is still clock skew, but at least we only have one


triggering edge.

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Sequential Circuit Timing

The best way to add a LD control signal is as follows:


LD

D Q

D
CLK

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Sequential Circuit Timing

15

5. Synchronous System Structure and Timing

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Sequential Circuit Timing

6. Review
How the flip-flop and gate timing parameters affect
the maximum possible clock frequency.

How clock skew affect maximum possible clock frequency.

How the delay of logic between flip-flops affects the


maximum allowable clock skew.
How flip-flop setup and hold times are translated by
the combinational logic delays to get global setup and
hold times.
The detrimental effect of gating the clock signal.

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Sequential Circuit Timing

16

Extra Timing Problems


The following logic diagram shows the implementation of the ith bit slice of
a register. Derive the global setup and hold times TSU and TH for CLR and
the maximum and minimum propagation delays max TP and min TP from
CLK to the flip-flop outputs. Use the following timing parameters.
JK Flip-Flop:
5ns tPFF 15ns tsu = 12ns th = 6ns
NAND Gate:
3ns tPNAND 10ns
Inverter:
2ns tPINV 8ns
A[i]
CLR

B[i]
CLKEN
CLK

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Sequential Circuit Timing

Determine the minimal clock period TW for the following circuit. Use the
following delay values for the flip-flops and gates.
Flip-Flop:
5 tPFF 14ns; tsu = 6ns; th = 10ns
Inverter:
2 tPINV 12
XOR Gate:
7 tXOR 22

D Q

Q0

D Q

Q1

D Q

Q2

D Q

Q3

CLK

Part a) Work the problem under the assumption that the clock is
symmetrical. That is, it is high for 50% of the clock period and low for
50% of the clock period.
Part b) Work the problem under the assumption that the clock is high
for 20% of the clock period and low for 80% of the clock period.
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Sequential Circuit Timing

17

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