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The document describes the initialization of a design including setting ground and power nets, loading LEF files for blocks and macros, and loading a Verilog netlist. It issues warnings that some pins in the 'mult_32_pg3' macro are missing antenna area values in the library, so antenna rules cannot be fully checked.

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Æshok IncreĐible King

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0% found this document useful (0 votes)

268 views

Log File

Uploaded by

Æshok IncreĐible King

Available Formats

Download as DOCX, PDF, TXT or read online on Scribd

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04/04 16:42:34 386s] <CMD> set init_gnd_net gnd

[04/04 16:42:34 386s] <CMD> set init_lef_file {../../LEF/gsclib045.lef

../sub_block/mult_32.lef ../sub_block/mult_32_pg1.lef
../sub_block/mult_32_pg2.lef suraj/rectilinear_block.lef}
[04/04 16:42:34 386s] <CMD> set init_mmmc_file gopi/mmmc.view
[04/04 16:42:34 386s] <CMD> set init_pwr_net vdd
[04/04 16:42:34 386s] <CMD> set init_verilog
../../NETLIST/tdsp_core_top_changed.v
[04/04 16:42:34 386s] <CMD> set lsgOCPGainMult 1.000000
[04/04 16:42:34 386s] <CMD> set pegDefaultResScaleFactor 1.000000
[04/04 16:42:34 386s] <CMD> set pegDetailResScaleFactor 1.000000
[04/04 16:42:34 386s] <CMD> set timing_library_float_precision_tol 0.000010
[04/04 16:42:34 386s] <CMD> set timing_library_load_pin_cap_indices {}
[04/04 16:42:34 386s] <CMD> set
timing_library_mark_cell_latch_construct_flag 0
[04/04 16:42:34 386s] <CMD> set so_post_client_restore_command
{update_timing ; write_eco_opt_db ;}
[04/04 16:42:36 387s] <CMD> init_design
[04/04 16:42:36 387s] **ERROR: (TCLCMD-994): Cannot find 'analysis view'
object with the name 'Arise_analysis_view_test_max_cmax_T140V102'. This can
happen when the specified name of any MMMC object is incorrectly spelled or
has been removed from the running session.
[04/04 16:42:36 387s]
[04/04 16:42:36 387s] Loading LEF file. /../LEF/gsclib045.lef...
[04/04 16:42:36 387s] Set DBUPerIGU to M2 pitch 200.
[04/04 16:42:36 387s]
[04/04 16:42:36 387s] Loading LEF file ../sub_block/mult_32.lef ...
[04/04 16:42:36 387s]
[04/04 16:42:36 387s] Loading LEF file ../sub_block/mult_32_pg1.lef ...
[04/04 16:42:36 387s]
[04/04 16:42:36 387s] Loading LEF file ../sub_block/mult_32_pg2.lef ...

[04/04 16:42:36 387s]

[04/04 16:42:36 387s] Loading LEF file suraj/rectilinear_block.lef ...
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'ovm' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[15]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[14]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[13]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[12]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[11]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[10]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[9]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.

[04/04 16:42:36 387s] **WARN: (ENCLF-200):

Pin 'op_a[8]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[7]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[6]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[5]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[4]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[3]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[2]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[1]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_a[0]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.

[04/04 16:42:36 387s] **WARN: (ENCLF-200):

Pin 'op_b[15]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_b[14]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-200):
Pin 'op_b[13]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-200' for more detail.
[04/04 16:42:36 387s] **WARN: (EMS-63): Message <ENCLF-200> has
exceeded the default message display limit of 20.
[04/04 16:42:36 387s] To avoid this warning, increase the display limit per
unique message by
[04/04 16:42:36 387s] using the set_message -limit <number> command.
[04/04 16:42:36 387s] The message limit can be removed by using the
set_message -no_limit command.
[04/04 16:42:36 387s] Note that setting a very large number using the
set_message -limit command
[04/04 16:42:36 387s] or removing the message limit using the set_message
-no_limit command can
[04/04 16:42:36 387s] significantly increase the log file size.
[04/04 16:42:36 387s] To suppress a message, use the set_message -suppress
command.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[31]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[30]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.

[04/04 16:42:36 387s] **WARN: (ENCLF-201):

Pin 'result[29]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[28]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[27]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[26]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[25]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[24]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[23]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[22]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[21]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.

[04/04 16:42:36 387s] **WARN: (ENCLF-201):

Pin 'result[20]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[19]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[18]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[17]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[16]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[15]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[14]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[13]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.
[04/04 16:42:36 387s] **WARN: (ENCLF-201):
Pin 'result[12]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 16:42:36 387s] Type 'man ENCLF-201' for more detail.

[04/04 16:42:36 387s] **WARN: (EMS-63): Message <ENCLF-201> has

exceeded the default message display limit of 20.
[04/04 16:42:36 387s] To avoid this warning, increase the display limit per
unique message by
[04/04 16:42:36 387s] using the set_message -limit <number> command.
[04/04 16:42:36 387s] The message limit can be removed by using the
set_message -no_limit command.
[04/04 16:42:36 387s] Note that setting a very large number using the
set_message -limit command
[04/04 16:42:36 387s] or removing the message limit using the set_message
-no_limit command can
[04/04 16:42:36 387s] significantly increase the log file size.
[04/04 16:42:36 387s] To suppress a message, use the set_message -suppress
command.
[04/04 16:42:36 387s]
[04/04 16:42:36 387s] viaInitial starts at Mon Apr 4 16:42:36 2016
viaInitial ends at Mon Apr 4 16:42:36 2016
*** Begin netlist parsing (mem=916.1M) ***
[04/04 16:42:36 387s] Reading netlist ...
[04/04 16:42:36 387s] Backslashed names will retain backslash and a trailing
blank character.
[04/04 16:42:36 387s] Reading verilog netlist
'../../NETLIST/tdsp_core_top_changed.v'
[04/04 16:42:36 387s]
[04/04 16:42:36 387s] *** Memory Usage v#1 (Current mem = 916.109M,
initial mem = 98.977M) ***
[04/04 16:42:36 387s] *** End netlist parsing (cpu=0:00:00.1, real=0:00:00.0,
mem=916.1M) ***
[04/04 16:42:36 387s] Top level cell is tdsp_core.
[04/04 16:42:36 387s] Loading view definition files from gopi/mmmc.view
[04/04 16:42:36 387s] Reading Arise_max_library_T150V08_set timing library
'/Projects/Training/user5/work/suraj/LIB/slow_T150_08V.lib...
[04/04 16:42:37 388s] Read 477 cells in library 'gpdk045bc'

[04/04 16:42:37 388s] Reading Arise_min_library_T0V132_set timing library

'/Projects/Training/user5/work/suraj/LIB/fast_T0_132V.lib' ...
[04/04 16:42:38 388s] Read 477 cells in library 'gpdk045wc'
[04/04 16:42:38 388s] *** End library_loading (cpu=0.00min, mem=0.0M,
fe_cpu=6.46min, fe_real=44.43min, fe_mem=918.1M) ***
[04/04 16:42:38 388s] Starting recursive module instantiation check.
[04/04 16:42:38 388s] No recursion found.
[04/04 16:42:38 388s] Building hierarchical netlist for Cell tdsp_core ...
[04/04 16:42:38 388s] *** Netlist is unique.
[04/04 16:42:38 388s] ** info: there are 1523 modules.
[04/04 16:42:38 388s] ** info: there are 2213 stdCell insts.
[04/04 16:42:38 388s] ** info: there are 4 macros.
[04/04 16:42:38 388s]
[04/04 16:42:38 388s] *** Memory Usage v#1 (Current mem = 918.133M,
initial mem = 98.977M) ***
[04/04 16:42:38 388s] *info: set bottom ioPad orient R0
[04/04 16:42:38 388s] Horizontal Layer M1 offset = 95 (derived)
[04/04 16:42:38 388s] Vertical Layer M2 offset = 100 (derived)
[04/04 16:42:38 388s] Generated pitch 0.2 in Metal9 is different from 0.33
defined in technology file in unpreferred direction.
[04/04 16:42:38 388s] Generated pitch 0.38 in Metal9 is different from 0.33
defined in technology file in preferred direction.
[04/04 16:42:38 388s] Generated pitch 0.285 in Metal8 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 16:42:38 388s] Generated pitch 0.285 in Metal7 is different from 0.2
defined in technology file in preferred direction.
[04/04 16:42:38 388s] Generated pitch 0.19 in Metal6 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 16:42:38 388s] Generated pitch 0.19 in Metal5 is different from 0.2
defined in technology file in preferred direction.
[04/04 16:42:38 388s] Generated pitch 0.19 in Metal4 is different from 0.2
defined in technology file in unpreferred direction.

[04/04 16:42:38 388s] Generated pitch 0.19 in Metal3 is different from 0.2
defined in technology file in preferred direction.
[04/04 16:42:38 388s] Generated pitch 0.19 in Metal2 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 16:42:38 388s] Generated pitch 0.2 in Metal1 is different from 0.19
defined in technology file in unpreferred direction.
[04/04 16:42:38 388s] Set Default Net Delay as 1000 ps.
[04/04 16:42:38 388s] Set Default Net Load as 0.5 pF.
[04/04 16:42:38 388s] Set Input Pin Transition Delay as 0.1 ps.
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_T0V132 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_T0V132 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_Tm20V15 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_Tm20V15 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_Tm40V18 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_Tm40V18 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T25V12 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T25V12 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T50V13 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T50V13 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T15V11 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T15V11 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_T0V132 not found, use default_view_setup

[04/04 16:42:38 389s] **WARN: analysis view

Arise_analysis_view_test_min_cmax_T0V132 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_Tm20V15 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_Tm40V15 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_min_cmax_Tm40V15 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_min_cmax_Tm20V15 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T25V12 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T25V12 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T20V13 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T20V13 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T15V11 not found, use default_view_setup
[04/04 16:42:38 389s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T15V11 not found, use default_view_setup
[04/04 16:42:38 389s] Initializing multi-corner RC extraction with 2 active RC
Corners ...
[04/04 16:42:38 389s] **WARN: (ENCEXT-6202): In addition to the technology
file, capacitance table file is specified for all RC corners. If the technology file for
all RC corners is already specified, the capacitance table file is not required for
preRoute and postRoute extraction. In a new session, the capacitance table files
can be removed from the create_rc_corner command. In this case, the
technology file will be used for preRoute extraction and effort level
medium/high/signoff of postRoute extraction.
[04/04 16:42:38 389s] Type 'man ENCEXT-6202' for more detail.
[04/04 16:42:38 389s] Reading Capacitance Table File
../../DATA/captable_cmax ...
[04/04 16:42:38 389s] Cap table was created using Encounter 09.10-p004_1.
[04/04 16:42:38 389s] Process name: GPDK45.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2760): Layer M10 specified in the

cap table is ignored because it is greater than the maximum number of layers, 9,
specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2760): Layer M11 specified in the
cap table is ignored because it is greater than the maximum number of layers, 9,
specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M1 and M2 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M2 and M3 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M3 and M4 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M4 and M5 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between

layers M6 and M7 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M7 and M8 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M8 and M9 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2710): Basic Cap table for layer M10
is ignored because the layer is not specified in the technology LEF file.
[04/04 16:42:38 389s] Reading Capacitance Table File
../../DATA/captable_cmin ...
[04/04 16:42:38 389s] Cap table was created using Encounter 09.10-p004_1.
[04/04 16:42:38 389s] Process name: GPDK45.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2760): Layer M10 specified in the
cap table is ignored because it is greater than the maximum number of layers, 9,
specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2760): Layer M11 specified in the
cap table is ignored because it is greater than the maximum number of layers, 9,
specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M1 and M2 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M2 and M3 is not defined in the capacitance table file. The via resistance

of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M5 and M6 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M6 and M7 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M7 and M8 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.
[04/04 16:42:38 389s] **WARN: (ENCEXT-2776): The via resistance between
layers M8 and M9 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 16:42:38 389s] Type 'man ENCEXT-2776' for more detail.

[04/04 16:42:38 389s] **WARN: (ENCEXT-2710): Basic Cap table for layer M10
is ignored because the layer is not specified in the technology LEF file.
[04/04 16:42:38 389s] Importing multi-corner RC tables ...
[04/04 16:42:38 389s] Summary of Active RC-Corners :
[04/04 16:42:38 389s]
[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_max_cmax_T150V08
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_max_cmax_T140V102
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_max_cmax_T125V108
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_max_cmax_T125V108
[04/04 16:42:38 389s]

RC-Corner Name

[04/04 16:42:38 389s]

RC-Corner Index

: Arise_rc_corner_cmax
:0

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_max_cmin_T150V08
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_max_cmin_T150V08
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_max_cmin_T140V102
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_max_cmin_T140V102
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_max_cmin_T125V108
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_max_cmin_T125V108
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_min_cmin_T0V132
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_min_cmin_T0V132
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmin

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 25 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmin'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_min_cmax_T0V132
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_min_cmax_T0V132
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s]

[04/04 16:42:38 389s] Analysis View:
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 16:42:38 389s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 16:42:38 389s]

RC-Corner Index

[04/04 16:42:38 389s]

RC-Corner Temperature : 125 Celsius

[04/04 16:42:38 389s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 16:42:38 389s]

RC-Corner PreRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Res Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute Cap Factor

[04/04 16:42:38 389s]

RC-Corner PostRoute XCap Factor

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 16:42:38 389s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 16:42:38 389s] Technology file '../../DATA/qrcTechFile' associated with

[04/04 16:42:41 391s] Read 477 cells in library 'typical'

[04/04 16:42:41 391s] Reading Arise_nom_library_T50V13_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T50_13V.lib' ...
[04/04 16:42:41 392s] Read 477 cells in library 'typical'
[04/04 16:42:41 392s] Reading Arise_nom_library_T15V11_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T15_11V.lib' ...
[04/04 16:42:42 393s] Read 477 cells in library 'typical'
[04/04 16:42:42 393s] Reading Arise_min_library_Tm20V15_set timing library
'/Projects/Training/user5/work/suraj/LIB/fast_Tm20_15V.lib' ...
[04/04 16:42:43 393s] Read 477 cells in library 'gpdk045wc'
[04/04 16:42:43 393s] Reading Arise_min_library_Tm40V18_set timing library
'/Projects/Training/user5/work/suraj/LIB/fast_Tm40_18V.lib' ...
[04/04 16:42:43 394s] Read 477 cells in library 'gpdk045wc'
[04/04 16:42:44 394s] CTE reading timing constraint file '../../SDC/test.sdc' ...
[04/04 16:42:44 394s] Current (total cpu=0:06:34, real=0:44:32, peak
res=1143.3M, current mem=1023.2M)
[04/04 16:42:44 394s] **WARN: (TCLNL-330):
set_input_delay on clock root
'clk' is not supported. You should use the -source option to set_clock_latency to
provide this offset. You can also use the global
timing_allow_input_delay_on_clock_source to allow set_input_delay assertion to
have an effect on clock source paths beginning at this clock root. (File
../../SDC/test.sdc, Line 188).
[04/04 16:42:44 394s]
[04/04 16:42:44 394s] Number of path exceptions in the constraint file = 47
[04/04 16:42:44 394s] Number of paths exceptions after getting compressed =
5
[04/04 16:42:44 394s] INFO (CTE): read_dc_script finished with 1 WARNING.
[04/04 16:42:44 394s] Ending "Constraint file reading stats" (total
cpu=0:00:00.1, real=0:00:00.0, peak res=726.2M, current mem=1033.2M)
[04/04 16:42:44 394s] Current (total cpu=0:06:34, real=0:44:32, peak
res=1143.3M, current mem=1033.2M)
[04/04 16:42:44 394s] CTE reading timing constraint file '../../SDC/func.sdc' ...
[04/04 16:42:44 394s] Current (total cpu=0:06:34, real=0:44:32, peak
res=1143.3M, current mem=1033.2M)

[04/04 16:42:44 394s] **WARN: (TCLNL-330):

set_input_delay on clock root
'clk' is not supported. You should use the -source option to set_clock_latency to
provide this offset. You can also use the global
timing_allow_input_delay_on_clock_source to allow set_input_delay assertion to
have an effect on clock source paths beginning at this clock root. (File
../../SDC/func.sdc, Line 188).
[04/04 16:42:44 394s]
[04/04 16:42:44 394s] Number of path exceptions in the constraint file = 47
[04/04 16:42:44 394s] Number of paths exceptions after getting compressed =
5
[04/04 16:42:44 395s] INFO (CTE): read_dc_script finished with 1 WARNING.
[04/04 16:42:44 395s] Ending "Constraint file reading stats" (total
cpu=0:00:00.1, real=0:00:00.0, peak res=726.5M, current mem=1033.2M)
[04/04 16:42:44 395s] Current (total cpu=0:06:34, real=0:44:32, peak
res=1143.3M, current mem=1033.2M)
[04/04 16:42:44 395s] Total number of combinational cells: 317
[04/04 16:42:44 395s] Total number of sequential cells: 150
[04/04 16:42:44 395s] Total number of tristate cells: 10
[04/04 16:42:44 395s] Total number of level shifter cells: 0
[04/04 16:42:44 395s] Total number of power gating cells: 0
[04/04 16:42:44 395s] Total number of isolation cells: 0
[04/04 16:42:44 395s] Total number of power switch cells: 0
[04/04 16:42:44 395s] Total number of pulse generator cells: 0
[04/04 16:42:44 395s] Total number of always on buffers: 0
[04/04 16:42:44 395s] Total number of retention cells: 0
[04/04 16:42:44 395s] List of usable buffers: BUFX2 BUFX12 BUFX16 BUFX20
CLKBUFX2 BUFX3 BUFX4 CLKBUFX12 CLKBUFX16 CLKBUFX20 CLKBUFX4
CLKBUFX6 CLKBUFX8 BUFX8 CLKBUFX3 BUFX6
[04/04 16:42:44 395s] Total number of usable buffers: 16
[04/04 16:42:44 395s] List of unusable buffers:
[04/04 16:42:44 395s] Total number of unusable buffers: 0

[04/04 16:42:44 395s] List of usable inverters: CLKINVX1 CLKINVX2 CLKINVX12

CLKINVX16 CLKINVX20 INVX1 CLKINVX3 CLKINVX4 CLKINVX6 INVX12 INVX2
INVX3 CLKINVX8 INVX20 INVX4 INVX6 INVX16 INVXL INVX8
[04/04 16:42:44 395s] Total number of usable inverters: 19
[04/04 16:42:44 395s] List of unusable inverters:
[04/04 16:42:44 395s] Total number of unusable inverters: 0
[04/04 16:42:44 395s] List of identified usable delay cells: DLY1X4 DLY2X4
DLY3X4 DLY1X1 DLY4X1 DLY2X1 DLY3X1 DLY4X4
[04/04 16:42:44 395s] Total number of identified usable delay cells: 8
[04/04 16:42:44 395s] List of identified unusable delay cells:
[04/04 16:42:44 395s] Total number of identified unusable delay cells: 0
[04/04 16:42:44 395s]
[04/04 16:42:44 395s] *** Summary of all messages that are not suppressed in
this session:
[04/04 16:42:44 395s] Severity ID

Count Summary

[04/04 16:42:44 395s] WARNING ENCLF-200

has no ANTENNAGAT...

132 Pin '%s' in macro '%s'

[04/04 16:42:44 395s] WARNING ENCLF-201

has no ANTENNADIF...

128 Pin '%s' in macro '%s'

[04/04 16:42:44 395s] WARNING ENCEXT-6202

technology file, capa...

1 In addition to the

[04/04 16:42:44 395s] WARNING ENCEXT-2710

layer M%d is ignored...

2 Basic Cap table for

[04/04 16:42:44 395s] WARNING ENCEXT-2760

the cap table is ...

4 Layer M%d specified in

[04/04 16:42:44 395s] WARNING ENCEXT-2776

between layers %s and...

16 The via resistance

[04/04 16:42:44 395s] *** Message Summary: 283 warning(s), 0 error(s)

[04/04 16:42:44 395s]
[04/04 16:42:48 395s] <CMD> setDrawView fplan
[04/04 16:42:50 395s] <CMD> selectInst test_MPY_32_INST
[04/04 16:42:51 395s] <CMD> uiSetTool move

[04/04 16:42:54 396s] <CMD> setObjFPlanBox Instance test_MPY_32_INST

147.454 2.376 239.474 91.551
[04/04 16:42:55 396s] <CMD> deselectAll
[04/04 16:42:55 396s] <CMD> selectInst ashok_MPY_32_INST
[04/04 16:42:57 396s] <CMD> setObjFPlanBox Instance ashok_MPY_32_INST
2.332 3.327 93.662 94.547
[04/04 16:42:58 396s] <CMD> panPage 1 0
[04/04 16:42:58 396s] <CMD> panPage 1 0
[04/04 16:42:59 396s] <CMD> deselectAll
[04/04 16:42:59 396s] <CMD> selectInst suraj_MPY_32_INST
[04/04 16:43:01 396s] <CMD> fit
[04/04 16:43:03 397s] <CMD> setObjFPlanBox Instance suraj_MPY_32_INST
1.796 144.358 93.126 235.578
[04/04 16:43:04 397s] <CMD> panPage 1 0
[04/04 16:43:04 397s] <CMD> panPage 1 0
[04/04 16:43:05 397s] <CMD> panPage 1 0
[04/04 16:43:05 397s] <CMD> deselectAll
[04/04 16:43:05 397s] <CMD> selectInst gopi_MPY_32
[04/04 16:43:07 397s] <CMD> fit
[04/04 16:43:09 398s] <CMD> setObjFPlanBox Instance gopi_MPY_32 147.08
144.553 238.41 235.773
[04/04 16:43:10 398s] <CMD> uiSetTool select
[04/04 16:43:14 398s] <CMD> flipOrRotateObject -name suraj_MPY_32_INST
-flip MX
[04/04 16:43:16 398s] <CMD> flipOrRotateObject -name gopi_MPY_32 -flip MY
[04/04 16:43:18 398s] <CMD> flipOrRotateObject -name gopi_MPY_32 -flip MX
[04/04 16:43:20 399s] <CMD> deselectAll
[04/04 16:43:21 399s] <CMD> selectInst suraj_MPY_32_INST
[04/04 16:43:31 399s] <CMD> relativeFPlan --relativePlace suraj_MPY_32_INST
BR Top_Core_Boundary BL 0 0 MX
[04/04 16:43:31 399s] <CMD> setDrawView fplan

[04/04 16:43:32 399s] <CMD> deselectAll

[04/04 16:43:32 399s] <CMD> selectInst gopi_MPY_32
[04/04 16:43:36 399s] <CMD> relativeFPlan --relativePlace gopi_MPY_32 BL
Top_Core_Boundary BR 0 0 R180
[04/04 16:43:36 399s] <CMD> setDrawView fplan
[04/04 16:43:37 400s] <CMD> deselectAll
[04/04 16:43:37 400s] <CMD> selectInst ashok_MPY_32_INST
[04/04 16:43:45 400s] <CMD> relativeFPlan --relativePlace ashok_MPY_32_INST
TR Bottom_Core_Boundary TL 0 0 R0
[04/04 16:43:45 400s] <CMD> setDrawView fplan
[04/04 16:43:45 400s] <CMD> deselectAll
[04/04 16:43:45 400s] <CMD> selectInst test_MPY_32_INST
[04/04 16:43:52 400s] <CMD> relativeFPlan --relativePlace test_MPY_32_INST
TL Bottom_Core_Boundary TR 0 0 R0
[04/04 16:43:52 400s] <CMD> setDrawView fplan
[04/04 16:43:55 400s] <CMD> deselectAll
[04/04 16:44:09 401s] <CMD> getIoFlowFlag
[04/04 16:44:29 401s] <CMD> setIoFlowFlag 0
[04/04 16:44:29 401s] <CMD> floorPlan -site CoreSite -s 220 217 0.0 0.0 0.0
0.0
[04/04 16:44:29 401s] Horizontal Layer M1 offset = 95 (derived)
[04/04 16:44:29 401s] Vertical Layer M2 offset = 100 (derived)
[04/04 16:44:29 401s] Generated pitch 0.2 in Metal9 is different from 0.33
defined in technology file in unpreferred direction.
[04/04 16:44:29 401s] Generated pitch 0.38 in Metal9 is different from 0.33
defined in technology file in preferred direction.
[04/04 16:44:29 401s] Generated pitch 0.285 in Metal8 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 16:44:29 401s] Generated pitch 0.285 in Metal7 is different from 0.2
defined in technology file in preferred direction.
[04/04 16:44:29 401s] Generated pitch 0.19 in Metal6 is different from 0.2
defined in technology file in unpreferred direction.

[04/04 16:44:29 401s] Generated pitch 0.19 in Metal5 is different from 0.2
defined in technology file in preferred direction.
[04/04 16:44:29 401s] Generated pitch 0.19 in Metal4 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 16:44:29 401s] Generated pitch 0.19 in Metal3 is different from 0.2
defined in technology file in preferred direction.
[04/04 16:44:29 401s] Generated pitch 0.19 in Metal2 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 16:44:29 401s] Generated pitch 0.2 in Metal1 is different from 0.19
defined in technology file in unpreferred direction.
[04/04 16:44:29 401s] **WARN: (ENCFP-325):
Floorplan of the design is
resized. All current floorplan objects are automatically derived based on specified
new floorplan. This may change blocks, fixed standard cells, existing routes and
blockages.
[04/04 16:44:29 401s] <CMD> uiSetTool select
[04/04 16:44:29 401s] <CMD> getIoFlowFlag
[04/04 16:44:29 401s] <CMD> fit
[04/04 16:44:46 402s] <CMD> loadIoFile io/tdsp_core.save.io
[04/04 16:44:46 402s] Reading IO assignment file "io/tdsp_core.save.io" ...
[04/04 16:44:47 402s] <CMD> fit
[04/04 16:44:58 403s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 16:45:05 404s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 16:45:07 404s] <CMD> uiSetTool select
[04/04 16:45:10 404s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 16:45:13 404s] <CMD> uiSetTool select
[04/04 16:45:16 405s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 16:45:16 405s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Right -layer 3 -spreadType range
-start 219.236 123.644 -end 218.289 92.389 -pin {{address[0]} {address[1]}
{address[2]} {address[3]} {address[4]} {address[5]} {address[6]}
{address[7]} {p_address[0]} {p_address[1]} {p_address[2]} {p_address[3]}
{p_address[4]} {p_address[5]} {p_address[6]} {p_address[7]} {p_address[8]}
{port_address[0]} {port_address[1]} {port_address[2]} {rom_data_in[0]}
{rom_data_in[1]} {rom_data_in[2]} {rom_data_in[3]} {rom_data_in[4]}

{rom_data_in[5]} {rom_data_in[6]} {rom_data_in[7]} {rom_data_in[8]}

{rom_data_in[9]} {rom_data_in[10]} {rom_data_in[11]} {rom_data_in[12]}
{rom_data_in[13]} {rom_data_in[14]} {rom_data_in[15]} {t_data_in[0]}
{t_data_in[1]} {t_data_in[2]} {t_data_in[3]} {t_data_in[4]} {t_data_in[5]}
{t_data_in[6]} {t_data_in[7]} {t_data_in[8]} {t_data_in[9]} {t_data_in[10]}
{t_data_in[11]} {t_data_in[12]} {t_data_in[13]} {t_data_in[14]}
{t_data_in[15]}}
[04/04 16:45:16 405s] Successfully spread [52] pins.
[04/04 16:45:16 405s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1033.2M).
[04/04 16:45:16 405s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 16:45:23 405s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 16:45:28 406s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 16:45:31 406s] <CMD> uiSetTool select
[04/04 16:45:33 406s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 16:45:37 407s] <CMD> uiSetTool select
[04/04 16:45:39 407s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 16:45:39 407s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 92.951 217.095 -end 105.58 216.148 -pin {{port_pad_data_out[0]}
{port_pad_data_out[1]} {port_pad_data_out[2]} {port_pad_data_out[3]}
{port_pad_data_out[4]} {port_pad_data_out[5]} {port_pad_data_out[6]}
{port_pad_data_out[7]} {port_pad_data_out[8]} {port_pad_data_out[9]}
{port_pad_data_out[10]} {port_pad_data_out[11]} {port_pad_data_out[12]}
{port_pad_data_out[13]} {port_pad_data_out[14]} {port_pad_data_out[15]}
{rom_data_out[0]} {rom_data_out[1]} {rom_data_out[2]} {rom_data_out[3]}
{rom_data_out[4]} {rom_data_out[5]} {rom_data_out[6]} {rom_data_out[7]}
{rom_data_out[8]} {rom_data_out[9]} {rom_data_out[10]} {rom_data_out[11]}
{rom_data_out[12]} {rom_data_out[13]} {rom_data_out[14]}
{rom_data_out[15]}}
[04/04 16:45:39 407s] Successfully spread [32] pins.
[04/04 16:45:39 407s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1033.2M).
[04/04 16:45:39 407s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 16:45:42 407s] <CMD> getPinAssignMode -pinEditInBatch -quiet

[04/04 16:45:51 408s] <CMD> uiSetTool getLocation

Rda_PE::Attr:getStartCoord
[04/04 16:45:54 408s] <CMD> uiSetTool select
[04/04 16:45:57 408s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 16:46:01 408s] <CMD> uiSetTool select
[04/04 16:46:08 409s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 16:46:08 409s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 107.79 216.779 -end 126.101 216.148 -pin {as bio bus_grant bus_request
clk DFT_sen int p_as p_read p_write p_write_h port_as {port_pad_data_in[0]}
{port_pad_data_in[1]} {port_pad_data_in[2]} {port_pad_data_in[3]}
{port_pad_data_in[4]} {port_pad_data_in[5]} {port_pad_data_in[6]}
{port_pad_data_in[7]} {port_pad_data_in[8]} {port_pad_data_in[9]}
{port_pad_data_in[10]} {port_pad_data_in[11]} {port_pad_data_in[12]}
{port_pad_data_in[13]} {port_pad_data_in[14]} {port_pad_data_in[15]}
port_read port_write port_write_h RC_CG_TEST_PORT read reset SRPG_PG_in
SRPG_PG_in_1 {t_data_out[0]} {t_data_out[1]} {t_data_out[2]} {t_data_out[3]}
{t_data_out[4]} {t_data_out[5]} {t_data_out[6]} {t_data_out[7]}
{t_data_out[8]} {t_data_out[9]} {t_data_out[10]} {t_data_out[11]}
{t_data_out[12]} {t_data_out[13]} {t_data_out[14]} {t_data_out[15]} {t_sdi[0]}
{t_sdi[1]} {t_sdi[2]} {t_sdo[0]} {t_sdo[1]} {t_sdo[2]} write write_h}
[04/04 16:46:08 409s] Successfully spread [60] pins.
[04/04 16:46:08 409s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1033.2M).
[04/04 16:46:08 409s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 16:46:10 409s] <CMD> fit
[04/04 16:46:15 409s] <CMD> uiSetTool ruler
[04/04 16:47:17 411s] <CMD> clearGlobalNets
[04/04 16:47:17 411s] <CMD> globalNetConnect vdd -type pgpin -pin V_Sub
-inst *
[04/04 16:47:17 411s] <CMD> globalNetConnect gnd -type pgpin -pin gnd -inst
*
[04/04 16:47:17 411s] <CMD> globalNetConnect vdd -type pgpin -pin vdd -inst
*
[04/04 16:47:17 411s] <CMD> globalNetConnect vdd -type pgpin -pin VDD -inst
*

[04/04 16:47:17 411s] <CMD> globalNetConnect gnd -type pgpin -pin VSS -inst
*
[04/04 16:47:17 411s] Warning: term ovm of inst gopi_MPY_32 is not connect to
global special net.
[04/04 16:47:17 411s] Warning: term ovm of inst suraj_MPY_32_INST is not
connect to global special net.
[04/04 16:47:17 411s] Warning: term ovm of inst ashok_MPY_32_INST is not
connect to global special net.
[04/04 16:47:17 411s] Warning: term ovm of inst test_MPY_32_INST is not
connect to global special net.
[04/04 16:47:17 411s] Warning: pg term V_Core of inst gopi_MPY_32 is not
connect to global special net.
[04/04 16:47:17 411s] Warning: pg term V_Core of inst suraj_MPY_32_INST is
not connect to global special net.
[04/04 16:47:17 411s] Warning: pg term V_Core of inst ashok_MPY_32_INST is
not connect to global special net.
[04/04 16:47:46 412s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal9 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal7 -number_of_sets 2 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal9
-spacing 0.45 -xleft_offset 100 -xright_offset 100 -merge_stripes_value 0.165
-layer Metal8 -block_ring_bottom_layer_limit Metal7 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1
[04/04 16:47:46 412s]
[04/04 16:47:46 412s] Starting stripe generation ...
[04/04 16:47:46 412s] Non-Default setAddStripeOption Settings :
[04/04 16:47:46 412s] NONE
[04/04 16:47:46 412s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:47:46 412s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:47:46 412s] Stripe generation is complete; vias are now being
generated.
[04/04 16:47:46 412s] The power planner created 4 wires.

[04/04 16:47:46 412s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:

0:00:00.0, mem: 1033.2M) ***
[04/04 16:47:49 412s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal9 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal7 -number_of_sets 2 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal9
-spacing 0.45 -xleft_offset 100 -xright_offset 100 -merge_stripes_value 0.165
-layer Metal8 -block_ring_bottom_layer_limit Metal7 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1
[04/04 16:47:49 412s]
[04/04 16:47:49 412s] Starting stripe generation ...
[04/04 16:47:49 412s] Non-Default setAddStripeOption Settings :
[04/04 16:47:49 412s] NONE
[04/04 16:47:49 412s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:47:49 412s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:47:49 412s] Stripe generation is complete; vias are now being
generated.
[04/04 16:47:49 412s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (101.05, 0.00) (101.05, 216.98) because same wire already
exists.
[04/04 16:47:49 412s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (116.40, 0.00) (116.40, 216.98) because same wire already
exists.
[04/04 16:47:49 412s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (103.60, 0.00) (103.60, 216.98) because same wire already
exists.
[04/04 16:47:49 412s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (118.95, 0.00) (118.95, 216.98) because same wire already
exists.
[04/04 16:47:49 412s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1033.2M) ***
[04/04 16:48:09 413s] <CMD> zoomBox 115.998 101.544 144.728 74.393
[04/04 16:48:12 413s] <CMD> fit

[04/04 16:48:23 413s] <CMD> addStripe -skip_via_on_wire_shape Noshape

-block_ring_top_layer_limit Metal9 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal7 -number_of_sets 2 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal9
-spacing 0.45 -xleft_offset 100 -merge_stripes_value 0.165 -layer Metal8
-block_ring_bottom_layer_limit Metal7 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1
[04/04 16:48:23 413s]
[04/04 16:48:23 413s] Starting stripe generation ...
[04/04 16:48:23 413s] Non-Default setAddStripeOption Settings :
[04/04 16:48:23 413s] NONE
[04/04 16:48:23 413s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:48:23 413s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:48:23 413s] Stripe generation is complete; vias are now being
generated.
[04/04 16:48:23 413s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (101.05, 0.00) (101.05, 216.98) because same wire already
exists.
[04/04 16:48:23 413s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (103.60, 0.00) (103.60, 216.98) because same wire already
exists.
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (217.45, 10.00) (217.45, 12.10)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (217.45, 31.50) (217.45, 33.60)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (217.45, 53.01) (217.45, 55.11)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (217.45, 74.51) (217.45, 76.61)
[04/04 16:48:23 413s] **WARN: (ENCPP-612):
The intersection area is
insufficient to satisfy the LEF MINIMUMCUT rule, so no via was created between
layer: Metal7 & Metal8, size: 0.70 x 0.07 at (215.70, 125.79)

[04/04 16:48:23 413s] **WARN: (ENCPP-612):

The intersection area is
insufficient to satisfy the LEF MINIMUMCUT rule, so no via was created between
layer: Metal7 & Metal8, size: 0.70 x 0.07 at (215.70, 216.95)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 194.69) (220.00, 194.81)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 198.11) (220.00, 198.23)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 201.53) (220.00, 201.65)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal5 & Metal8 at (219.93, 209.88) (220.00, 211.98)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 204.95) (220.00, 205.07)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 208.37) (220.00, 208.49)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 211.79) (220.00, 211.91)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 215.21) (220.00, 215.33)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal5 & Metal8 at (219.93, 162.17) (220.00, 164.27)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 160.49) (220.00, 160.61)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 163.91) (220.00, 164.03)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 167.33) (220.00, 167.45)

[04/04 16:48:23 413s] **WARN: (ENCPP-532):

ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 170.75) (220.00, 170.87)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 174.17) (220.00, 174.29)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 177.59) (220.00, 177.71)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 181.01) (220.00, 181.13)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 184.43) (220.00, 184.55)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal5 & Metal8 at (219.93, 186.02) (220.00, 188.12)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 187.85) (220.00, 187.97)
[04/04 16:48:23 413s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal1 & Metal8 at (219.94, 191.27) (220.00, 191.39)
[04/04 16:48:23 413s] **WARN: (EMS-63): Message <ENCPP-532> has
exceeded the default message display limit of 20.
[04/04 16:48:23 413s] To avoid this warning, increase the display limit per
unique message by
[04/04 16:48:23 413s] using the set_message -limit <number> command.
[04/04 16:48:23 413s] The message limit can be removed by using the
set_message -no_limit command.
[04/04 16:48:23 413s] Note that setting a very large number using the
set_message -limit command
[04/04 16:48:23 413s] or removing the message limit using the set_message
-no_limit command can
[04/04 16:48:23 413s] significantly increase the log file size.

[04/04 16:48:23 413s] To suppress a message, use the set_message -suppress

command.
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 12.55) (220.00, 14.65)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 12.55) (220.00, 14.65)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 34.06) (220.00, 36.15)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 34.06) (220.00, 36.15)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 55.56) (220.00, 57.66)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 55.56) (220.00, 57.66)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 77.07) (220.00, 79.17)
[04/04 16:48:23 413s] **WARN: (ENCPP-531):
ViaGen Warning: MINAREA
rule violation, no via created on layer Metal7 at (220.00, 77.07) (220.00, 79.17)
[04/04 16:48:23 413s] **WARN: (ENCPP-612):
The intersection area is
insufficient to satisfy the LEF MINIMUMCUT rule, so no via was created between
layer: Metal7 & Metal8, size: 0.70 x 0.07 at (218.25, 125.79)
[04/04 16:48:23 413s] **WARN: (ENCPP-610):
Could not find a matching
VIARULE, so not create via between layer: Metal7 & Metal8, size: 0.06 x 0.06 at
(219.97, 126.38)
[04/04 16:48:23 413s] **WARN: (ENCPP-612):
The intersection area is
insufficient to satisfy the LEF MINIMUMCUT rule, so no via was created between
layer: Metal7 & Metal8, size: 0.70 x 0.07 at (218.25, 216.95)
[04/04 16:48:23 413s] The power planner created 2 wires.
[04/04 16:48:23 413s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1033.2M) ***
[04/04 16:48:30 413s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal9 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal7 -number_of_sets 1 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal9
-spacing 0.45 -xleft_offset 100 -merge_stripes_value 0.165 -layer Metal8
-block_ring_bottom_layer_limit Metal7 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1

[04/04 16:48:30 413s]

[04/04 16:48:30 413s] Starting stripe generation ...
[04/04 16:48:30 413s] Non-Default setAddStripeOption Settings :
[04/04 16:48:30 413s] NONE
[04/04 16:48:30 413s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:48:30 413s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:48:30 413s] Stripe generation is complete; vias are now being
generated.
[04/04 16:48:30 413s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (101.05, 0.00) (101.05, 216.98) because same wire already
exists.
[04/04 16:48:30 413s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (103.60, 0.00) (103.60, 216.98) because same wire already
exists.
[04/04 16:48:30 413s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1033.2M) ***
[04/04 16:48:46 413s] <CMD> setLayerPreference allM0 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM1Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM1 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM2Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM2 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM3Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM3 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM4Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM4 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM5Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM5 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM6Cont -isVisible 1

[04/04 16:48:46 413s] <CMD> setLayerPreference allM6 -isVisible 1

[04/04 16:48:46 413s] <CMD> setLayerPreference allM7Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM7 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM8Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM8 -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM9Cont -isVisible 1
[04/04 16:48:46 413s] <CMD> setLayerPreference allM9 -isVisible 1
[04/04 16:48:52 414s] <CMD> uiSetTool select
[04/04 16:48:53 414s] <CMD> selectWire 215.3500 0.0000 217.4500 216.9800
8 gnd
[04/04 16:48:54 414s] <CMD> selectWire 217.9000 0.0000 220.0000 216.9800
8 vdd
[04/04 16:48:55 414s] <CMD> deleteSelectedFromFPlan
[04/04 16:48:57 414s] <CMD> zoomBox 78.429 130.274 135.888 74.709
[04/04 16:48:58 414s] <CMD> fit
[04/04 16:49:02 415s] <CMD> uiSetTool ruler
[04/04 16:49:18 415s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal8 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal6 -number_of_sets 1 -ybottom_offset 100
-skip_via_on_pin Standardcell -stacked_via_top_layer Metal9
-padcore_ring_top_layer_limit Metal8 -spacing 0.45 -merge_stripes_value 0.165
-direction horizontal -layer Metal7 -block_ring_bottom_layer_limit Metal6
-ytop_offset 100 -width 2.1 -nets {gnd vdd} -stacked_via_bottom_layer Metal1
[04/04 16:49:18 415s]
[04/04 16:49:18 415s] Starting stripe generation ...
[04/04 16:49:18 415s] Non-Default setAddStripeOption Settings :
[04/04 16:49:18 415s] NONE
[04/04 16:49:18 415s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:49:18 415s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.

[04/04 16:49:18 415s] Stripe generation is complete; vias are now being
generated.
[04/04 16:49:18 415s] The power planner created 2 wires.
[04/04 16:49:18 415s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1033.2M) ***
[04/04 16:49:28 415s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal8 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal6 -number_of_sets 1 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal8
-start_from top -spacing 0.45 -merge_stripes_value 0.165 -direction horizontal
-layer Metal7 -block_ring_bottom_layer_limit Metal6 -ytop_offset 100 -width 2.1
-nets {gnd vdd} -stacked_via_bottom_layer Metal1
[04/04 16:49:28 415s]
[04/04 16:49:28 415s] Starting stripe generation ...
[04/04 16:49:28 415s] Non-Default setAddStripeOption Settings :
[04/04 16:49:28 415s] NONE
[04/04 16:49:28 415s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:49:28 415s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:49:28 415s] **WARN: (ENCPP-4034):
Value for start_x/start_y is
less than value for stop_x/stop_y. addStripe will exchange their values.
[04/04 16:49:28 415s] Stripe generation is complete; vias are now being
generated.
[04/04 16:49:28 415s] The power planner created 2 wires.
[04/04 16:49:28 415s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1033.2M) ***
[04/04 16:49:48 416s] <CMD> sroute -connect { blockPin } -layerChangeRange
{ Metal1 Metal9 } -blockPinTarget { nearestTarget } -allowJogging 0
-crossoverViaLayerRange { Metal1 Metal4 } -allowLayerChange 0 -nets { vdd
gnd } -blockPin useLef -targetViaLayerRange { Metal1 Metal4 }
[04/04 16:49:48 416s] *** Begin SPECIAL ROUTE on Mon Apr 4 16:49:48 2016
***

[04/04 16:49:48 416s] SPECIAL ROUTE ran on directory:

/Projects/Training/user5/work/suraj/encounter/rundir
[04/04 16:49:48 416s] SPECIAL ROUTE ran on machine: SRV01 (Linux 2.6.18308.el5 x86_64 2.66Ghz)
[04/04 16:49:48 416s]
[04/04 16:49:48 416s] Begin option processing ...
[04/04 16:49:48 416s] srouteConnectPowerBump set to false
[04/04 16:49:48 416s] routeSelectNet set to "vdd gnd"
[04/04 16:49:48 416s] routeSpecial set to true
[04/04 16:49:48 416s] srouteBlockPin set to "useLef"
[04/04 16:49:48 416s] srouteBottomLayerLimit set to 1
[04/04 16:49:48 416s] srouteBottomTargetLayerLimit set to 1
[04/04 16:49:48 416s] srouteConnectConverterPin set to false
[04/04 16:49:48 416s] srouteConnectCorePin set to false
[04/04 16:49:48 416s] srouteConnectPadPin set to false
[04/04 16:49:48 416s] srouteConnectStripe set to false
[04/04 16:49:48 416s] srouteCrossoverViaBottomLayer set to 1
[04/04 16:49:48 416s] srouteCrossoverViaTopLayer set to 4
[04/04 16:49:48 416s] srouteFollowCorePinEnd set to 3
[04/04 16:49:48 416s] srouteFollowPadPin set to false
[04/04 16:49:48 416s] srouteNoLayerChangeRoute set to true
[04/04 16:49:48 416s] sroutePadPinAllPorts set to true
[04/04 16:49:48 416s] sroutePreserveExistingRoutes set to true
[04/04 16:49:48 416s] srouteRoutePowerBarPortOnBothDir set to true
[04/04 16:49:48 416s] srouteStopBlockPin set to "nearestTarget"
[04/04 16:49:48 416s] srouteStraightConnections set to "straightWithDrcClean"
[04/04 16:49:48 416s] srouteTopLayerLimit set to 9
[04/04 16:49:48 416s] srouteTopTargetLayerLimit set to 4

[04/04 16:49:48 416s] End option processing: cpu: 0:00:00, real: 0:00:00, peak:
1698.00 megs.
[04/04 16:49:48 416s]
[04/04 16:49:48 416s] Reading DB technology information...
[04/04 16:49:48 416s] Finished reading DB technology information.
[04/04 16:49:48 416s] Reading floorplan and netlist information...
[04/04 16:49:48 416s] Finished reading floorplan and netlist information.
[04/04 16:49:48 416s] Read in 19 layers, 9 routing layers, 1 overlap layer
[04/04 16:49:48 416s] Read in 2 nondefault rules, 0 used
[04/04 16:49:48 416s] Read in 68 macros, 68 used
[04/04 16:49:48 416s] Read in 68 components
[04/04 16:49:48 416s] 64 core components: 64 unplaced, 0 placed, 0 fixed
[04/04 16:49:48 416s] 4 block/ring components: 0 unplaced, 0 placed, 4 fixed
[04/04 16:49:48 416s] Read in 160 physical pins
[04/04 16:49:48 416s] 160 physical pins: 0 unplaced, 0 placed, 160 fixed
[04/04 16:49:48 416s] Read in 144 nets
[04/04 16:49:48 416s] Read in 2 special nets, 2 routed
[04/04 16:49:48 416s] Read in 299 terminals
[04/04 16:49:48 416s] 2 nets selected.
[04/04 16:49:48 416s]
[04/04 16:49:48 416s] Begin power routing ...
[04/04 16:49:48 416s] **WARN: (ENCSR-486):
Ring/Stripe at (0.000,
112.330) (220.000, 114.430) on layer Metal7 is out of layer range and is ignored.
The ports will route to other nearby rings/stripes. (Same type of warning will be
suppressed)
[04/04 16:49:48 416s] Number of Block ports routed: 0 open: 348
[04/04 16:49:48 416s] Number of Power Bump ports routed: 0
[04/04 16:49:48 416s] 7 ports open due to poor power planning
[04/04 16:49:48 416s] End power routing: cpu: 0:00:00, real: 0:00:00, peak:
1701.00 megs.

[04/04 16:49:48 416s]

[04/04 16:49:48 416s]
[04/04 16:49:48 416s]
[04/04 16:49:48 416s] Begin updating DB with routing results ...
[04/04 16:49:48 416s] Updating DB with 145 via definition ...
[04/04 16:49:48 416s] Updating DB with 160 io pins ...Extracting standard cell
pins and blockage ......
[04/04 16:49:48 416s] Pin and blockage extraction finished
[04/04 16:49:48 416s]
[04/04 16:49:48 416s] sroute: Total CPU time used = 0:0:0
[04/04 16:49:48 416s] sroute: Total Real time used = 0:0:0
[04/04 16:49:48 416s] sroute: Total Memory used = 0.00 megs
[04/04 16:49:48 416s] sroute: Total Peak Memory used = 1033.19 megs
[04/04 16:49:52 416s] <CMD> setLayerPreference violation -isVisible 1
[04/04 16:49:52 416s] <CMD> violationBrowser -all -no_display_false
[04/04 16:49:54 417s] <CMD> clearDrc
[04/04 16:50:09 417s] <CMD> sroute -connect { blockPin } -layerChangeRange
{ Metal1 Metal9 } -blockPinTarget { stripe } -allowJogging 0
-crossoverViaLayerRange { Metal1 Metal4 } -allowLayerChange 0 -nets { vdd
gnd } -blockPin useLef -targetViaLayerRange { Metal1 Metal4 }
[04/04 16:50:09 417s] *** Begin SPECIAL ROUTE on Mon Apr 4 16:50:09 2016
***
[04/04 16:50:09 417s] SPECIAL ROUTE ran on directory:
/Projects/Training/user5/work/suraj/encounter/rundir
[04/04 16:50:09 417s] SPECIAL ROUTE ran on machine: SRV01 (Linux 2.6.18308.el5 x86_64 2.66Ghz)
[04/04 16:50:09 417s]
[04/04 16:50:09 417s] Begin option processing ...
[04/04 16:50:09 417s] srouteConnectPowerBump set to false
[04/04 16:50:09 417s] routeSelectNet set to "vdd gnd"
[04/04 16:50:09 417s] routeSpecial set to true

[04/04 16:50:09 417s] srouteBlockPin set to "useLef"

[04/04 16:50:09 417s] srouteBlockPinTarget set to "stripe"
[04/04 16:50:09 417s] srouteBottomLayerLimit set to 1
[04/04 16:50:09 417s] srouteBottomTargetLayerLimit set to 1
[04/04 16:50:09 417s] srouteConnectConverterPin set to false
[04/04 16:50:09 417s] srouteConnectCorePin set to false
[04/04 16:50:09 417s] srouteConnectPadPin set to false
[04/04 16:50:09 417s] srouteConnectStripe set to false
[04/04 16:50:09 417s] srouteCrossoverViaBottomLayer set to 1
[04/04 16:50:09 417s] srouteCrossoverViaTopLayer set to 4
[04/04 16:50:09 417s] srouteFollowCorePinEnd set to 3
[04/04 16:50:09 417s] srouteFollowPadPin set to false
[04/04 16:50:09 417s] srouteNoLayerChangeRoute set to true
[04/04 16:50:09 417s] sroutePadPinAllPorts set to true
[04/04 16:50:09 417s] sroutePreserveExistingRoutes set to true
[04/04 16:50:09 417s] srouteRoutePowerBarPortOnBothDir set to true
[04/04 16:50:09 417s] srouteStraightConnections set to "straightWithDrcClean"
[04/04 16:50:09 417s] srouteTopLayerLimit set to 9
[04/04 16:50:09 417s] srouteTopTargetLayerLimit set to 4
[04/04 16:50:09 417s] End option processing: cpu: 0:00:00, real: 0:00:00, peak:
1701.00 megs.
[04/04 16:50:09 417s]
[04/04 16:50:09 417s] Reading DB technology information...
[04/04 16:50:09 417s] Finished reading DB technology information.
[04/04 16:50:09 417s] Reading floorplan and netlist information...
[04/04 16:50:09 417s] Finished reading floorplan and netlist information.
[04/04 16:50:09 417s] Read in 19 layers, 9 routing layers, 1 overlap layer
[04/04 16:50:09 417s] Read in 2 nondefault rules, 0 used
[04/04 16:50:09 417s] Read in 68 macros, 68 used

[04/04 16:50:09 417s] Read in 68 components

[04/04 16:50:09 417s] 64 core components: 64 unplaced, 0 placed, 0 fixed
[04/04 16:50:09 417s] 4 block/ring components: 0 unplaced, 0 placed, 4 fixed
[04/04 16:50:09 417s] Read in 160 physical pins
[04/04 16:50:09 417s] 160 physical pins: 0 unplaced, 0 placed, 160 fixed
[04/04 16:50:09 417s] Read in 144 nets
[04/04 16:50:09 417s] Read in 2 special nets, 2 routed
[04/04 16:50:09 417s] Read in 299 terminals
[04/04 16:50:09 417s] 2 nets selected.
[04/04 16:50:09 417s]
[04/04 16:50:09 417s] Begin power routing ...
[04/04 16:50:09 417s] **WARN: (ENCSR-486):
Ring/Stripe at (0.000,
112.330) (220.000, 114.430) on layer Metal7 is out of layer range and is ignored.
The ports will route to other nearby rings/stripes. (Same type of warning will be
suppressed)
[04/04 16:50:09 417s] Number of Block ports routed: 0 open: 348
[04/04 16:50:09 417s] Number of Power Bump ports routed: 0
[04/04 16:50:09 417s] 7 ports open due to poor power planning
[04/04 16:50:09 417s] End power routing: cpu: 0:00:00, real: 0:00:00, peak:
1701.00 megs.
[04/04 16:50:09 417s]
[04/04 16:50:09 417s]
[04/04 16:50:09 417s]
[04/04 16:50:09 417s] Begin updating DB with routing results ...
[04/04 16:50:09 417s] Updating DB with 145 via definition ...
[04/04 16:50:09 417s] Updating DB with 160 io pins ...
[04/04 16:50:09 417s] sroute: Total CPU time used = 0:0:0
[04/04 16:50:09 417s] sroute: Total Real time used = 0:0:0
[04/04 16:50:09 417s] sroute: Total Memory used = 0.00 megs
[04/04 16:50:09 417s] sroute: Total Peak Memory used = 1033.19 megs

[04/04 16:50:11 417s] <CMD> setLayerPreference violation -isVisible 1

[04/04 16:50:11 417s] <CMD> violationBrowser -all -no_display_false
[04/04 16:50:13 418s] <CMD> clearDrc
[04/04 16:50:25 418s] <CMD> zoomBox 94.846 80.392 114.104 59.870
[04/04 16:50:26 418s] <CMD> fit
[04/04 16:50:27 418s] <CMD> zoomBox 69.904 63.659 111.263 31.456
[04/04 16:50:36 419s] <CMD> setLayerPreference pinObj -isVisible 1
[04/04 16:50:44 419s] <CMD> zoomBox 87.602 57.781 91.734 51.178
[04/04 16:50:50 420s] <CMD> uiSetTool select
[04/04 16:50:54 420s] <CMD> fit
[04/04 16:51:24 421s] <CMD> sroute -connect { blockPin } -layerChangeRange
{ Metal1 Metal9 } -blockPinTarget { stripe } -allowJogging 0
-crossoverViaLayerRange { Metal1 Metal9 } -allowLayerChange 0 -nets { vdd
gnd } -blockPin useLef -targetViaLayerRange { Metal1 Metal9 }
[04/04 16:51:24 421s] *** Begin SPECIAL ROUTE on Mon Apr 4 16:51:24 2016
***
[04/04 16:51:24 421s] SPECIAL ROUTE ran on directory:
/Projects/Training/user5/work/suraj/encounter/rundir
[04/04 16:51:24 421s] SPECIAL ROUTE ran on machine: SRV01 (Linux 2.6.18308.el5 x86_64 2.66Ghz)
[04/04 16:51:24 421s]
[04/04 16:51:24 421s] Begin option processing ...
[04/04 16:51:24 421s] srouteConnectPowerBump set to false
[04/04 16:51:24 421s] routeSelectNet set to "vdd gnd"
[04/04 16:51:24 421s] routeSpecial set to true
[04/04 16:51:24 421s] srouteBlockPin set to "useLef"
[04/04 16:51:24 421s] srouteBlockPinTarget set to "stripe"
[04/04 16:51:24 421s] srouteBottomLayerLimit set to 1
[04/04 16:51:24 421s] srouteBottomTargetLayerLimit set to 1
[04/04 16:51:24 421s] srouteConnectConverterPin set to false
[04/04 16:51:24 421s] srouteConnectCorePin set to false

[04/04 16:51:24 421s] srouteConnectPadPin set to false

[04/04 16:51:24 421s] srouteConnectStripe set to false
[04/04 16:51:24 421s] srouteCrossoverViaBottomLayer set to 1
[04/04 16:51:24 421s] srouteCrossoverViaTopLayer set to 9
[04/04 16:51:24 421s] srouteFollowCorePinEnd set to 3
[04/04 16:51:24 421s] srouteFollowPadPin set to false
[04/04 16:51:24 421s] srouteNoLayerChangeRoute set to true
[04/04 16:51:24 421s] sroutePadPinAllPorts set to true
[04/04 16:51:24 421s] sroutePreserveExistingRoutes set to true
[04/04 16:51:24 421s] srouteRoutePowerBarPortOnBothDir set to true
[04/04 16:51:24 421s] srouteStraightConnections set to "straightWithDrcClean"
[04/04 16:51:24 421s] srouteTopLayerLimit set to 9
[04/04 16:51:24 421s] srouteTopTargetLayerLimit set to 9
[04/04 16:51:24 421s] End option processing: cpu: 0:00:00, real: 0:00:00, peak:
1701.00 megs.
[04/04 16:51:24 421s]
[04/04 16:51:24 421s] Reading DB technology information...
[04/04 16:51:24 421s] Finished reading DB technology information.
[04/04 16:51:24 421s] Reading floorplan and netlist information...
[04/04 16:51:24 421s] Finished reading floorplan and netlist information.
[04/04 16:51:24 421s] Read in 19 layers, 9 routing layers, 1 overlap layer
[04/04 16:51:24 421s] Read in 2 nondefault rules, 0 used
[04/04 16:51:24 421s] Read in 68 macros, 68 used
[04/04 16:51:24 421s] Read in 68 components
[04/04 16:51:24 421s] 64 core components: 64 unplaced, 0 placed, 0 fixed
[04/04 16:51:24 421s] 4 block/ring components: 0 unplaced, 0 placed, 4 fixed
[04/04 16:51:24 421s] Read in 160 physical pins
[04/04 16:51:24 421s] 160 physical pins: 0 unplaced, 0 placed, 160 fixed
[04/04 16:51:24 421s] Read in 144 nets

[04/04 16:51:24 421s] Read in 2 special nets, 2 routed

[04/04 16:51:24 421s] Read in 299 terminals
[04/04 16:51:24 421s] 2 nets selected.
[04/04 16:51:24 421s]
[04/04 16:51:24 421s] Begin power routing ...
[04/04 16:51:25 421s] Number of Block ports routed: 89 open: 259
[04/04 16:51:25 421s] Number of Power Bump ports routed: 0
[04/04 16:51:25 421s] End power routing: cpu: 0:00:00, real: 0:00:01, peak:
1701.00 megs.
[04/04 16:51:25 421s]
[04/04 16:51:25 421s]
[04/04 16:51:25 421s]
[04/04 16:51:25 421s] Begin updating DB with routing results ...
[04/04 16:51:25 421s] Updating DB with 149 via definition ...
[04/04 16:51:25 421s] Updating DB with 160 io pins ...
[04/04 16:51:25 421s]
sroute post-processing starts at Mon Apr 4 16:51:25 2016
The viaGen is rebuilding shadow vias for net gnd.
[04/04 16:51:25 421s] sroute post-processing ends at Mon Apr 4 16:51:25
2016

sroute post-processing starts at Mon Apr 4 16:51:25 2016

The viaGen is rebuilding shadow vias for net vdd.
[04/04 16:51:25 421s] sroute post-processing ends at Mon Apr 4 16:51:25
2016
sroute: Total CPU time used = 0:0:0
[04/04 16:51:25 421s] sroute: Total Real time used = 0:0:1
[04/04 16:51:25 421s] sroute: Total Memory used = 0.00 megs
[04/04 16:51:25 421s] sroute: Total Peak Memory used = 1033.19 megs

[04/04 16:51:30 422s] <CMD> setLayerPreference violation -isVisible 1

[04/04 16:51:30 422s] <CMD> violationBrowser -all -no_display_false
[04/04 16:51:32 422s] <CMD> clearDrc
[04/04 16:51:35 423s] <CMD> selectWire 60.3300 114.8800 62.4300 158.6600
6 gnd
[04/04 16:51:36 423s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:38 423s] <CMD> selectWire 23.4000 114.8800 25.5000 125.7950
4 gnd
[04/04 16:51:38 423s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:40 423s] <CMD> selectWire 23.4000 91.1850 25.5000 102.1000
4 gnd
[04/04 16:51:40 423s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:42 423s] <CMD> selectWire 44.4000 90.1700 46.5000 102.1000
6 gnd
[04/04 16:51:42 423s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:43 424s] <CMD> selectWire 60.3300 58.3200 62.4300 102.1000
6 gnd
[04/04 16:51:43 424s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:45 424s] <CMD> selectWire 157.5700 114.8800 159.6700
158.6600 6 gnd
[04/04 16:51:45 424s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:47 424s] <CMD> selectWire 173.5000 114.8800 175.6000
125.7950 6 gnd
[04/04 16:51:47 424s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:49 425s] <CMD> selectWire 194.5000 114.8800 196.6000
125.7950 4 gnd
[04/04 16:51:49 425s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:53 425s] <CMD> selectWire 44.4000 114.8800 46.5000 125.7950
6 gnd
[04/04 16:51:55 425s] <CMD> deleteSelectedFromFPlan
[04/04 16:51:56 425s] <CMD> selectWire 44.4000 114.8800 46.5000 126.8100
6 gnd

[04/04 16:51:56 425s] <CMD> deleteSelectedFromFPlan

[04/04 16:51:59 426s] <CMD> fit
[04/04 16:52:01 426s] <CMD> uiSetTool ruler
[04/04 16:52:08 426s] <CMD> zoomBox 97.371 118.908 111.578 100.281
[04/04 16:52:10 426s] <CMD> fit
[04/04 16:52:20 427s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal5 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal3 -number_of_sets 1 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal5
-spacing 0.45 -xleft_offset 106 -merge_stripes_value 0.165 -layer Metal4
-block_ring_bottom_layer_limit Metal3 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1
[04/04 16:52:20 427s]
[04/04 16:52:20 427s] Starting stripe generation ...
[04/04 16:52:20 427s] Non-Default setAddStripeOption Settings :
[04/04 16:52:20 427s] NONE
[04/04 16:52:20 427s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:52:20 427s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:52:20 427s] Stripe generation is complete; vias are now being
generated.
[04/04 16:52:20 427s] The power planner created 2 wires.
[04/04 16:52:20 427s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1033.2M) ***
[04/04 16:52:22 427s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal5 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal3 -number_of_sets 1 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal5
-spacing 0.45 -xleft_offset 106 -merge_stripes_value 0.165 -layer Metal4
-block_ring_bottom_layer_limit Metal3 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1
[04/04 16:52:22 427s]
[04/04 16:52:22 427s] Starting stripe generation ...

[04/04 16:52:22 427s] Non-Default setAddStripeOption Settings :

[04/04 16:52:22 427s] NONE
[04/04 16:52:22 427s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:52:22 427s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 16:52:22 427s] Stripe generation is complete; vias are now being
generated.
[04/04 16:52:22 427s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (107.05, 0.00) (107.05, 216.98) because same wire already
exists.
[04/04 16:52:22 427s] **WARN: (ENCPP-170):
The power planner failed to
create a wire at (109.60, 0.00) (109.60, 216.98) because same wire already
exists.
[04/04 16:52:22 427s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1033.2M) ***
[04/04 16:52:51 427s] <CMD> sroute -connect { corePin } -layerChangeRange
{ Metal1 Metal9 } -blockPinTarget { stripe } -corePinTarget { firstAfterRowEnd }
-allowJogging 0 -crossoverViaLayerRange { Metal1 Metal4 } -allowLayerChange 0
-nets { vdd gnd } -targetViaLayerRange { Metal1 Metal4 }
[04/04 16:52:51 427s] **WARN: (ENCSR-4058):
Sroute option: blockPinTarget
should be used in conjunction with option: -connect blockPin.
[04/04 16:52:51 427s] *** Begin SPECIAL ROUTE on Mon Apr 4 16:52:51 2016
***
[04/04 16:52:51 427s] SPECIAL ROUTE ran on directory:
/Projects/Training/user5/work/suraj/encounter/rundir
[04/04 16:52:51 427s] SPECIAL ROUTE ran on machine: SRV01 (Linux 2.6.18308.el5 x86_64 2.66Ghz)
[04/04 16:52:51 427s]
[04/04 16:52:51 427s] Begin option processing ...
[04/04 16:52:51 427s] srouteConnectPowerBump set to false
[04/04 16:52:51 427s] routeSelectNet set to "vdd gnd"
[04/04 16:52:51 427s] routeSpecial set to true

[04/04 16:52:51 427s] srouteBlockPinTarget set to "stripe"

[04/04 16:52:51 427s] srouteBottomLayerLimit set to 1
[04/04 16:52:51 427s] srouteBottomTargetLayerLimit set to 1
[04/04 16:52:51 427s] srouteConnectBlockPin set to false
[04/04 16:52:51 427s] srouteConnectConverterPin set to false
[04/04 16:52:51 427s] srouteConnectPadPin set to false
[04/04 16:52:51 427s] srouteConnectStripe set to false
[04/04 16:52:51 427s] srouteCrossoverViaBottomLayer set to 1
[04/04 16:52:51 427s] srouteCrossoverViaTopLayer set to 4
[04/04 16:52:51 427s] srouteFollowCorePinEnd set to 3
[04/04 16:52:51 427s] srouteFollowPadPin set to false
[04/04 16:52:51 427s] srouteNoLayerChangeRoute set to true
[04/04 16:52:51 427s] sroutePadPinAllPorts set to true
[04/04 16:52:51 427s] sroutePreserveExistingRoutes set to true
[04/04 16:52:51 427s] srouteRoutePowerBarPortOnBothDir set to true
[04/04 16:52:51 427s] srouteStraightConnections set to "straightWithDrcClean"
[04/04 16:52:51 427s] srouteTopLayerLimit set to 9
[04/04 16:52:51 427s] srouteTopTargetLayerLimit set to 4
[04/04 16:52:51 427s] End option processing: cpu: 0:00:00, real: 0:00:00, peak:
1701.00 megs.
[04/04 16:52:51 427s]
[04/04 16:52:51 427s] Reading DB technology information...
[04/04 16:52:51 428s] Finished reading DB technology information.
[04/04 16:52:51 428s] Reading floorplan and netlist information...
[04/04 16:52:51 428s] Finished reading floorplan and netlist information.
[04/04 16:52:51 428s] Read in 19 layers, 9 routing layers, 1 overlap layer
[04/04 16:52:51 428s] Read in 2 nondefault rules, 0 used
[04/04 16:52:51 428s] Read in 491 macros, 68 used
[04/04 16:52:51 428s] Read in 68 components

[04/04 16:52:51 428s] 64 core components: 64 unplaced, 0 placed, 0 fixed

[04/04 16:52:51 428s] 4 block/ring components: 0 unplaced, 0 placed, 4 fixed
[04/04 16:52:51 428s] Read in 164 physical pins
[04/04 16:52:51 428s] 164 physical pins: 0 unplaced, 0 placed, 164 fixed
[04/04 16:52:51 428s] Read in 144 nets
[04/04 16:52:51 428s] Read in 2 special nets, 2 routed
[04/04 16:52:51 428s] Read in 303 terminals
[04/04 16:52:51 428s] 2 nets selected.
[04/04 16:52:51 428s]
[04/04 16:52:51 428s] Begin power routing ...
[04/04 16:52:51 428s] CPU time for FollowPin 0 seconds
[04/04 16:52:51 428s] CPU time for FollowPin 0 seconds
[04/04 16:52:51 428s] Number of Core ports routed: 0 open: 213
[04/04 16:52:51 428s] Number of Followpin connections: 127
[04/04 16:52:51 428s] End power routing: cpu: 0:00:00, real: 0:00:00, peak:
1701.00 megs.
[04/04 16:52:51 428s]
[04/04 16:52:51 428s]
[04/04 16:52:51 428s]
[04/04 16:52:51 428s] Begin updating DB with routing results ...
[04/04 16:52:51 428s] Updating DB with 158 via definition ...
[04/04 16:52:51 428s] Updating DB with 164 io pins ...
[04/04 16:52:51 428s]
sroute post-processing starts at Mon Apr 4 16:52:51 2016
The viaGen is rebuilding shadow vias for net gnd.
[04/04 16:52:51 428s] sroute post-processing ends at Mon Apr 4 16:52:51
2016

sroute post-processing starts at Mon Apr 4 16:52:51 2016

The viaGen is rebuilding shadow vias for net vdd.

[04/04 16:52:51 428s] sroute post-processing ends at Mon Apr 4 16:52:51
2016
sroute: Total CPU time used = 0:0:0
[04/04 16:52:52 428s] sroute: Total Real time used = 0:0:0
[04/04 16:52:52 428s] sroute: Total Memory used = 0.00 megs
[04/04 16:52:52 428s] sroute: Total Peak Memory used = 1033.19 megs
[04/04 16:52:53 428s] <CMD> setLayerPreference violation -isVisible 1
[04/04 16:52:53 428s] <CMD> violationBrowser -all -no_display_false
[04/04 16:52:56 428s] <CMD> clearDrc
[04/04 16:52:59 428s] <CMD> zoomBox 101.160 139.430 125.154 108.174
[04/04 16:53:01 428s] <CMD> fit
[04/04 16:53:12 429s] <CMD> setPlaceMode -fp false
[04/04 16:53:12 429s] <CMD> placeDesign
[04/04 16:53:12 429s] *** Starting placeDesign default flow ***
[04/04 16:53:12 429s] **INFO: Enable pre-place timing setting for timing
analysis
[04/04 16:53:12 429s] Set Using Default Delay Limit as 101.
[04/04 16:53:12 429s] **WARN: (ENCDC-1629):
The default delay limit was
set to 101. This is less than the default of 1000 and may result in inaccurate
delay calculation for nets with a fanout higher than the setting. If needed, the
default delay limit may be adjusted by running the command 'set
delaycal_use_default_delay_limit'.
[04/04 16:53:12 429s] Set Default Net Delay as 0 ps.
[04/04 16:53:12 429s] Set Default Net Load as 0 pF.
[04/04 16:53:12 429s] **INFO: Analyzing IO path groups for slack adjustment
[04/04 16:53:12 429s] Effort level <high> specified for reg2reg_tmp.12308
path_group
[04/04 16:53:12 429s]
################################################
#################################
[04/04 16:53:12 429s] # Design Stage: PreRoute

[04/04 16:53:12 429s] # Design Mode: 90nm

[04/04 16:53:12 429s] # Analysis Mode: MMMC non-OCV
[04/04 16:53:12 429s] # Extraction Mode: default
[04/04 16:53:12 429s] # Delay Calculation Options: engine=aae
SIAware=false(opt_signoff)
[04/04 16:53:12 429s] # Switching Delay Calculation Engine to AAE
[04/04 16:53:12 429s]
################################################
#################################
[04/04 16:53:12 429s] Calculate delays in BcWc mode...
[04/04 16:53:12 429s] Calculate delays in BcWc mode...
[04/04 16:53:12 429s] Calculate delays in BcWc mode...
[04/04 16:53:12 429s] Calculate delays in BcWc mode...
[04/04 16:53:12 429s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...

[04/04 16:53:12 430s] Calculate delays in BcWc mode...

[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Calculate delays in BcWc mode...
[04/04 16:53:12 430s] Topological Sorting (CPU = 0:00:00.0, MEM = 1052.5M,
InitMEM = 1052.5M)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:53:19 436s] AAE_THRD: End delay calculation. (MEM=1345.46
CPU=0:00:04.9 REAL=0:00:05.0)
[04/04 16:53:19 436s] *** CDM Built up (cpu=0:00:06.7 real=0:00:07.0 mem=
1345.5M) ***
[04/04 16:53:21 438s] *** Start deleteBufferTree ***

[04/04 16:53:21 438s] Info: Detect buffers to remove automatically.

[04/04 16:53:21 438s] Analyzing netlist ...
[04/04 16:53:21 438s] All-RC-Corners-Per-Net-In-Memory is turned ON...
[04/04 16:53:21 438s] Updating netlist
[04/04 16:53:21 438s]
[04/04 16:53:21 438s] *summary: 49 instances (buffers/inverters) removed
[04/04 16:53:21 438s] *** Finish deleteBufferTree (0:00:00.1) ***
[04/04 16:53:21 438s] **INFO: Disable pre-place timing setting for timing
analysis
[04/04 16:53:21 438s] Set Using Default Delay Limit as 1000.
[04/04 16:53:21 438s] Set Default Net Delay as 1000 ps.
[04/04 16:53:21 438s] Set Default Net Load as 0.5 pF.
[04/04 16:53:21 438s] *** Starting "NanoPlace(TM) placement v#1
(mem=1161.4M)" ...
[04/04 16:53:35 453s] *** Build Buffered Sizing Timing Model
[04/04 16:53:35 453s] (cpu=0:00:14.4 mem=1161.4M) ***
[04/04 16:53:36 453s] *** Build Virtual Sizing Timing Model
[04/04 16:53:36 453s] (cpu=0:00:14.8 mem=1161.4M) ***
[04/04 16:53:36 453s] Options: timingDriven clkGateAware ignoreScan
pinGuide congEffort=auto gpeffort=medium
[04/04 16:53:36 453s] **WARN: (ENCSP-9042):
defined, -ignoreScan option will be ignored.

Scan chains were not

Est. stn bbox = 6.290e+04 (3.06e+04

[04/04 16:53:45 462s]

1338.3M

cpu = 0:00:00.8 real = 0:00:01.0 mem =

[04/04 16:53:45 462s] Congestion driven padding in post-place stage.

[04/04 16:53:45 462s] Congestion driven padding increases utilization from
0.564 to 0.628

[04/04 16:53:45 462s] Congestion driven padding runtime: cpu = 0:00:00.0 real
= 0:00:00.0 mem = 1341.3M
[04/04 16:53:45 462s] Iteration 7: Total net bbox = 6.004e+04 (2.98e+04
3.02e+04)
[04/04 16:53:45 462s]
3.68e+04)

Est. stn bbox = 7.301e+04 (3.62e+04

[04/04 16:53:45 462s]

1341.3M

cpu = 0:00:00.2 real = 0:00:00.0 mem =

[04/04 16:53:47 464s] nrCritNet: 4.97% ( 113 / 2274 ) cutoffSlk: -294.7ps

stdDelay: 11.6ps
[04/04 16:53:47 464s] nrCritNet: 0.00% ( 0 / 2274 ) cutoffSlk: -441.4ps
stdDelay: 11.6ps
[04/04 16:53:47 464s] Iteration 8: Total net bbox = 6.042e+04 (3.00e+04
3.04e+04)
[04/04 16:53:47 464s]
3.70e+04)

Est. stn bbox = 7.340e+04 (3.64e+04

[04/04 16:53:47 464s]

1344.2M

cpu = 0:00:01.5 real = 0:00:02.0 mem =

[04/04 16:53:48 465s] Congestion driven padding in post-place stage.

[04/04 16:53:48 465s] Congestion driven padding increases utilization from
0.564 to 0.630
[04/04 16:53:48 465s] Congestion driven padding runtime: cpu = 0:00:00.0 real
= 0:00:00.0 mem = 1344.2M
[04/04 16:53:48 465s] Iteration 9: Total net bbox = 6.188e+04 (3.09e+04
3.09e+04)
[04/04 16:53:48 465s]
3.76e+04)

Est. stn bbox = 7.505e+04 (3.75e+04

[04/04 16:53:48 465s]

1344.2M

cpu = 0:00:01.0 real = 0:00:01.0 mem =

[04/04 16:53:49 466s] nrCritNet: 4.97% ( 113 / 2274 ) cutoffSlk: -293.4ps

stdDelay: 11.6ps
[04/04 16:53:49 466s] nrCritNet: 0.00% ( 0 / 2274 ) cutoffSlk: -468.0ps
stdDelay: 11.6ps
[04/04 16:53:49 466s] Iteration 10: Total net bbox = 6.191e+04 (3.10e+04
3.10e+04)

[04/04 16:53:49 466s]

3.76e+04)

Est. stn bbox = 7.508e+04 (3.75e+04

[04/04 16:53:49 466s]

1344.2M

cpu = 0:00:01.5 real = 0:00:01.0 mem =

[04/04 16:53:51 468s] Iteration 11: Total net bbox = 6.400e+04 (3.18e+04
3.22e+04)
[04/04 16:53:51 468s]
3.89e+04)

Est. stn bbox = 7.721e+04 (3.83e+04

[04/04 16:53:51 468s]

1344.2M

cpu = 0:00:01.5 real = 0:00:02.0 mem =

[04/04 16:53:51 468s] Iteration 12: Total net bbox = 6.400e+04 (3.18e+04
3.22e+04)
[04/04 16:53:51 468s]
3.89e+04)

Est. stn bbox = 7.721e+04 (3.83e+04

[04/04 16:53:51 468s]

1344.2M

cpu = 0:00:00.0 real = 0:00:00.0 mem =

[04/04 16:53:51 468s] *** cost = 6.400e+04 (3.18e+04 3.22e+04) (cpu for
global=0:00:09.2) real=0:00:09.0***
[04/04 16:53:51 468s] Info: 12 clock gating cells identified, 12 (on average)
moved
[04/04 16:53:51 468s] Core Placement runtime cpu: 0:00:04.9 real: 0:00:05.0
[04/04 16:53:51 469s] **WARN: (ENCSP-9025):
specified/traced.

No scan chain

[04/04 16:53:51 469s] Type 'man ENCSP-9025' for more detail.

[04/04 16:53:51 469s] Core basic site is CoreSite
[04/04 16:53:51 469s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 16:53:52 469s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 16:53:52 469s] *** Starting refinePlace (0:07:48 mem=1127.0M) ***
[04/04 16:53:52 469s] Total net length = 5.586e+04 (2.767e+04 2.819e+04)
(ext = 8.438e+03)
[04/04 16:53:52 469s] # spcSbClkGt: 12
[04/04 16:53:52 469s] Starting refinePlace ...
[04/04 16:53:52 469s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um

[04/04 16:53:52 469s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 16:53:52 469s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.3,
real=0:00:00.0, mem=1131.6MB) @(0:07:48 - 0:07:48).
[04/04 16:53:52 469s] Move report: preRPlace moves 2185 insts, mean move:
0.55 um, max move: 4.78 um
[04/04 16:53:52 469s] Max move on inst
(EXECUTE_INST/pc_reg[2]/state_remap/LTIEHI): (178.44, 123.76) --> (176.00,
121.41)
[04/04 16:53:52 469s]
cell type: TIEHI

Length: 3 sites, height: 1 rows, site name: CoreSite,

[04/04 16:53:52 469s] wireLenOptFixPriorityInst 0 inst fixed

[04/04 16:53:52 469s] Placement tweakage begins.
[04/04 16:53:52 469s] wire length = 6.917e+04
[04/04 16:53:52 469s] wire length = 6.878e+04
[04/04 16:53:52 469s] Placement tweakage ends.
[04/04 16:53:52 469s] Move report: tweak moves 517 insts, mean move: 3.30
um, max move: 19.91 um
[04/04 16:53:52 469s] Max move on inst
(EXECUTE_INST/pc_acc_reg/state_remap/DFF): (91.60, 157.32) --> (109.80,
155.61)
[04/04 16:53:52 469s] [CPU] RefinePlace/TweakPlacement (cpu=0:00:00.2,
real=0:00:00.0, mem=1131.6MB) @(0:07:48 - 0:07:49).
[04/04 16:53:52 469s] Move report: legalization moves 73 insts, mean move:
0.18 um, max move: 3.42 um
[04/04 16:53:52 469s] Max move on inst (EXECUTE_INST/g16376): (101.00,
177.84) --> (101.00, 181.26)
[04/04 16:53:52 469s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1131.6MB) @(0:07:49 - 0:07:49).
[04/04 16:53:52 469s] Move report: Detail placement moves 2185 insts, mean
move: 1.25 um, max move: 19.70 um
[04/04 16:53:52 469s] Max move on inst
(EXECUTE_INST/pc_acc_reg/state_remap/DFF): (91.45, 156.96) --> (109.80,
155.61)
[04/04 16:53:52 469s]
1131.6MB

Runtime: CPU: 0:00:00.5 REAL: 0:00:00.0 MEM:

[04/04 16:53:52 469s] Statistics of distance of Instance movement in refine

placement:
[04/04 16:53:52 469s] maximum (X+Y) =

19.70 um

[04/04 16:53:52 469s] inst (EXECUTE_INST/pc_acc_reg/state_remap/DFF) with

max move: (91.454, 156.964) -> (109.8, 155.61)
[04/04 16:53:52 469s] mean

(X+Y) =

1.25 um

[04/04 16:53:52 469s] Summary Report:

[04/04 16:53:52 469s] Instances move: 2185 (out of 2185 movable)
[04/04 16:53:52 469s] Mean displacement: 1.25 um
[04/04 16:53:52 469s] Max displacement: 19.70 um (Instance:
EXECUTE_INST/pc_acc_reg/state_remap/DFF) (91.454, 156.964) -> (109.8,
155.61)
[04/04 16:53:52 469s]
cell type: SDFFRX4

Length: 39 sites, height: 1 rows, site name: CoreSite,

[04/04 16:53:52 469s] Total instances moved : 2185

[04/04 16:53:52 469s] Total net length = 5.578e+04 (2.752e+04 2.826e+04)
(ext = 8.412e+03)
[04/04 16:53:52 469s] Runtime: CPU: 0:00:00.5 REAL: 0:00:00.0 MEM:
1131.6MB
[04/04 16:53:52 469s] [CPU] RefinePlace/total (cpu=0:00:00.5, real=0:00:00.0,
mem=1131.6MB) @(0:07:48 - 0:07:49).
[04/04 16:53:52 469s] *** Finished refinePlace (0:07:49 mem=1131.6M) ***
[04/04 16:53:52 469s] Total net length = 5.573e+04 (2.752e+04 2.821e+04)
(ext = 8.409e+03)
[04/04 16:53:52 469s] *** End of Placement (cpu=0:00:31.3, real=0:00:31.0,
mem=1131.6M) ***
[04/04 16:53:52 469s] Core basic site is CoreSite
[04/04 16:53:52 469s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 16:53:52 469s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 16:53:52 469s] default core: bins with density > 0.75 = 69.8 % ( 118 /
169 )
[04/04 16:53:52 469s] Density distribution unevenness ratio = 11.440%
[04/04 16:53:52 470s] *** Free Virtual Timing Model ...(mem=1131.6M)

[04/04 16:53:52 470s] Starting IO pin assignment...

[04/04 16:53:52 470s] Starting congestion repair ...
[04/04 16:53:52 470s] congRepair options: -clkGateAware 1
-rplaceIncrNPClkGateAwareMode 4.
[04/04 16:53:52 470s] *** Starting trialRoute (mem=1131.6M) ***
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 16:53:52 470s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 16:53:52 470s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 16:53:52 470s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Nr of prerouted/Fixed nets = 0
[04/04 16:53:52 470s] routingBox: (-200 -330) (220200 217310)
[04/04 16:53:52 470s] coreBox:

(0 0) (220000 216980)

[04/04 16:53:52 470s] Number of multi-gpin terms=2369, multi-gpins=5631,

moved blk term=63/63
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Phase 1a route (0:00:00.0 1131.6M):
[04/04 16:53:52 470s] Est net length = 6.389e+04um = 3.137e+04H +
3.252e+04V
[04/04 16:53:52 470s] Usage: (8.2%H 10.3%V) = (3.456e+04um
4.477e+04um) = (34555 26179)
[04/04 16:53:52 470s] Obstruct: 8394 = 4197 (15.0%H) + 4197 (15.0%V)
[04/04 16:53:52 470s] Overflow: 74 = 63 (0.27% H) + 11 (0.04% V)
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Phase 1b route (0:00:00.0 1131.6M):
[04/04 16:53:52 470s] Usage: (8.2%H 10.3%V) = (3.448e+04um
4.475e+04um) = (34481 26169)

[04/04 16:53:52 470s] Overflow: 10 = 0 (0.00% H) + 10 (0.04% V)

[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Phase 1c route (0:00:00.0 1131.6M):
[04/04 16:53:52 470s] Usage: (8.2%H 10.3%V) = (3.442e+04um
4.472e+04um) = (34421 26151)
[04/04 16:53:52 470s] Overflow: 9 = 0 (0.00% H) + 9 (0.04% V)
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Phase 1d route (0:00:00.0 1131.6M):
[04/04 16:53:52 470s] Usage: (8.2%H 10.3%V) = (3.442e+04um
4.472e+04um) = (34421 26151)
[04/04 16:53:52 470s] Overflow: 9 = 0 (0.00% H) + 9 (0.04% V)
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Phase 1a-1d Overflow: 0.00% H + 0.04% V (0:00:00.1
1131.6M)

[04/04 16:53:52 470s]

[04/04 16:53:52 470s] Phase 1e route (0:00:00.0 1131.6M):
[04/04 16:53:52 470s] Usage: (8.2%H 10.3%V) = (3.443e+04um
4.473e+04um) = (34430 26155)
[04/04 16:53:52 470s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Phase 1f route (0:00:00.0 1131.6M):
[04/04 16:53:52 470s] Usage: (8.2%H 10.3%V) = (3.443e+04um
4.473e+04um) = (34434 26156)
[04/04 16:53:52 470s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Congestion distribution:
[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Remain cntH

cntV

[04/04 16:53:52 470s] --------------------------------------

[04/04 16:53:52 470s] -------------------------------------[04/04 16:53:52 470s] 0:

0.00%

0.04%

[04/04 16:53:52 470s] 1:

0.00%

0.03%

[04/04 16:53:52 470s] 2:

0.00%

0.07%

[04/04 16:53:52 470s] 3:

0.01%

0.37%

[04/04 16:53:52 470s] 4:

0.02%

729

3.07%

[04/04 16:53:52 470s] 5:

2373699.97%

2289396.42%

[04/04 16:53:52 470s]

[04/04 16:53:52 470s]
[04/04 16:53:52 470s] Phase 1e-1f Overflow: 0.00% H + 0.00% V (0:00:00.0
1131.6M)

[04/04 16:53:52 470s] Global route (cpu=0.1s real=0.1s 1131.6M)

[04/04 16:53:52 470s] Updating RC grid for preRoute extraction ...
[04/04 16:53:52 470s] Initializing multi-corner capacitance tables ...
[04/04 16:53:53 470s] Initializing multi-corner resistance tables ...
[04/04 16:53:53 470s]
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] *** After '-updateRemainTrks' operation:
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] Usage: (8.4%H 10.8%V) = (3.542e+04um
4.700e+04um) = (35422 27484)
[04/04 16:53:53 470s] Overflow: 17 = 0 (0.00% H) + 17 (0.07% V)
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] Phase 1l Overflow: 0.00% H + 0.07% V (0:00:00.3
1139.6M)

[04/04 16:53:53 470s]

[04/04 16:53:53 470s] Congestion distribution:

[04/04 16:53:53 470s]

[04/04 16:53:53 470s] Remain cntH

cntV

0.00%

134

0.56%

[04/04 16:53:53 470s] 4:

0.08%

777

3.27%

[04/04 16:53:53 470s] 5:

2372399.92%

2274395.79%

[04/04 16:53:53 470s]

[04/04 16:53:53 470s]
[04/04 16:53:53 470s] *** Completed Phase 1 route (0:00:00.5 1139.6M) ***
[04/04 16:53:53 470s]
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] ** np local hotspot detection info verbose **
[04/04 16:53:53 470s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 16:53:53 470s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 16:53:53 470s]
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] Total length: 6.568e+04um, number of vias: 19627
[04/04 16:53:53 470s] M1(H) length: 1.898e+01um, number of vias: 8391
[04/04 16:53:53 470s] M2(V) length: 1.835e+04um, number of vias: 8073
[04/04 16:53:53 470s] M3(H) length: 2.536e+04um, number of vias: 1401

[04/04 16:53:53 470s] M4(V) length: 9.278e+03um, number of vias: 739

[04/04 16:53:53 470s] M5(H) length: 3.381e+03um, number of vias: 592
[04/04 16:53:53 470s] M6(V) length: 2.991e+03um, number of vias: 211
[04/04 16:53:53 470s] M7(H) length: 2.063e+03um, number of vias: 184
[04/04 16:53:53 470s] M8(V) length: 3.381e+03um, number of vias: 36
[04/04 16:53:53 470s] M9(H) length: 8.630e+02um
[04/04 16:53:53 470s] *** Completed Phase 2 route (0:00:00.2 1139.6M) ***
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] *** Finished all Phases (cpu=0:00:00.7 mem=1139.6M)
***
[04/04 16:53:53 470s] dbSprFixZeroViaCodes runtime= 0:00:00.0
[04/04 16:53:53 470s] Peak Memory Usage was 1139.6M
[04/04 16:53:53 470s] TrialRoute+GlbRouteEst total runtime= +0:00:00.7 =
0:00:05.5
[04/04 16:53:53 470s] TrialRoute full (called 7x) runtime= 0:00:05.1
[04/04 16:53:53 470s] TrialRoute check only (called 3x) runtime= 0:00:00.1
[04/04 16:53:53 470s] GlbRouteEst (called 13x) runtime= 0:00:00.4
[04/04 16:53:53 470s] *** Finished trialRoute (cpu=0:00:00.7 mem=1139.6M)
***
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] Local HotSpot Analysis: normalized max congestion
hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in
unit of 4 std-cell row bins)
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] ** np local hotspot detection info verbose **
[04/04 16:53:53 470s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 16:53:53 470s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] describeCongestion: hCong = 0.00 vCong = 0.00

[04/04 16:53:53 470s] Trial Route Overflow 0.000000(H) 0.070048(V).

[04/04 16:53:53 470s] Start repairing congestion with level 1.
[04/04 16:53:53 470s] Skipped repairing congestion.
[04/04 16:53:53 470s] End of congRepair (cpu=0:00:00.7, real=0:00:01.0)
[04/04 16:53:53 470s] *** Finishing placeDesign default flow ***
[04/04 16:53:53 470s] **placeDesign ... cpu = 0: 0:41, real = 0: 0:41, mem =
1124.8M **
[04/04 16:53:53 470s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 16:53:53 470s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13

Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 16:53:53 470s]
[04/04 16:53:53 470s] *** Summary of all messages that are not suppressed in
this session:
[04/04 16:53:53 470s] Severity ID

Count Summary

[04/04 16:53:53 470s] WARNING ENCDC-1629

was set to %d. T...

1 The default delay limit

[04/04 16:53:53 470s] WARNING ENCSP-9025

specified/traced.

1 No scan chain

[04/04 16:53:53 470s] WARNING ENCSP-9042

defined, -ignoreSca...

1 Scan chains were not

[04/04 16:53:53 470s] *** Message Summary: 3 warning(s), 0 error(s)

[04/04 16:53:53 470s]
[04/04 16:54:00 470s] <CMD> setDrawView place
[04/04 16:54:03 471s] <CMD> setLayerPreference allM0 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM1Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM1 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM2Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM2 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM3Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM3 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM4Cont -isVisible 0

[04/04 16:54:03 471s] <CMD> setLayerPreference allM4 -isVisible 0

[04/04 16:54:03 471s] <CMD> setLayerPreference allM5Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM5 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM6Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM6 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM7Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM7 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM8Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM8 -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM9Cont -isVisible 0
[04/04 16:54:03 471s] <CMD> setLayerPreference allM9 -isVisible 0
[04/04 16:54:06 471s] <CMD> zoomBox 63.906 126.801 109.684 79.445
[04/04 16:54:07 471s] <CMD> fit
[04/04 16:54:11 472s] <CMD> setLayerPreference allM0 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM1Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM1 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM2Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM2 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM3Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM3 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM4Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM4 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM5Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM5 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM6Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM6 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM7Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM7 -isVisible 1

[04/04 16:54:11 472s] <CMD> setLayerPreference allM8Cont -isVisible 1

[04/04 16:54:11 472s] <CMD> setLayerPreference allM8 -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM9Cont -isVisible 1
[04/04 16:54:11 472s] <CMD> setLayerPreference allM9 -isVisible 1
[04/04 16:54:25 472s] <CMD> timeDesign -preCTS -outDir gopi/prects
[04/04 16:54:25 472s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but
to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".
[04/04 16:54:25 472s] *** Starting trialRoute (mem=1124.8M) ***
[04/04 16:54:25 472s]
[04/04 16:54:25 472s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 16:54:25 472s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 16:54:25 472s] Start to check current routing status for nets...
[04/04 16:54:25 472s] All nets are already routed correctly.
[04/04 16:54:25 472s] TrialRoute+GlbRouteEst total runtime= +0:00:00.0 =
0:00:05.6
[04/04 16:54:25 472s] TrialRoute full (called 7x) runtime= 0:00:05.1
[04/04 16:54:25 472s] TrialRoute check only (called 4x) runtime= 0:00:00.1
[04/04 16:54:25 472s] GlbRouteEst (called 13x) runtime= 0:00:00.4
[04/04 16:54:25 472s] *** Finishing trialRoute (mem=1124.8M) ***
[04/04 16:54:25 472s]
[04/04 16:54:25 472s] Extraction called for design 'tdsp_core' of
instances=2189 and nets=2596 using extraction engine 'preRoute' .
[04/04 16:54:25 472s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 16:54:25 472s] Type 'man ENCEXT-3530' for more detail.
[04/04 16:54:25 472s] PreRoute RC Extraction called for design tdsp_core.

[04/04 16:54:25 472s] RC Extraction called in multi-corner(2) mode.

[04/04 16:54:25 472s] RCMode: PreRoute
[04/04 16:54:25 472s]

RC Corner Indexes

[04/04 16:54:25 472s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 16:54:25 472s] Resistance Scaling Factor

: 1.00000 1.00000

[04/04 16:54:25 472s] Clock Cap. Scaling Factor

: 1.00000 1.00000

[04/04 16:54:25 472s] Clock Res. Scaling Factor

: 1.00000 1.00000

[04/04 16:54:25 472s] Shrink Factor

: 1.00000

[04/04 16:54:25 472s] PreRoute extraction is honoring

NDR/Shielding/ExtraSpace for clock nets.
[04/04 16:54:25 472s] Using capacitance table file ...
[04/04 16:54:25 472s] Updating RC grid for preRoute extraction ...
[04/04 16:54:25 472s] Initializing multi-corner capacitance tables ...
[04/04 16:54:25 472s] Initializing multi-corner resistance tables ...
[04/04 16:54:25 472s] PreRoute RC Extraction DONE (CPU Time: 0:00:00.1 Real
Time: 0:00:00.0 MEM: 1124.832M)
[04/04 16:54:25 472s] Effort level <high> specified for reg2reg path_group
[04/04 16:54:25 472s] Effort level <high> specified for reg2cgate path_group
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13

[04/04 16:54:25 472s] Found active setup analysis view

Arise_analysis_view_test_nom_cmax_T25V12
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 16:54:25 472s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132

[04/04 16:54:25 472s] Found active hold analysis view

Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12

[04/04 16:54:25 472s] Found active hold analysis view

Arise_analysis_view_func_nom_cmin_T20V13
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 16:54:25 472s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 16:54:32 479s] AAE_THRD: End delay calculation. (MEM=1373.27
CPU=0:00:06.1 REAL=0:00:06.0)
[04/04 16:54:35 482s]

-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -5.059 | -2.396 | 0.201 | -5.059 |

TNS (ns):|-801.347 | -82.624 | 0.000 |-718.723 |

|
|

Violating Paths:| 269 | 43

| 226 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

| max_tran

3 (3)

| -0.311 |

41 (707)

| -10.391 |

4 (4)

41 (707)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 56.411%
Routing Overflow: 0.00% H and 0.07% V
-----------------------------------------------------------Reported timing to dir gopi/prects

[04/04 16:54:35 482s] Total CPU time: 10.1 sec

[04/04 16:54:35 482s] Total Real time: 10.0 sec
[04/04 16:54:35 482s] Total Memory Usage: 1337.105469 Mbytes
[04/04 16:54:41 482s] <CMD> setCTSMode -engine ck
[04/04 16:54:51 482s] <CMD> clockDesign -specFile ../../DATA/clock.ctstch
-outDir clock_report -fixedInstBeforeCTS
[04/04 16:54:51 482s] -engine ck
ccopt_from_edi_spec}, default=auto, user setting

# enums={ck ccopt auto

[04/04 16:54:51 482s] **clockDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1337.1M **
[04/04 16:54:51 482s] setCTSMode -engine ck -moveGateLimit 25
[04/04 16:54:51 482s] <clockDesign INFO> 'setCTSMode -routeClkNet true' is
set inside clockDesign.
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] <clockDesign CMD> cleanupSpecifyClockTree
[04/04 16:54:51 482s] <clockDesign CMD> specifyClockTree -file
../../DATA/clock.ctstch
[04/04 16:54:51 482s] Checking spec file integrity...
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] Reading clock tree spec file '../../DATA/clock.ctstch' ...
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] **WARN: (ENCCK-2070):
is obsolete.
[04/04 16:54:51 482s] RouteType

: FE_CTS_DEFAULT

[04/04 16:54:51 482s] PreferredExtraSpace

[04/04 16:54:51 482s] Shield
[04/04 16:54:51 482s] PreferLayer

The PadBufAfterGate option

: NONE
: M3 M4

[04/04 16:54:51 482s] RC Information for View

Arise_analysis_view_test_max_cmax_T150V08 :
[04/04 16:54:51 482s] Est. Cap
H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 16:54:51 482s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 16:54:51 482s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 16:54:51 482s] Est. Via Cap

: 0.0480942(ff)

[04/04 16:54:51 482s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

es=0.32(um) cap=0.109(ff/um) res=1.23(ohm/um) viaRes=0(ohm) viaCap=0(ff)
[04/04 16:54:51 482s] M2(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.04792(ohm)
viaCap=0.0558832(ff)
[04/04 16:54:51 482s] M3(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M4(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 16:54:51 482s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 16:54:51 482s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] RC Information for View
Arise_analysis_view_func_max_cmax_T150V08 :
[04/04 16:54:51 482s] Est. Cap
H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 16:54:51 482s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 16:54:51 482s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 16:54:51 482s] Est. Via Cap

: 0.0480942(ff)

[04/04 16:54:51 482s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

es=0.32(um) cap=0.109(ff/um) res=1.23(ohm/um) viaRes=0(ohm) viaCap=0(ff)
[04/04 16:54:51 482s] M2(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.04792(ohm)
viaCap=0.0558832(ff)
[04/04 16:54:51 482s] M3(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M4(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 16:54:51 482s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 16:54:51 482s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] RC Information for View
Arise_analysis_view_func_max_cmax_T140V102 :
[04/04 16:54:51 482s] Est. Cap
H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 16:54:51 482s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 16:54:51 482s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 16:54:51 482s] Est. Via Cap

: 0.0480942(ff)

[04/04 16:54:51 482s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

es=0.32(um) cap=0.109(ff/um) res=1.23(ohm/um) viaRes=0(ohm) viaCap=0(ff)
[04/04 16:54:51 482s] M2(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.04792(ohm)
viaCap=0.0558832(ff)
[04/04 16:54:51 482s] M3(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M4(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 16:54:51 482s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 16:54:51 482s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] RC Information for View
Arise_analysis_view_test_min_cmin_Tm20V15 :
[04/04 16:54:51 482s] Est. Cap
H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 16:54:51 482s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 16:54:51 482s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 16:54:51 482s] Est. Via Cap

: 0.0480942(ff)

[04/04 16:54:51 482s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

es=0.32(um) cap=0.109(ff/um) res=1.23(ohm/um) viaRes=0(ohm) viaCap=0(ff)
[04/04 16:54:51 482s] M2(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.04792(ohm)
viaCap=0.0558832(ff)
[04/04 16:54:51 482s] M3(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M4(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 16:54:51 482s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 16:54:51 482s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 16:54:51 482s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
04/04 16:54:51 482s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um) es=0.59(um)
cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.478584(ff)
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] RouteType

: FE_CTS_DEFAULT_LEAF

[04/04 16:54:51 482s] PreferredExtraSpace

[04/04 16:54:51 482s] Shield
[04/04 16:54:51 482s] PreferLayer

: NONE
: M3 M4

[04/04 16:54:51 482s] RC Information for View

Arise_analysis_view_test_max_cmax_T150V08 :

[04/04 16:54:51 482s] Est. Cap

H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 16:54:51 482s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 16:54:51 482s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 16:54:51 482s] Est. Via Cap

: 0.0480942(ff)

[04/04 16:54:51 482s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 16:54:51 482s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)

cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 16:54:51 482s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] Switching off Advanced RC Correlation modes in AAE
mode.
[04/04 16:54:51 482s] Active Analysis Views for CTS are,
[04/04 16:54:51 482s] #1 Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:54:51 482s] #2 Arise_analysis_view_func_max_cmax_T150V08
[04/04 16:54:51 482s] #3 Arise_analysis_view_func_max_cmax_T140V102
[04/04 16:54:51 482s] #4 Arise_analysis_view_func_max_cmax_T125V108
[04/04 16:54:51 482s] #5 Arise_analysis_view_test_max_cmax_T125V108
[04/04 16:54:51 482s] #6 Arise_analysis_view_func_nom_cmax_T25V12
[04/04 16:54:51 482s] #7 Arise_analysis_view_func_nom_cmax_T50V13
[04/04 16:54:51 482s] #8 Arise_analysis_view_test_nom_cmax_T25V12
[04/04 16:54:51 482s] #9 Arise_analysis_view_test_nom_cmax_T50V13
[04/04 16:54:51 482s] #10 Arise_analysis_view_func_nom_cmax_T15V11
[04/04 16:54:51 482s] #11 Arise_analysis_view_test_nom_cmax_T15V11
[04/04 16:54:51 482s] #12 Arise_analysis_view_func_max_cmin_T150V08
[04/04 16:54:51 482s] #13 Arise_analysis_view_test_max_cmin_T150V08
[04/04 16:54:51 482s] #14 Arise_analysis_view_func_max_cmin_T140V102
[04/04 16:54:51 482s] #15 Arise_analysis_view_test_max_cmin_T140V102
[04/04 16:54:51 482s] #16 Arise_analysis_view_func_max_cmin_T125V108
[04/04 16:54:51 482s] #17 Arise_analysis_view_test_max_cmin_T125V108
[04/04 16:54:51 482s] #18 Arise_analysis_view_func_nom_cmin_T25V12
[04/04 16:54:51 482s] #19 Arise_analysis_view_test_nom_cmin_T25V12

[04/04 16:54:51 482s] #20 Arise_analysis_view_func_nom_cmin_T20V13

[04/04 16:54:51 482s] #21 Arise_analysis_view_test_nom_cmin_T20V13
[04/04 16:54:51 482s] #22 Arise_analysis_view_func_nom_cmin_T15V11
[04/04 16:54:51 482s] #23 Arise_analysis_view_test_nom_cmin_T15V11
[04/04 16:54:51 482s] #24 Arise_analysis_view_func_min_cmin_T0V132
[04/04 16:54:51 482s] #25 Arise_analysis_view_test_min_cmin_T0V132
[04/04 16:54:51 482s] #26 Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 16:54:51 482s] #27 Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 16:54:51 482s] #28 Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 16:54:51 482s] #29 Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 16:54:51 482s] #30 Arise_analysis_view_func_min_cmax_T0V132
[04/04 16:54:51 482s] #31 Arise_analysis_view_test_min_cmax_T0V132
[04/04 16:54:51 482s] #32 Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 16:54:51 482s] #27 Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 16:54:51 482s] #28 Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 16:54:51 482s] #29 Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 16:54:51 482s] #30 Arise_analysis_view_func_min_cmax_T0V132
[04/04 16:54:51 482s] #31 Arise_analysis_view_test_min_cmax_T0V132
[04/04 16:54:51 482s] #32 Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 16:54:51 482s] #33 Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 16:54:51 482s] #34 Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 16:54:51 482s] #35 Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 16:54:51 482s] Default Analysis Views is
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:54:51 482s]
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] ****** AutoClockRootPin ******
[04/04 16:54:51 482s] AutoClockRootPin 1: clk
[04/04 16:54:51 482s] # NoGating

[04/04 16:54:51 482s] # SetDPinAsSync

[04/04 16:54:51 482s] # SetIoPinAsSync NO

[04/04 16:54:51 482s] # SetAsyncSRPinAsSync NO
[04/04 16:54:51 482s] # SetTriStEnPinAsSync NO
[04/04 16:54:51 482s] # SetBBoxPinAsSync NO
[04/04 16:54:51 482s] # RouteClkNet
[04/04 16:54:51 482s] # PostOpt

YES
YES

[04/04 16:54:51 482s] # RouteType

[04/04 16:54:51 482s] # LeafRouteType

FE_CTS_DEFAULT
FE_CTS_DEFAULT_LEAF

[04/04 16:54:51 482s]

[04/04 16:54:51 482s] ***** !! NOTE !! *****
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] CTS treats D-pins and I/O pins as non-synchronous pins
by default.
[04/04 16:54:51 482s] If you want to change the behavior, you need to use the
SetDPinAsSync
[04/04 16:54:51 482s] or SetIoPinAsSync statement in the clock tree
specification file,
[04/04 16:54:51 482s] or use the setCTSMode -traceDPinAsLeaf {true|false}
command,
[04/04 16:54:51 482s] or use the setCTSMode -traceIoPinAsLeaf {true|false}
command
[04/04 16:54:51 482s] before specifyClockTree command.
[04/04 16:54:51 482s]
[04/04 16:54:51 482s] *** End specifyClockTree (cpu=0:00:00.2,
real=0:00:00.0, mem=1347.1M) ***
[04/04 16:54:51 482s] <clockDesign CMD> changeClockStatus -all -fixedBuffers
[04/04 16:54:51 482s] Redoing specifyClockTree ...
[04/04 16:54:51 482s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 16:54:51 482s] Checking spec file integrity...

[04/04 16:54:52 482s] *** Changed status on (270) instances, and (0) nets in
Clock clk.
[04/04 16:54:52 483s] *** End changeClockStatus (cpu=0:00:00.2,
real=0:00:01.0, mem=1347.1M) ***
[04/04 16:54:52 483s] <clockDesign CMD> deleteClockTree -all
[04/04 16:54:52 483s] Redoing specifyClockTree ...
[04/04 16:54:52 483s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 16:54:52 483s] Checking spec file integrity...

[04/04 16:54:52 483s]
[04/04 16:54:52 483s] deleteClockTree Option : -all
[04/04 16:54:52 483s] List of dont use cells: HOLDX1
[04/04 16:54:52 483s] List of dont touch cells:
[04/04 16:54:52 483s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 16:54:52 483s] *** Removed (0) buffers and (0) inverters in Clock clk.
[04/04 16:54:52 483s] ***** Delete Clock Tree Finished (CPU Time: 0:00:00.0
MEM: 1347.113M)
[04/04 16:54:52 483s] *** End deleteClockTree (cpu=0:00:00.0, real=0:00:00.0,
mem=1347.1M) ***
[04/04 16:54:52 483s] <clockDesign CMD> ckSynthesis -report
clock_report/clock.report -forceReconvergent -breakLoop
[04/04 16:54:52 483s] Redoing specifyClockTree ...
[04/04 16:54:52 483s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 16:54:52 483s] Checking spec file integrity...

[04/04 16:54:52 483s] List of dont use cells: HOLDX1
[04/04 16:54:52 483s] List of dont touch cells:
[04/04 16:54:52 483s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 16:54:52 483s] ***** Allocate Placement Memory Finished (MEM:
1347.113M)
[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Start to trace clock trees ...

[04/04 16:54:52 483s] *** Begin Tracer (mem=1347.1M) ***
[04/04 16:54:52 483s] Tracing Clock clk ...
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Reconvergent mux Check for spec:clk
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Reconvergent mux Checks Finished, CPU=0:00:00.0
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s] *** End Tracer (mem=1347.1M) ***
[04/04 16:54:52 483s] ***** Allocate Obstruction Memory Finished (MEM:
1347.113M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s]
################################################
#############################
[04/04 16:54:52 483s] #
[04/04 16:54:52 483s] # Pre-Synthesis Checks and Parameters
[04/04 16:54:52 483s] #
[04/04 16:54:52 483s]
################################################
#############################
[04/04 16:54:52 483s]
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Types of Check
Disabled

Enabled|

[04/04 16:54:52 483s] ---------------------------------------------------------------------------[04/04 16:54:52 483s]

:
:

enabled
:

enabled

[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Parameters of checking :
[04/04 16:54:52 483s] CTS uses following values to determine if diagnostic
checks are successful.
[04/04 16:54:52 483s] Use setCTSMode to change default values.
[04/04 16:54:52 483s] ---------------------------------------------------------------------------[04/04 16:54:52 483s]
[04/04 16:54:52 483s] 1) Pin capacitance check
[04/04 16:54:52 483s]
of constraint (default)

Threshold for MaxCap check

90%

[04/04 16:54:52 483s] 2) Gating depth check

[04/04 16:54:52 483s]
levels (default)

Maximum gating depth

[04/04 16:54:52 483s] 3) Placement near clock pin check

[04/04 16:54:52 483s]
5.13(um) (default)

Threshold distance for placeable location

[04/04 16:54:52 483s] 4) Clock gating location check

[04/04 16:54:52 483s]

(default)

Allowed clock gate detour

290(um)

[04/04 16:54:52 483s]

0.5 (default)

180(ps) derived from 90% (default) MaxSinkTran constraint

[04/04 16:54:52 483s] Root Input Transition

0.1(ps)]

[0.1(ps)

[04/04 16:54:52 483s]

[04/04 16:54:52 483s]
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Max Cap Limit Checks
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Max Cap Limit Checks Finished, CPU=0:00:00.0
[04/04 16:54:52 483s]
================================================
============

[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Deep Gating Level Checks
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s] ** INFO Clock clk has a maximum of 1 levels of logic
before synthesis.
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Deep Gating Level Checks Finished, CPU=0:00:00.0
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Max placement distance Checks
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Max placement distance Checks Finished,
CPU=0:00:00.0
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Root input tran Checks
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Root input tran Checks Finished, CPU=0:00:00.0
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Routing OBS checks

[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Routing OBS Checks Finished, CPU=0:00:00.1
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] MacroModel Debugging Check
[04/04 16:54:52 483s] ==========================
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] MacroModel Debugging Check Finished, CPU=0:00:00.0
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Clock gating checks
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Clock gating Checks Finished, CPU=0:00:00.0
[04/04 16:54:52 483s]
================================================
============
[04/04 16:54:52 483s]
[04/04 16:54:52 483s]
################################################
#############################
[04/04 16:54:52 483s] #
[04/04 16:54:52 483s] # Summary of Pre-Synthesis Checks

[04/04 16:54:52 483s] #

[04/04 16:54:52 483s]
################################################
#############################
[04/04 16:54:52 483s]
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Types of Check
warnings

Number of

[04/04 16:54:52 483s] ---------------------------------------------------------------------------[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Check cell drive strength
0(disabled)

[04/04 16:54:52 483s] Check root input transition

[04/04 16:54:52 483s] Check pin capacitance

[04/04 16:54:52 483s] Check multiple path through MUX

[04/04 16:54:52 483s] Check gating depth

:
:

[04/04 16:54:52 483s] Check placement near clock pins

0
0

[04/04 16:54:52 483s] Check route blockages over clock pins

0
:

[04/04 16:54:52 483s] Report FIXED, DontUse and DontTouch

0(disabled)
[04/04 16:54:52 483s] clock gating checks
[04/04 16:54:52 483s] MacroModel checks

:
:

0
:

[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Switching off Advanced RC Correlation modes in AAE
mode.
[04/04 16:54:52 483s]
[04/04 16:54:52 483s]
################################################
#############################
[04/04 16:54:52 483s] #
[04/04 16:54:52 483s] # During-Synthesis Checks and Parameters

[04/04 16:54:52 483s] #

[04/04 16:54:52 483s]
################################################
#############################
[04/04 16:54:52 483s]
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Types of Check
Disabled

Enabled|

[04/04 16:54:52 483s] ---------------------------------------------------------------------------[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Check RefinePlacement move distance
enabled

[04/04 16:54:52 483s] Check route layer follows preference

enabled

[04/04 16:54:52 483s] Check route follows guide

[04/04 16:54:52 483s] clock gating checks

enabled

[04/04 16:54:52 483s] Wire resistance check

enabled
:

enabled

[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Parameters of checking :
[04/04 16:54:52 483s] CTS uses following values to determine if diagnostic
checks are successful.
[04/04 16:54:52 483s] Use setCTSMode to change default values.
[04/04 16:54:52 483s] ---------------------------------------------------------------------------[04/04 16:54:52 483s]
[04/04 16:54:52 483s] 1) Route layer follows preference check
[04/04 16:54:52 483s]
(default)

Minimum preferred layer utilization

(default)

Delay threshold

:
:

10(ps)

[04/04 16:54:52 483s] 3) Saving intermediate database

[04/04 16:54:52 483s]
0(min) (default)

Save long-running subtrees time

[04/04 16:54:52 483s]

(default)

Maximum number of saved databases

[04/04 16:54:52 483s] 4) Clock gating location check

[04/04 16:54:52 483s]
(default)

Allowed clock gate detour

290(um)

[04/04 16:54:52 483s] 5) Wire resistance check

[04/04 16:54:52 483s]
(default)

Allowed resistance deviation

[04/04 16:54:52 483s]

Ohm (user set)

Resistance threshold

0.2

97.15

[04/04 16:54:52 483s] Net length threshold for resistance checks

um (derived 200*M2 layer pitch)

[04/04 16:54:52 483s]

[04/04 16:54:52 483s]
[04/04 16:54:52 483s] ****** Clock (clk) Diagnostic check Parameters
[04/04 16:54:52 483s] Assumed driver input transition
28.4(ps) (derived from BUFX8)

[04/04 16:54:52 483s] Threshold for MaxBufTran check

180(ps) derived from 90% (default) MaxBufTran constraint

[04/04 16:54:52 483s] Threshold for MaxSinkTran check

180(ps) derived from 90% (default) MaxSinkTran constraint

[04/04 16:54:52 483s] Movement threshold

5.424500(um) (derived 5% of MaxBuf strength)
[04/04 16:54:52 483s] Root Input Transition
0.1(ps)]
[04/04 16:54:52 483s]
[04/04 16:54:52 483s]

:
:

[0.1(ps)

[04/04 16:54:52 483s]

[04/04 16:54:52 483s] ****** Clock Tree (clk) Structure
[04/04 16:54:52 483s] Max. Skew

: 20(ps)

[04/04 16:54:52 483s] Max. Sink Transition: 200(ps)

[04/04 16:54:52 483s] Max. Buf Transition : 200(ps)
[04/04 16:54:52 483s] Max. Delay

: 950(ps)

[04/04 16:54:52 483s] Min. Delay

: 950(ps)

[04/04 16:54:52 483s] Buffer

(BUFX8)

: (BUFX2) (BUFX3) (BUFX4) (BUFX6)

[04/04 16:54:52 483s] Nr. Subtrees

[04/04 16:54:52 483s] Nr. Sinks
[04/04 16:54:52 483s] Nr.

: 13
: 258

Rising Sync Pins : 258

[04/04 16:54:52 483s] Nr. Inverter Rising Sync Pins : 0

[04/04 16:54:52 483s] Nr.

Falling Sync Pins : 0

[04/04 16:54:52 483s] Nr. Inverter Falling Sync Pins : 0

[04/04 16:54:52 483s] Nr. Unsync Pins

[04/04 16:54:52 483s]

***********************************************************
[04/04 16:54:52 483s] SubTree No: 0
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(TDSP_CORE_MACH_INST/RC_CG_HIER_INST29/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(TDSP_CORE_MACH_INST/RC_CG_HIER_INST29/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (TDSP_CORE_MACH_INST/rc_gclk)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[250,250]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)

[04/04 16:54:52 483s] SubTree No: 1

[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(PROG_BUS_MACH_INST/RC_CG_HIER_INST28/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(PROG_BUS_MACH_INST/RC_CG_HIER_INST28/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (PROG_BUS_MACH_INST/rc_gclk)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[258,259]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 2
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(PORT_BUS_MACH_INST/RC_CG_HIER_INST27/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(PORT_BUS_MACH_INST/RC_CG_HIER_INST27/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (PORT_BUS_MACH_INST/rc_gclk)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[258,259]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 3
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH/ECK)

[04/04 16:54:52 483s] Output_Net: (EXECUTE_INST/rc_gclk_11928)

[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[261,262]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 4
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST25/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST25/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (EXECUTE_INST/rc_gclk_11925)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[250,250]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 5
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (EXECUTE_INST/rc_gclk_11922)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[254,254]ps N1 inTran=0/0ps.

[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,

real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 6
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST23/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST23/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (EXECUTE_INST/rc_gclk_11919)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=3[275,278]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 7
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST22/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST22/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (EXECUTE_INST/rc_gclk_11916)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=1[262,263]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 8
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST21/RC_CGIC_INST/LATCH/CK)

[04/04 16:54:52 483s] Output_Pin:

(EXECUTE_INST/RC_CG_HIER_INST21/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (EXECUTE_INST/rc_gclk_11913)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[263,264]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 9
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST20/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST20/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (EXECUTE_INST/rc_gclk)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=3[273,276]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 10
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(DECODE_INST/RC_CG_HIER_INST19/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(DECODE_INST/RC_CG_HIER_INST19/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (DECODE_INST/rc_gclk)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]

[04/04 16:54:52 483s] Macro model: Skew=1[270,271]ps N1 inTran=0/0ps.

[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 11
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin:
(DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/LATCH/CK)
[04/04 16:54:52 483s] Output_Pin:
(DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/LATCH/ECK)
[04/04 16:54:52 483s] Output_Net: (DATA_BUS_MACH_INST/rc_gclk)
[04/04 16:54:52 483s] **** CK_START: Macro Models Generation
(mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Macro model: Skew=0[259,260]ps N1 inTran=0/0ps.
[04/04 16:54:52 483s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1359.1M)
[04/04 16:54:52 483s] SubTree No: 12
[04/04 16:54:52 483s]
[04/04 16:54:52 483s] Input_Pin: (NULL)
[04/04 16:54:52 483s] Output_Pin: (clk)
[04/04 16:54:52 483s] Output_Net: (clk)
[04/04 16:54:52 483s] **** CK_START: TopDown Tree Construction for clk (58leaf) (12 macro model) (mem=1359.1M)
[04/04 16:54:52 483s]
[04/04 16:54:54 485s] Total 3 topdown clustering.
[04/04 16:54:54 485s] Trig. Edge Skew=*31[374,406*] N58 B4 G13 A7(7.2)
L[2,5] C1/3 score=61430 cpu=0:00:01.0 mem=1357M
[04/04 16:54:54 485s]
[04/04 16:54:54 485s] **** CK_END: TopDown Tree Construction for clk
(cpu=0:00:01.5, real=0:00:02.0, mem=1357.1M)
[04/04 16:54:54 485s]

[04/04 16:54:54 485s]

[04/04 16:54:54 485s]
[04/04 16:54:54 485s] **** CK_START: Update Database (mem=1357.1M)
[04/04 16:54:54 485s] 4 Clock Buffers/Inverters inserted.
[04/04 16:54:54 485s] **** CK_END: Update Database (cpu=0:00:00.0,
real=0:00:00.0, mem=1357.1M)
[04/04 16:54:54 485s]
[04/04 16:54:54 485s] Refine place movement check
[04/04 16:54:54 485s]
================================================
============
[04/04 16:54:54 485s]
[04/04 16:54:54 485s]
[04/04 16:54:54 485s] **INFO: The distance threshold for maximum refine
placement move is 5.424500 microns (5% of max driving distance).
[04/04 16:54:54 485s]
[04/04 16:54:54 485s] ***** Start Refine Placement.....
[04/04 16:54:54 485s] *** Starting refinePlace (0:08:04 mem=1357.1M) ***
[04/04 16:54:54 485s] Total net length = 5.598e+04 (2.761e+04 2.837e+04)
(ext = 8.160e+03)
[04/04 16:54:54 485s] Starting refinePlace ...
[04/04 16:54:54 485s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 16:54:54 485s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 16:54:54 485s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.6,
real=0:00:00.0, mem=1362.7MB) @(0:08:04 - 0:08:05).
[04/04 16:54:54 485s] Move report: preRPlace moves 151 insts, mean move:
0.06 um, max move: 0.48 um
[04/04 16:54:54 485s] Max move on inst (TDSP_CORE_GLUE_INST/g8486):
(106.20, 160.74) --> (105.78, 160.80)
[04/04 16:54:54 485s]
cell type: AO22X4

Length: 11 sites, height: 1 rows, site name: CoreSite,

[04/04 16:54:54 485s] wireLenOptFixPriorityInst 4 inst fixed

[04/04 16:54:54 485s] Move report: legalization moves 163 insts, mean move:
0.70 um, max move: 5.52 um
[04/04 16:54:54 485s] Max move on inst (EXECUTE_INST/g16227): (111.44,
157.26) --> (113.60, 153.90)
[04/04 16:54:54 485s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1362.7MB) @(0:08:05 - 0:08:05).
[04/04 16:54:54 485s] Move report: Detail placement moves 81 insts, mean
move: 1.40 um, max move: 5.62 um
[04/04 16:54:54 485s] Max move on inst (EXECUTE_INST/g16227): (111.40,
157.32) --> (113.60, 153.90)
[04/04 16:54:54 485s]
1362.7MB

Runtime: CPU: 0:00:00.6 REAL: 0:00:00.0 MEM:

[04/04 16:54:54 485s] Statistics of distance of Instance movement in refine

placement:
[04/04 16:54:54 485s] maximum (X+Y) =

5.62 um

[04/04 16:54:54 485s] inst (EXECUTE_INST/g16227) with max move: (111.4,

157.32) -> (113.6, 153.9)
[04/04 16:54:54 485s] mean

(X+Y) =

1.40 um

[04/04 16:54:54 485s] Summary Report:

[04/04 16:54:54 485s] Instances move: 81 (out of 1919 movable)
[04/04 16:54:54 485s] Mean displacement: 1.40 um
[04/04 16:54:54 485s] Max displacement: 5.62 um (Instance:
EXECUTE_INST/g16227) (111.4, 157.32) -> (113.6, 153.9)
[04/04 16:54:54 485s]
cell type: CLKINVX2

Length: 4 sites, height: 1 rows, site name: CoreSite,

[04/04 16:54:54 485s] Total instances moved : 81

[04/04 16:54:54 485s] Total net length = 5.598e+04 (2.761e+04 2.837e+04)
(ext = 8.160e+03)
[04/04 16:54:54 485s] Runtime: CPU: 0:00:00.7 REAL: 0:00:00.0 MEM:
1362.7MB
[04/04 16:54:54 485s] [CPU] RefinePlace/total (cpu=0:00:00.7, real=0:00:00.0,
mem=1362.7MB) @(0:08:04 - 0:08:05).
[04/04 16:54:54 485s] *** Finished refinePlace (0:08:05 mem=1362.7M) ***

[04/04 16:54:54 485s] ***** Refine Placement Finished (CPU Time: 0:00:00.8
MEM: 1362.676M)
[04/04 16:54:54 485s] **WARN: (ENCCK-6323):
The placement of
EXECUTE_INST/g16227 was moved by 5.62 microns during refinePlace. Original
location : (111.4, 157.32), Refined location : (113.6, 153.9)
[04/04 16:54:54 485s]
[04/04 16:54:54 485s]
[04/04 16:54:54 485s] **INFO: Total instances moved beyond threshold limit
during refinePlace are 1...
[04/04 16:54:54 485s]
[04/04 16:54:55 485s]
[04/04 16:54:55 485s] Refine place movement check finished, CPU=0:00:00.9
[04/04 16:54:55 485s]
================================================
============
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:54:55 486s] ********** Clock clk Pre-Route Timing Analysis **********
[04/04 16:54:55 486s] Nr. of Subtrees

: 13

[04/04 16:54:55 486s] Nr. of Sinks

: 258

[04/04 16:54:55 486s] Nr. of Buffer

[04/04 16:54:55 486s] Nr. of Level (including gates) : 4

[04/04 16:54:55 486s] Root Rise Input Tran
[04/04 16:54:55 486s] Root Fall Input Tran

: 0.1(ps)
: 0.1(ps)

[04/04 16:54:55 486s] No Driving Cell Specified!

[04/04 16:54:55 486s] Max trig. edge delay at sink(R):
EXECUTE_INST/p_reg[12]/state_remap/DFF/CK 406.3(ps)
[04/04 16:54:55 486s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_6_reg/state_remap/DFF/CK 375(ps)
[04/04 16:54:55 486s]
[04/04 16:54:55 486s]

[04/04 16:54:55 486s]

(Actual)

[04/04 16:54:55 486s] Rise Phase Delay

950~950(ps)

(Required)

: 375~406.3(ps)

[04/04 16:54:55 486s] Fall Phase Delay

950~950(ps)

: 352~416.8(ps)

[04/04 16:54:55 486s] Trig. Edge Skew

: 31.3(ps)

[04/04 16:54:55 486s] Rise Skew

[04/04 16:54:55 486s] Fall Skew
[04/04 16:54:55 486s] Max. Rise Buffer Tran.

: 31.3(ps)
: 64.8(ps)
: 87.5(ps)

[04/04 16:54:55 486s] Max. Fall Buffer Tran.

: 97.5(ps)

[04/04 16:54:55 486s] Max. Rise Sink Tran.

: 133.5(ps)

[04/04 16:54:55 486s] Max. Fall Sink Tran.

[04/04 16:54:55 486s] Min. Rise Buffer Tran.

20(ps)

: 151.3(ps)
: 20.3(ps)

200(ps)
200(ps)
200(ps)
200(ps)
0(ps)

[04/04 16:54:55 486s] Min. Fall Buffer Tran.

: 20.3(ps)

0(ps)

[04/04 16:54:55 486s] Min. Rise Sink Tran.

: 41.5(ps)

0(ps)

[04/04 16:54:55 486s] Min. Fall Sink Tran.

: 31(ps)

0(ps)

[04/04 16:54:55 486s]

[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 21.4ps (required = 20ps)

[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew

= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 31.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 21.4ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 19.8ps (required = 20ps)

[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmin_Tm20V15 :

skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 19.8ps (required = 20ps)
[04/04 16:54:55 486s]
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 16:54:55 486s]
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] Switching to the default view
'Arise_analysis_view_test_max_cmax_T150V08'...
[04/04 16:54:55 486s] *** Look For Reconvergent Clock Component ***
[04/04 16:54:55 486s] The clock tree clk has no reconvergent cell.
[04/04 16:54:55 486s] Reducing the latency of clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] Calculating pre-route downstream delay for clock tree
'clk'...

[04/04 16:54:55 486s] *** Look For PreservePin And Optimized CrossOver Root
Pin ***
[04/04 16:54:55 486s] moving 'clk__L1_I0' from (109000 210330) to (103000
155610)
[04/04 16:54:55 486s] MaxTriggerDelay: 404.8 (ps)
[04/04 16:54:55 486s] MinTriggerDelay: 374.9 (ps)
[04/04 16:54:55 486s] Skew: 29.9 (ps)
[04/04 16:54:55 486s] *** Finished Latency Reduction ((cpu=0:00:00.0
real=0:00:00.0 mem=1362.7M) ***
[04/04 16:54:55 486s] Reducing the skew of clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] MaxTriggerDelay: 404.8 (ps)
[04/04 16:54:55 486s] MinTriggerDelay: 374.9 (ps)
[04/04 16:54:55 486s] Skew: 29.9 (ps)
[04/04 16:54:55 486s] *** Finished Skew Reduction ((cpu=0:00:00.0
real=0:00:00.0 mem=1362.7M) ***
[04/04 16:54:55 486s] Resized (BUFX2->BUFX3): clk__L3_I0
[04/04 16:54:55 486s] resized 1 standard cell(s).
[04/04 16:54:55 486s] inserted 0 standard cell(s).
[04/04 16:54:55 486s] deleted 0 standard cell(s).
[04/04 16:54:55 486s] moved 1 standard cell(s).
[04/04 16:54:55 486s] *** Optimized Clock Tree Latency (cpu=0:00:00.0
real=0:00:00.0 mem=1362.7M) ***
[04/04 16:54:55 486s] Doing the final refine placement ...
[04/04 16:54:55 486s] ***** Start Refine Placement.....
[04/04 16:54:55 486s] *** Starting refinePlace (0:08:05 mem=1362.7M) ***
[04/04 16:54:55 486s] Total net length = 5.606e+04 (2.763e+04 2.843e+04)
(ext = 8.219e+03)
[04/04 16:54:55 486s] Starting refinePlace ...

[04/04 16:54:55 486s] Move report: placeLevelShifters moves 0 insts, mean

move: 0.00 um, max move: 0.00 um
[04/04 16:54:55 486s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 16:54:55 486s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.0,
real=0:00:00.0, mem=1362.7MB) @(0:08:05 - 0:08:05).
[04/04 16:54:55 486s] Move report: preRPlace moves 0 insts, mean move: 0.00
um, max move: 0.00 um
[04/04 16:54:55 486s] wireLenOptFixPriorityInst 4 inst fixed
[04/04 16:54:55 486s] Move report: legalization moves 0 insts, mean move:
0.00 um, max move: 0.00 um
[04/04 16:54:55 486s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1362.7MB) @(0:08:05 - 0:08:05).
[04/04 16:54:55 486s] Move report: Detail placement moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 16:54:55 486s]
1362.7MB

Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:

[04/04 16:54:55 486s] Statistics of distance of Instance movement in refine

placement:
[04/04 16:54:55 486s] maximum (X+Y) =
[04/04 16:54:55 486s] mean

(X+Y) =

0.00 um
0.00 um

[04/04 16:54:55 486s] Summary Report:

[04/04 16:54:55 486s] Instances move: 0 (out of 1919 movable)
[04/04 16:54:55 486s] Mean displacement: 0.00 um
[04/04 16:54:55 486s] Max displacement: 0.00 um
[04/04 16:54:55 486s] Total instances moved : 0
[04/04 16:54:55 486s] Total net length = 5.606e+04 (2.763e+04 2.843e+04)
(ext = 8.219e+03)
[04/04 16:54:55 486s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
1362.7MB
[04/04 16:54:55 486s] [CPU] RefinePlace/total (cpu=0:00:00.0, real=0:00:00.0,
mem=1362.7MB) @(0:08:05 - 0:08:05).
[04/04 16:54:55 486s] *** Finished refinePlace (0:08:05 mem=1362.7M) ***

[04/04 16:54:55 486s] ***** Refine Placement Finished (CPU Time: 0:00:00.3
MEM: 1362.676M)
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:54:55 486s] ********** Clock clk Pre-Route Timing Analysis **********
[04/04 16:54:55 486s] Nr. of Subtrees

: 13

[04/04 16:54:55 486s] Nr. of Sinks

: 258

[04/04 16:54:55 486s] Nr. of Buffer

[04/04 16:54:55 486s] Nr. of Level (including gates) : 4

[04/04 16:54:55 486s] Root Rise Input Tran

: 0.1(ps)

[04/04 16:54:55 486s] Root Fall Input Tran

: 0.1(ps)

[04/04 16:54:55 486s] No Driving Cell Specified!

[04/04 16:54:55 486s] Max trig. edge delay at sink(R):
EXECUTE_INST/p_reg[12]/state_remap/DFF/CK 404.8(ps)
[04/04 16:54:55 486s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_6_reg/state_remap/DFF/CK 374.9(ps)
[04/04 16:54:55 486s]
[04/04 16:54:55 486s]
[04/04 16:54:55 486s]

(Actual)

[04/04 16:54:55 486s] Rise Phase Delay

950~950(ps)

(Required)

: 374.9~404.8(ps)

[04/04 16:54:55 486s] Fall Phase Delay

950~950(ps)

: 352~395.8(ps)

[04/04 16:54:55 486s] Trig. Edge Skew

: 29.9(ps)

[04/04 16:54:55 486s] Rise Skew

[04/04 16:54:55 486s] Fall Skew
[04/04 16:54:55 486s] Max. Rise Buffer Tran.

: 29.9(ps)
: 43.8(ps)
: 87.8(ps)

[04/04 16:54:55 486s] Max. Fall Buffer Tran.

: 97.9(ps)

[04/04 16:54:55 486s] Max. Rise Sink Tran.

: 133.6(ps)

[04/04 16:54:55 486s] Max. Fall Sink Tran.

20(ps)

: 151.2(ps)

200(ps)
200(ps)
200(ps)
200(ps)

[04/04 16:54:55 486s] Min. Rise Buffer Tran.

: 21.1(ps)

0(ps)

[04/04 16:54:55 486s] Min. Fall Buffer Tran.

: 21.2(ps)

0(ps)

[04/04 16:54:55 486s] Min. Rise Sink Tran.

: 41.5(ps)

0(ps)

[04/04 16:54:55 486s] Min. Fall Sink Tran.

: 31(ps)

0(ps)

[04/04 16:54:55 486s]

[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 29.9ps (required = 20ps)

[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmin_T140V102 :

skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 19.1ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 16.3ps (required = 20ps)

[04/04 16:54:55 486s] view Arise_analysis_view_func_min_cmax_Tm40V15 :

skew = 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 16.3ps (required = 20ps)
[04/04 16:54:55 486s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 16.3ps (required = 20ps)
[04/04 16:54:55 486s]
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] Generating Clock Analysis Report
clock_report/clock.report ....
[04/04 16:54:55 486s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 16:54:55 486s]
[04/04 16:54:55 486s]
[04/04 16:54:55 486s] *** ckSynthesis Opt Latency (cpu=0:00:00.7
real=0:00:00.0 mem=1362.7M) ***
[04/04 16:54:56 487s] ***** Start Refine Placement.....
[04/04 16:54:56 487s] *** Starting refinePlace (0:08:06 mem=1358.1M) ***
[04/04 16:54:56 487s] Total net length = 5.632e+04 (2.776e+04 2.856e+04)
(ext = 8.219e+03)
[04/04 16:54:56 487s] Starting refinePlace ...
[04/04 16:54:56 487s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 16:54:56 487s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 16:54:56 487s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.1,
real=0:00:00.0, mem=1358.1MB) @(0:08:06 - 0:08:06).
[04/04 16:54:56 487s] Move report: preRPlace moves 27 insts, mean move:
0.02 um, max move: 0.17 um
[04/04 16:54:56 487s] Max move on inst (TDSP_CORE_GLUE_INST/g8509):
(87.80, 83.79) --> (87.91, 83.84)
[04/04 16:54:56 487s]
cell type: AOI222X4

Length: 28 sites, height: 1 rows, site name: CoreSite,

[04/04 16:54:56 487s] wireLenOptFixPriorityInst 10 inst fixed

[04/04 16:54:56 487s] Move report: legalization moves 32 insts, mean move:
0.48 um, max move: 3.29 um
[04/04 16:54:56 487s] Max move on inst
(TDSP_CORE_GLUE_INST/lsh_120_82/g2922): (93.02, 88.92) --> (94.60, 87.21)
[04/04 16:54:56 487s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1358.1MB) @(0:08:06 - 0:08:06).
[04/04 16:54:56 487s] Move report: Detail placement moves 10 insts, mean
move: 1.48 um, max move: 3.31 um
[04/04 16:54:56 487s] Max move on inst
(TDSP_CORE_GLUE_INST/lsh_120_82/g2922): (93.00, 88.92) --> (94.60, 87.21)
[04/04 16:54:56 487s]
1358.1MB

Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM:

[04/04 16:54:56 487s] Statistics of distance of Instance movement in refine

placement:
[04/04 16:54:56 487s] maximum (X+Y) =

3.31 um

[04/04 16:54:56 487s] inst (TDSP_CORE_GLUE_INST/lsh_120_82/g2922) with

max move: (93, 88.92) -> (94.6, 87.21)
[04/04 16:54:56 487s] mean

(X+Y) =

1.48 um

[04/04 16:54:56 487s] Summary Report:

[04/04 16:54:56 487s] Instances move: 10 (out of 1925 movable)
[04/04 16:54:56 487s] Mean displacement: 1.48 um
[04/04 16:54:56 487s] Max displacement: 3.31 um (Instance:
TDSP_CORE_GLUE_INST/lsh_120_82/g2922) (93, 88.92) -> (94.6, 87.21)
[04/04 16:54:56 487s]
cell type: AO21X4

Length: 10 sites, height: 1 rows, site name: CoreSite,

[04/04 16:54:56 487s] Total instances moved : 10

[04/04 16:54:56 487s] Total net length = 5.632e+04 (2.776e+04 2.856e+04)
(ext = 8.219e+03)
[04/04 16:54:56 487s] Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM:
1358.1MB
[04/04 16:54:56 487s] [CPU] RefinePlace/total (cpu=0:00:00.1, real=0:00:00.0,
mem=1358.1MB) @(0:08:06 - 0:08:06).
[04/04 16:54:56 487s] *** Finished refinePlace (0:08:06 mem=1358.1M) ***

[04/04 16:54:56 487s] ***** Refine Placement Finished (CPU Time: 0:00:00.4
MEM: 1358.145M)
[04/04 16:54:56 487s]
[04/04 16:54:56 487s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:54:56 487s] ********** Clock clk Pre-Route Timing Analysis **********
[04/04 16:54:56 487s] Nr. of Subtrees

: 13

[04/04 16:54:56 487s] Nr. of Sinks

: 258

[04/04 16:54:56 487s] Nr. of Buffer

: 10

[04/04 16:54:56 487s] Nr. of Level (including gates) : 10

[04/04 16:54:56 487s] Root Rise Input Tran

: 0.1(ps)

[04/04 16:54:56 487s] Root Fall Input Tran

: 0.1(ps)

[04/04 16:54:56 487s] No Driving Cell Specified!

[04/04 16:54:56 487s] Max trig. edge delay at sink(R):
EXECUTE_INST/p_reg[12]/state_remap/DFF/CK 954.9(ps)
[04/04 16:54:56 487s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_6_reg/state_remap/DFF/CK 925.8(ps)
[04/04 16:54:56 487s]
[04/04 16:54:56 487s]
[04/04 16:54:56 487s]

(Actual)

[04/04 16:54:56 487s] Rise Phase Delay

950~950(ps)

(Required)

: 925.8~954.9(ps)

[04/04 16:54:56 487s] Fall Phase Delay

950~950(ps)

: 903.4~947.2(ps)

[04/04 16:54:56 487s] Trig. Edge Skew

: 29.1(ps)

[04/04 16:54:56 487s] Rise Skew

[04/04 16:54:56 487s] Fall Skew

: 31(ps)

0(ps)

[04/04 16:54:56 487s]

[04/04 16:54:56 487s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 29.1ps (required = 20ps)

[04/04 16:54:56 487s] view Arise_analysis_view_test_max_cmin_T140V102 :

skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 29.1ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 18.2ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 15.4ps (required = 20ps)

[04/04 16:54:56 487s] view Arise_analysis_view_func_min_cmax_Tm40V15 :

skew = 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 15.4ps (required = 20ps)
[04/04 16:54:56 487s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 15.4ps (required = 20ps)
[04/04 16:54:56 487s]
[04/04 16:54:56 487s]
[04/04 16:54:56 487s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 16:54:56 487s]
[04/04 16:54:56 487s]
[04/04 16:54:56 487s]
[04/04 16:54:56 487s] globalDetailRoute
[04/04 16:54:56 487s]
[04/04 16:54:56 487s] #setNanoRouteMode -drouteAutoStop false
[04/04 16:54:56 487s] #setNanoRouteMode -drouteEndIteration 5
[04/04 16:54:56 487s] #setNanoRouteMode -drouteStartIteration 0
[04/04 16:54:56 487s] #setNanoRouteMode -routeSelectedNetOnly true
[04/04 16:54:56 487s] #setNanoRouteMode -routeWithEco true
[04/04 16:54:56 487s] #setNanoRouteMode -routeWithTimingDriven false
[04/04 16:54:56 487s] #Start globalDetailRoute on Mon Apr 4 16:54:56 2016
[04/04 16:54:56 487s] #
[04/04 16:54:56 487s] ### Ignoring a total of 1 master slice layers:
[04/04 16:54:56 487s] ### Oxide
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[0] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[1] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[2] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.

[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[3] in CELL_VIEW

mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[4] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[5] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[6] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[7] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[8] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[9] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[10] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[11] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[12] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[13] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[14] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[15] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[16] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[17] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[18] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (NRDB-728) PIN result[19] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 16:54:56 487s] #WARNING (EMS-27) Message (NRDB-728) has exceeded
the current message display limit of 20.

[04/04 16:54:56 487s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 16:54:57 488s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 16:54:57 488s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 16:54:57 488s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 16:54:57 488s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 16:54:57 488s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 16:54:57 488s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 16:54:57 488s] #WARNING (NRDB-976) The TRACK STEP 0.1900 for
preferred direction tracks is smaller than the PITCH 0.2000 for LAYER Metal3. This
will cause routability problems for NanoRoute.
[04/04 16:54:57 488s] #WARNING (NRDB-976) The TRACK STEP 0.1900 for
preferred direction tracks is smaller than the PITCH 0.2000 for LAYER Metal5. This
will cause routability problems for NanoRoute.
[04/04 16:54:57 488s] #NanoRoute Version v14.28-s005 NR1603131959/14_28-UB
[04/04 16:54:57 488s] #Bottom routing layer is M1, bottom routing layer for
shielding is M1, bottom shield layer is M1
[04/04 16:54:57 488s] #Start routing data preparation.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.

[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal5 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal5 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal5 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal5 is not specified for width 0.070.

[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal7 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal7 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal7 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal7 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal9 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal9 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.
[04/04 16:54:57 488s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 16:54:57 488s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal2 is not specified for width 0.070.

0.445

H Track-Pitch = 0.285

Line-2-Via Pitch =

[04/04 16:55:00 491s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 16:55:00 491s] # Metal8
0.385

V Track-Pitch = 0.200

Line-2-Via Pitch =

[04/04 16:55:00 491s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 16:55:00 491s] # Metal9
0.385

H Track-Pitch = 0.380

Line-2-Via Pitch =

[04/04 16:55:00 491s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 16:55:00 491s] #Regenerating Ggrids automatically.
[04/04 16:55:00 491s] #Auto generating G-grids with size=15 tracks, using
layer Metal2's pitch = 0.200.
[04/04 16:55:00 491s] #Using automatically generated G-grids.
[04/04 16:55:00 491s] #Done routing data preparation.
[04/04 16:55:00 491s] #cpu time = 00:00:03, elapsed time = 00:00:03,
memory = 1233.61 (MB), peak = 1396.38 (MB)
[04/04 16:55:00 491s] #Merging special wires...
[04/04 16:55:00 491s] #reading routing guides ......
[04/04 16:55:00 491s] #Number of eco nets is 0
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Start data preparation...
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Data preparation is done on Mon Apr 4 16:55:00 2016
[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] #Analyzing routing resource...

[04/04 16:55:00 491s] #Routing resource analysis is done on Mon Apr 4
16:55:00 2016
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] # Resource Analysis:
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] # Layer
Blocked

Routing #Avail
Direction Track

405

107

5329

17.56%

[04/04 16:55:00 491s] # Metal 9

482

5329

14.82%

[04/04 16:55:00 491s] # -------------------------------------------------------------[04/04 16:55:00 491s] # Total

3777

48.32% 47961

46.42%

[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] # 23 nets (0.88%) with 1 preferred extra spacing.
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Routing guide is on.
[04/04 16:55:00 491s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1234.73 (MB), peak = 1396.38 (MB)
[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] #start global routing iteration 1...

[04/04 16:55:00 491s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1235.25 (MB), peak = 1396.38 (MB)
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #start global routing iteration 2...
[04/04 16:55:00 491s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1235.25 (MB), peak = 1396.38 (MB)
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Total number of trivial nets (e.g. < 2 pins) = 322
(skipped).
[04/04 16:55:00 491s] #Total number of selected nets for routing = 23.
[04/04 16:55:00 491s] #Total number of unselected nets (but routable) for
routing = 2261 (skipped).
[04/04 16:55:00 491s] #Total number of nets in the design = 2606.
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #2261 skipped nets do not have any wires.
[04/04 16:55:00 491s] #23 routable nets have only global wires.
[04/04 16:55:00 491s] #23 global routed or unrouted (routable) nets have been
constrained (e.g. have preferred extra spacing, require shielding etc.)
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Routed net constraints summary:
[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

Rules Pref Extra Space Unconstrained

[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

Default

[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

Total

[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] #Routing constraints summary of the whole design:

[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

Rules Pref Extra Space Unconstrained

[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

Default

2261

[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

Total

2261

[04/04 16:55:00 491s] #-----------------------------------------------[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] # Congestion Analysis: (blocked Gcells are excluded)
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] # Metal 5

[04/04 16:55:00 491s] # Metal 6

[04/04 16:55:00 491s] # Metal 7

[04/04 16:55:00 491s] #-----------------------

[04/04 16:55:00 491s] #

801

[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] #Max overcon = 0 track.
[04/04 16:55:00 491s] #Total overcon = 0.00%.
[04/04 16:55:00 491s] #Worst layer Gcell overcon rate = 0.00%.
[04/04 16:55:00 491s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1235.37 (MB), peak = 1396.38 (MB)
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Start data preparation for track assignment...
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Data preparation is done on Mon Apr 4 16:55:00 2016
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1235.38 (MB), peak = 1396.38 (MB)
[04/04 16:55:00 491s] #Start Track Assignment.
[04/04 16:55:00 491s] #Done with 186 horizontal wires in 1 hboxes and 170
vertical wires in 1 hboxes.
[04/04 16:55:00 491s] #Done with 9 horizontal wires in 1 hboxes and 1 vertical
wires in 1 hboxes.
[04/04 16:55:00 491s] #Complete Track Assignment.
[04/04 16:55:00 491s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 16:55:00 491s] #Total wire length = 2121 um.
[04/04 16:55:00 491s] #Total half perimeter of net bounding box = 1480 um.
[04/04 16:55:00 491s] #Total wire length on LAYER Metal1 = 0 um.
[04/04 16:55:00 491s] #Total wire length on LAYER Metal2 = 12 um.
[04/04 16:55:00 491s] #Total wire length on LAYER Metal3 = 1058 um.
[04/04 16:55:00 491s] #Total wire length on LAYER Metal4 = 996 um.
[04/04 16:55:00 491s] #Total wire length on LAYER Metal5 = 8 um.

[04/04 16:55:00 491s] #Total wire length on LAYER Metal6 = 3 um.

[04/04 16:55:00 491s] #Total wire length on LAYER Metal7 = 26 um.
[04/04 16:55:00 491s] #Total wire length on LAYER Metal8 = 18 um.
[04/04 16:55:00 491s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 16:55:00 491s] #Total number of vias = 801
[04/04 16:55:00 491s] #Up-Via Summary (total 801):
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #----------------------[04/04 16:55:00 491s] # Metal 1

302

[04/04 16:55:00 491s] # Metal 2

254

[04/04 16:55:00 491s] # Metal 3

228

[04/04 16:55:00 491s] # Metal 4

[04/04 16:55:00 491s] # Metal 5

[04/04 16:55:00 491s] # Metal 6

[04/04 16:55:00 491s] # Metal 7

[04/04 16:55:00 491s] #----------------------[04/04 16:55:00 491s] #

801

[04/04 16:55:00 491s] #

[04/04 16:55:00 491s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1203.33 (MB), peak = 1396.38 (MB)
[04/04 16:55:00 491s] #
[04/04 16:55:00 491s] #Cpu time = 00:00:04
[04/04 16:55:00 491s] #Elapsed time = 00:00:04
[04/04 16:55:00 491s] #Increased memory = 12.04 (MB)
[04/04 16:55:00 491s] #Total memory = 1203.33 (MB)
[04/04 16:55:00 491s] #Peak memory = 1396.38 (MB)
[04/04 16:55:01 492s] #
[04/04 16:55:01 492s] #Start Detail Routing..
[04/04 16:55:01 492s] #start initial detail routing ...

[04/04 16:55:04 495s] # ECO: 3.5% of the total area was rechecked for DRC,
and 27.1% required routing.
[04/04 16:55:04 495s] #

number of violations = 0

[04/04 16:55:04 495s] #cpu time = 00:00:02, elapsed time = 00:00:02,

memory = 1273.43 (MB), peak = 1396.38 (MB)
[04/04 16:55:04 495s] #start 1st optimization iteration ...
[04/04 16:55:04 495s] #

number of violations = 0

[04/04 16:55:04 495s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1273.53 (MB), peak = 1396.38 (MB)
[04/04 16:55:04 495s] #Complete Detail Routing.
[04/04 16:55:04 495s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 16:55:04 495s] #Total wire length = 2148 um.
[04/04 16:55:04 495s] #Total half perimeter of net bounding box = 1480 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal1 = 23 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal2 = 131 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal3 = 1033 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal4 = 961 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal5 = 0 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 16:55:04 495s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 16:55:04 495s] #Total number of vias = 863
[04/04 16:55:04 495s] #Up-Via Summary (total 863):
[04/04 16:55:04 495s] #
[04/04 16:55:04 495s] #----------------------[04/04 16:55:04 495s] # Metal 1

312

[04/04 16:55:04 495s] # Metal 2

257

[04/04 16:55:04 495s] # Metal 3

294

[04/04 16:55:04 495s] #----------------------[04/04 16:55:04 495s] #

863

[04/04 16:55:04 495s] #

[04/04 16:55:04 495s] #Total number of DRC violations = 0
[04/04 16:55:04 495s] #Cpu time = 00:00:03
[04/04 16:55:04 495s] #Elapsed time = 00:00:03
[04/04 16:55:04 495s] #Increased memory = 70.20 (MB)
[04/04 16:55:04 495s] #Total memory = 1273.53 (MB)
[04/04 16:55:04 495s] #Peak memory = 1396.38 (MB)
[04/04 16:55:04 495s] #detailRoute Statistics:
[04/04 16:55:04 495s] #Cpu time = 00:00:03
[04/04 16:55:04 495s] #Elapsed time = 00:00:03
[04/04 16:55:04 495s] #Increased memory = 70.20 (MB)
[04/04 16:55:04 495s] #Total memory = 1273.53 (MB)
[04/04 16:55:04 495s] #Peak memory = 1396.38 (MB)
[04/04 16:55:04 495s] #
[04/04 16:55:04 495s] #globalDetailRoute statistics:
[04/04 16:55:04 495s] #Cpu time = 00:00:07
[04/04 16:55:04 495s] #Elapsed time = 00:00:07
[04/04 16:55:04 495s] #Increased memory = -90.35 (MB)
[04/04 16:55:04 495s] #Total memory = 1089.49 (MB)
[04/04 16:55:04 495s] #Peak memory = 1396.38 (MB)
[04/04 16:55:04 495s] #Number of warnings = 78
[04/04 16:55:04 495s] #Total number of warnings = 156
[04/04 16:55:04 495s] #Number of fails = 0
[04/04 16:55:04 495s] #Total number of fails = 0
[04/04 16:55:04 495s] #Complete globalDetailRoute on Mon Apr 4 16:55:04
2016
[04/04 16:55:04 495s] #

[04/04 16:55:04 495s] *** Look For Un-Routed Clock Tree Net ***
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] Routing correlation check
[04/04 16:55:04 495s]
================================================
============
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] Min length threshold value is :: 40 microns
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] Allowed deviation from route guide is 50%
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] **WARN: (ENCCK-6328):
The utilization of preferred
routing layers (layer M3 to M4) for net "EXECUTE_INST/rc_gclk" is 0.762498
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] Routing correlation check finished, CPU=0:00:00.0
[04/04 16:55:04 495s]
================================================
============
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] Wire resistance checks
[04/04 16:55:04 495s]
================================================
============
[04/04 16:55:04 495s] Calculating clock delays in preRoute mode...
[04/04 16:55:04 495s] Calculating clock delays in clkRouteOnly mode...
[04/04 16:55:04 495s] Updating RC grid for preRoute extraction ...
[04/04 16:55:04 495s] Initializing multi-corner capacitance tables ...
[04/04 16:55:04 495s] Initializing multi-corner resistance tables ...
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
DATA_BUS_MACH_INST/rc_gclk has 48.7373 percent resistance deviation between
preRoute resistance (189.377 ohm) and after route resistance (369.425 ohm)
values. This may indicate correlation issues like jogging in routing for this net.

[04/04 16:55:04 495s] **WARN: (ENCCK-6350):

Clock net
EXECUTE_INST/rc_gclk_11916 has 47.7953 percent resistance deviation between
preRoute resistance (214.159 ohm) and after route resistance (410.229 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
PROG_BUS_MACH_INST/rc_gclk has 46.2945 percent resistance deviation
between preRoute resistance (183.855 ohm) and after route resistance (342.339
ohm) values. This may indicate correlation issues like jogging in routing for this
net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
DECODE_INST/rc_gclk has 45.6104 percent resistance deviation between
preRoute resistance (402.318 ohm) and after route resistance (739.696 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11928 has 44.6472 percent resistance deviation between
preRoute resistance (218.783 ohm) and after route resistance (395.252 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11919 has 41.2375 percent resistance deviation between
preRoute resistance (442.01 ohm) and after route resistance (752.197 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11913 has 40.3871 percent resistance deviation between
preRoute resistance (260.501 ohm) and after route resistance (436.988 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
PORT_BUS_MACH_INST/rc_gclk has 40.2652 percent resistance deviation between
preRoute resistance (191.465 ohm) and after route resistance (320.525 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net clk__L4_N0 has
37.0342 percent resistance deviation between preRoute resistance (748.952
ohm) and after route resistance (1189.46 ohm) values. This may indicate
correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk has 36.4403 percent resistance deviation between
preRoute resistance (418.299 ohm) and after route resistance (658.119 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 16:55:04 495s] **WARN: (ENCCK-6350):
Clock net
clk__L1_N0__CASCADE_L7_N0 has 22.633 percent resistance deviation between
preRoute resistance (404.998 ohm) and after route resistance (523.477 ohm)
values. This may indicate correlation issues like jogging in routing for this net.

[04/04 16:55:04 495s]

[04/04 16:55:04 495s] Wire resistance checks Finished, CPU=0:00:00.1
[04/04 16:55:04 495s]
================================================
============
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:55:04 495s] ********** Clock clk Clk-Route-Only Timing Analysis
**********
[04/04 16:55:04 495s] Nr. of Subtrees

: 13

[04/04 16:55:04 495s] Nr. of Sinks

: 258

[04/04 16:55:04 495s] Nr. of Buffer

: 10

[04/04 16:55:04 495s] Nr. of Level (including gates) : 10

[04/04 16:55:04 495s] Root Rise Input Tran

: 0.1(ps)

[04/04 16:55:04 495s] Root Fall Input Tran

: 0.1(ps)

[04/04 16:55:04 495s] No Driving Cell Specified!

[04/04 16:55:04 495s] Max trig. edge delay at sink(R):
EXECUTE_INST/p_reg[12]/state_remap/DFF/CK 958(ps)
[04/04 16:55:04 495s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 928.1(ps)
[04/04 16:55:04 495s]
[04/04 16:55:04 495s]
[04/04 16:55:04 495s]

(Actual)

(Required)

[04/04 16:55:04 495s] Rise Phase Delay

950~950(ps)

: 928.1~958(ps)

[04/04 16:55:04 495s] Fall Phase Delay

950~950(ps)

: 906.2~950.9(ps)

[04/04 16:55:04 495s] Trig. Edge Skew

: 29.9(ps)

[04/04 16:55:04 495s] Rise Skew

[04/04 16:55:04 495s] Fall Skew

: 29.9(ps)
: 44.7(ps)

20(ps)

[04/04 16:55:04 495s] Max. Rise Buffer Tran.

: 92.5(ps)

200(ps)

[04/04 16:55:04 495s] Max. Fall Buffer Tran.

: 103.2(ps)

200(ps)

[04/04 16:55:04 495s] Max. Rise Sink Tran.

: 135.8(ps)

200(ps)

[04/04 16:55:04 495s] Max. Fall Sink Tran.

[04/04 16:55:04 495s] Min. Rise Buffer Tran.

: 153.8(ps)
: 20.1(ps)

200(ps)
0(ps)

[04/04 16:55:04 495s] Min. Fall Buffer Tran.

: 19.9(ps)

0(ps)

[04/04 16:55:04 495s] Min. Rise Sink Tran.

: 41.5(ps)

0(ps)

[04/04 16:55:04 495s] Min. Fall Sink Tran.

: 31(ps)

0(ps)

[04/04 16:55:04 495s]

[04/04 16:55:04 495s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 29.9ps (required = 20ps)

[04/04 16:55:04 495s] view Arise_analysis_view_test_max_cmin_T150V08 :

skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 15.8ps (required = 20ps)

[04/04 16:55:04 495s] view Arise_analysis_view_test_min_cmax_T0V132 : skew

= 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:04 495s]
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 16:55:04 495s]
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_max_cmax_T150V08'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_max_cmax_T150V08'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_max_cmax_T140V102'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_max_cmax_T125V108'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_max_cmax_T125V108'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_nom_cmax_T25V12'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_nom_cmax_T50V13'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_nom_cmax_T25V12'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_nom_cmax_T50V13'...

[04/04 16:55:04 495s] setting up for view

'Arise_analysis_view_func_nom_cmax_T15V11'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_nom_cmax_T15V11'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_max_cmin_T150V08'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_max_cmin_T150V08'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_max_cmin_T140V102'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_max_cmin_T140V102'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_max_cmin_T125V108'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_max_cmin_T125V108'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_nom_cmin_T25V12'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_nom_cmin_T25V12'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_nom_cmin_T20V13'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_nom_cmin_T20V13'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_nom_cmin_T15V11'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_nom_cmin_T15V11'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_min_cmin_T0V132'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_min_cmin_T0V132'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_min_cmin_Tm20V15'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_min_cmin_Tm20V15'...

[04/04 16:55:04 495s] setting up for view

'Arise_analysis_view_func_min_cmin_Tm40V18'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_min_cmin_Tm40V18'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_min_cmax_T0V132'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_min_cmax_T0V132'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm20V15'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm40V15'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_min_cmax_Tm40V15'...
[04/04 16:55:04 495s] setting up for view
'Arise_analysis_view_test_min_cmax_Tm20V15'...
[04/04 16:55:04 495s] View 'Arise_analysis_view_func_max_cmax_T150V08' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_max_cmax_T125V108' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_nom_cmax_T25V12' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_nom_cmax_T50V13' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_nom_cmax_T15V11' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_max_cmin_T150V08' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_max_cmin_T140V102' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_max_cmin_T125V108' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_nom_cmin_T25V12' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_nom_cmin_T20V13' in
clock tree 'clk' is redundant

[04/04 16:55:04 495s] View 'Arise_analysis_view_test_nom_cmin_T15V11' in

clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_min_cmin_T0V132' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_min_cmin_Tm20V15' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_min_cmin_Tm40V18' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_min_cmax_T0V132' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_func_min_cmax_Tm40V15' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] View 'Arise_analysis_view_test_min_cmax_Tm20V15' in
clock tree 'clk' is redundant
[04/04 16:55:04 495s] Selecting the worst MMMC view of clock tree 'clk' ...
[04/04 16:55:04 495s] Optimizing clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] Calculating clk-route-only downstream delay for clock
tree 'clk' ...
[04/04 16:55:04 495s] *** Look For Reconvergent Clock Component ***
[04/04 16:55:04 495s] The clock tree clk has no reconvergent cell.
[04/04 16:55:04 495s] *** Look For PreservePin And Optimized CrossOver Root
Pin ***
[04/04 16:55:04 495s] resized 0 standard cell(s).
[04/04 16:55:04 495s] inserted 0 standard cell(s).
[04/04 16:55:04 495s] *** Gated Clock Tree Optimization (cpu=0:00:00.1
real=0:00:00.0 mem=1259.0M) ***
[04/04 16:55:04 495s] *** Finished Clock Tree Skew Optimization
(cpu=0:00:00.1 real=0:00:00.0 mem=1259.0M) ***
[04/04 16:55:04 495s]
[04/04 16:55:04 495s] None of the clock tree buffers/gates are modified by the
skew optimization.
[04/04 16:55:04 495s]

[04/04 16:55:04 495s] Switching to the default view

'Arise_analysis_view_test_max_cmax_T150V08' ...
[04/04 16:55:05 495s] Tuning the min phase delay of clock tree 'clk' ...
[04/04 16:55:05 495s]
[04/04 16:55:05 495s] Calculating clk-route-only downstream delay for clock
tree 'clk' ...
[04/04 16:55:05 495s] resized 0 standard cell(s).
[04/04 16:55:05 495s] inserted 0 standard cell(s).
[04/04 16:55:05 495s] *** Tuned Min Phase Delay (cpu=0:00:00.1
mem=1259.0M) ***
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] *** None of the buffer chains at roots are modified by the
fine-tune process.
[04/04 16:55:05 496s]
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:55:05 496s] ********** Clock clk Clk-Route-Only Timing Analysis
**********
[04/04 16:55:05 496s] Nr. of Subtrees

: 13

[04/04 16:55:05 496s] Nr. of Sinks

: 258

[04/04 16:55:05 496s] Nr. of Buffer

: 10

[04/04 16:55:05 496s] Nr. of Level (including gates) : 10

[04/04 16:55:05 496s] Root Rise Input Tran
[04/04 16:55:05 496s] Root Fall Input Tran

: 0.1(ps)
: 0.1(ps)

[04/04 16:55:05 496s] No Driving Cell Specified!

[04/04 16:55:05 496s] Max trig. edge delay at sink(R):
EXECUTE_INST/p_reg[12]/state_remap/DFF/CK 958(ps)
[04/04 16:55:05 496s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 928.1(ps)
[04/04 16:55:05 496s]

[04/04 16:55:05 496s]

(Actual)

(Required)

[04/04 16:55:05 496s] Rise Phase Delay

950~950(ps)

: 928.1~958(ps)

[04/04 16:55:05 496s] Fall Phase Delay

950~950(ps)

: 906.2~950.9(ps)

[04/04 16:55:05 496s] Trig. Edge Skew

: 29.9(ps)

[04/04 16:55:05 496s] Rise Skew

[04/04 16:55:05 496s] Fall Skew

20(ps)

: 29.9(ps)
: 44.7(ps)

[04/04 16:55:05 496s] Max. Rise Buffer Tran.

: 92.5(ps)

200(ps)

[04/04 16:55:05 496s] Max. Fall Buffer Tran.

: 103.2(ps)

200(ps)

[04/04 16:55:05 496s] Max. Rise Sink Tran.

: 135.8(ps)

200(ps)

[04/04 16:55:05 496s] Max. Fall Sink Tran.

[04/04 16:55:05 496s] Min. Rise Buffer Tran.

: 153.8(ps)
: 20.1(ps)

200(ps)
0(ps)

[04/04 16:55:05 496s] Min. Fall Buffer Tran.

: 19.9(ps)

0(ps)

[04/04 16:55:05 496s] Min. Rise Sink Tran.

: 41.5(ps)

0(ps)

[04/04 16:55:05 496s] Min. Fall Sink Tran.

: 31(ps)

0(ps)

[04/04 16:55:05 496s]

[04/04 16:55:05 496s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 18.9ps (required = 20ps)

[04/04 16:55:05 496s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew

= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 29.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 18.9ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 15.8ps (required = 20ps)

[04/04 16:55:05 496s] view Arise_analysis_view_func_min_cmin_Tm20V15 :

skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 15.8ps (required = 20ps)
[04/04 16:55:05 496s]
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] Clock clk has been routed. Routing guide will not be
generated.
[04/04 16:55:05 496s] Generating Clock Analysis Report
clock_report/clock.report ....
[04/04 16:55:05 496s] Generating Clock Routing Guide tdsp_core.rguide ....
[04/04 16:55:05 496s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 16:55:05 496s]
[04/04 16:55:05 496s]
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] Clock gating checks

[04/04 16:55:05 496s]

================================================
============
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] Clock gating Checks Finished, CPU=0:00:00.0
[04/04 16:55:05 496s]
================================================
============
[04/04 16:55:05 496s]
[04/04 16:55:05 496s]
################################################
#############################
[04/04 16:55:05 496s] #
[04/04 16:55:05 496s] # Summary of During-Synthesis Checks
[04/04 16:55:05 496s] #
[04/04 16:55:05 496s]
################################################
#############################
[04/04 16:55:05 496s]
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] Types of Check
warnings

Number of

[04/04 16:55:05 496s] ---------------------------------------------------------------------------[04/04 16:55:05 496s]

[04/04 16:55:05 496s] Check RefinePlacement move distance

[04/04 16:55:05 496s] Check route layer follows preference

[04/04 16:55:05 496s] Check route follows guide

[04/04 16:55:05 496s] clock gating checks
[04/04 16:55:05 496s] Wire resistance checks

:
:

1
0

[04/04 16:55:05 496s]

[04/04 16:55:05 496s] *** End ckSynthesis (cpu=0:00:13.7, real=0:00:13.0,
mem=1259.0M) ***

[04/04 16:55:05 496s] <clockDesign CMD> specifyClockTree -update

{AutoCTSRootPin * PostOpt YES}
[04/04 16:55:05 496s] <clockDesign CMD> ckECO -postCTS
-useSpecFileCellsOnly -report clock_report/clock.postCTS.report
[04/04 16:55:05 496s] Redoing specifyClockTree ...
[04/04 16:55:05 496s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 16:55:05 496s] Checking spec file integrity...

[04/04 16:55:05 496s] List of dont use cells: HOLDX1
[04/04 16:55:05 496s] List of dont touch cells:
[04/04 16:55:05 496s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 16:55:05 496s] ***** Doing trialRoute -handlePreroute.
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] *** Starting trialRoute (mem=1259.0M) ***
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 16:55:05 496s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 16:55:05 496s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 16:55:05 496s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] Nr of prerouted/Fixed nets = 23
[04/04 16:55:05 496s] There are 23 nets with 1 extra space.
[04/04 16:55:05 496s] routingBox: (-200 -330) (220200 217310)
[04/04 16:55:05 496s] coreBox:

(0 0) (220000 216980)

[04/04 16:55:05 496s] There are 23 prerouted nets with extraSpace.

[04/04 16:55:05 496s] Number of multi-gpin terms=2363, multi-gpins=5611,
moved blk term=63/63
[04/04 16:55:05 496s]

[04/04 16:55:05 496s] Phase 1a route (0:00:00.0 1259.0M):

[04/04 16:55:05 496s] Est net length = 6.241e+04um = 3.061e+04H +
3.180e+04V
[04/04 16:55:05 496s] Usage: (8.9%H 11.1%V) = (3.737e+04um
4.836e+04um) = (37374 28277)
[04/04 16:55:05 496s] Obstruct: 8394 = 4197 (15.0%H) + 4197 (15.0%V)
[04/04 16:55:05 496s] Overflow: 72 = 65 (0.27% H) + 8 (0.03% V)
[04/04 16:55:05 496s]
[04/04 16:55:05 496s] Phase 1b route (0:00:00.0 1259.0M):
[04/04 16:55:05 496s] Usage: (8.9%H 11.1%V) = (3.730e+04um
4.834e+04um) = (37299 28266)
[04/04 16:55:05 496s] Overflow: 7 = 0 (0.00% H) + 7 (0.03% V)
[04/04 16:55:05 496s]
[04/04 16:55:06 496s] Phase 1c route (0:00:00.0 1259.0M):
[04/04 16:55:06 496s] Usage: (8.9%H 11.1%V) = (3.724e+04um
4.830e+04um) = (37241 28247)
[04/04 16:55:06 496s] Overflow: 6 = 0 (0.00% H) + 6 (0.02% V)
[04/04 16:55:06 496s]
[04/04 16:55:06 496s] Phase 1d route (0:00:00.0 1259.0M):
[04/04 16:55:06 496s] Usage: (8.9%H 11.1%V) = (3.724e+04um
4.830e+04um) = (37241 28247)
[04/04 16:55:06 496s] Overflow: 6 = 0 (0.00% H) + 6 (0.02% V)
[04/04 16:55:06 496s]
[04/04 16:55:06 496s] Phase 1a-1d Overflow: 0.00% H + 0.02% V (0:00:00.1
1259.0M)

0.03%

786

3.31%

[04/04 16:55:06 496s] 5:

2373199.95%

2284096.20%

[04/04 16:55:06 496s]

[04/04 16:55:06 496s]
[04/04 16:55:06 496s] Phase 1e-1f Overflow: 0.00% H + 0.00% V (0:00:00.0
1259.0M)

[04/04 16:55:06 496s] Global route (cpu=0.1s real=0.1s 1259.0M)

[04/04 16:55:06 496s] Updating RC grid for preRoute extraction ...
[04/04 16:55:06 496s] Initializing multi-corner capacitance tables ...
[04/04 16:55:06 496s] Initializing multi-corner resistance tables ...
[04/04 16:55:06 497s] There are 23 prerouted nets with extraSpace.
[04/04 16:55:06 497s]
[04/04 16:55:06 497s]

0.01%

127

0.53%

[04/04 16:55:06 497s] 4:

0.07%

820

3.45%

[04/04 16:55:06 497s] 5:

2372099.90%

2269795.59%

[04/04 16:55:06 497s]

[04/04 16:55:06 497s]
[04/04 16:55:06 497s] *** Completed Phase 1 route (0:00:00.4 1259.0M) ***
[04/04 16:55:06 497s]
[04/04 16:55:06 497s]

[04/04 16:55:06 497s] Total length: 6.651e+04um, number of vias: 19788

[04/04 16:55:06 497s] M1(H) length: 4.158e+01um, number of vias: 8421
[04/04 16:55:06 497s] M2(V) length: 1.855e+04um, number of vias: 8077
[04/04 16:55:06 497s] M3(H) length: 2.579e+04um, number of vias: 1608
[04/04 16:55:06 497s] M4(V) length: 9.918e+03um, number of vias: 687
[04/04 16:55:06 497s] M5(H) length: 3.209e+03um, number of vias: 560
[04/04 16:55:06 497s] M6(V) length: 2.763e+03um, number of vias: 213
[04/04 16:55:06 497s] M7(H) length: 2.104e+03um, number of vias: 186
[04/04 16:55:06 497s] M8(V) length: 3.280e+03um, number of vias: 36
[04/04 16:55:06 497s] M9(H) length: 8.544e+02um
[04/04 16:55:06 497s] *** Completed Phase 2 route (0:00:00.2 1259.0M) ***
[04/04 16:55:06 497s]
[04/04 16:55:06 497s] *** Finished all Phases (cpu=0:00:00.7 mem=1259.0M)
***
[04/04 16:55:06 497s] dbSprFixZeroViaCodes runtime= 0:00:00.0
[04/04 16:55:06 497s] Peak Memory Usage was 1259.0M
[04/04 16:55:06 497s] TrialRoute+GlbRouteEst total runtime= +0:00:00.7 =
0:00:06.3
[04/04 16:55:06 497s] TrialRoute full (called 8x) runtime= 0:00:05.8
[04/04 16:55:06 497s] TrialRoute check only (called 4x) runtime= 0:00:00.1
[04/04 16:55:06 497s] GlbRouteEst (called 13x) runtime= 0:00:00.4
[04/04 16:55:06 497s] *** Finished trialRoute (cpu=0:00:00.7 mem=1259.0M)
***
[04/04 16:55:06 497s]
[04/04 16:55:06 497s] Extraction called for design 'tdsp_core' of
instances=2199 and nets=2606 using extraction engine 'preRoute' .
[04/04 16:55:06 497s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 16:55:06 497s] Type 'man ENCEXT-3530' for more detail.
[04/04 16:55:06 497s] PreRoute RC Extraction called for design tdsp_core.

[04/04 16:55:06 497s] RC Extraction called in multi-corner(2) mode.

[04/04 16:55:06 497s] RCMode: PreRoute
[04/04 16:55:06 497s]

RC Corner Indexes

[04/04 16:55:06 497s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 16:55:06 497s] Resistance Scaling Factor

: 1.00000 1.00000

[04/04 16:55:06 497s] Clock Cap. Scaling Factor

: 1.00000 1.00000

[04/04 16:55:06 497s] Clock Res. Scaling Factor

: 1.00000 1.00000

[04/04 16:55:06 497s] Shrink Factor

: 1.00000

[04/04 16:55:06 497s] PreRoute extraction is honoring

NDR/Shielding/ExtraSpace for clock nets.
[04/04 16:55:06 497s] Using capacitance table file ...
[04/04 16:55:06 497s] Updating RC grid for preRoute extraction ...
[04/04 16:55:06 497s] Initializing multi-corner capacitance tables ...
[04/04 16:55:06 497s] Initializing multi-corner resistance tables ...
[04/04 16:55:06 497s] PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real
Time: 0:00:00.0 MEM: 1258.965M)
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_max_cmax_T150V08'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_max_cmax_T150V08'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_max_cmax_T140V102'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_max_cmax_T125V108'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_max_cmax_T125V108'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_nom_cmax_T25V12'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_nom_cmax_T50V13'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_nom_cmax_T25V12'...

[04/04 16:55:06 497s] setting up for view

'Arise_analysis_view_test_nom_cmax_T50V13'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_nom_cmax_T15V11'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_nom_cmax_T15V11'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_max_cmin_T150V08'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_max_cmin_T150V08'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_max_cmin_T140V102'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_max_cmin_T140V102'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_max_cmin_T125V108'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_max_cmin_T125V108'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_nom_cmin_T25V12'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_nom_cmin_T25V12'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_nom_cmin_T20V13'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_nom_cmin_T20V13'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_nom_cmin_T15V11'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_nom_cmin_T15V11'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_min_cmin_T0V132'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_min_cmin_T0V132'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_min_cmin_Tm20V15'...

[04/04 16:55:06 497s] setting up for view

'Arise_analysis_view_test_min_cmin_Tm20V15'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_min_cmin_Tm40V18'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_min_cmin_Tm40V18'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_min_cmax_T0V132'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_min_cmax_T0V132'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm20V15'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm40V15'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_min_cmax_Tm40V15'...
[04/04 16:55:06 497s] setting up for view
'Arise_analysis_view_test_min_cmax_Tm20V15'...
[04/04 16:55:06 497s] View 'Arise_analysis_view_func_max_cmax_T150V08' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_max_cmax_T125V108' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_nom_cmax_T25V12' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_nom_cmax_T50V13' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_nom_cmax_T15V11' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_max_cmin_T150V08' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_max_cmin_T140V102' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_max_cmin_T125V108' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_nom_cmin_T25V12' in
clock tree 'clk' is redundant

[04/04 16:55:06 497s] View 'Arise_analysis_view_test_nom_cmin_T20V13' in

clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_nom_cmin_T15V11' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_min_cmin_T0V132' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_min_cmin_Tm20V15' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_min_cmin_Tm40V18' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_min_cmax_T0V132' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_func_min_cmax_Tm40V15' in
clock tree 'clk' is redundant
[04/04 16:55:06 497s] View 'Arise_analysis_view_test_min_cmax_Tm20V15' in
clock tree 'clk' is redundant
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:55:07 498s] ********** Clock clk Post-CTS Timing Analysis **********
[04/04 16:55:07 498s] Nr. of Subtrees

: 13

[04/04 16:55:07 498s] Nr. of Sinks

: 258

[04/04 16:55:07 498s] Nr. of Buffer

: 10

[04/04 16:55:07 498s] Nr. of Level (including gates) : 10

[04/04 16:55:07 498s] Root Rise Input Tran
[04/04 16:55:07 498s] Root Fall Input Tran

: 0.1(ps)
: 0.1(ps)

[04/04 16:55:07 498s] No Driving Cell Specified!

[04/04 16:55:07 498s] Max trig. edge delay at sink(R):
EXECUTE_INST/p_reg[12]/state_remap/DFF/CK 981.7(ps)
[04/04 16:55:07 498s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 952.4(ps)
[04/04 16:55:07 498s]
[04/04 16:55:07 498s]

[04/04 16:55:07 498s]

(Actual)

[04/04 16:55:07 498s] Rise Phase Delay

950~950(ps)

(Required)

: 952.4~981.7(ps)

[04/04 16:55:07 498s] Fall Phase Delay

950~950(ps)

: 932.8~983.7(ps)

[04/04 16:55:07 498s] Trig. Edge Skew

: 29.3(ps)

[04/04 16:55:07 498s] Rise Skew

[04/04 16:55:07 498s] Fall Skew
[04/04 16:55:07 498s] Max. Rise Buffer Tran.

20(ps)

: 29.3(ps)
: 50.9(ps)
: 100.3(ps)

200(ps)

[04/04 16:55:07 498s] Max. Fall Buffer Tran.

: 112.1(ps)

200(ps)

[04/04 16:55:07 498s] Max. Rise Sink Tran.

: 147.1(ps)

200(ps)

[04/04 16:55:07 498s] Max. Fall Sink Tran.

[04/04 16:55:07 498s] Min. Rise Buffer Tran.

: 166.8(ps)
: 20.2(ps)

200(ps)
0(ps)

[04/04 16:55:07 498s] Min. Fall Buffer Tran.

: 20.1(ps)

0(ps)

[04/04 16:55:07 498s] Min. Rise Sink Tran.

: 42.1(ps)

0(ps)

[04/04 16:55:07 498s] Min. Fall Sink Tran.

: 31.7(ps)

0(ps)

[04/04 16:55:07 498s]

[04/04 16:55:07 498s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 17.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 17.2ps (required = 20ps)

[04/04 16:55:07 498s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew

= 17.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 17.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 17.3ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 17.2ps (required = 20ps)

[04/04 16:55:07 498s] view Arise_analysis_view_func_min_cmin_Tm20V15 :

skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:07 498s]
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] Clock Analysis (CPU Time 0:00:00.4)
[04/04 16:55:07 498s]
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] Switching to the default view
'Arise_analysis_view_test_max_cmax_T150V08' ...
[04/04 16:55:07 498s] *** Finished Rebuilding Buffer Chain (cpu=0:00:00.0
real=0:00:00.0 mem=1259.0M) ***
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] *** None of the buffer chains at roots are modified by the
re-build process.
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] Selecting the worst MMMC view of clock tree 'clk' ...

[04/04 16:55:07 498s] Optimizing clock tree 'clk' in

'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] Calculating post-route downstream delay for clock tree
'clk' ...
[04/04 16:55:07 498s] *** Look For Reconvergent Clock Component ***
[04/04 16:55:07 498s] The clock tree clk has no reconvergent cell.
[04/04 16:55:07 498s] *** Look For PreservePin And Optimized CrossOver Root
Pin ***
[04/04 16:55:07 498s] resized 0 standard cell(s).
[04/04 16:55:07 498s] inserted 0 standard cell(s).
[04/04 16:55:07 498s] *** Gated Clock Tree Optimization (cpu=0:00:00.3
real=0:00:00.0 mem=1259.0M) ***
[04/04 16:55:07 498s] *** Finished Clock Tree Skew Optimization
(cpu=0:00:00.3 real=0:00:00.0 mem=1259.0M) ***
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] *** None of the clock tree buffers/gates are modified by
the skew optimization.
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] Switching to the default view
'Arise_analysis_view_test_max_cmax_T150V08' ...
[04/04 16:55:07 498s] Tuning the min phase delay of clock tree 'clk' ...
[04/04 16:55:07 498s]
[04/04 16:55:07 498s] Calculating post-route downstream delay for clock tree
'clk' ...
[04/04 16:55:08 499s] resized 0 standard cell(s).
[04/04 16:55:08 499s] inserted 0 standard cell(s).
[04/04 16:55:08 499s] *** Tuned Min Phase Delay (cpu=0:00:00.3
mem=1259.0M) ***
[04/04 16:55:08 499s]
[04/04 16:55:08 499s] *** None of the buffer chains at roots are modified by the
fine-tune process.

[04/04 16:55:08 499s]

[04/04 16:55:08 499s]
[04/04 16:55:08 499s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 16:55:08 499s] ********** Clock clk Post-CTS Timing Analysis **********
[04/04 16:55:08 499s] Nr. of Subtrees

: 13

[04/04 16:55:08 499s] Nr. of Sinks

: 258

[04/04 16:55:08 499s] Nr. of Buffer

: 10

[04/04 16:55:08 499s] Nr. of Level (including gates) : 10

[04/04 16:55:08 499s] Root Rise Input Tran

: 0.1(ps)

[04/04 16:55:08 499s] Root Fall Input Tran

: 0.1(ps)

[04/04 16:55:08 499s] No Driving Cell Specified!

[04/04 16:55:08 499s] Max trig. edge delay at sink(R):
EXECUTE_INST/p_reg[12]/state_remap/DFF/CK 981.7(ps)
[04/04 16:55:08 499s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 952.4(ps)
[04/04 16:55:08 499s]
[04/04 16:55:08 499s]
[04/04 16:55:08 499s]

(Actual)

[04/04 16:55:08 499s] Rise Phase Delay

950~950(ps)

(Required)

: 952.4~981.7(ps)

[04/04 16:55:08 499s] Fall Phase Delay

950~950(ps)

: 932.8~983.7(ps)

[04/04 16:55:08 499s] Trig. Edge Skew

: 29.3(ps)

[04/04 16:55:08 499s] Rise Skew

[04/04 16:55:08 499s] Fall Skew
[04/04 16:55:08 499s] Max. Rise Buffer Tran.

20(ps)

[04/04 16:55:08 499s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 17.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 17.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 29.3ps (required = 20ps)

[04/04 16:55:08 499s] view Arise_analysis_view_test_max_cmin_T140V102 :

skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 29.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 17.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 17.3ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 17.2ps (required = 20ps)

[04/04 16:55:08 499s] view Arise_analysis_view_func_min_cmax_Tm40V15 :

skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 17.2ps (required = 20ps)
[04/04 16:55:08 499s]
[04/04 16:55:08 499s]
[04/04 16:55:08 499s] Generating Clock Analysis Report
clock_report/clock.postCTS.report ....
[04/04 16:55:08 499s] Clock Analysis (CPU Time 0:00:00.4)
[04/04 16:55:08 499s]
[04/04 16:55:08 499s]
[04/04 16:55:08 499s] *** End ckECO (cpu=0:00:03.0, real=0:00:03.0,
mem=1259.0M) ***
[04/04 16:55:08 499s] **clockDesign ... cpu = 0:00:17, real = 0:00:17, mem =
1195.0M **
[04/04 16:55:08 499s]
[04/04 16:55:08 499s] *** Summary of all messages that are not suppressed in
this session:
[04/04 16:55:08 499s] Severity ID

Count Summary

[04/04 16:55:08 499s] WARNING ENCEXT-3530

not set. Use the com...

1 The process node is

[04/04 16:55:08 499s] WARNING ENCCK-2070

option is obsolete.

5 The PadBufAfterGate

[04/04 16:55:08 499s] WARNING ENCCK-6323

was moved by %g micr...

1 The placement of %s

[04/04 16:55:08 499s] WARNING ENCCK-6328

preferred routing lay...

1 The utilization of

[04/04 16:55:08 499s] WARNING ENCCK-6350

percent resistance d...

11 Clock net %s has %g

[04/04 16:55:08 499s] *** Message Summary: 19 warning(s), 0 error(s)

[04/04 16:55:08 499s]

[04/04 17:00:28 500s] <CMD> setPlaceMode -fp false

[04/04 17:00:28 500s] <CMD> placeDesign
[04/04 17:00:28 500s] **WARN: (ENCEXT-3493): The design extraction status
has been reset by the setExtractRCMode command. The parasitic data can be
regenerated either by extracting the design using the extractRC command or by
loading the SPEF or RCDB file(s).
[04/04 17:00:28 500s] Type 'man ENCEXT-3493' for more detail.
[04/04 17:00:28 500s] *** Starting placeDesign default flow ***
[04/04 17:00:28 500s] **INFO: Enable pre-place timing setting for timing
analysis
[04/04 17:00:28 500s] Set Using Default Delay Limit as 101.
[04/04 17:00:28 500s] **WARN: (ENCDC-1629):
The default delay limit was
set to 101. This is less than the default of 1000 and may result in inaccurate
delay calculation for nets with a fanout higher than the setting. If needed, the
default delay limit may be adjusted by running the command 'set
delaycal_use_default_delay_limit'.
[04/04 17:00:28 500s] Set Default Net Delay as 0 ps.
[04/04 17:00:28 500s] Set Default Net Load as 0 pF.
[04/04 17:00:28 500s] **INFO: Analyzing IO path groups for slack adjustment
[04/04 17:00:28 500s] Effort level <high> specified for reg2reg_tmp.12308
path_group
[04/04 17:00:28 500s]
################################################
#################################
[04/04 17:00:28 500s] # Design Stage: PreRoute
[04/04 17:00:28 500s] # Design Mode: 90nm
[04/04 17:00:28 500s] # Analysis Mode: MMMC non-OCV
[04/04 17:00:28 500s] # Extraction Mode: default
[04/04 17:00:28 500s] # Delay Calculation Options: engine=aae
SIAware=false(opt_signoff)
[04/04 17:00:28 500s] # Switching Delay Calculation Engine to AAE
[04/04 17:00:28 500s]
################################################
#################################

[04/04 17:00:29 501s] Calculate delays in BcWc mode...

[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Calculate delays in BcWc mode...
[04/04 17:00:29 501s] Topological Sorting (CPU = 0:00:00.0, MEM = 1193.0M,
InitMEM = 1193.0M)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:00:34 506s] AAE_THRD: End delay calculation. (MEM=1410.1
CPU=0:00:05.0 REAL=0:00:05.0)
[04/04 17:00:34 506s] *** CDM Built up (cpu=0:00:05.5 real=0:00:06.0 mem=
1410.1M) ***
[04/04 17:00:35 507s] *** Start deleteBufferTree ***
[04/04 17:00:35 507s] Info: Detect buffers to remove automatically.
[04/04 17:00:35 507s] Analyzing netlist ...
[04/04 17:00:35 507s] Updating netlist
[04/04 17:00:35 507s]
[04/04 17:00:35 507s] *summary: 0 instances (buffers/inverters) removed
[04/04 17:00:35 507s] *** Finish deleteBufferTree (0:00:00.6) ***
[04/04 17:00:35 507s] **INFO: Disable pre-place timing setting for timing
analysis
[04/04 17:00:35 507s] Set Using Default Delay Limit as 1000.

[04/04 17:00:35 507s] Set Default Net Delay as 1000 ps.

[04/04 17:01:01 533s]

4.19e+04)

Est. stn bbox = 8.478e+04 (4.29e+04

[04/04 17:01:01 533s]

1405.0M

cpu = 0:00:00.2 real = 0:00:00.0 mem =

[04/04 17:01:03 535s] nrCritNet: 4.95% ( 113 / 2284 ) cutoffSlk: -725.4ps

stdDelay: 11.6ps
[04/04 17:01:03 535s] nrCritNet: 0.00% ( 0 / 2284 ) cutoffSlk: -877.9ps
stdDelay: 11.6ps
[04/04 17:01:03 535s] Iteration 8: Total net bbox = 7.028e+04 (3.55e+04
3.47e+04)
[04/04 17:01:03 535s]
4.20e+04)

Est. stn bbox = 8.510e+04 (4.30e+04

[04/04 17:01:03 535s]

1407.0M

cpu = 0:00:01.5 real = 0:00:02.0 mem =

[04/04 17:01:05 536s] Congestion driven padding in post-place stage.

[04/04 17:01:05 536s] Congestion driven padding increases utilization from
0.514 to 0.730
[04/04 17:01:05 536s] Congestion driven padding runtime: cpu = 0:00:00.0 real
= 0:00:00.0 mem = 1407.0M
[04/04 17:01:05 536s] Iteration 9: Total net bbox = 7.142e+04 (3.59e+04
3.55e+04)
[04/04 17:01:05 536s]
4.29e+04)

Est. stn bbox = 8.637e+04 (4.35e+04

[04/04 17:01:05 536s]

1407.0M

cpu = 0:00:01.7 real = 0:00:02.0 mem =

19.62 um

[04/04 17:01:12 544s] inst (EXECUTE_INST/g16452) with max move: (93.029,

119.332) -> (109.6, 116.28)

[04/04 17:01:12 544s] mean

(X+Y) =

1.06 um

[04/04 17:01:12 544s] Summary Report:

[04/04 17:01:12 544s] Instances move: 1915 (out of 1915 movable)
[04/04 17:01:12 544s] Mean displacement: 1.06 um
[04/04 17:01:12 544s] Max displacement: 19.62 um (Instance:
EXECUTE_INST/g16452) (93.029, 119.332) -> (109.6, 116.28)
[04/04 17:01:12 544s]
cell type: INVXL

Length: 3 sites, height: 1 rows, site name: CoreSite,

[04/04 17:01:12 544s] Total instances moved : 1915

[04/04 17:01:12 544s] Total net length = 6.214e+04 (3.057e+04 3.157e+04)
(ext = 8.799e+03)
[04/04 17:01:12 544s] Runtime: CPU: 0:00:03.4 REAL: 0:00:03.0 MEM:
1203.0MB
[04/04 17:01:12 544s] [CPU] RefinePlace/total (cpu=0:00:03.4, real=0:00:03.0,
mem=1203.0MB) @(0:09:00 - 0:09:03).
[04/04 17:01:12 544s] *** Finished refinePlace (0:09:03 mem=1203.0M) ***
[04/04 17:01:12 544s] Total net length = 6.207e+04 (3.057e+04 3.150e+04)
(ext = 8.797e+03)
[04/04 17:01:12 544s] *** End of Placement (cpu=0:00:36.7, real=0:00:37.0,
mem=1203.0M) ***
[04/04 17:01:13 544s] Core basic site is CoreSite
[04/04 17:01:13 544s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:01:13 544s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:01:13 544s] default core: bins with density > 0.75 = 67.5 % ( 114 /
169 )
[04/04 17:01:13 544s] Density distribution unevenness ratio = 11.343%
[04/04 17:01:13 545s] *** Free Virtual Timing Model ...(mem=1203.0M)
[04/04 17:01:13 545s] Starting IO pin assignment...
[04/04 17:01:13 545s] Starting congestion repair ...
[04/04 17:01:13 545s] congRepair options: -clkGateAware 1
-rplaceIncrNPClkGateAwareMode 4.
[04/04 17:01:13 545s] *** Starting trialRoute (mem=1203.0M) ***

[04/04 17:01:13 545s]

[04/04 17:01:13 545s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:01:13 545s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:01:13 545s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:01:13 545s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Nr of prerouted/Fixed nets = 23
[04/04 17:01:13 545s] There are 23 nets with 1 extra space.
[04/04 17:01:13 545s] routingBox: (-200 -330) (220200 217310)
[04/04 17:01:13 545s] coreBox:

(0 0) (220000 216980)

[04/04 17:01:13 545s] There are 23 prerouted nets with extraSpace.

[04/04 17:01:13 545s] Number of multi-gpin terms=2373, multi-gpins=5632,
moved blk term=63/63
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Phase 1a route (0:00:00.0 1203.0M):
[04/04 17:01:13 545s] Est net length = 6.905e+04um = 3.378e+04H +
3.527e+04V
[04/04 17:01:13 545s] Usage: (9.7%H 11.9%V) = (4.061e+04um
5.184e+04um) = (40611 30316)
[04/04 17:01:13 545s] Obstruct: 8394 = 4197 (15.0%H) + 4197 (15.0%V)
[04/04 17:01:13 545s] Overflow: 21 = 21 (0.09% H) + 0 (0.00% V)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Phase 1b route (0:00:00.0 1203.0M):
[04/04 17:01:13 545s] Usage: (9.6%H 11.9%V) = (4.050e+04um
5.183e+04um) = (40502 30307)
[04/04 17:01:13 545s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Phase 1c route (0:00:00.0 1203.0M):

[04/04 17:01:13 545s] Usage: (9.6%H 11.9%V) = (4.042e+04um

5.179e+04um) = (40422 30287)
[04/04 17:01:13 545s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Phase 1d route (0:00:00.0 1203.0M):
[04/04 17:01:13 545s] Usage: (9.6%H 11.9%V) = (4.042e+04um
5.179e+04um) = (40422 30287)
[04/04 17:01:13 545s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Phase 1a-1d Overflow: 0.00% H + 0.00% V (0:00:00.1
1203.0M)

[04/04 17:01:13 545s]

[04/04 17:01:13 545s] Phase 1e route (0:00:00.0 1203.0M):
[04/04 17:01:13 545s] Usage: (9.6%H 11.9%V) = (4.042e+04um
5.179e+04um) = (40422 30287)
[04/04 17:01:13 545s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Overflow: 0.00% H + 0.00% V (0:00:00.0 1203.0M)

[04/04 17:01:13 545s] Usage: (9.6%H 11.9%V) = (4.042e+04um

5.179e+04um) = (40422 30287)
[04/04 17:01:13 545s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Congestion distribution:
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Remain cntH

cntV

[04/04 17:01:13 545s] -------------------------------------[04/04 17:01:13 545s] -------------------------------------[04/04 17:01:13 545s] 0:

0.00%

[04/04 17:01:13 545s] 1:

0.00%

0.04%

[04/04 17:01:13 545s] 2:

0.00%

0.10%

[04/04 17:01:13 545s] 3:

0.00%

134

0.56%

[04/04 17:01:13 545s] 4:

0.02%

607

2.56%

[04/04 17:01:13 545s] 5:

2373799.97%

2296896.74%

[04/04 17:01:13 545s]

[04/04 17:01:13 545s] Global route (cpu=0.1s real=0.1s 1203.0M)
[04/04 17:01:13 545s] Updating RC grid for preRoute extraction ...
[04/04 17:01:13 545s] Initializing multi-corner capacitance tables ...
[04/04 17:01:13 545s] Initializing multi-corner resistance tables ...
[04/04 17:01:13 545s] There are 23 prerouted nets with extraSpace.
[04/04 17:01:13 545s]
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] *** After '-updateRemainTrks' operation:
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Usage: (9.8%H 12.4%V) = (4.134e+04um
5.390e+04um) = (41336 31516)
[04/04 17:01:13 545s] Overflow: 11 = 0 (0.00% H) + 11 (0.05% V)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Phase 1l Overflow: 0.00% H + 0.05% V (0:00:00.3
1211.0M)

[04/04 17:01:13 545s]

[04/04 17:01:13 545s] Congestion distribution:
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Remain cntH

cntV

0.00%

161

0.68%

[04/04 17:01:13 545s] 4:

0.03%

637

2.68%

[04/04 17:01:13 545s] 5:

2373499.96%

2285796.27%

[04/04 17:01:13 545s]

[04/04 17:01:13 545s]
[04/04 17:01:13 545s] *** Completed Phase 1 route (0:00:00.5 1211.0M) ***
[04/04 17:01:13 545s]
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] ** np local hotspot detection info verbose **
[04/04 17:01:13 545s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:01:13 545s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Total length: 7.298e+04um, number of vias: 19768
[04/04 17:01:13 545s] M1(H) length: 4.158e+01um, number of vias: 8421
[04/04 17:01:13 545s] M2(V) length: 2.047e+04um, number of vias: 8122
[04/04 17:01:13 545s] M3(H) length: 2.845e+04um, number of vias: 1609
[04/04 17:01:13 545s] M4(V) length: 1.111e+04um, number of vias: 654
[04/04 17:01:13 545s] M5(H) length: 3.549e+03um, number of vias: 556
[04/04 17:01:13 545s] M6(V) length: 3.044e+03um, number of vias: 197
[04/04 17:01:13 545s] M7(H) length: 2.427e+03um, number of vias: 178
[04/04 17:01:13 545s] M8(V) length: 3.234e+03um, number of vias: 31

[04/04 17:01:13 545s] M9(H) length: 6.586e+02um

[04/04 17:01:13 545s] *** Completed Phase 2 route (0:00:00.2 1211.0M) ***
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] *** Finished all Phases (cpu=0:00:00.7 mem=1211.0M)
***
[04/04 17:01:13 545s] dbSprFixZeroViaCodes runtime= 0:00:00.0
[04/04 17:01:13 545s] Peak Memory Usage was 1211.0M
[04/04 17:01:13 545s] TrialRoute+GlbRouteEst total runtime= +0:00:00.7 =
0:00:07.1
[04/04 17:01:13 545s] TrialRoute full (called 9x) runtime= 0:00:06.5
[04/04 17:01:13 545s] TrialRoute check only (called 4x) runtime= 0:00:00.1
[04/04 17:01:13 545s] GlbRouteEst (called 15x) runtime= 0:00:00.5
[04/04 17:01:13 545s] *** Finished trialRoute (cpu=0:00:00.8 mem=1211.0M)
***
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] Local HotSpot Analysis: normalized max congestion
hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in
unit of 4 std-cell row bins)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] ** np local hotspot detection info verbose **
[04/04 17:01:13 545s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:01:13 545s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] describeCongestion: hCong = 0.00 vCong = 0.00
[04/04 17:01:13 545s] Trial Route Overflow 0.000000(H) 0.047967(V).
[04/04 17:01:13 545s] Start repairing congestion with level 1.
[04/04 17:01:13 545s] Skipped repairing congestion.
[04/04 17:01:13 545s] End of congRepair (cpu=0:00:00.8, real=0:00:00.0)
[04/04 17:01:13 545s] *** Finishing placeDesign default flow ***

[04/04 17:01:13 545s] **placeDesign ... cpu = 0: 0:45, real = 0: 0:45, mem =
1200.0M **
[04/04 17:01:13 545s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:01:13 545s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12

Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:01:13 545s]
[04/04 17:01:13 545s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:01:13 545s] Severity ID

Count Summary

[04/04 17:01:13 545s] WARNING ENCEXT-3493

status has been re...

1 The design extraction

[04/04 17:01:13 545s] WARNING ENCCK-2070

option is obsolete.

1 The PadBufAfterGate

[04/04 17:01:13 545s] WARNING ENCDC-1629

was set to %d. T...

1 The default delay limit

[04/04 17:01:13 545s] WARNING ENCSP-9025

specified/traced.

1 No scan chain

[04/04 17:01:13 545s] WARNING ENCSP-9042

defined, -ignoreSca...

1 Scan chains were not

[04/04 17:01:13 545s] *** Message Summary: 5 warning(s), 0 error(s)

[04/04 17:01:13 545s]
[04/04 17:01:19 546s] <CMD> setLayerPreference allM0 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM1Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM1 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM2Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM2 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM3Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM3 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM4Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM4 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM5Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM5 -isVisible 0

[04/04 17:01:19 546s] <CMD> setLayerPreference allM6Cont -isVisible 0

[04/04 17:01:19 546s] <CMD> setLayerPreference allM6 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM7Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM7 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM8Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM8 -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM9Cont -isVisible 0
[04/04 17:01:19 546s] <CMD> setLayerPreference allM9 -isVisible 0
[04/04 17:01:23 546s] <CMD> zoomBox 69.904 122.697 104.001 94.599
[04/04 17:01:25 546s] <CMD> fit
[04/04 17:01:38 547s] <CMD> reportGateCount
[04/04 17:01:38 547s] Gate area 1.0260 um^2
[04/04 17:01:38 547s] [0] tdsp_core Gates=38215 Cells=2199 Area=39208.9
um^2
[04/04 17:02:14 547s] <CMD> selectObjByProp Instance <Status>=<Fixed>
[04/04 17:02:30 548s] <CMD> uiSetTool select
[04/04 17:02:31 548s] <CMD> deselectAll
[04/04 17:02:32 548s] <CMD> zoomBox 73.377 127.748 111.263 82.286
[04/04 17:02:32 548s] <CMD> uiSetTool select
[04/04 17:02:34 548s] <CMD> fit
[04/04 17:02:40 549s] <CMD> setPlaceMode -fp false
[04/04 17:02:40 549s] <CMD> placeDesign
[04/04 17:02:40 549s] *** Starting placeDesign default flow ***
[04/04 17:02:40 549s] **INFO: Enable pre-place timing setting for timing
analysis
[04/04 17:02:40 549s] Set Using Default Delay Limit as 101.
[04/04 17:02:40 549s] **WARN: (ENCDC-1629):
The default delay limit was
set to 101. This is less than the default of 1000 and may result in inaccurate
delay calculation for nets with a fanout higher than the setting. If needed, the
default delay limit may be adjusted by running the command 'set
delaycal_use_default_delay_limit'.

[04/04 17:02:40 549s] Set Default Net Delay as 0 ps.

[04/04 17:02:40 549s] Set Default Net Load as 0 pF.
[04/04 17:02:40 549s] **INFO: Analyzing IO path groups for slack adjustment
[04/04 17:02:41 550s] Effort level <high> specified for reg2reg_tmp.12308
path_group
[04/04 17:02:41 550s]
################################################
#################################
[04/04 17:02:41 550s] # Design Stage: PreRoute
[04/04 17:02:41 550s] # Design Mode: 90nm
[04/04 17:02:41 550s] # Analysis Mode: MMMC non-OCV
[04/04 17:02:41 550s] # Extraction Mode: default
[04/04 17:02:41 550s] # Delay Calculation Options: engine=aae
SIAware=false(opt_signoff)
[04/04 17:02:41 550s] # Switching Delay Calculation Engine to AAE
[04/04 17:02:41 550s]
################################################
#################################
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...

[04/04 17:02:41 550s] Calculate delays in BcWc mode...

[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Calculate delays in BcWc mode...
[04/04 17:02:41 550s] Topological Sorting (CPU = 0:00:00.0, MEM = 1212.8M,
InitMEM = 1212.8M)
[04/04 17:02:41 550s] Updating RC grid for preRoute extraction ...
[04/04 17:02:41 550s] Initializing multi-corner capacitance tables ...
[04/04 17:02:41 550s] Initializing multi-corner resistance tables ...
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:02:46 555s] AAE_THRD: End delay calculation. (MEM=1439.91
CPU=0:00:05.0 REAL=0:00:05.0)
[04/04 17:02:46 555s] *** CDM Built up (cpu=0:00:05.6 real=0:00:05.0 mem=
1439.9M) ***
[04/04 17:02:47 556s] *** Start deleteBufferTree ***
[04/04 17:02:47 556s] Info: Detect buffers to remove automatically.
[04/04 17:02:47 556s] Analyzing netlist ...
[04/04 17:02:48 557s] Updating netlist
[04/04 17:02:48 557s]
[04/04 17:02:48 557s] *summary: 0 instances (buffers/inverters) removed
[04/04 17:02:48 557s] *** Finish deleteBufferTree (0:00:00.5) ***
[04/04 17:02:48 557s] **INFO: Disable pre-place timing setting for timing
analysis
[04/04 17:02:48 557s] Set Using Default Delay Limit as 1000.
[04/04 17:02:48 557s] Set Default Net Delay as 1000 ps.
[04/04 17:02:48 557s] Set Default Net Load as 0.5 pF.
[04/04 17:02:48 557s] Some Marcos are marked as preplaced.
[04/04 17:02:48 557s] *** Starting "NanoPlace(TM) placement v#1
(mem=1255.9M)" ...
[04/04 17:03:02 571s] *** Build Buffered Sizing Timing Model
[04/04 17:03:02 571s] (cpu=0:00:14.5 mem=1255.9M) ***
[04/04 17:03:03 571s] *** Build Virtual Sizing Timing Model
[04/04 17:03:03 571s] (cpu=0:00:14.8 mem=1255.9M) ***

[04/04 17:03:03 571s] Options: timingDriven clkGateAware ignoreScan

pinGuide congEffort=auto gpeffort=medium
[04/04 17:03:03 572s] **WARN: (ENCSP-9042):
defined, -ignoreScan option will be ignored.

Scan chains were not

[04/04 17:03:03 572s] Define the scan chains before using this option.
[04/04 17:03:03 572s] Type 'man ENCSP-9042' for more detail.
[04/04 17:03:04 572s] #std cell=2195 (0 fixed + 2195 movable) #block=4 (0
floating + 4 preplaced)
[04/04 17:03:04 572s] #ioInst=0 #net=2284 #term=8784 #term/net=3.85,
#fixedIo=144, #floatIo=0, #fixedPin=117, #floatPin=0
[04/04 17:03:04 572s] stdCell: 2195 single + 0 double + 0 multi
[04/04 17:03:04 572s] Total standard cell length = 5.9824 (mm), area = 0.0102
(mm^2)
[04/04 17:03:04 572s] Core basic site is CoreSite
[04/04 17:03:04 572s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:03:04 572s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:03:04 572s] Average module density = 0.566.
[04/04 17:03:04 572s] Density for the design = 0.566.
[04/04 17:03:04 572s]
= stdcell_area 29912 sites (10230 um^2) /
alloc_area 52885 sites (18087 um^2).
[04/04 17:03:04 572s] Pin Density = 0.069.
[04/04 17:03:04 572s]
127198.

= total # of pins 8784 / total Instance area

[04/04 17:03:04 572s] === lastAutoLevel = 8

[04/04 17:03:04 573s] Found multi-fanin net mpy_result[0]
[04/04 17:03:04 573s] Found multi-fanin net mpy_result[1]
[04/04 17:03:04 573s] Found multi-fanin net mpy_result[2]
[04/04 17:03:04 573s] Found multi-fanin net mpy_result[3]
[04/04 17:03:04 573s] Found multi-fanin net mpy_result[4]
[04/04 17:03:04 573s] Found multi-fanin net mpy_result[5]
[04/04 17:03:04 573s] Found multi-fanin net mpy_result[6]

[04/04 17:03:04 573s] Found multi-fanin net mpy_result[7]

[04/04 17:03:04 573s] Found multi-fanin net mpy_result[8]
[04/04 17:03:04 573s] Found multi-fanin net mpy_result[9]
[04/04 17:03:04 573s] ......
[04/04 17:03:04 573s] Found 32 (out of 2316) multi-fanin nets.
[04/04 17:03:09 578s] Redoing specifyClockTree ...
[04/04 17:03:09 578s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:03:09 578s] Checking spec file integrity...

[04/04 17:03:09 578s] Clock gating cells inferred from clock spec file.
[04/04 17:03:09 578s] Effort level <high> specified for reg2reg path_group
[04/04 17:03:09 578s] Effort level <high> specified for reg2cgate path_group
[04/04 17:03:11 579s] Iteration 1: Total net bbox = 3.849e+04 (1.73e+04
2.11e+04)
[04/04 17:03:11 579s]
2.49e+04)

Est. stn bbox = 4.519e+04 (2.03e+04

[04/04 17:03:11 579s]

1407.1M

cpu = 0:00:00.0 real = 0:00:00.0 mem =

[04/04 17:03:11 579s] Iteration 2: Total net bbox = 3.849e+04 (1.73e+04

2.11e+04)
[04/04 17:03:11 579s]
2.49e+04)

Est. stn bbox = 4.519e+04 (2.03e+04

[04/04 17:03:11 579s]

1407.1M

cpu = 0:00:00.0 real = 0:00:00.0 mem =

[04/04 17:03:11 579s] Iteration 3: Total net bbox = 3.709e+04 (1.73e+04

1.98e+04)
[04/04 17:03:11 579s]
2.42e+04)

Est. stn bbox = 4.522e+04 (2.10e+04

[04/04 17:03:11 579s]

1407.1M

cpu = 0:00:00.4 real = 0:00:00.0 mem =

[04/04 17:03:11 579s] Total number of setup views is 23.

cpu = 0:00:01.5 real = 0:00:02.0 mem =

[04/04 17:03:19 588s] Iteration 11: Total net bbox = 6.407e+04 (3.17e+04
3.23e+04)
[04/04 17:03:19 588s]
3.89e+04)

Est. stn bbox = 7.697e+04 (3.80e+04

[04/04 17:03:19 588s]

1408.1M

cpu = 0:00:01.6 real = 0:00:01.0 mem =

[04/04 17:03:19 588s] Iteration 12: Total net bbox = 6.407e+04 (3.17e+04
3.23e+04)
[04/04 17:03:19 588s]
3.89e+04)

Est. stn bbox = 7.697e+04 (3.80e+04

[04/04 17:03:19 588s]

1408.1M

cpu = 0:00:00.0 real = 0:00:00.0 mem =

[04/04 17:03:19 588s] *** cost = 6.407e+04 (3.17e+04 3.23e+04) (cpu for
global=0:00:10.3) real=0:00:10.0***
[04/04 17:03:19 588s] Info: 0 clock gating cells identified, 0 (on average)
moved
[04/04 17:03:19 588s] Core Placement runtime cpu: 0:00:05.7 real: 0:00:05.0
[04/04 17:03:20 589s] **WARN: (ENCSP-9025):
specified/traced.

No scan chain

[04/04 17:03:20 589s] Type 'man ENCSP-9025' for more detail.

[04/04 17:03:20 589s] Core basic site is CoreSite
[04/04 17:03:21 589s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:03:21 589s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:03:21 589s] *** Starting refinePlace (0:09:48 mem=1204.0M) ***
[04/04 17:03:21 589s] Total net length = 5.593e+04 (2.762e+04 2.831e+04)
(ext = 8.301e+03)
[04/04 17:03:21 589s] Starting refinePlace ...
[04/04 17:03:21 589s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:03:21 589s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:03:21 589s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.1,
real=0:00:00.0, mem=1208.6MB) @(0:09:48 - 0:09:48).
[04/04 17:03:21 589s] Move report: preRPlace moves 2195 insts, mean move:
0.54 um, max move: 4.34 um
[04/04 17:03:21 589s] Max move on inst
(EXECUTE_INST/acc_reg[12]/state_remap/DFF): (116.51, 79.55) --> (116.60,
83.79)
[04/04 17:03:21 589s]
cell type: SDFFRX4

Length: 39 sites, height: 1 rows, site name: CoreSite,

[04/04 17:03:21 589s] wireLenOptFixPriorityInst 280 inst fixed

[04/04 17:03:21 589s] Placement tweakage begins.
[04/04 17:03:21 589s] wire length = 6.890e+04
[04/04 17:03:21 589s] wire length = 6.852e+04

[04/04 17:03:21 589s] Placement tweakage ends.

[04/04 17:03:21 589s] Move report: tweak moves 403 insts, mean move: 2.84
um, max move: 13.20 um
[04/04 17:03:21 589s] Max move on inst (TDSP_CORE_GLUE_INST/g8334):
(109.00, 83.79) --> (95.80, 83.79)
[04/04 17:03:21 589s] [CPU] RefinePlace/TweakPlacement (cpu=0:00:00.2,
real=0:00:00.0, mem=1208.6MB) @(0:09:48 - 0:09:48).
[04/04 17:03:21 589s] Move report: legalization moves 73 insts, mean move:
0.31 um, max move: 3.42 um
[04/04 17:03:21 589s] Max move on inst (EXECUTE_INST/g16450): (85.00,
147.06) --> (85.00, 150.48)
[04/04 17:03:21 589s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1208.6MB) @(0:09:48 - 0:09:48).
[04/04 17:03:21 589s] Move report: Detail placement moves 2195 insts, mean
move: 1.01 um, max move: 13.48 um
[04/04 17:03:21 589s] Max move on inst (ACCUM_STAT_INST/g673): (109.92,
112.31) --> (112.60, 123.12)
[04/04 17:03:21 589s]
1208.6MB

Runtime: CPU: 0:00:00.3 REAL: 0:00:00.0 MEM:

[04/04 17:03:21 589s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:03:21 589s] maximum (X+Y) =

13.48 um

[04/04 17:03:21 589s] inst (ACCUM_STAT_INST/g673) with max move: (109.92,

112.315) -> (112.6, 123.12)
[04/04 17:03:21 589s] mean

(X+Y) =

1.01 um

[04/04 17:03:21 589s] Summary Report:

[04/04 17:03:21 589s] Instances move: 2195 (out of 2195 movable)
[04/04 17:03:21 589s] Mean displacement: 1.01 um
[04/04 17:03:21 589s] Max displacement: 13.48 um (Instance:
ACCUM_STAT_INST/g673) (109.92, 112.315) -> (112.6, 123.12)
[04/04 17:03:21 589s]
cell type: NOR2BX1

Length: 5 sites, height: 1 rows, site name: CoreSite,

[04/04 17:03:21 589s] Total instances moved : 2195

[04/04 17:03:21 589s] Total net length = 5.681e+04 (2.789e+04 2.892e+04)

(ext = 8.354e+03)
[04/04 17:03:21 589s] Runtime: CPU: 0:00:00.3 REAL: 0:00:00.0 MEM:
1208.6MB
[04/04 17:03:21 589s] [CPU] RefinePlace/total (cpu=0:00:00.3, real=0:00:00.0,
mem=1208.6MB) @(0:09:48 - 0:09:48).
[04/04 17:03:21 589s] *** Finished refinePlace (0:09:48 mem=1208.6M) ***
[04/04 17:03:21 589s] Total net length = 5.679e+04 (2.789e+04 2.890e+04)
(ext = 8.350e+03)
[04/04 17:03:21 589s] *** End of Placement (cpu=0:00:32.4, real=0:00:33.0,
mem=1208.6M) ***
[04/04 17:03:21 589s] Core basic site is CoreSite
[04/04 17:03:21 589s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:03:21 589s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:03:21 589s] default core: bins with density > 0.75 = 70.4 % ( 119 /
169 )
[04/04 17:03:21 589s] Density distribution unevenness ratio = 11.344%
[04/04 17:03:21 589s] *** Free Virtual Timing Model ...(mem=1208.6M)
[04/04 17:03:21 589s] Starting IO pin assignment...
[04/04 17:03:21 590s] Starting congestion repair ...
[04/04 17:03:21 590s] congRepair options: -clkGateAware 1
-rplaceIncrNPClkGateAwareMode 4.
[04/04 17:03:21 590s] *** Starting trialRoute (mem=1208.6M) ***
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:03:21 590s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:03:21 590s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:03:21 590s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:03:21 590s]

[04/04 17:03:21 590s] Nr of prerouted/Fixed nets = 23

[04/04 17:03:21 590s] There are 23 nets with 1 extra space.
[04/04 17:03:21 590s] routingBox: (-200 -330) (220200 217310)
[04/04 17:03:21 590s] coreBox:

(0 0) (220000 216980)

[04/04 17:03:21 590s] There are 23 prerouted nets with extraSpace.

[04/04 17:03:21 590s] Number of multi-gpin terms=2397, multi-gpins=5647,
moved blk term=63/63
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] Phase 1a route (0:00:00.0 1208.6M):
[04/04 17:03:21 590s] Est net length = 6.239e+04um = 3.050e+04H +
3.188e+04V
[04/04 17:03:21 590s] Usage: (8.9%H 11.1%V) = (3.723e+04um
4.824e+04um) = (37231 28207)
[04/04 17:03:21 590s] Obstruct: 8394 = 4197 (15.0%H) + 4197 (15.0%V)
[04/04 17:03:21 590s] Overflow: 36 = 36 (0.15% H) + 0 (0.00% V)
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] Phase 1b route (0:00:00.0 1208.6M):
[04/04 17:03:21 590s] Usage: (8.8%H 11.1%V) = (3.715e+04um
4.822e+04um) = (37150 28199)
[04/04 17:03:21 590s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] Phase 1c route (0:00:00.0 1208.6M):
[04/04 17:03:21 590s] Usage: (8.8%H 11.1%V) = (3.709e+04um
4.820e+04um) = (37091 28184)
[04/04 17:03:21 590s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] Phase 1d route (0:00:00.0 1208.6M):
[04/04 17:03:21 590s] Usage: (8.8%H 11.1%V) = (3.709e+04um
4.820e+04um) = (37091 28184)
[04/04 17:03:21 590s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:03:21 590s]

[04/04 17:03:21 590s] Phase 1a-1d Overflow: 0.00% H + 0.00% V (0:00:00.1

1208.6M)

[04/04 17:03:21 590s]

[04/04 17:03:21 590s] Phase 1e route (0:00:00.0 1208.6M):
[04/04 17:03:21 590s] Usage: (8.8%H 11.1%V) = (3.709e+04um
4.820e+04um) = (37091 28184)
[04/04 17:03:21 590s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] Overflow: 0.00% H + 0.00% V (0:00:00.0 1208.6M)

[04/04 17:03:21 590s] Usage: (8.8%H 11.1%V) = (3.709e+04um

4.820e+04um) = (37091 28184)
[04/04 17:03:21 590s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] Congestion distribution:
[04/04 17:03:21 590s]
[04/04 17:03:21 590s] Remain cntH

cntV

[04/04 17:03:21 590s] -------------------------------------[04/04 17:03:21 590s] -------------------------------------[04/04 17:03:21 590s] 0:

0.00%

[04/04 17:03:21 590s] 1:

0.00%

0.02%

[04/04 17:03:21 590s] 2:

0.00%

0.06%

[04/04 17:03:21 590s] 3:

0.00%

0.22%

[04/04 17:03:21 590s] 4:

0.01%

709

2.99%

[04/04 17:03:21 590s] 5:

2373999.98%

2296296.71%

[04/04 17:03:21 590s]

[04/04 17:03:21 590s] Global route (cpu=0.1s real=0.1s 1208.6M)
[04/04 17:03:21 590s] Updating RC grid for preRoute extraction ...

0.00%

0.28%

[04/04 17:03:22 590s] 4:

0.02%

727

3.06%

[04/04 17:03:22 590s] 5:

2373799.97%

2287996.36%

[04/04 17:03:22 590s]

[04/04 17:03:22 590s]
[04/04 17:03:22 590s] *** Completed Phase 1 route (0:00:00.5 1216.6M) ***
[04/04 17:03:22 590s]
[04/04 17:03:22 590s]
[04/04 17:03:22 590s] ** np local hotspot detection info verbose **
[04/04 17:03:22 590s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:03:22 590s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:03:22 590s]
[04/04 17:03:22 590s]
[04/04 17:03:22 590s] Total length: 6.637e+04um, number of vias: 19316
[04/04 17:03:22 590s] M1(H) length: 4.158e+01um, number of vias: 8421
[04/04 17:03:22 590s] M2(V) length: 1.847e+04um, number of vias: 7888
[04/04 17:03:22 590s] M3(H) length: 2.576e+04um, number of vias: 1506
[04/04 17:03:22 590s] M4(V) length: 9.745e+03um, number of vias: 605
[04/04 17:03:22 590s] M5(H) length: 2.979e+03um, number of vias: 512
[04/04 17:03:22 590s] M6(V) length: 3.092e+03um, number of vias: 191
[04/04 17:03:22 590s] M7(H) length: 2.224e+03um, number of vias: 163
[04/04 17:03:22 590s] M8(V) length: 3.263e+03um, number of vias: 30
[04/04 17:03:22 590s] M9(H) length: 7.872e+02um
[04/04 17:03:22 590s] *** Completed Phase 2 route (0:00:00.2 1216.6M) ***
[04/04 17:03:22 590s]
[04/04 17:03:22 590s] *** Finished all Phases (cpu=0:00:00.8 mem=1216.6M)
***
[04/04 17:03:22 590s] dbSprFixZeroViaCodes runtime= 0:00:00.0
[04/04 17:03:22 590s] Peak Memory Usage was 1216.6M
[04/04 17:03:22 590s] TrialRoute+GlbRouteEst total runtime= +0:00:00.8 =
0:00:07.9

[04/04 17:03:22 590s] TrialRoute full (called 10x) runtime= 0:00:07.3

[04/04 17:03:22 590s] TrialRoute check only (called 4x) runtime= 0:00:00.1
[04/04 17:03:22 590s] GlbRouteEst (called 17x) runtime= 0:00:00.5
[04/04 17:03:22 590s] *** Finished trialRoute (cpu=0:00:00.8 mem=1216.6M)
***
[04/04 17:03:22 590s]
[04/04 17:03:22 590s] Local HotSpot Analysis: normalized max congestion
hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in
unit of 4 std-cell row bins)
[04/04 17:03:22 590s]
[04/04 17:03:22 590s] ** np local hotspot detection info verbose **
[04/04 17:03:22 590s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:03:22 590s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:03:22 590s]
[04/04 17:03:22 590s] describeCongestion: hCong = 0.00 vCong = 0.00
[04/04 17:03:22 590s] Trial Route Overflow 0.000000(H) 0.047562(V).
[04/04 17:03:22 590s] Start repairing congestion with level 1.
[04/04 17:03:22 590s] Skipped repairing congestion.
[04/04 17:03:22 590s] End of congRepair (cpu=0:00:00.8, real=0:00:01.0)
[04/04 17:03:22 590s] *** Finishing placeDesign default flow ***
[04/04 17:03:22 590s] **placeDesign ... cpu = 0: 0:41, real = 0: 0:42, mem =
1204.0M **
[04/04 17:03:22 590s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11

Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:03:22 590s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:03:22 590s]
[04/04 17:03:22 590s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:03:22 590s] Severity ID

Count Summary

[04/04 17:03:22 590s] WARNING ENCCK-2070

option is obsolete.

1 The PadBufAfterGate

[04/04 17:03:22 590s] WARNING ENCDC-1629

was set to %d. T...

1 The default delay limit

[04/04 17:03:22 590s] WARNING ENCSP-9025

specified/traced.

1 No scan chain

[04/04 17:03:22 590s] WARNING ENCSP-9042

defined, -ignoreSca...

1 Scan chains were not

[04/04 17:03:22 590s] *** Message Summary: 4 warning(s), 0 error(s)

[04/04 17:03:22 590s]
[04/04 17:03:31 590s] <CMD> reportGateCount
[04/04 17:03:31 590s] Gate area 1.0260 um^2
[04/04 17:03:31 590s] [0] tdsp_core Gates=38215 Cells=2199 Area=39208.9
um^2
[04/04 17:03:40 592s] <CMD> zoomBox 50.962 123.644 77.166 92.073
[04/04 17:03:41 592s] <CMD> fit
[04/04 17:03:43 592s] <CMD> zoomBox 99.581 35.561 118.208 21.669
[04/04 17:03:45 592s] <CMD> fit
[04/04 17:03:48 593s] <CMD> selectInst gopi_MPY_32
[04/04 17:03:49 593s] <CMD> deselectAll
[04/04 17:04:11 598s] <CMD> clockDesign -specFile ../../DATA/clock.ctstch
-outDir clock_report -fixedInstBeforeCTS
[04/04 17:04:11 598s] -engine ck
ccopt_from_edi_spec}, default=auto, user setting

# enums={ck ccopt auto

[04/04 17:04:11 598s] **clockDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1204.0M **
[04/04 17:04:11 598s] setCTSMode -engine ck -moveGateLimit 25
[04/04 17:04:11 598s] <clockDesign INFO> 'setCTSMode -routeClkNet true' is
set inside clockDesign.
[04/04 17:04:11 598s]
[04/04 17:04:12 598s] <clockDesign CMD> cleanupSpecifyClockTree
[04/04 17:04:12 598s] <clockDesign CMD> specifyClockTree -file
../../DATA/clock.ctstch
[04/04 17:04:12 598s] Checking spec file integrity...

[04/04 17:04:12 598s]

[04/04 17:04:12 598s] Reading clock tree spec file '../../DATA/clock.ctstch' ...
[04/04 17:04:12 598s]
[04/04 17:04:12 598s] Updating RC grid for preRoute extraction ...
[04/04 17:04:12 598s] Initializing multi-corner capacitance tables ...
[04/04 17:04:12 598s] Initializing multi-corner resistance tables ...
[04/04 17:04:12 598s] RouteType

: 4.8575(ohm) [8.90542]

[04/04 17:04:12 598s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:04:12 598s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:04:12 598s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:04:12 598s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:04:12 598s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

: 0.0937833(V=0.0937833

[04/04 17:04:12 598s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 17:04:12 598s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:04:12 598s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:04:12 598s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

: 0.0937833(V=0.0937833

[04/04 17:04:12 598s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 17:04:12 598s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:04:12 598s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:04:12 598s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[-clkfile <string> | -file <string> |

[04/04 17:04:12 598s]

[-create <string> | -delete <string> |
-update <string> | -file <string> | -template ]
[04/04 17:04:12 598s]

[04/04 17:04:12 598s] -help

usage

# Prints out the command

[04/04 17:04:12 598s] -create <string>

# (string, optional)

[04/04 17:04:12 598s] -delete <string>

# (string, optional)

[04/04 17:04:12 598s] -dont_use

file defined

# Excludes buffers from CTS

[04/04 17:04:12 598s]

file.

# as dont_use : true in the .lib

[04/04 17:04:12 598s]

# (bool, optional)

[04/04 17:04:12 598s] -file <string>

clock tree

# Specifies the name of the

[04/04 17:04:12 598s]

optional)

# specification file. (string,

[04/04 17:04:12 598s] -template

template file

# Creates a sample CTS

[04/04 17:04:12 598s]

optional)

# template.ctstch. (bool,

[04/04 17:04:12 598s] -update <string>

# (string, optional)

[04/04 17:04:12 598s]

# enums={ck ccopt auto

[04/04 17:04:41 599s] **clockDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1194.0M **
[04/04 17:04:41 599s] setCTSMode -engine ck -moveGateLimit 25
[04/04 17:04:41 599s] <clockDesign INFO> 'setCTSMode -routeClkNet true' is
set inside clockDesign.
[04/04 17:04:41 599s]
[04/04 17:04:41 599s] <clockDesign CMD> cleanupSpecifyClockTree
[04/04 17:04:41 599s] <clockDesign CMD> specifyClockTree -file
../../DATA/clock.ctstch
[04/04 17:04:41 599s] Checking spec file integrity...
[04/04 17:04:41 599s]
[04/04 17:04:41 599s] Reading clock tree spec file '../../DATA/clock.ctstch' ...
[04/04 17:04:41 599s]
[04/04 17:04:41 599s] **ERROR: (ENCCK-3105):
The PreferredExtraSpace
statement must appear after the RouteTypeName statement and before the End
statement in the clock tree specification file.
[04/04 17:04:41 599s] **ERROR: (ENCCK-427):
The clock tree specification
file contains an error at line 5: PreferredExtraSpace 0
[04/04 17:04:41 599s]
[04/04 17:04:41 599s] Usage: specifyClockTree [-help] [-dont_use]
[04/04 17:04:41 599s]
-specFile <string>]

[-clkfile <string> | -file <string> |

[04/04 17:04:41 599s]

[-create <string> | -delete <string> |
-update <string> | -file <string> | -template ]
[04/04 17:04:41 599s]
[04/04 17:04:41 599s] -help
usage
[04/04 17:04:41 599s] -create <string>

# Prints out the command

# (string, optional)

[04/04 17:04:41 599s] -delete <string>

# (string, optional)

[04/04 17:04:41 599s] -dont_use

file defined

# Excludes buffers from CTS

[04/04 17:04:41 599s]

file.

# as dont_use : true in the .lib

[04/04 17:04:41 599s]

# (bool, optional)

[04/04 17:04:41 599s] -file <string>

clock tree

# Specifies the name of the

[04/04 17:04:41 599s]

optional)

# specification file. (string,

[04/04 17:04:41 599s] -template

template file

# Creates a sample CTS

[04/04 17:04:41 599s]

optional)

# template.ctstch. (bool,

[04/04 17:04:41 599s] -update <string>

# (string, optional)

[04/04 17:04:41 599s]

[04/04 17:04:41 599s]
[04/04 17:04:41 599s] **ERROR: (ENCSYC-194):
'specifyClockTree'.

Incorrect usage for command

[04/04 17:04:41 599s] **ERROR: (ENCCK-9000):

0:00:00, real = 0:00:00, mem = 1194.0M **

**clockDesign ... cpu =

[04/04 17:04:41 599s]

[04/04 17:04:41 599s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:04:41 599s] Severity ID

Count Summary

ENCCK-427

1 %s %d: %s

[04/04 17:04:41 599s] *** Message Summary: 0 warning(s), 4 error(s)

[04/04 17:04:41 599s]

[04/04 17:05:15 600s] <CMD> setCTSMode -engine ck

[04/04 17:05:22 601s] <CMD> clockDesign -specFile ../../DATA/clock.ctstch
-outDir clock_report -fixedInstBeforeCTS
[04/04 17:05:22 601s] -engine ck
ccopt_from_edi_spec}, default=auto, user setting

# enums={ck ccopt auto

[04/04 17:05:22 601s] **clockDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1194.0M **
[04/04 17:05:22 601s] setCTSMode -engine ck -moveGateLimit 25
[04/04 17:05:22 601s] <clockDesign INFO> 'setCTSMode -routeClkNet true' is
set inside clockDesign.
[04/04 17:05:22 601s]
[04/04 17:05:22 601s] <clockDesign CMD> cleanupSpecifyClockTree
[04/04 17:05:22 601s] <clockDesign CMD> specifyClockTree -file
../../DATA/clock.ctstch
[04/04 17:05:22 601s] Checking spec file integrity...
[04/04 17:05:22 601s]
[04/04 17:05:22 601s] Reading clock tree spec file '../../DATA/clock.ctstch' ...
[04/04 17:05:22 601s]
[04/04 17:05:22 601s] **ERROR: (ENCCK-3105):
The TopPreferredLayer
statement must appear after the RouteTypeName statement and before the End
statement in the clock tree specification file.
[04/04 17:05:22 601s] **ERROR: (ENCCK-427):
The clock tree specification
file contains an error at line 6: TopPreferredLayer 6
[04/04 17:05:22 601s]
[04/04 17:05:22 601s] Usage: specifyClockTree [-help] [-dont_use]
[04/04 17:05:22 601s]
-specFile <string>]

[-clkfile <string> | -file <string> |

[04/04 17:05:22 601s]

[-create <string> | -delete <string> |
-update <string> | -file <string> | -template ]
[04/04 17:05:22 601s]
[04/04 17:05:22 601s] -help
usage
[04/04 17:05:22 601s] -create <string>

# Prints out the command

# (string, optional)

[04/04 17:05:22 601s] -delete <string>

# (string, optional)

[04/04 17:05:22 601s] -dont_use

file defined

# Excludes buffers from CTS

[04/04 17:05:22 601s]

file.

# as dont_use : true in the .lib

[04/04 17:05:22 601s]

# (bool, optional)

[04/04 17:05:22 601s] -file <string>

clock tree

# Specifies the name of the

[04/04 17:05:22 601s]

optional)

# specification file. (string,

[04/04 17:05:22 601s] -template

template file

# Creates a sample CTS

[04/04 17:05:22 601s]

optional)

# template.ctstch. (bool,

[04/04 17:05:22 601s] -update <string>

# (string, optional)

[04/04 17:05:22 601s]

[04/04 17:05:22 601s]
[04/04 17:05:22 601s] **ERROR: (ENCSYC-194):
'specifyClockTree'.

Incorrect usage for command

[04/04 17:05:22 601s] **ERROR: (ENCCK-9000):

0:00:00, real = 0:00:00, mem = 1194.0M **

**clockDesign ... cpu =

[04/04 17:05:22 601s]

[04/04 17:05:22 601s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:05:22 601s] Severity ID

Count Summary

ENCCK-427

1 %s %d: %s

[04/04 17:05:22 601s] *** Message Summary: 0 warning(s), 4 error(s)

[04/04 17:05:22 601s]

[04/04 17:06:31 602s] <CMD> clockDesign -specFile ../../DATA/clock.ctstch

-outDir clock_report -fixedInstBeforeCTS
[04/04 17:06:31 602s] -engine ck
ccopt_from_edi_spec}, default=auto, user setting

# enums={ck ccopt auto

[04/04 17:06:31 602s] **clockDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1194.0M **
[04/04 17:06:31 602s] setCTSMode -engine ck -moveGateLimit 25
[04/04 17:06:31 602s] <clockDesign INFO> 'setCTSMode -routeClkNet true' is
set inside clockDesign.
[04/04 17:06:31 602s]
[04/04 17:06:31 602s] <clockDesign CMD> cleanupSpecifyClockTree
[04/04 17:06:31 602s] <clockDesign CMD> specifyClockTree -file
../../DATA/clock.ctstch
[04/04 17:06:31 602s] Checking spec file integrity...
[04/04 17:06:31 602s]
[04/04 17:06:31 602s] Reading clock tree spec file '../../DATA/clock.ctstch' ...
[04/04 17:06:31 602s]
[04/04 17:06:31 602s] **WARN: (ENCCK-2070):
is obsolete.
[04/04 17:06:31 602s] RouteType

: FE_CTS_DEFAULT

[04/04 17:06:31 602s] PreferredExtraSpace

[04/04 17:06:31 602s] Shield
[04/04 17:06:31 602s] PreferLayer

The PadBufAfterGate option

: NONE
: M3 M4

[04/04 17:06:31 602s] RC Information for View

Arise_analysis_view_test_max_cmax_T150V08 :
[04/04 17:06:31 602s] Est. Cap
H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 17:06:31 602s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 17:06:31 602s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:06:31 602s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:06:31 602s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

es=0.32(um) cap=0.109(ff/um) res=1.23(ohm/um) viaRes=0(ohm) viaCap=0(ff)
[04/04 17:06:31 602s] M2(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.04792(ohm)
viaCap=0.0558832(ff)
[04/04 17:06:31 602s] M3(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 17:06:31 602s] M4(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 17:06:31 602s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 17:06:31 602s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 17:06:31 602s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:06:31 602s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:06:31 602s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 17:06:31 602s]
[04/04 17:06:31 602s] RC Information for View
Arise_analysis_view_func_max_cmax_T150V08 :
[04/04 17:06:31 602s] Est. Cap
H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 17:06:31 602s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 17:06:31 602s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:06:31 602s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:06:31 602s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:06:31 602s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:06:32 602s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:06:32 602s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:06:32 602s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

es=0.32(um) cap=0.109(ff/um) res=1.23(ohm/um) viaRes=0(ohm) viaCap=0(ff)

[04/04 17:06:32 602s] M2(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)

cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.04792(ohm)
viaCap=0.0558832(ff)
[04/04 17:06:32 602s] M3(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 17:06:32 602s] M4(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 17:06:32 602s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 17:06:32 602s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 17:06:32 602s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:06:32 602s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:06:32 602s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 17:06:32 602s]
[04/04 17:06:32 602s] Switching off Advanced RC Correlation modes in AAE
mode.
[04/04 17:06:32 602s] Active Analysis Views for CTS are,
[04/04 17:06:32 602s] #1 Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:06:32 602s] #2 Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:06:32 602s] #3 Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:06:32 602s] #4 Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:06:32 602s] #5 Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:06:32 602s] #6 Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:06:32 602s] #7 Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:06:32 602s] #8 Arise_analysis_view_test_nom_cmax_T25V12

[04/04 17:06:32 602s] #9 Arise_analysis_view_test_nom_cmax_T50V13

[04/04 17:06:32 602s] #10 Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:06:32 602s] #11 Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:06:32 602s] #12 Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:06:32 602s] #13 Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:06:32 602s] #14 Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:06:32 602s] #15 Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:06:32 602s] #16 Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:06:32 602s] #17 Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:06:32 602s] #18 Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:06:32 602s] #19 Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:06:32 602s] #20 Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:06:32 602s] #21 Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:06:32 602s] #22 Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:06:32 602s] #23 Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:06:32 602s] #24 Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:06:32 602s] #25 Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:06:32 602s] #26 Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:06:32 602s] #27 Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:06:32 602s] #28 Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:06:32 602s] #29 Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:06:32 602s] #30 Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:06:32 602s] #31 Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:06:32 602s] #32 Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:06:32 602s] #33 Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:06:32 602s] #34 Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:06:32 602s] #35 Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:06:32 602s] Default Analysis Views is
Arise_analysis_view_test_max_cmax_T150V08

[04/04 17:06:32 602s]

[04/04 17:06:32 602s]
[04/04 17:06:32 602s] ****** AutoClockRootPin ******
[04/04 17:06:32 602s] AutoClockRootPin 1: clk
[04/04 17:06:32 602s] # NoGating

[04/04 17:06:32 602s] # SetDPinAsSync

[04/04 17:06:32 602s] # SetIoPinAsSync NO

[04/04 17:06:32 602s] # SetAsyncSRPinAsSync NO
[04/04 17:06:32 602s] # SetTriStEnPinAsSync NO
[04/04 17:06:32 602s] # SetBBoxPinAsSync NO
[04/04 17:06:32 602s] # RouteClkNet
[04/04 17:06:32 602s] # PostOpt

YES
YES

[04/04 17:06:32 602s] # RouteType

[04/04 17:06:32 602s] # LeafRouteType

FE_CTS_DEFAULT
FE_CTS_DEFAULT_LEAF

[04/04 17:06:32 602s]

[04/04 17:06:32 602s] ***** !! NOTE !! *****
[04/04 17:06:32 602s]
[04/04 17:06:32 602s] CTS treats D-pins and I/O pins as non-synchronous pins
by default.
[04/04 17:06:32 602s] If you want to change the behavior, you need to use the
SetDPinAsSync
[04/04 17:06:32 602s] or SetIoPinAsSync statement in the clock tree
specification file,
[04/04 17:06:32 602s] or use the setCTSMode -traceDPinAsLeaf {true|false}
command,
[04/04 17:06:32 602s] or use the setCTSMode -traceIoPinAsLeaf {true|false}
command
[04/04 17:06:32 602s] before specifyClockTree command.
[04/04 17:06:32 602s]
[04/04 17:06:32 602s] *** End specifyClockTree (cpu=0:00:00.1,
real=0:00:01.0, mem=1204.0M) ***

[04/04 17:06:32 602s] <clockDesign CMD> changeClockStatus -all -fixedBuffers

[04/04 17:06:32 602s] Redoing specifyClockTree ...
[04/04 17:06:32 602s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:06:32 602s] Checking spec file integrity...

[04/04 17:06:32 602s] *** Changed status on (280) instances, and (0) nets in
Clock clk.
[04/04 17:06:32 602s] *** End changeClockStatus (cpu=0:00:00.2,
real=0:00:00.0, mem=1204.0M) ***
[04/04 17:06:32 602s] <clockDesign CMD> deleteClockTree -all
[04/04 17:06:32 602s] Redoing specifyClockTree ...
[04/04 17:06:32 602s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:06:32 602s] Checking spec file integrity...

[04/04 17:06:32 602s]
[04/04 17:06:32 602s] deleteClockTree Option : -all
[04/04 17:06:32 602s] List of dont use cells: HOLDX1
[04/04 17:06:32 602s] List of dont touch cells:
[04/04 17:06:32 602s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 17:06:32 602s] **WARN: (ENCCK-767):
the clock tree.

Find clock buffer clk__L1_I0 in

[04/04 17:06:32 602s] Type 'man ENCCK-767' for more detail.

[04/04 17:06:32 602s] *** 10 Buffers found to be either having FIXED attribute
or constraints on it. deleteClockTree may not delete them.***
[04/04 17:06:32 602s] *** Use changeClockStatus to change the FIXED status.
***
[04/04 17:06:32 602s] *** Removed (0) buffers and (0) inverters in Clock clk.
[04/04 17:06:32 602s] ***** Delete Clock Tree Finished (CPU Time: 0:00:00.0
MEM: 1204.043M)
[04/04 17:06:32 602s] *** End deleteClockTree (cpu=0:00:00.0, real=0:00:00.0,
mem=1204.0M) ***

[04/04 17:06:32 602s] <clockDesign CMD> ckSynthesis -report

clock_report/clock.report -forceReconvergent -breakLoop
[04/04 17:06:32 602s] Redoing specifyClockTree ...
[04/04 17:06:32 602s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:06:32 602s] Checking spec file integrity...

[04/04 17:06:32 602s] List of dont use cells: HOLDX1
[04/04 17:06:32 602s] List of dont touch cells:
[04/04 17:06:32 602s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 17:06:32 602s] ***** Allocate Placement Memory Finished (MEM:
1204.043M)
[04/04 17:06:32 602s]
[04/04 17:06:32 602s] Start to trace clock trees ...
[04/04 17:06:32 602s] *** Begin Tracer (mem=1204.0M) ***
[04/04 17:06:32 602s] **WARN: (ENCCK-767):
the clock tree.

Find clock buffer clk__L1_I0 in

[04/04 17:06:32 602s] Type 'man ENCCK-767' for more detail.

[04/04 17:06:32 602s] **WARN: (ENCCK-209):
Clock clk has been
synthesized. Type 'man ENCCK-209' to see extended message about this
warning.
[04/04 17:06:32 602s] Type 'man ENCCK-209' for more detail.
[04/04 17:06:32 602s] *** End Tracer (mem=1204.0M) ***
[04/04 17:06:32 602s] **WARN: (ENCCK-719):
synthesized.

No clock tree has been

[04/04 17:06:32 602s] *** End ckSynthesis (cpu=0:00:00.3, real=0:00:00.0,

mem=1204.0M) ***
[04/04 17:06:32 602s] **clockDesign ... cpu = 0:00:01, real = 0:00:01, mem =
1204.0M **
[04/04 17:06:32 602s]
[04/04 17:06:32 602s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:06:32 602s] Severity ID

Count Summary

[04/04 17:06:32 602s] WARNING ENCCK-2070

option is obsolete.

4 The PadBufAfterGate

[04/04 17:06:32 602s] WARNING ENCCK-719

synthesized.

1 No clock tree has been

[04/04 17:06:32 602s] WARNING ENCCK-209

synthesized. Type 'man...

1 Clock %s has been

[04/04 17:06:32 602s] WARNING ENCCK-767

the clock tree.

2 Find clock buffer %s in

[04/04 17:06:32 602s] *** Message Summary: 8 warning(s), 0 error(s)

[04/04 17:06:32 602s]
[04/04 17:07:01 603s] <CMD> zoomBox 72.114 98.072 94.214 72.499
[04/04 17:07:03 603s] <CMD> fit
[04/04 17:08:05 606s] <CMD> selectObjByProp Instance <Status>=<Fixed>
[04/04 17:08:16 607s] <CMD> deselectAll
[04/04 17:08:23 608s] <CMD> setPlaceMode -fp false
[04/04 17:08:23 608s] <CMD> placeDesign
[04/04 17:08:23 608s] *** Starting placeDesign default flow ***
[04/04 17:08:23 608s] **INFO: Enable pre-place timing setting for timing
analysis
[04/04 17:08:23 608s] Set Using Default Delay Limit as 101.
[04/04 17:08:23 608s] **WARN: (ENCDC-1629):
The default delay limit was
set to 101. This is less than the default of 1000 and may result in inaccurate
delay calculation for nets with a fanout higher than the setting. If needed, the
default delay limit may be adjusted by running the command 'set
delaycal_use_default_delay_limit'.
[04/04 17:08:23 608s] Set Default Net Delay as 0 ps.
[04/04 17:08:23 608s] Set Default Net Load as 0 pF.
[04/04 17:08:23 608s] **INFO: Analyzing IO path groups for slack adjustment
[04/04 17:08:23 608s] Effort level <high> specified for reg2reg_tmp.12308
path_group
[04/04 17:08:23 608s]
################################################
#################################

[04/04 17:08:23 608s] # Design Stage: PreRoute

[04/04 17:08:23 608s] # Design Mode: 90nm
[04/04 17:08:23 608s] # Analysis Mode: MMMC non-OCV
[04/04 17:08:23 608s] # Extraction Mode: default
[04/04 17:08:23 608s] # Delay Calculation Options: engine=aae
SIAware=false(opt_signoff)
[04/04 17:08:23 608s] # Switching Delay Calculation Engine to AAE
[04/04 17:08:23 608s]
################################################
#################################
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...

[04/04 17:08:23 608s] Calculate delays in BcWc mode...

[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Calculate delays in BcWc mode...
[04/04 17:08:23 608s] Topological Sorting (CPU = 0:00:00.0, MEM = 1213.8M,
InitMEM = 1213.8M)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:08:28 613s] AAE_THRD: End delay calculation. (MEM=1440.91
CPU=0:00:04.9 REAL=0:00:05.0)
[04/04 17:08:28 613s] *** CDM Built up (cpu=0:00:05.3 real=0:00:05.0 mem=
1440.9M) ***

[04/04 17:08:29 614s] * Start deleteBufferTree *

[04/04 17:08:29 614s] Info: Detect buffers to remove automatically.
[04/04 17:08:29 614s] Analyzing netlist ...
[04/04 17:08:30 615s] Updating netlist
[04/04 17:08:30 615s]
[04/04 17:08:30 615s] *summary: 0 instances (buffers/inverters) removed
[04/04 17:08:30 615s] *** Finish deleteBufferTree (0:00:00.5) ***
[04/04 17:08:30 615s] **INFO: Disable pre-place timing setting for timing
analysis
[04/04 17:08:30 615s] Set Using Default Delay Limit as 1000.
[04/04 17:08:30 615s] Set Default Net Delay as 1000 ps.
[04/04 17:08:30 615s] Set Default Net Load as 0.5 pF.
[04/04 17:08:30 615s] Some Marcos are marked as preplaced.
[04/04 17:08:30 615s] *** Starting "NanoPlace(TM) placement v#1
(mem=1256.9M)" ...
[04/04 17:08:44 629s] *** Build Buffered Sizing Timing Model
[04/04 17:08:44 629s] (cpu=0:00:14.4 mem=1256.9M) ***
[04/04 17:08:44 629s] *** Build Virtual Sizing Timing Model
[04/04 17:08:44 629s] (cpu=0:00:14.7 mem=1256.9M) ***
[04/04 17:08:44 630s] Options: timingDriven clkGateAware ignoreScan
pinGuide congEffort=auto gpeffort=medium
[04/04 17:08:45 630s] **WARN: (ENCSP-9042):
defined, -ignoreScan option will be ignored.

Scan chains were not

[04/04 17:08:45 630s] Define the scan chains before using this option.
[04/04 17:08:45 630s] Type 'man ENCSP-9042' for more detail.
[04/04 17:08:45 630s] #std cell=2195 (0 fixed + 2195 movable) #block=4 (0
floating + 4 preplaced)
[04/04 17:08:45 630s] #ioInst=0 #net=2284 #term=8784 #term/net=3.85,
#fixedIo=144, #floatIo=0, #fixedPin=117, #floatPin=0
[04/04 17:08:45 630s] stdCell: 2195 single + 0 double + 0 multi

[04/04 17:08:45 630s] Total standard cell length = 5.9824 (mm), area = 0.0102
(mm^2)
[04/04 17:08:45 630s] Core basic site is CoreSite
[04/04 17:08:45 630s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:08:45 631s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:08:45 631s] Average module density = 0.566.
[04/04 17:08:45 631s] Density for the design = 0.566.
[04/04 17:08:45 631s]
= stdcell_area 29912 sites (10230 um^2) /
alloc_area 52885 sites (18087 um^2).
[04/04 17:08:45 631s] Pin Density = 0.069.
[04/04 17:08:45 631s]
127198.

= total # of pins 8784 / total Instance area

[04/04 17:08:45 631s] === lastAutoLevel = 8

[04/04 17:08:45 631s] Found multi-fanin net mpy_result[0]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[1]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[2]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[3]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[4]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[5]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[6]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[7]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[8]
[04/04 17:08:45 631s] Found multi-fanin net mpy_result[9]
[04/04 17:08:45 631s] ......
[04/04 17:08:45 631s] Found 32 (out of 2316) multi-fanin nets.
[04/04 17:08:51 636s] Redoing specifyClockTree ...
[04/04 17:08:51 636s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

cpu = 0:00:01.5 real = 0:00:02.0 mem =

[04/04 17:08:57 643s] Congestion driven padding in post-place stage.

[04/04 17:08:58 643s] Congestion driven padding increases utilization from
0.565 to 0.631
[04/04 17:08:58 643s] Congestion driven padding runtime: cpu = 0:00:00.0 real
= 0:00:01.0 mem = 1415.9M
[04/04 17:08:58 643s] Iteration 9: Total net bbox = 6.195e+04 (3.09e+04
3.11e+04)

[04/04 17:08:58 643s]

3.76e+04)

Est. stn bbox = 7.492e+04 (3.73e+04

[04/04 17:08:58 643s]

1415.9M

cpu = 0:00:01.0 real = 0:00:01.0 mem =

[04/04 17:08:59 644s] nrCritNet: 4.95% ( 113 / 2284 ) cutoffSlk: -274.7ps

stdDelay: 11.6ps
[04/04 17:08:59 644s] nrCritNet: 0.00% ( 0 / 2284 ) cutoffSlk: -419.1ps
stdDelay: 11.6ps
[04/04 17:08:59 644s] Iteration 10: Total net bbox = 6.206e+04 (3.09e+04
3.11e+04)
[04/04 17:08:59 644s]
3.77e+04)

Est. stn bbox = 7.503e+04 (3.73e+04

[04/04 17:08:59 644s]

1415.9M

cpu = 0:00:01.5 real = 0:00:01.0 mem =

[04/04 17:09:00 645s] Iteration 11: Total net bbox = 6.407e+04 (3.17e+04
3.23e+04)
[04/04 17:09:00 645s]
3.89e+04)

Est. stn bbox = 7.697e+04 (3.80e+04

[04/04 17:09:00 645s]

1415.9M

cpu = 0:00:01.4 real = 0:00:01.0 mem =

[04/04 17:09:00 645s] Iteration 12: Total net bbox = 6.407e+04 (3.17e+04
3.23e+04)
[04/04 17:09:00 645s]
3.89e+04)

Est. stn bbox = 7.697e+04 (3.80e+04

[04/04 17:09:00 645s]

1415.9M

cpu = 0:00:00.0 real = 0:00:00.0 mem =

[04/04 17:09:00 645s] *** cost = 6.407e+04 (3.17e+04 3.23e+04) (cpu for
global=0:00:09.9) real=0:00:09.0***
[04/04 17:09:00 645s] Info: 0 clock gating cells identified, 0 (on average)
moved
[04/04 17:09:00 645s] Core Placement runtime cpu: 0:00:05.4 real: 0:00:04.0
[04/04 17:09:01 646s] **WARN: (ENCSP-9025):
specified/traced.

No scan chain

[04/04 17:09:01 646s] Type 'man ENCSP-9025' for more detail.

[04/04 17:09:01 646s] Core basic site is CoreSite

[04/04 17:09:01 646s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:09:01 646s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:09:01 646s] *** Starting refinePlace (0:10:45 mem=1202.0M) ***
[04/04 17:09:01 646s] Total net length = 5.593e+04 (2.762e+04 2.831e+04)
(ext = 8.301e+03)
[04/04 17:09:01 646s] Starting refinePlace ...
[04/04 17:09:01 646s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:09:02 647s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:09:02 647s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.1,
real=0:00:01.0, mem=1206.6MB) @(0:10:45 - 0:10:45).
[04/04 17:09:02 647s] Move report: preRPlace moves 2195 insts, mean move:
0.54 um, max move: 4.34 um
[04/04 17:09:02 647s] Max move on inst
(EXECUTE_INST/acc_reg[12]/state_remap/DFF): (116.51, 79.55) --> (116.60,
83.79)
[04/04 17:09:02 647s]
cell type: SDFFRX4

Length: 39 sites, height: 1 rows, site name: CoreSite,

[04/04 17:09:02 647s] wireLenOptFixPriorityInst 280 inst fixed

[04/04 17:09:02 647s] Placement tweakage begins.
[04/04 17:09:02 647s] wire length = 6.890e+04
[04/04 17:09:02 647s] wire length = 6.852e+04
[04/04 17:09:02 647s] Placement tweakage ends.
[04/04 17:09:02 647s] Move report: tweak moves 403 insts, mean move: 2.84
um, max move: 13.20 um
[04/04 17:09:02 647s] Max move on inst (TDSP_CORE_GLUE_INST/g8334):
(109.00, 83.79) --> (95.80, 83.79)
[04/04 17:09:02 647s] [CPU] RefinePlace/TweakPlacement (cpu=0:00:00.2,
real=0:00:00.0, mem=1206.6MB) @(0:10:45 - 0:10:45).
[04/04 17:09:02 647s] Move report: legalization moves 73 insts, mean move:
0.31 um, max move: 3.42 um
[04/04 17:09:02 647s] Max move on inst (EXECUTE_INST/g16450): (85.00,
147.06) --> (85.00, 150.48)

[04/04 17:09:02 647s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,

real=0:00:00.0, mem=1206.6MB) @(0:10:45 - 0:10:45).
[04/04 17:09:02 647s] Move report: Detail placement moves 2195 insts, mean
move: 1.01 um, max move: 13.48 um
[04/04 17:09:02 647s] Max move on inst (ACCUM_STAT_INST/g673): (109.92,
112.31) --> (112.60, 123.12)
[04/04 17:09:02 647s]
1206.6MB

Runtime: CPU: 0:00:00.3 REAL: 0:00:01.0 MEM:

[04/04 17:09:02 647s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:09:02 647s] maximum (X+Y) =

13.48 um

[04/04 17:09:02 647s] inst (ACCUM_STAT_INST/g673) with max move: (109.92,

112.315) -> (112.6, 123.12)
[04/04 17:09:02 647s] mean

(X+Y) =

1.01 um

[04/04 17:09:02 647s] Summary Report:

[04/04 17:09:02 647s] Instances move: 2195 (out of 2195 movable)
[04/04 17:09:02 647s] Mean displacement: 1.01 um
[04/04 17:09:02 647s] Max displacement: 13.48 um (Instance:
ACCUM_STAT_INST/g673) (109.92, 112.315) -> (112.6, 123.12)
[04/04 17:09:02 647s]
cell type: NOR2BX1

Length: 5 sites, height: 1 rows, site name: CoreSite,

[04/04 17:09:02 647s] Total instances moved : 2195

[04/04 17:09:02 647s] Total net length = 5.681e+04 (2.789e+04 2.892e+04)
(ext = 8.354e+03)
[04/04 17:09:02 647s] Runtime: CPU: 0:00:00.3 REAL: 0:00:01.0 MEM:
1206.6MB
[04/04 17:09:02 647s] [CPU] RefinePlace/total (cpu=0:00:00.3, real=0:00:01.0,
mem=1206.6MB) @(0:10:45 - 0:10:45).
[04/04 17:09:02 647s] *** Finished refinePlace (0:10:45 mem=1206.6M) ***
[04/04 17:09:02 647s] Total net length = 5.679e+04 (2.789e+04 2.890e+04)
(ext = 8.350e+03)
[04/04 17:09:02 647s] *** End of Placement (cpu=0:00:31.7, real=0:00:32.0,
mem=1206.6M) ***
[04/04 17:09:02 647s] Core basic site is CoreSite

[04/04 17:09:02 647s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:09:02 647s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:09:02 647s] default core: bins with density > 0.75 = 70.4 % ( 119 /
169 )
[04/04 17:09:02 647s] Density distribution unevenness ratio = 11.344%
[04/04 17:09:02 647s] *** Free Virtual Timing Model ...(mem=1206.6M)
[04/04 17:09:02 647s] Starting IO pin assignment...
[04/04 17:09:02 647s] Starting congestion repair ...
[04/04 17:09:02 647s] congRepair options: -clkGateAware 1
-rplaceIncrNPClkGateAwareMode 4.
[04/04 17:09:02 647s] *** Starting trialRoute (mem=1206.6M) ***
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:09:02 647s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:09:02 647s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:09:02 647s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Nr of prerouted/Fixed nets = 23
[04/04 17:09:02 647s] There are 23 nets with 1 extra space.
[04/04 17:09:02 647s] routingBox: (-200 -330) (220200 217310)
[04/04 17:09:02 647s] coreBox:

(0 0) (220000 216980)

[04/04 17:09:02 647s] There are 23 prerouted nets with extraSpace.

[04/04 17:09:02 647s] Number of multi-gpin terms=2397, multi-gpins=5647,
moved blk term=63/63
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Phase 1a route (0:00:00.0 1206.6M):
[04/04 17:09:02 647s] Est net length = 6.239e+04um = 3.050e+04H +
3.188e+04V

[04/04 17:09:02 647s] Usage: (8.9%H 11.1%V) = (3.723e+04um

4.824e+04um) = (37231 28207)
[04/04 17:09:02 647s] Obstruct: 8394 = 4197 (15.0%H) + 4197 (15.0%V)
[04/04 17:09:02 647s] Overflow: 36 = 36 (0.15% H) + 0 (0.00% V)
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Phase 1b route (0:00:00.0 1206.6M):
[04/04 17:09:02 647s] Usage: (8.8%H 11.1%V) = (3.715e+04um
4.822e+04um) = (37150 28199)
[04/04 17:09:02 647s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Phase 1c route (0:00:00.0 1206.6M):
[04/04 17:09:02 647s] Usage: (8.8%H 11.1%V) = (3.709e+04um
4.820e+04um) = (37091 28184)
[04/04 17:09:02 647s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Phase 1d route (0:00:00.0 1206.6M):
[04/04 17:09:02 647s] Usage: (8.8%H 11.1%V) = (3.709e+04um
4.820e+04um) = (37091 28184)
[04/04 17:09:02 647s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Phase 1a-1d Overflow: 0.00% H + 0.00% V (0:00:00.1
1206.6M)

[04/04 17:09:02 647s]

[04/04 17:09:02 647s] Phase 1e route (0:00:00.0 1206.6M):
[04/04 17:09:02 647s] Usage: (8.8%H 11.1%V) = (3.709e+04um
4.820e+04um) = (37091 28184)
[04/04 17:09:02 647s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Overflow: 0.00% H + 0.00% V (0:00:00.0 1206.6M)

[04/04 17:09:02 647s] Usage: (8.8%H 11.1%V) = (3.709e+04um

4.820e+04um) = (37091 28184)
[04/04 17:09:02 647s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Congestion distribution:
[04/04 17:09:02 647s]
[04/04 17:09:02 647s] Remain cntH

cntV

[04/04 17:09:02 647s] -------------------------------------[04/04 17:09:02 647s] -------------------------------------[04/04 17:09:02 647s] 0:

0.00%

[04/04 17:09:02 647s] 1:

0.00%

0.02%

[04/04 17:09:02 647s] 2:

0.00%

0.06%

[04/04 17:09:02 647s] 3:

0.00%

0.22%

[04/04 17:09:02 647s] 4:

0.01%

709

2.99%

[04/04 17:09:02 647s] 5:

2373999.98%

2296296.71%

[04/04 17:09:02 647s]

[04/04 17:09:02 647s] Global route (cpu=0.1s real=0.1s 1206.6M)
[04/04 17:09:02 647s] Updating RC grid for preRoute extraction ...
[04/04 17:09:02 647s] Initializing multi-corner capacitance tables ...
[04/04 17:09:02 647s] Initializing multi-corner resistance tables ...
[04/04 17:09:02 648s] There are 23 prerouted nets with extraSpace.
[04/04 17:09:02 648s]
[04/04 17:09:02 648s]
[04/04 17:09:02 648s] *** After '-updateRemainTrks' operation:
[04/04 17:09:02 648s]
[04/04 17:09:02 648s] Usage: (9.0%H 11.5%V) = (3.787e+04um
5.008e+04um) = (37871 29282)
[04/04 17:09:02 648s] Overflow: 11 = 0 (0.00% H) + 11 (0.05% V)
[04/04 17:09:02 648s]

0.00%

0.28%

[04/04 17:09:02 648s] 4:

0.02%

727

3.06%

[04/04 17:09:02 648s] 5:

2373799.97%

2287996.36%

[04/04 17:09:02 648s]

[04/04 17:09:02 648s]
[04/04 17:09:02 648s] *** Completed Phase 1 route (0:00:00.5 1214.6M) ***
[04/04 17:09:02 648s]
[04/04 17:09:02 648s]
[04/04 17:09:02 648s] ** np local hotspot detection info verbose **
[04/04 17:09:02 648s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:09:02 648s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:09:02 648s]

[04/04 17:09:03 648s]

[04/04 17:09:03 648s] Total length: 6.637e+04um, number of vias: 19316
[04/04 17:09:03 648s] M1(H) length: 4.158e+01um, number of vias: 8421
[04/04 17:09:03 648s] M2(V) length: 1.847e+04um, number of vias: 7888
[04/04 17:09:03 648s] M3(H) length: 2.576e+04um, number of vias: 1506
[04/04 17:09:03 648s] M4(V) length: 9.745e+03um, number of vias: 605
[04/04 17:09:03 648s] M5(H) length: 2.979e+03um, number of vias: 512
[04/04 17:09:03 648s] M6(V) length: 3.092e+03um, number of vias: 191
[04/04 17:09:03 648s] M7(H) length: 2.224e+03um, number of vias: 163
[04/04 17:09:03 648s] M8(V) length: 3.263e+03um, number of vias: 30
[04/04 17:09:03 648s] M9(H) length: 7.872e+02um
[04/04 17:09:03 648s] *** Completed Phase 2 route (0:00:00.2 1214.6M) ***
[04/04 17:09:03 648s]
[04/04 17:09:03 648s] *** Finished all Phases (cpu=0:00:00.7 mem=1214.6M)
***
[04/04 17:09:03 648s] dbSprFixZeroViaCodes runtime= 0:00:00.0
[04/04 17:09:03 648s] Peak Memory Usage was 1214.6M
[04/04 17:09:03 648s] TrialRoute+GlbRouteEst total runtime= +0:00:00.8 =
0:00:08.8
[04/04 17:09:03 648s] TrialRoute full (called 11x) runtime= 0:00:08.1
[04/04 17:09:03 648s] TrialRoute check only (called 4x) runtime= 0:00:00.1
[04/04 17:09:03 648s] GlbRouteEst (called 19x) runtime= 0:00:00.6
[04/04 17:09:03 648s] *** Finished trialRoute (cpu=0:00:00.8 mem=1214.6M)
***
[04/04 17:09:03 648s]
[04/04 17:09:03 648s] Local HotSpot Analysis: normalized max congestion
hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in
unit of 4 std-cell row bins)
[04/04 17:09:03 648s]
[04/04 17:09:03 648s] ** np local hotspot detection info verbose **

[04/04 17:09:03 648s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:09:03 648s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:09:03 648s]
[04/04 17:09:03 648s] describeCongestion: hCong = 0.00 vCong = 0.00
[04/04 17:09:03 648s] Trial Route Overflow 0.000000(H) 0.047562(V).
[04/04 17:09:03 648s] Start repairing congestion with level 1.
[04/04 17:09:03 648s] Skipped repairing congestion.
[04/04 17:09:03 648s] End of congRepair (cpu=0:00:00.8, real=0:00:01.0)
[04/04 17:09:03 648s] *** Finishing placeDesign default flow ***
[04/04 17:09:03 648s] **placeDesign ... cpu = 0: 0:40, real = 0: 0:40, mem =
1203.6M **
[04/04 17:09:03 648s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:09:03 648s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132

Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:09:03 648s]
[04/04 17:09:03 648s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:09:03 648s] Severity ID

Count Summary

[04/04 17:09:03 648s] WARNING ENCCK-2070

option is obsolete.

1 The PadBufAfterGate

[04/04 17:09:03 648s] WARNING ENCDC-1629

was set to %d. T...

1 The default delay limit

[04/04 17:09:03 648s] WARNING ENCSP-9025

specified/traced.

1 No scan chain

[04/04 17:09:03 648s] WARNING ENCSP-9042

defined, -ignoreSca...

1 Scan chains were not

[04/04 17:09:03 648s] *** Message Summary: 4 warning(s), 0 error(s)

[04/04 17:09:03 648s]
[04/04 17:09:05 648s] <CMD> fit
[04/04 17:09:06 648s] <CMD> fit
[04/04 17:09:07 648s] <CMD> fit

[04/04 17:09:16 649s] <CMD> clockDesign -specFile ../../DATA/clock.ctstch

-outDir clock_report -fixedInstBeforeCTS
[04/04 17:09:16 649s] -engine ck
ccopt_from_edi_spec}, default=auto, user setting

# enums={ck ccopt auto

[04/04 17:09:16 649s] **clockDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1223.6M **
[04/04 17:09:16 649s] setCTSMode -engine ck -moveGateLimit 25
[04/04 17:09:16 649s] <clockDesign INFO> 'setCTSMode -routeClkNet true' is
set inside clockDesign.
[04/04 17:09:16 649s]
[04/04 17:09:16 649s] <clockDesign CMD> cleanupSpecifyClockTree
[04/04 17:09:16 649s] <clockDesign CMD> specifyClockTree -file
../../DATA/clock.ctstch
[04/04 17:09:16 649s] Checking spec file integrity...
[04/04 17:09:16 649s]
[04/04 17:09:16 649s] Reading clock tree spec file '../../DATA/clock.ctstch' ...
[04/04 17:09:16 649s]
[04/04 17:09:16 649s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:09:16 649s] Updating RC grid for preRoute extraction ...

[04/04 17:09:16 649s] Initializing multi-corner capacitance tables ...
[04/04 17:09:17 649s] Initializing multi-corner resistance tables ...
[04/04 17:09:17 649s] RouteType

: FE_CTS_DEFAULT

[04/04 17:09:17 649s] PreferredExtraSpace

[04/04 17:09:17 649s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:09:17 649s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:09:17 649s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:09:17 649s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:09:17 649s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:09:17 649s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:09:17 649s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:09:17 649s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:09:17 649s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:09:17 649s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

es=0.32(um) cap=0.109(ff/um) res=1.23(ohm/um) viaRes=0(ohm) viaCap=0(ff)

[04/04 17:09:17 649s] M2(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)

cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.04792(ohm)
viaCap=0.0558832(ff)
[04/04 17:09:17 649s] M3(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 17:09:17 649s] M4(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.8575(ohm)
viaCap=0.0480942(ff)
[04/04 17:09:17 649s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 17:09:17 649s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 17:09:17 649s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:09:17 649s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:09:17 649s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 17:09:17 649s]
[04/04 17:09:17 649s] Switching off Advanced RC Correlation modes in AAE
mode.
[04/04 17:09:17 649s] Active Analysis Views for CTS are,
[04/04 17:09:17 649s] #1 Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:09:17 649s] #2 Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:09:17 649s] #3 Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:09:17 649s] #4 Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:09:17 649s] #5 Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:09:17 649s] #6 Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:09:17 649s] #7 Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:09:17 649s] #8 Arise_analysis_view_test_nom_cmax_T25V12

[04/04 17:09:17 649s] #9 Arise_analysis_view_test_nom_cmax_T50V13

[04/04 17:09:17 649s] #10 Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:09:17 649s] #11 Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:09:17 649s] #12 Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:09:17 649s] #13 Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:09:17 649s] #14 Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:09:17 649s] #15 Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:09:17 649s] #16 Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:09:17 649s] #17 Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:09:17 649s] #18 Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:09:17 649s] #19 Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:09:17 649s] #20 Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:09:17 649s] #21 Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:09:17 649s] #22 Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:09:17 649s] #23 Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:09:17 649s] #24 Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:09:17 649s] #25 Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:09:17 649s] #26 Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:09:17 649s] #27 Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:09:17 649s] #28 Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:09:17 649s] #29 Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:09:17 649s] #30 Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:09:17 649s] #31 Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:09:17 649s] #32 Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:09:17 649s] #33 Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:09:17 649s] #34 Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:09:17 649s] #35 Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:09:17 649s] Default Analysis Views is
Arise_analysis_view_test_max_cmax_T150V08

[04/04 17:09:17 649s]

[04/04 17:09:17 649s]
[04/04 17:09:17 649s] ****** AutoClockRootPin ******
[04/04 17:09:17 649s] AutoClockRootPin 1: clk
[04/04 17:09:17 649s] # NoGating

[04/04 17:09:17 649s] # SetDPinAsSync

[04/04 17:09:17 649s] # SetIoPinAsSync NO

[04/04 17:09:17 649s] # SetAsyncSRPinAsSync NO
[04/04 17:09:17 649s] # SetTriStEnPinAsSync NO
[04/04 17:09:17 649s] # SetBBoxPinAsSync NO
[04/04 17:09:17 649s] # RouteClkNet
[04/04 17:09:17 649s] # PostOpt

YES
YES

[04/04 17:09:17 649s] # RouteType

[04/04 17:09:17 649s] # LeafRouteType

FE_CTS_DEFAULT
FE_CTS_DEFAULT_LEAF

[04/04 17:09:17 649s]

[04/04 17:09:17 649s] ***** !! NOTE !! *****
[04/04 17:09:17 649s]
[04/04 17:09:17 649s] CTS treats D-pins and I/O pins as non-synchronous pins
by default.
[04/04 17:09:17 649s] If you want to change the behavior, you need to use the
SetDPinAsSync
[04/04 17:09:17 649s] or SetIoPinAsSync statement in the clock tree
specification file,
[04/04 17:09:17 649s] or use the setCTSMode -traceDPinAsLeaf {true|false}
command,
[04/04 17:09:17 649s] or use the setCTSMode -traceIoPinAsLeaf {true|false}
command
[04/04 17:09:17 649s] before specifyClockTree command.
[04/04 17:09:17 649s]
[04/04 17:09:17 649s] *** End specifyClockTree (cpu=0:00:00.3,
real=0:00:01.0, mem=1223.6M) ***

[04/04 17:09:17 649s] <clockDesign CMD> changeClockStatus -all -fixedBuffers

[04/04 17:09:17 649s] Redoing specifyClockTree ...
[04/04 17:09:17 649s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:09:17 649s] Checking spec file integrity...

[04/04 17:09:17 649s] *** Changed status on (280) instances, and (0) nets in
Clock clk.
[04/04 17:09:17 649s] *** End changeClockStatus (cpu=0:00:00.2,
real=0:00:00.0, mem=1223.6M) ***
[04/04 17:09:17 649s] <clockDesign CMD> deleteClockTree -all
[04/04 17:09:17 649s] Redoing specifyClockTree ...
[04/04 17:09:17 649s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:09:17 649s] Checking spec file integrity...

[04/04 17:09:17 649s]
[04/04 17:09:17 649s] deleteClockTree Option : -all
[04/04 17:09:17 649s] List of dont use cells: HOLDX1
[04/04 17:09:17 649s] List of dont touch cells:
[04/04 17:09:17 649s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 17:09:17 649s] **WARN: (ENCCK-767):
the clock tree.

Find clock buffer clk__L1_I0 in

[04/04 17:09:17 649s] Type 'man ENCCK-767' for more detail.

[04/04 17:09:17 649s] *** 10 Buffers found to be either having FIXED attribute
or constraints on it. deleteClockTree may not delete them.***
[04/04 17:09:17 649s] *** Use changeClockStatus to change the FIXED status.
***
[04/04 17:09:17 649s] *** Removed (0) buffers and (0) inverters in Clock clk.
[04/04 17:09:17 649s] ***** Delete Clock Tree Finished (CPU Time: 0:00:00.0
MEM: 1223.598M)
[04/04 17:09:17 649s] *** End deleteClockTree (cpu=0:00:00.0, real=0:00:00.0,
mem=1223.6M) ***

[04/04 17:09:17 649s] <clockDesign CMD> ckSynthesis -report

clock_report/clock.report -forceReconvergent -breakLoop
[04/04 17:09:17 649s] Redoing specifyClockTree ...
[04/04 17:09:17 649s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:09:17 649s] Checking spec file integrity...

[04/04 17:09:17 649s] List of dont use cells: HOLDX1
[04/04 17:09:17 649s] List of dont touch cells:
[04/04 17:09:17 649s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 17:09:17 650s] ***** Allocate Placement Memory Finished (MEM:
1223.598M)
[04/04 17:09:17 650s]
[04/04 17:09:17 650s] Start to trace clock trees ...
[04/04 17:09:17 650s] *** Begin Tracer (mem=1223.6M) ***
[04/04 17:09:17 650s] **WARN: (ENCCK-767):
the clock tree.

Find clock buffer clk__L1_I0 in

[04/04 17:09:17 650s] Type 'man ENCCK-767' for more detail.

[04/04 17:09:17 650s] **WARN: (ENCCK-209):
Clock clk has been
synthesized. Type 'man ENCCK-209' to see extended message about this
warning.
[04/04 17:09:17 650s] Type 'man ENCCK-209' for more detail.
[04/04 17:09:17 650s] *** End Tracer (mem=1223.6M) ***
[04/04 17:09:17 650s] **WARN: (ENCCK-719):
synthesized.

No clock tree has been

[04/04 17:09:17 650s] *** End ckSynthesis (cpu=0:00:00.3, real=0:00:00.0,

mem=1223.6M) ***
[04/04 17:09:17 650s] **clockDesign ... cpu = 0:00:01, real = 0:00:01, mem =
1223.6M **
[04/04 17:09:17 650s]
[04/04 17:09:17 650s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:09:17 650s] Severity ID

Count Summary

[04/04 17:09:17 650s] WARNING ENCCK-2070

option is obsolete.

4 The PadBufAfterGate

[04/04 17:09:17 650s] WARNING ENCCK-719

synthesized.

1 No clock tree has been

[04/04 17:09:17 650s] WARNING ENCCK-209

synthesized. Type 'man...

1 Clock %s has been

[04/04 17:09:17 650s] WARNING ENCCK-767

the clock tree.

2 Find clock buffer %s in

[04/04 17:09:17 650s] *** Message Summary: 8 warning(s), 0 error(s)

[04/04 17:09:17 650s]
[04/04 17:10:09 650s] <CMD> saveRelativeFPlan tcl/relative_placement.tcl
[04/04 17:10:44 651s] <CMD> freeDesign
[04/04 17:10:44 651s] **WARN: (ENCSYC-6163): Command 'freeDesign' is
obsolete and will be made private and will be unsupported in future release. To
avoid this warning, please remove the obsolete command from your script.
[04/04 17:10:44 651s] Reset to color id 0 for ACCUM_STAT_INST (accum_stat)
and all their descendants.
[04/04 17:10:44 651s] Reset to color id 0 for ALU_32_INST (alu_32) and all their
descendants.
[04/04 17:10:44 651s] Reset to color id 0 for DATA_BUS_MACH_INST
(data_bus_mach) and all their descendants.
[04/04 17:10:44 651s] Reset to color id 0 for DECODE_INST (decode_i) and all
their descendants.
[04/04 17:10:44 651s] Reset to color id 0 for EXECUTE_INST (execute_i) and all
their descendants.
[04/04 17:10:44 651s] Reset to color id 0 for PORT_BUS_MACH_INST
(port_bus_mach) and all their descendants.
[04/04 17:10:44 651s] Reset to color id 0 for PROG_BUS_MACH_INST
(prog_bus_mach) and all their descendants.
[04/04 17:10:44 651s] Reset to color id 0 for TDSP_CORE_GLUE_INST
(tdsp_core_glue) and all their descendants.
[04/04 17:10:44 651s] Reset to color id 0 for TDSP_CORE_MACH_INST
(tdsp_core_mach) and all their descendants.
[04/04 17:10:44 651s] ### Ignoring a total of 1 master slice layers:

[04/04 17:10:44 651s] ### Oxide

[04/04 17:10:44 651s] Free PSO.
[04/04 17:10:44 651s] Reset cap table.
[04/04 17:10:44 651s] Cleaning up the current multi-corner RC extraction setup.
[04/04 17:10:44 651s] Design tdsp_core was changed but not saved - it will be
overwritten.
[04/04 17:10:44 651s] Set DBUPerIGU to 1000.
[04/04 17:10:44 651s] Set net toggle Scale Factor to 1.00
[04/04 17:10:44 651s] Set Shrink Factor to 1.00000
[04/04 17:10:45 651s] Set net toggle Scale Factor to 1.00
[04/04 17:10:45 651s] Set Shrink Factor to 1.00000
[04/04 17:10:45 651s] Set net toggle Scale Factor to 1.00
[04/04 17:10:45 651s] Set Shrink Factor to 1.00000
[04/04 17:10:45 651s]
[04/04 17:10:45 651s] *** Memory Usage v#1 (Current mem = 1204.414M,
initial mem = 98.977M) ***
[04/04 17:10:45 651s]
[04/04 17:10:45 651s]
[04/04 17:10:45 651s] Info (SM2C): Status of key globals:
[04/04 17:10:45 651s]

MMMC-by-default flow

[04/04 17:10:45 651s]

Default MMMC objs envvar : 0

[04/04 17:10:45 651s]

Data portability

[04/04 17:10:45 651s]

[04/04 17:11:06 652s] <CMD> init_design

[04/04 17:11:06 652s] **ERROR: (TCLCMD-994): Can not find 'analysis view'
object with the name 'Arise_analysis_view_test_max_cmax_T140V102'. This can
happen when the specified name of any MMMC object is incorrectly spelled or
has been removed from the running session.
[04/04 17:11:06 652s]
[04/04 17:11:06 652s] Loading LEF file ../../LEF/gsclib045.lef ...
[04/04 17:11:06 652s] Set DBUPerIGU to M2 pitch 200.
[04/04 17:11:06 652s]
[04/04 17:11:06 652s] Loading LEF file ../sub_block/mult_32.lef ...
[04/04 17:11:06 652s]
[04/04 17:11:06 652s] Loading LEF file ../sub_block/mult_32_pg1.lef ...
[04/04 17:11:06 652s]
[04/04 17:11:06 652s] Loading LEF file ../sub_block/mult_32_pg2.lef ...
[04/04 17:11:06 652s]
[04/04 17:11:06 652s] Loading LEF file suraj/rectilinear_block.lef ...
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'ovm' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[15]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[14]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[13]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.

[04/04 17:11:06 652s] **WARN: (ENCLF-200):

Pin 'op_a[12]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[11]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[10]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[9]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[8]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[7]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[6]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[5]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[4]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.

[04/04 17:11:06 652s] **WARN: (ENCLF-200):

Pin 'op_a[3]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[2]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[1]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_a[0]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_b[15]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_b[14]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-200):
Pin 'op_b[13]' in macro
'mult_32_pg3' has no ANTENNAGATEAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-200' for more detail.
[04/04 17:11:06 652s] **WARN: (EMS-63): Message <ENCLF-200> has
exceeded the default message display limit of 20.
[04/04 17:11:06 652s] To avoid this warning, increase the display limit per
unique message by
[04/04 17:11:06 652s] using the set_message -limit <number> command.
[04/04 17:11:06 652s] The message limit can be removed by using the
set_message -no_limit command.

[04/04 17:11:06 652s] Note that setting a very large number using the
set_message -limit command
[04/04 17:11:06 652s] or removing the message limit using the set_message
-no_limit command can
[04/04 17:11:06 652s] significantly increase the log file size.
[04/04 17:11:06 652s] To suppress a message, use the set_message -suppress
command.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[31]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[30]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[29]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[28]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[27]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[26]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[25]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.

[04/04 17:11:06 652s] **WARN: (ENCLF-201):

Pin 'result[24]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[23]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[22]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[21]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[20]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[19]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[18]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[17]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[16]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.

[04/04 17:11:06 652s] **WARN: (ENCLF-201):

Pin 'result[15]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[14]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[13]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (ENCLF-201):
Pin 'result[12]' in macro
'mult_32_pg3' has no ANTENNADIFFAREA value defined. The library data is
incomplete and some process antenna rules will not be checked correctly.
[04/04 17:11:06 652s] Type 'man ENCLF-201' for more detail.
[04/04 17:11:06 652s] **WARN: (EMS-63): Message <ENCLF-201> has
exceeded the default message display limit of 20.
[04/04 17:11:06 652s] To avoid this warning, increase the display limit per
unique message by
[04/04 17:11:06 652s] using the set_message -limit <number> command.
[04/04 17:11:06 652s] The message limit can be removed by using the
set_message -no_limit command.
[04/04 17:11:06 652s] Note that setting a very large number using the
set_message -limit command
[04/04 17:11:06 652s] or removing the message limit using the set_message
-no_limit command can
[04/04 17:11:06 652s] significantly increase the log file size.
[04/04 17:11:06 652s] To suppress a message, use the set_message -suppress
command.
[04/04 17:11:06 652s]
[04/04 17:11:06 652s] viaInitial starts at Mon Apr 4 17:11:06 2016
viaInitial ends at Mon Apr 4 17:11:06 2016
*** Begin netlist parsing (mem=997.2M) ***

[04/04 17:11:06 652s] Reading netlist ...

[04/04 17:11:06 652s] Backslashed names will retain backslash and a trailing
blank character.
[04/04 17:11:06 652s] Reading verilog netlist
'../../NETLIST/tdsp_core_top_changed.v'
[04/04 17:11:06 652s]
[04/04 17:11:06 652s] *** Memory Usage v#1 (Current mem = 997.203M,
initial mem = 98.977M) ***
[04/04 17:11:06 652s] *** End netlist parsing (cpu=0:00:00.1, real=0:00:00.0,
mem=997.2M) ***
[04/04 17:11:06 652s] Top level cell is tdsp_core.
[04/04 17:11:07 653s] Loading view definition file from gopi/mmmc.view
[04/04 17:11:07 653s] Reading Arise_max_library_T150V08_set timing library
'/Projects/Training/user5/work/suraj/LIB/slow_T150_08V.lib' ...
[04/04 17:11:07 653s] Read 477 cells in library 'gpdk045bc'
[04/04 17:11:07 653s] Reading Arise_min_library_T0V132_set timing library
'/Projects/Training/user5/work/suraj/LIB/fast_T0_132V.lib' ...
[04/04 17:11:08 654s] Read 477 cells in library 'gpdk045wc'
[04/04 17:11:08 654s] *** End library_loading (cpu=0.00min, mem=0.0M,
fe_cpu=10.87min, fe_real=72.93min, fe_mem=1011.2M) ***
[04/04 17:11:08 654s] Starting recursive module instantiation check.
[04/04 17:11:08 654s] No recursion found.
[04/04 17:11:08 654s] Building hierarchical netlist for Cell tdsp_core ...
[04/04 17:11:08 654s] *** Netlist is unique.
[04/04 17:11:08 654s] ** info: there are 1523 modules.
[04/04 17:11:08 654s] ** info: there are 2213 stdCell insts.
[04/04 17:11:08 654s] ** info: there are 4 macros.
[04/04 17:11:08 654s]
[04/04 17:11:08 654s] *** Memory Usage v#1 (Current mem = 1011.227M,
initial mem = 98.977M) ***
[04/04 17:11:08 654s] *info: set bottom ioPad orient R0

[04/04 17:11:08 654s] Horizontal Layer M1 offset = 95 (derived)

[04/04 17:11:08 654s] Vertical Layer M2 offset = 100 (derived)
[04/04 17:11:08 654s] Generated pitch 0.2 in Metal9 is different from 0.33
defined in technology file in unpreferred direction.
[04/04 17:11:08 654s] Generated pitch 0.38 in Metal9 is different from 0.33
defined in technology file in preferred direction.
[04/04 17:11:08 654s] Generated pitch 0.285 in Metal8 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:11:08 654s] Generated pitch 0.285 in Metal7 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:11:08 654s] Generated pitch 0.19 in Metal6 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:11:08 654s] Generated pitch 0.19 in Metal5 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:11:08 654s] Generated pitch 0.19 in Metal4 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:11:08 654s] Generated pitch 0.19 in Metal3 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:11:08 654s] Generated pitch 0.19 in Metal2 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:11:08 654s] Generated pitch 0.2 in Metal1 is different from 0.19
defined in technology file in unpreferred direction.
[04/04 17:11:08 654s] Set Default Net Delay as 1000 ps.
[04/04 17:11:08 654s] Set Default Net Load as 0.5 pF.
[04/04 17:11:08 654s] Set Input Pin Transition Delay as 0.1 ps.
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_Tm20V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_Tm20V15 not found, use default_view_setup

[04/04 17:11:08 654s] **WARN: analysis view

Arise_analysis_view_func_min_cmin_Tm40V18 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_Tm40V18 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T50V13 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T50V13 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmax_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_Tm20V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_Tm40V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmax_Tm40V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmax_Tm20V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T20V13 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T20V13 not found, use default_view_setup

[04/04 17:11:08 654s] **WARN: analysis view

Arise_analysis_view_func_nom_cmin_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_Tm20V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_Tm20V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmin_Tm40V18 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmin_Tm40V18 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T50V13 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T50V13 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmax_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmax_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmax_T0V132 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_Tm20V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_min_cmax_Tm40V15 not found, use default_view_setup

[04/04 17:11:08 654s] **WARN: analysis view

Arise_analysis_view_test_min_cmax_Tm40V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_min_cmax_Tm20V15 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T25V12 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T20V13 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T20V13 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_func_nom_cmin_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] **WARN: analysis view
Arise_analysis_view_test_nom_cmin_T15V11 not found, use default_view_setup
[04/04 17:11:08 654s] Initializing multi-corner RC extraction with 2 active RC
Corners ...
[04/04 17:11:08 654s] **WARN: (ENCEXT-6202): In addition to the technology
file, capacitance table file is specified for all RC corners. If the technology file for
all RC corners is already specified, the capacitance table file is not required for
preRoute and postRoute extraction. In a new session, the capacitance table files
can be removed from the create_rc_corner command. In this case, the
technology file will be used for preRoute extraction and effort level
medium/high/signoff of postRoute extraction.
[04/04 17:11:08 654s] Type 'man ENCEXT-6202' for more detail.
[04/04 17:11:08 654s] Reading Capacitance Table File
../../DATA/captable_cmax ...
[04/04 17:11:08 654s] Cap table was created using Encounter 09.10-p004_1.
[04/04 17:11:08 654s] Process name: GPDK45.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2760): Layer M10 specified in the
cap table is ignored because it is greater than the maximum number of layers, 9,
specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2760): Layer M11 specified in the
cap table is ignored because it is greater than the maximum number of layers, 9,

specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2776): The via resistance between
layers M1 and M2 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 17:11:08 654s] Type 'man ENCEXT-2776' for more detail.

[04/04 17:11:08 654s] **WARN: (ENCEXT-2776): The via resistance between
layers M2 and M3 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 17:11:08 654s] Type 'man ENCEXT-2776' for more detail.

[04/04 17:11:08 654s] **WARN: (ENCEXT-2776): The via resistance between
layers M3 and M4 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 17:11:08 654s] Type 'man ENCEXT-2776' for more detail.

[04/04 17:11:08 654s] **WARN: (ENCEXT-2776): The via resistance between
layers M4 and M5 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 17:11:08 654s] Type 'man ENCEXT-2776' for more detail.

[04/04 17:11:08 654s] **WARN: (ENCEXT-2776): The via resistance between

layers M7 and M8 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 17:11:08 654s] Type 'man ENCEXT-2776' for more detail.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2776): The via resistance between
layers M8 and M9 is not defined in the capacitance table file. The via resistance
of 1.675 Ohms defined in the LEF technology file will be used as via resistance
between these layers.
[04/04 17:11:08 654s] Type 'man ENCEXT-2776' for more detail.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2710): Basic Cap table for layer M10
is ignored because the layer is not specified in the technology LEF file.
[04/04 17:11:08 654s] Reading Capacitance Table File
../../DATA/captable_cmin ...
[04/04 17:11:08 654s] Cap table was created using Encounter 09.10-p004_1.
[04/04 17:11:08 654s] Process name: GPDK45.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2760): Layer M10 specified in the
cap table is ignored because it is greater than the maximum number of layers, 9,
specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2760): Layer M11 specified in the
cap table is ignored because it is greater than the maximum number of layers, 9,
specified in the technology LEF file. Check the cap table for the invalid layer
specification.
[04/04 17:11:08 654s] **WARN: (ENCEXT-2776): The via resistance between
layers M1 and M2 is not defined in the capacitance table file. The via resistance
of 6.7 Ohms defined in the LEF technology file will be used as via resistance
between these layers.

[04/04 17:11:08 654s] Type 'man ENCEXT-2776' for more detail.

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s]

[04/04 17:11:08 654s] Analysis View:
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:11:08 654s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 17:11:08 654s]

RC-Corner Index

[04/04 17:11:08 654s]

RC-Corner Temperature : 125 Celsius

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s]

[04/04 17:11:08 654s] Analysis View:
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:11:08 654s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 17:11:08 654s]

RC-Corner Index

[04/04 17:11:08 654s]

RC-Corner Temperature : 125 Celsius

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s]

[04/04 17:11:08 654s] Analysis View:
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:11:08 654s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 17:11:08 654s]

RC-Corner Index

[04/04 17:11:08 654s]

RC-Corner Temperature : 125 Celsius

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s]

[04/04 17:11:08 654s] Analysis View:
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:11:08 654s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 17:11:08 654s]

RC-Corner Index

[04/04 17:11:08 654s]

RC-Corner Temperature : 125 Celsius

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s]

[04/04 17:11:08 654s] Analysis View:
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:11:08 654s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 17:11:08 654s]

RC-Corner Index

[04/04 17:11:08 654s]

RC-Corner Temperature : 125 Celsius

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s]

[04/04 17:11:08 654s] Analysis View:
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:11:08 654s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 17:11:08 654s]

RC-Corner Index

[04/04 17:11:08 654s]

RC-Corner Temperature : 125 Celsius

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s]

[04/04 17:11:08 654s] Analysis View:
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:11:08 654s]

RC-Corner Name

: Arise_rc_corner_cmax

[04/04 17:11:08 654s]

RC-Corner Index

[04/04 17:11:08 654s]

RC-Corner Temperature : 125 Celsius

[04/04 17:11:08 654s]

RC-Corner Cap Table : '../../DATA/captable_cmax'

[04/04 17:11:08 654s]

RC-Corner PreRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Res Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute Cap Factor

[04/04 17:11:08 654s]

RC-Corner PostRoute XCap Factor

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PreRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Cap Factor : 1
from postRoute_cap (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner PostRoute Clock Res Factor : 1
from postRoute_res (effortLevel low)]

[Derived

[04/04 17:11:08 654s]

RC-Corner Technology file: '../../DATA/qrcTechFile'

[04/04 17:11:08 654s] Technology file '../../DATA/qrcTechFile' associated with

first view 'Arise_analysis_view_test_max_cmax_T150V08' specified to command
'set_analysis_view' will be used as the primary corner for the multi-corner
extraction. TQRC/IQRC extraction leverages a single primary corner extraction,
then derives the other corners based on their technology files and operating
conditions from the primary corner.
[04/04 17:11:08 654s] *Info: initialize multi-corner CTS.
[04/04 17:11:08 654s] Reading Arise_max_library_T140V102_set timing library
'/Projects/Training/user5/work/suraj/LIB/slow_T140_102V.lib' ...
[04/04 17:11:09 655s] Read 477 cells in library 'gpdk045bc'
[04/04 17:11:09 655s] Reading Arise_max_library_T125V108_set timing library
'/Projects/Training/user5/work/suraj/LIB/slow_T125_108V.lib' ...
[04/04 17:11:10 656s] Read 477 cells in library 'gpdk045bc'
[04/04 17:11:10 656s] Reading Arise_nom_library_T25V12_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T25_12V.lib' ...
[04/04 17:11:10 657s] Read 477 cells in library 'typical'
[04/04 17:11:10 657s] Reading Arise_nom_library_T50V13_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T50_13V.lib' ...
[04/04 17:11:11 657s] Read 477 cells in library 'typical'
[04/04 17:11:11 657s] Reading Arise_nom_library_T15V11_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T15_11V.lib' ...
[04/04 17:11:12 658s] Read 477 cells in library 'typical'

[04/04 17:11:12 658s] Reading Arise_min_library_Tm20V15_set timing library

'/Projects/Training/user5/work/suraj/LIB/fast_Tm20_15V.lib' ...
[04/04 17:11:13 659s] Read 477 cells in library 'gpdk045wc'
[04/04 17:11:13 659s] Reading Arise_min_library_Tm40V18_set timing library
'/Projects/Training/user5/work/suraj/LIB/fast_Tm40_18V.lib' ...
[04/04 17:11:13 659s] Read 477 cells in library 'gpdk045wc'
[04/04 17:11:13 660s] CTE reading timing constraint file '../../SDC/test.sdc' ...
[04/04 17:11:14 660s] Current (total cpu=0:10:58, real=1:13:02, peak
res=1143.3M, current mem=1118.3M)
[04/04 17:11:14 660s] **WARN: (TCLNL-330):
set_input_delay on clock root
'clk' is not supported. You should use the -source option to set_clock_latency to
provide this offset. You can also use the global
timing_allow_input_delay_on_clock_source to allow set_input_delay assertion to
have an effect on clock source paths beginning at this clock root. (File
../../SDC/test.sdc, Line 188).
[04/04 17:11:14 660s]
[04/04 17:11:14 660s] Number of path exceptions in the constraint file = 47
[04/04 17:11:14 660s] Number of paths exceptions after getting compressed =
5
[04/04 17:11:14 660s] INFO (CTE): read_dc_script finished with 1 WARNING.
[04/04 17:11:14 660s] Ending "Constraint file reading stats" (total
cpu=0:00:00.1, real=0:00:00.0, peak res=757.8M, current mem=1128.3M)
[04/04 17:11:14 660s] Current (total cpu=0:10:58, real=1:13:02, peak
res=1143.3M, current mem=1128.3M)
[04/04 17:11:14 660s] CTE reading timing constraint file '../../SDC/func.sdc' ...
[04/04 17:11:14 660s] Current (total cpu=0:10:58, real=1:13:02, peak
res=1143.3M, current mem=1128.3M)
[04/04 17:11:14 660s] **WARN: (TCLNL-330):
set_input_delay on clock root
'clk' is not supported. You should use the -source option to set_clock_latency to
provide this offset. You can also use the global
timing_allow_input_delay_on_clock_source to allow set_input_delay assertion to
have an effect on clock source paths beginning at this clock root. (File
../../SDC/func.sdc, Line 188).
[04/04 17:11:14 660s]
[04/04 17:11:14 660s] Number of path exceptions in the constraint file = 47

[04/04 17:11:14 660s] Number of paths exceptions after getting compressed =

5
[04/04 17:11:14 660s] INFO (CTE): read_dc_script finished with 1 WARNING.
[04/04 17:11:14 660s] Ending "Constraint file reading stats" (total
cpu=0:00:00.1, real=0:00:00.0, peak res=758.0M, current mem=1128.3M)
[04/04 17:11:14 660s] Current (total cpu=0:10:58, real=1:13:02, peak
res=1143.3M, current mem=1128.3M)
[04/04 17:11:14 660s] Total number of combinational cells: 317
[04/04 17:11:14 660s] Total number of sequential cells: 150
[04/04 17:11:14 660s] Total number of tristate cells: 10
[04/04 17:11:14 660s] Total number of level shifter cells: 0
[04/04 17:11:14 660s] Total number of power gating cells: 0
[04/04 17:11:14 660s] Total number of isolation cells: 0
[04/04 17:11:14 660s] Total number of power switch cells: 0
[04/04 17:11:14 660s] Total number of pulse generator cells: 0
[04/04 17:11:14 660s] Total number of always on buffers: 0
[04/04 17:11:14 660s] Total number of retention cells: 0
[04/04 17:11:14 660s] List of usable buffers: BUFX2 BUFX12 BUFX16 BUFX20
CLKBUFX2 BUFX3 BUFX4 CLKBUFX12 CLKBUFX16 CLKBUFX20 CLKBUFX4
CLKBUFX6 CLKBUFX8 BUFX8 CLKBUFX3 BUFX6
[04/04 17:11:14 660s] Total number of usable buffers: 16
[04/04 17:11:14 660s] List of unusable buffers:
[04/04 17:11:14 660s] Total number of unusable buffers: 0
[04/04 17:11:14 660s] List of usable inverters: CLKINVX1 CLKINVX2 CLKINVX12
CLKINVX16 CLKINVX20 INVX1 CLKINVX3 CLKINVX4 CLKINVX6 INVX12 INVX2
INVX3 CLKINVX8 INVX20 INVX4 INVX6 INVX16 INVXL INVX8
[04/04 17:11:14 660s] Total number of usable inverters: 19
[04/04 17:11:14 660s] List of unusable inverters:
[04/04 17:11:14 660s] Total number of unusable inverters: 0
[04/04 17:11:14 660s] List of identified usable delay cells: DLY1X4 DLY2X4
DLY3X4 DLY1X1 DLY4X1 DLY2X1 DLY3X1 DLY4X4

[04/04 17:11:14 660s] Total number of identified usable delay cells: 8

[04/04 17:11:14 660s] List of identified unusable delay cells:
[04/04 17:11:14 660s] Total number of identified unusable delay cells: 0
[04/04 17:11:14 660s]
[04/04 17:11:14 660s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:11:14 660s] Severity ID

Count Summary

[04/04 17:11:14 660s] WARNING ENCLF-200

has no ANTENNAGAT...

132 Pin '%s' in macro '%s'

[04/04 17:11:14 660s] WARNING ENCLF-201

has no ANTENNADIF...

128 Pin '%s' in macro '%s'

[04/04 17:11:14 660s] WARNING ENCEXT-6202

technology file, capa...

1 In addition to the

[04/04 17:11:14 660s] WARNING ENCEXT-2710

layer M%d is ignored...

2 Basic Cap table for

[04/04 17:11:14 660s] WARNING ENCEXT-2760

the cap table is ...

4 Layer M%d specified in

[04/04 17:11:14 660s] WARNING ENCEXT-2776

between layers %s and...

16 The via resistance

[04/04 17:11:14 660s] *** Message Summary: 283 warning(s), 0 error(s)

[04/04 17:11:14 660s]
[04/04 17:11:16 660s] <CMD> fit
[04/04 17:11:43 660s] <CMD> relativePlace test_MPY_32_INST CORE
-orientation R0 -relation B -alignedBy R -xSpace 0.0000 -ySpace 0.0000
[04/04 17:11:43 660s] <CMD> relativePlace ashok_MPY_32_INST CORE
-orientation R0 -relation B -alignedBy L -xSpace 0.0000 -ySpace 0.0000
[04/04 17:11:43 660s] <CMD> relativePlace gopi_MPY_32 CORE -orientation
R180 -relation T -alignedBy R -xSpace 0.0000 -ySpace 0.0000
[04/04 17:11:43 660s] <CMD> relativePlace suraj_MPY_32_INST CORE
-orientation MX -relation T -alignedBy L -xSpace 0.0000 -ySpace 0.0000
[04/04 17:11:59 661s] <CMD> loadIoFile io/tdsp_core.save.io
[04/04 17:11:59 661s] Reading IO assignment file "io/tdsp_core.save.io" ...
[04/04 17:12:00 661s] <CMD> fit

[04/04 17:12:03 662s] <CMD> getPinAssignMode -pinEditInBatch -quiet

[04/04 17:12:08 662s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:12:11 662s] <CMD> uiSetTool select
[04/04 17:12:13 662s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:12:18 663s] <CMD> uiSetTool select
[04/04 17:12:22 663s] <CMD> getIoFlowFlag
[04/04 17:12:36 663s] <CMD> setIoFlowFlag 0
[04/04 17:12:36 663s] <CMD> floorPlan -site CoreSite -s 200 197 0.0 0.0 0.0
0.0
[04/04 17:12:36 663s] **WARN: (ENCFP-3300):
greater than 1.

FPlan core utilization is

[04/04 17:12:36 663s] Horizontal Layer M1 offset = 95 (derived)

[04/04 17:12:36 663s] Vertical Layer M2 offset = 100 (derived)
[04/04 17:12:36 663s] Generated pitch 0.2 in Metal9 is different from 0.33
defined in technology file in unpreferred direction.
[04/04 17:12:36 663s] Generated pitch 0.38 in Metal9 is different from 0.33
defined in technology file in preferred direction.
[04/04 17:12:36 663s] Generated pitch 0.285 in Metal8 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:12:36 663s] Generated pitch 0.285 in Metal7 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:12:36 663s] Generated pitch 0.19 in Metal6 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:12:36 663s] Generated pitch 0.19 in Metal5 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:12:36 663s] Generated pitch 0.19 in Metal4 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:12:36 663s] Generated pitch 0.19 in Metal3 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:12:36 663s] Generated pitch 0.19 in Metal2 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:12:36 663s] Generated pitch 0.2 in Metal1 is different from 0.19
defined in technology file in unpreferred direction.

[04/04 17:12:36 663s] **WARN: (ENCFP-325):

Floorplan of the design is
resized. All current floorplan objects are automatically derived based on specified
new floorplan. This may change blocks, fixed standard cells, existing routes and
blockages.
[04/04 17:12:36 663s] <CMD> uiSetTool select
[04/04 17:12:36 663s] <CMD> getIoFlowFlag
[04/04 17:12:36 663s] <CMD> fit
[04/04 17:12:47 663s] <CMD> getIoFlowFlag
[04/04 17:12:58 663s] <CMD> setIoFlowFlag 0
[04/04 17:12:58 663s] <CMD> floorPlan -site CoreSite -s 210 207 0.0 0.0 0.0
0.0
[04/04 17:12:58 663s] **WARN: (ENCFP-3300):
greater than 1.

FPlan core utilization is

[04/04 17:12:58 663s] Horizontal Layer M1 offset = 95 (derived)

[04/04 17:12:58 663s] Vertical Layer M2 offset = 100 (derived)
[04/04 17:12:58 663s] Generated pitch 0.2 in Metal9 is different from 0.33
defined in technology file in unpreferred direction.
[04/04 17:12:58 663s] Generated pitch 0.38 in Metal9 is different from 0.33
defined in technology file in preferred direction.
[04/04 17:12:58 663s] Generated pitch 0.285 in Metal8 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:12:58 663s] Generated pitch 0.285 in Metal7 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:12:58 663s] Generated pitch 0.19 in Metal6 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:12:58 663s] Generated pitch 0.19 in Metal5 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:12:58 663s] Generated pitch 0.19 in Metal4 is different from 0.2
defined in technology file in unpreferred direction.
[04/04 17:12:58 663s] Generated pitch 0.19 in Metal3 is different from 0.2
defined in technology file in preferred direction.
[04/04 17:12:58 663s] Generated pitch 0.19 in Metal2 is different from 0.2
defined in technology file in unpreferred direction.

[04/04 17:12:58 663s] Generated pitch 0.2 in Metal1 is different from 0.19
defined in technology file in unpreferred direction.
[04/04 17:12:58 663s] **WARN: (ENCFP-325):
Floorplan of the design is
resized. All current floorplan objects are automatically derived based on specified
new floorplan. This may change blocks, fixed standard cells, existing routes and
blockages.
[04/04 17:12:58 663s] <CMD> uiSetTool select
[04/04 17:12:58 663s] <CMD> getIoFlowFlag
[04/04 17:12:58 663s] <CMD> fit
[04/04 17:13:09 665s] <CMD> loadIoFile io/tdsp_core.save.io
[04/04 17:13:09 665s] Reading IO assignment file "io/tdsp_core.save.io" ...
[04/04 17:13:10 665s] <CMD> fit
[04/04 17:13:16 665s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:13:19 665s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:13:21 666s] <CMD> uiSetTool select
[04/04 17:13:24 666s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:13:27 666s] <CMD> uiSetTool select
[04/04 17:13:30 666s] **ERROR: (ENCSYT-16250): Choose the pin list first.
[04/04 17:13:32 667s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:13:32 667s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 209.769 113.39 -end 209.769 91.413 -pin {}
[04/04 17:13:32 667s] **ERROR: (ENCPTN-963): Either specified pin name for
the selected partition does not exist or has status 'cover'. Specify the pin or the
list of pins correctly and run the command again.
[04/04 17:13:32 667s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:13:35 668s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:13:39 668s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:13:42 668s] <CMD> uiSetTool select
[04/04 17:13:44 669s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord

[04/04 17:13:47 669s] <CMD> uiSetTool select

[04/04 17:13:50 669s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:13:50 669s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Right -layer 3 -spreadType range
-start 209.167 112.487 -end 209.468 91.112 -pin {{address[0]} {address[1]}
{address[2]} {address[3]} {address[4]} {address[5]} {address[6]}
{address[7]} {p_address[0]} {p_address[1]} {p_address[2]} {p_address[3]}
{p_address[4]} {p_address[5]} {p_address[6]} {p_address[7]} {p_address[8]}
{port_address[0]} {port_address[1]} {port_address[2]} {rom_data_in[0]}
{rom_data_in[1]} {rom_data_in[2]} {rom_data_in[3]} {rom_data_in[4]}
{rom_data_in[5]} {rom_data_in[6]} {rom_data_in[7]} {rom_data_in[8]}
{rom_data_in[9]} {rom_data_in[10]} {rom_data_in[11]} {rom_data_in[12]}
{rom_data_in[13]} {rom_data_in[14]} {rom_data_in[15]} {t_data_in[0]}
{t_data_in[1]} {t_data_in[2]} {t_data_in[3]} {t_data_in[4]} {t_data_in[5]}
{t_data_in[6]} {t_data_in[7]} {t_data_in[8]} {t_data_in[9]} {t_data_in[10]}
{t_data_in[11]} {t_data_in[12]} {t_data_in[13]} {t_data_in[14]}
{t_data_in[15]}}
[04/04 17:13:50 669s] Successfully spread [52] pins.
[04/04 17:13:50 669s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:13:50 669s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:14:02 670s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:14:08 670s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:14:11 670s] <CMD> uiSetTool select
[04/04 17:14:13 671s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:14:16 671s] <CMD> uiSetTool select
[04/04 17:14:20 671s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:14:20 671s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 92.958 206.117 -end 103.194 206.117 -pin {{port_pad_data_out[0]}
{port_pad_data_out[1]} {port_pad_data_out[2]} {port_pad_data_out[3]}
{port_pad_data_out[4]} {port_pad_data_out[5]} {port_pad_data_out[6]}
{port_pad_data_out[7]} {port_pad_data_out[8]} {port_pad_data_out[9]}
{port_pad_data_out[10]} {port_pad_data_out[11]} {port_pad_data_out[12]}
{port_pad_data_out[13]} {port_pad_data_out[14]} {port_pad_data_out[15]}
{rom_data_out[0]} {rom_data_out[1]} {rom_data_out[2]} {rom_data_out[3]}
{rom_data_out[4]} {rom_data_out[5]} {rom_data_out[6]} {rom_data_out[7]}
{rom_data_out[8]} {rom_data_out[9]} {rom_data_out[10]} {rom_data_out[11]}

{rom_data_out[12]} {rom_data_out[13]} {rom_data_out[14]}

{rom_data_out[15]}}
[04/04 17:14:20 671s] Successfully spread [32] pins.
[04/04 17:14:20 671s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:14:20 671s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:14:26 672s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:14:35 673s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:14:37 673s] <CMD> uiSetTool select
[04/04 17:14:41 673s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:14:44 673s] <CMD> uiSetTool select
[04/04 17:14:52 674s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:14:52 674s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 105.602 206.418 -end 117.042 206.719 -pin {as bio bus_grant bus_request
clk DFT_sen int p_as p_read p_write p_write_h port_as {port_pad_data_in[0]}
{port_pad_data_in[1]} {port_pad_data_in[2]} {port_pad_data_in[3]}
{port_pad_data_in[4]} {port_pad_data_in[5]} {port_pad_data_in[6]}
{port_pad_data_in[7]} {port_pad_data_in[8]} {port_pad_data_in[9]}
{port_pad_data_in[10]} {port_pad_data_in[11]} {port_pad_data_in[12]}
{port_pad_data_in[13]} {port_pad_data_in[14]} {port_pad_data_in[15]}
port_read port_write port_write_h RC_CG_TEST_PORT read reset SRPG_PG_in
SRPG_PG_in_1 {t_data_out[0]} {t_data_out[1]} {t_data_out[2]} {t_data_out[3]}
{t_data_out[4]} {t_data_out[5]} {t_data_out[6]} {t_data_out[7]}
{t_data_out[8]} {t_data_out[9]} {t_data_out[10]} {t_data_out[11]}
{t_data_out[12]} {t_data_out[13]} {t_data_out[14]} {t_data_out[15]} {t_sdi[0]}
{t_sdi[1]} {t_sdi[2]} {t_sdo[0]} {t_sdo[1]} {t_sdo[2]} write write_h}
[04/04 17:14:52 674s] **ERROR: (ENCPTN-970): Available [57] free track for
spreading the selected [60] pins is not sufficient to spread all the pins. Ensure
that the free space on the specified layer and side is enough to spread the pins
uniformly.
[04/04 17:14:52 674s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:14:52 674s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:15:18 675s] <CMD> getPinAssignMode -pinEditInBatch -quiet

[04/04 17:15:36 676s] <CMD> uiSetTool getLocation

Rda_PE::Attr:getStartCoord
[04/04 17:15:39 676s] <CMD> uiSetTool select
[04/04 17:15:41 676s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:15:45 676s] <CMD> uiSetTool select
[04/04 17:15:48 677s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:15:48 677s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 105.301 206.418 -end 117.344 206.418 -pin {write_h as bio bus_grant
bus_request clk DFT_sen int p_as p_read p_write p_write_h port_as port_read
port_write port_write_h RC_CG_TEST_PORT read reset SRPG_PG_in SRPG_PG_in_1
{t_sdi[0]} {t_sdi[1]} {t_sdi[2]} {t_sdo[0]} {t_sdo[1]} {t_sdo[2]} write}
[04/04 17:15:48 677s] Successfully spread [28] pins.
[04/04 17:15:48 677s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:15:48 677s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:15:53 677s] <CMD> zoomBox 204.651 121.820 219.403 102.853
[04/04 17:15:55 678s] <CMD> fit
[04/04 17:15:57 678s] <CMD> zoomBox 101.688 214.245 117.645 198.289
[04/04 17:15:59 678s] <CMD> fit
[04/04 17:16:03 679s] <CMD> zoomBox 60.443 9.223 86.936 -9.142
[04/04 17:16:06 679s] <CMD> panPage 1 0
[04/04 17:16:06 679s] <CMD> panPage 1 0
[04/04 17:16:08 679s] <CMD> panPage -1 0
[04/04 17:16:08 679s] <CMD> panPage -1 0
[04/04 17:16:10 679s] <CMD> fit
[04/04 17:16:15 679s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:16:24 680s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:16:26 680s] <CMD> uiSetTool select
[04/04 17:16:29 680s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord

[04/04 17:16:31 681s] <CMD> uiSetTool select

[04/04 17:16:34 681s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:16:34 681s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 67.066 207.02 -end 83.926 207.02 -pin {{port_pad_data_in[0]}
{port_pad_data_in[1]} {port_pad_data_in[2]} {port_pad_data_in[3]}
{port_pad_data_in[4]} {port_pad_data_in[5]} {port_pad_data_in[6]}
{port_pad_data_in[7]} {port_pad_data_in[8]} {port_pad_data_in[9]}
{port_pad_data_in[10]} {port_pad_data_in[11]} {port_pad_data_in[12]}
{port_pad_data_in[13]} {port_pad_data_in[14]} {port_pad_data_in[15]}}
[04/04 17:16:34 681s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:16:34 681s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:16:54 684s] <CMD> loadIoFile io/tdsp_core.save.io
[04/04 17:16:54 684s] Reading IO assignment file "io/tdsp_core.save.io" ...
[04/04 17:16:55 684s] <CMD> fit
[04/04 17:17:04 684s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:17:30 685s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:17:34 685s] <CMD> uiSetTool select
[04/04 17:17:37 686s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:17:40 686s] <CMD> uiSetTool select
[04/04 17:17:45 686s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:17:45 686s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 103.796 207.02 -end 117.042 206.719 -pin {as bio bus_grant bus_request
clk DFT_sen int p_as p_read p_write p_write_h port_as {port_pad_data_in[0]}
{port_pad_data_in[1]} {port_pad_data_in[2]} {port_pad_data_in[3]}
{port_pad_data_in[4]} {port_pad_data_in[5]} {port_pad_data_in[6]}
{port_pad_data_in[7]} {port_pad_data_in[8]} {port_pad_data_in[9]}
{port_pad_data_in[10]} {port_pad_data_in[11]} {port_pad_data_in[12]}
{port_pad_data_in[13]} {port_pad_data_in[14]} {port_pad_data_in[15]}
port_read port_write port_write_h RC_CG_TEST_PORT read reset SRPG_PG_in
SRPG_PG_in_1 {t_sdi[0]} {t_sdi[1]} {t_sdi[2]} {t_sdo[0]} {t_sdo[1]} {t_sdo[2]}
write write_h}
[04/04 17:17:45 686s] Successfully spread [44] pins.

[04/04 17:17:45 686s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:17:45 686s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:17:53 687s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:18:22 688s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:18:26 688s] <CMD> uiSetTool select
[04/04 17:18:29 688s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:18:32 689s] <CMD> uiSetTool select
[04/04 17:18:34 689s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:18:34 689s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Top -layer 2 -spreadType range
-start 92.657 206.719 -end 101.387 207.02 -pin {{port_pad_data_out[0]}
{port_pad_data_out[1]} {port_pad_data_out[2]} {port_pad_data_out[3]}
{port_pad_data_out[4]} {port_pad_data_out[5]} {port_pad_data_out[6]}
{port_pad_data_out[7]} {port_pad_data_out[8]} {port_pad_data_out[9]}
{port_pad_data_out[10]} {port_pad_data_out[11]} {port_pad_data_out[12]}
{port_pad_data_out[13]} {port_pad_data_out[14]} {port_pad_data_out[15]}
{rom_data_out[0]} {rom_data_out[1]} {rom_data_out[2]} {rom_data_out[3]}
{rom_data_out[4]} {rom_data_out[5]} {rom_data_out[6]} {rom_data_out[7]}
{rom_data_out[8]} {rom_data_out[9]} {rom_data_out[10]} {rom_data_out[11]}
{rom_data_out[12]} {rom_data_out[13]} {rom_data_out[14]}
{rom_data_out[15]}}
[04/04 17:18:34 689s] Successfully spread [32] pins.
[04/04 17:18:34 689s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:18:34 689s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:18:42 690s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:18:49 691s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:18:52 691s] <CMD> zoomBox 205.855 117.304 218.801 104.358
[04/04 17:18:54 691s] <CMD> uiSetTool select
[04/04 17:18:56 691s] <CMD> fit
[04/04 17:19:00 692s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:19:02 692s] <CMD> zoomBox 205.253 104.358 221.812 76.661

[04/04 17:19:04 692s] <CMD> uiSetTool select

[04/04 17:19:07 692s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:19:07 692s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Right -layer 3 -spreadType range
-start 209.964 115.181 -end 210.016 98.093 -pin {{address[0]} {address[1]}
{address[2]} {address[3]} {address[4]} {address[5]} {address[6]}
{address[7]} {p_address[0]} {p_address[1]} {p_address[2]} {p_address[3]}
{p_address[4]} {p_address[5]} {p_address[6]} {p_address[7]} {p_address[8]}
{port_address[0]} {port_address[1]} {port_address[2]} {rom_data_in[0]}
{rom_data_in[1]} {rom_data_in[2]} {rom_data_in[3]} {rom_data_in[4]}
{rom_data_in[5]} {rom_data_in[6]} {rom_data_in[7]} {rom_data_in[8]}
{rom_data_in[9]} {rom_data_in[10]} {rom_data_in[11]} {rom_data_in[12]}
{rom_data_in[13]} {rom_data_in[14]} {rom_data_in[15]} {t_data_in[0]}
{t_data_in[1]} {t_data_in[2]} {t_data_in[3]} {t_data_in[4]} {t_data_in[5]}
{t_data_in[6]} {t_data_in[7]} {t_data_in[8]} {t_data_in[9]} {t_data_in[10]}
{t_data_in[11]} {t_data_in[12]} {t_data_in[13]} {t_data_in[14]}
{t_data_in[15]}}
[04/04 17:19:07 692s] Successfully spread [52] pins.
[04/04 17:19:07 692s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:19:07 693s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:19:08 693s] <CMD> fit
[04/04 17:19:13 693s] <CMD> getPinAssignMode -pinEditInBatch -quiet
[04/04 17:19:17 694s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:19:23 694s] <CMD> uiSetTool getLocation
Rda_PE::Attr:getStartCoord
[04/04 17:19:26 694s] <CMD> zoomBox 204.651 101.950 221.812 83.585
[04/04 17:19:27 694s] <CMD> uiSetTool select
[04/04 17:19:30 694s] <CMD> uiSetTool getLocation Rda_PE::Attr:getEndCoord
[04/04 17:19:32 694s] <CMD> uiSetTool select
[04/04 17:19:36 695s] <CMD> setPinAssignMode -pinEditInBatch true
[04/04 17:19:36 695s] <CMD> editPin -pinWidth 0.07 -pinDepth 0.29 -fixedPin 1
-fixOverlap 1 -spreadDirection clockwise -side Right -layer 3 -spreadType range
-start 209.928 97.48 -end 209.976 89.852 -pin {{t_data_out[0]} {t_data_out[1]}
{t_data_out[2]} {t_data_out[3]} {t_data_out[4]} {t_data_out[5]}
{t_data_out[6]} {t_data_out[7]} {t_data_out[8]} {t_data_out[9]}

{t_data_out[10]} {t_data_out[11]} {t_data_out[12]} {t_data_out[13]}

{t_data_out[14]} {t_data_out[15]}}
[04/04 17:19:36 695s] Successfully spread [16] pins.
[04/04 17:19:36 695s] editPin : finished (cpu = 0:00:00.0 real = 0:00:00.0, mem
= 1128.3M).
[04/04 17:19:36 695s] <CMD> setPinAssignMode -pinEditInBatch false
[04/04 17:19:38 695s] <CMD> fit
[04/04 17:19:41 695s] <CMD> zoomBox 205.253 103.154 216.995 81.478
[04/04 17:19:42 696s] <CMD> zoomBox 208.428 97.018 211.754 91.972
[04/04 17:19:43 696s] <CMD> zoomBox 209.804 94.962 210.265 94.482
[04/04 17:19:45 696s] <CMD> setLayerPreference allM0 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM1Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM1 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM2Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM2 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM3Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM3 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM4Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM4 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM5Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM5 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM6Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM6 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM7Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM7 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM8Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM8 -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM9Cont -isVisible 1
[04/04 17:19:45 696s] <CMD> setLayerPreference allM9 -isVisible 1

[04/04 17:19:47 696s] <CMD> fit

[04/04 17:19:50 696s] <CMD> fit
[04/04 17:19:59 697s] <CMD> uiSetTool ruler
[04/04 17:20:30 698s] <CMD> zoomBox 108.914 69.134 132.397 43.243
[04/04 17:21:14 699s] <CMD> clearGlobalNets
[04/04 17:21:14 699s] <CMD> globalNetConnect vdd -type pgpin -pin V_Sub
-inst *
[04/04 17:21:14 699s] <CMD> globalNetConnect gnd -type pgpin -pin gnd -inst
*
[04/04 17:21:14 699s] <CMD> globalNetConnect vdd -type pgpin -pin vdd -inst
*
[04/04 17:21:14 699s] <CMD> globalNetConnect vdd -type pgpin -pin VDD -inst
*
[04/04 17:21:14 699s] <CMD> globalNetConnect gnd -type pgpin -pin VSS -inst
*
[04/04 17:21:15 699s] Warning: term ovm of inst gopi_MPY_32 is not connect to
global special net.
[04/04 17:21:15 699s] Warning: term ovm of inst suraj_MPY_32_INST is not
connect to global special net.
[04/04 17:21:15 699s] Warning: term ovm of inst ashok_MPY_32_INST is not
connect to global special net.
[04/04 17:21:15 699s] Warning: term ovm of inst test_MPY_32_INST is not
connect to global special net.
[04/04 17:21:15 699s] Warning: pg term V_Core of inst gopi_MPY_32 is not
connect to global special net.
[04/04 17:21:15 699s] Warning: pg term V_Core of inst suraj_MPY_32_INST is
not connect to global special net.
[04/04 17:21:15 699s] Warning: pg term V_Core of inst ashok_MPY_32_INST is
not connect to global special net.
[04/04 17:21:17 699s] <CMD> fit
[04/04 17:21:36 700s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal9 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal7 -number_of_sets 2 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal9
-spacing 0.45 -xleft_offset 96 -xright_offset 96 -merge_stripes_value 0.165 -layer

Metal8 -block_ring_bottom_layer_limit Metal7 -width 2.1 -nets {gnd vdd}

-stacked_via_bottom_layer Metal1
[04/04 17:21:36 700s]
[04/04 17:21:36 700s] Starting stripe generation ...
[04/04 17:21:36 700s] Non-Default setAddStripeOption Settings :
[04/04 17:21:36 700s] NONE
[04/04 17:21:36 700s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 17:21:36 700s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 17:21:36 700s] Stripe generation is complete; vias are now being
generated.
[04/04 17:21:36 700s] The power planner created 4 wires.
[04/04 17:21:36 700s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1128.3M) ***
[04/04 17:21:55 700s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal8 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal6 -number_of_sets 2 -ybottom_offset 96
-skip_via_on_pin Standardcell -stacked_via_top_layer Metal9
-padcore_ring_top_layer_limit Metal8 -start_from top -spacing 0.45
-merge_stripes_value 0.165 -direction horizontal -layer Metal7
-block_ring_bottom_layer_limit Metal6 -ytop_offset 96 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1
[04/04 17:21:55 700s]
[04/04 17:21:55 700s] Starting stripe generation ...
[04/04 17:21:55 700s] Non-Default setAddStripeOption Settings :
[04/04 17:21:55 700s] NONE
[04/04 17:21:55 700s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 17:21:55 700s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.

[04/04 17:21:55 700s] Stripe generation is complete; vias are now being
generated.
[04/04 17:21:55 700s] The power planner created 4 wires.
[04/04 17:21:55 700s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1128.3M) ***
[04/04 17:22:18 700s] <CMD> sroute -connect { blockPin } -layerChangeRange
{ Metal1 Metal9 } -blockPinTarget { stripe } -allowJogging 0
-crossoverViaLayerRange { Metal1 Metal9 } -allowLayerChange 0 -nets { vdd
gnd } -blockPin useLef -targetViaLayerRange { Metal1 Metal9 }
[04/04 17:22:18 700s] *** Begin SPECIAL ROUTE on Mon Apr 4 17:22:18 2016
***
[04/04 17:22:18 700s] SPECIAL ROUTE ran on directory:
/Projects/Training/user5/work/suraj/encounter/rundir
[04/04 17:22:18 700s] SPECIAL ROUTE ran on machine: SRV01 (Linux 2.6.18308.el5 x86_64 2.66Ghz)
[04/04 17:22:18 700s]
[04/04 17:22:18 700s] Begin option processing ...
[04/04 17:22:18 700s] srouteConnectPowerBump set to false
[04/04 17:22:18 700s] routeSelectNet set to "vdd gnd"
[04/04 17:22:18 700s] routeSpecial set to true
[04/04 17:22:18 700s] srouteBlockPin set to "useLef"
[04/04 17:22:18 700s] srouteBlockPinTarget set to "stripe"
[04/04 17:22:18 700s] srouteBottomLayerLimit set to 1
[04/04 17:22:18 700s] srouteBottomTargetLayerLimit set to 1
[04/04 17:22:18 700s] srouteConnectConverterPin set to false
[04/04 17:22:18 700s] srouteConnectCorePin set to false
[04/04 17:22:18 700s] srouteConnectPadPin set to false
[04/04 17:22:18 700s] srouteConnectStripe set to false
[04/04 17:22:18 700s] srouteCrossoverViaBottomLayer set to 1
[04/04 17:22:18 700s] srouteCrossoverViaTopLayer set to 9
[04/04 17:22:18 700s] srouteFollowCorePinEnd set to 3

[04/04 17:22:18 700s] srouteFollowPadPin set to false

[04/04 17:22:18 700s] srouteNoLayerChangeRoute set to true
[04/04 17:22:18 700s] sroutePadPinAllPorts set to true
[04/04 17:22:18 700s] sroutePreserveExistingRoutes set to true
[04/04 17:22:18 700s] srouteRoutePowerBarPortOnBothDir set to true
[04/04 17:22:18 700s] srouteStraightConnections set to "straightWithDrcClean"
[04/04 17:22:18 700s] srouteTopLayerLimit set to 9
[04/04 17:22:18 700s] srouteTopTargetLayerLimit set to 9
[04/04 17:22:18 700s] End option processing: cpu: 0:00:00, real: 0:00:00, peak:
1889.00 megs.
[04/04 17:22:18 700s]
[04/04 17:22:18 700s] Reading DB technology information...
[04/04 17:22:18 700s] Finished reading DB technology information.
[04/04 17:22:18 700s] Reading floorplan and netlist information...
[04/04 17:22:18 700s] Finished reading floorplan and netlist information.
[04/04 17:22:18 700s] Read in 19 layers, 9 routing layers, 1 overlap layer
[04/04 17:22:18 700s] Read in 2 nondefault rules, 0 used
[04/04 17:22:18 700s] Read in 68 macros, 68 used
[04/04 17:22:18 700s] Read in 68 components
[04/04 17:22:18 700s] 64 core components: 64 unplaced, 0 placed, 0 fixed
[04/04 17:22:18 700s] 4 block/ring components: 0 unplaced, 0 placed, 4 fixed
[04/04 17:22:18 700s] Read in 160 physical pins
[04/04 17:22:18 700s] 160 physical pins: 0 unplaced, 0 placed, 160 fixed
[04/04 17:22:18 700s] Read in 144 nets
[04/04 17:22:18 700s] Read in 2 special nets, 2 routed
[04/04 17:22:18 700s] Read in 299 terminals
[04/04 17:22:18 700s] 2 nets selected.
[04/04 17:22:18 700s]
[04/04 17:22:18 700s] Begin power routing ...

[04/04 17:22:19 701s] Number of Block ports routed: 89 open: 259

[04/04 17:22:19 701s] Number of Power Bump ports routed: 0
[04/04 17:22:19 701s] End power routing: cpu: 0:00:00, real: 0:00:01, peak:
1892.00 megs.
[04/04 17:22:19 701s]
[04/04 17:22:19 701s]
[04/04 17:22:19 701s]
[04/04 17:22:19 701s] Begin updating DB with routing results ...
[04/04 17:22:19 701s] Updating DB with 149 via definition ...
[04/04 17:22:19 701s] Updating DB with 160 io pins ...Extracting standard cell
pins and blockage ......
[04/04 17:22:19 701s] Pin and blockage extraction finished
[04/04 17:22:19 701s]
[04/04 17:22:19 701s]
sroute post-processing starts at Mon Apr 4 17:22:19 2016
The viaGen is rebuilding shadow vias for net gnd.
[04/04 17:22:19 701s] sroute post-processing ends at Mon Apr 4 17:22:19
2016

sroute post-processing starts at Mon Apr 4 17:22:19 2016

The viaGen is rebuilding shadow vias for net vdd.
[04/04 17:22:19 701s] sroute post-processing ends at Mon Apr 4 17:22:19
2016
sroute: Total CPU time used = 0:0:0
[04/04 17:22:19 701s] sroute: Total Real time used = 0:0:1
[04/04 17:22:19 701s] sroute: Total Memory used = 0.00 megs
[04/04 17:22:19 701s] sroute: Total Peak Memory used = 1128.29 megs
[04/04 17:22:22 701s] <CMD> setLayerPreference violation -isVisible 1
[04/04 17:22:22 701s] <CMD> violationBrowser -all -no_display_false
[04/04 17:22:24 701s] <CMD> clearDrc

[04/04 17:22:29 702s] <CMD> uiSetTool select

[04/04 17:22:30 702s] <CMD> selectWire 23.4000 108.8100 25.5000 115.7250
4 gnd
[04/04 17:22:31 702s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:32 702s] <CMD> selectWire 23.4000 91.1850 25.5000 100.6500
4 gnd
[04/04 17:22:32 702s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:34 702s] <CMD> selectWire 60.3300 58.3200 62.4300 100.6500
6 gnd
[04/04 17:22:34 702s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:35 703s] <CMD> selectWire 44.4000 90.1700 46.5000 100.6500
6 gnd
[04/04 17:22:35 703s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:36 703s] <CMD> selectWire 44.4000 108.8100 46.5000 115.7250
6 gnd
[04/04 17:22:37 703s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:40 703s] <CMD> selectWire 60.3300 108.8100 62.4300 148.5900
6 gnd
[04/04 17:22:40 703s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:41 703s] <CMD> selectWire 147.5700 108.8100 149.6700
148.5900 6 gnd
[04/04 17:22:41 704s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:43 704s] <CMD> selectWire 163.5000 108.8100 165.6000
115.7250 6 gnd
[04/04 17:22:43 704s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:44 704s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:44 704s] <CMD> selectWire 184.5000 108.8100 186.6000
115.7250 4 gnd
[04/04 17:22:45 704s] <CMD> deleteSelectedFromFPlan
[04/04 17:22:50 705s] <CMD> zoomBox 88.743 70.338 131.493 35.114
[04/04 17:22:51 706s] <CMD> zoomBox 96.466 47.181 103.361 39.680
[04/04 17:22:54 706s] <CMD> zoomOut

[04/04 17:22:55 706s] <CMD> zoomOut

[04/04 17:22:56 706s] <CMD> zoomOut
[04/04 17:22:57 707s] <CMD> uiSetTool ruler
[04/04 17:23:02 707s] <CMD> zoomBox 87.589 54.682 127.775 16.640
[04/04 17:23:03 707s] <CMD> zoomBox 101.291 42.857 108.537 33.397
[04/04 17:23:13 708s] <CMD> fit
[04/04 17:23:16 708s] <CMD> uiSetTool select
[04/04 17:23:33 709s] <CMD> addStripe -skip_via_on_wire_shape Noshape
-block_ring_top_layer_limit Metal5 -max_same_layer_jog_length 0.14
-padcore_ring_bottom_layer_limit Metal3 -number_of_sets 2 -skip_via_on_pin
Standardcell -stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal5
-spacing 0.45 -xleft_offset 102 -merge_stripes_value 0.165 -layer Metal4
-block_ring_bottom_layer_limit Metal3 -width 2.1 -nets {gnd vdd}
-stacked_via_bottom_layer Metal1
[04/04 17:23:33 709s]
[04/04 17:23:33 709s] Starting stripe generation ...
[04/04 17:23:33 709s] Non-Default setAddStripeOption Settings :
[04/04 17:23:33 709s] NONE
[04/04 17:23:33 709s] The core ring for gnd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 17:23:33 709s] The core ring for vdd is incomplete. The core ring will not
be used as a boundary for stripes. In this situation, the power planner will
generate stripes only within the core area.
[04/04 17:23:33 709s] Stripe generation is complete; vias are now being
generated.
[04/04 17:23:33 709s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal4 & Metal6 at (207.90, 106.26) (208.60, 113.82)
[04/04 17:23:33 709s] **WARN: (ENCPP-532):
ViaGen Warning: top layer
and bottom layer have same direction but only orthogonal via is allowed
between layer: Metal4 & Metal6 at (205.35, 108.81) (206.05, 113.82)
[04/04 17:23:33 709s] The power planner created 4 wires.
[04/04 17:23:33 709s] *** Ending Stripe Generation (totcpu: 0:00:00.0,real:
0:00:00.0, mem: 1128.3M) ***

[04/04 17:23:47 709s] <CMD> sroute -connect { corePin } -layerChangeRange

{ Metal1 Metal9 } -blockPinTarget { stripe } -corePinTarget { firstAfterRowEnd }
-allowJogging 0 -crossoverViaLayerRange { Metal1 Metal4 } -allowLayerChange 0
-nets { vdd gnd } -targetViaLayerRange { Metal1 Metal4 }
[04/04 17:23:47 709s] **WARN: (ENCSR-4058):
Sroute option: blockPinTarget
should be used in conjunction with option: -connect blockPin.
[04/04 17:23:47 709s] *** Begin SPECIAL ROUTE on Mon Apr 4 17:23:47 2016
***
[04/04 17:23:47 709s] SPECIAL ROUTE ran on directory:
/Projects/Training/user5/work/suraj/encounter/rundir
[04/04 17:23:47 709s] SPECIAL ROUTE ran on machine: SRV01 (Linux 2.6.18308.el5 x86_64 2.66Ghz)
[04/04 17:23:47 709s]
[04/04 17:23:47 709s] Begin option processing ...
[04/04 17:23:47 709s] srouteConnectPowerBump set to false
[04/04 17:23:47 709s] routeSelectNet set to "vdd gnd"
[04/04 17:23:47 709s] routeSpecial set to true
[04/04 17:23:47 709s] srouteBlockPinTarget set to "stripe"
[04/04 17:23:47 709s] srouteBottomLayerLimit set to 1
[04/04 17:23:47 709s] srouteBottomTargetLayerLimit set to 1
[04/04 17:23:47 709s] srouteConnectBlockPin set to false
[04/04 17:23:47 709s] srouteConnectConverterPin set to false
[04/04 17:23:47 709s] srouteConnectPadPin set to false
[04/04 17:23:47 709s] srouteConnectStripe set to false
[04/04 17:23:47 709s] srouteCrossoverViaBottomLayer set to 1
[04/04 17:23:47 709s] srouteCrossoverViaTopLayer set to 4
[04/04 17:23:47 709s] srouteFollowCorePinEnd set to 3
[04/04 17:23:47 709s] srouteFollowPadPin set to false
[04/04 17:23:47 709s] srouteNoLayerChangeRoute set to true
[04/04 17:23:47 709s] sroutePadPinAllPorts set to true
[04/04 17:23:47 709s] sroutePreserveExistingRoutes set to true

[04/04 17:23:47 709s] srouteRoutePowerBarPortOnBothDir set to true

[04/04 17:23:47 709s] srouteStraightConnections set to "straightWithDrcClean"
[04/04 17:23:47 709s] srouteTopLayerLimit set to 9
[04/04 17:23:47 709s] srouteTopTargetLayerLimit set to 4
[04/04 17:23:47 709s] End option processing: cpu: 0:00:00, real: 0:00:00, peak:
1892.00 megs.
[04/04 17:23:47 709s]
[04/04 17:23:47 709s] Reading DB technology information...
[04/04 17:23:47 709s] Finished reading DB technology information.
[04/04 17:23:47 709s] Reading floorplan and netlist information...
[04/04 17:23:47 709s] Finished reading floorplan and netlist information.
[04/04 17:23:48 710s] Read in 19 layers, 9 routing layers, 1 overlap layer
[04/04 17:23:48 710s] Read in 2 nondefault rules, 0 used
[04/04 17:23:48 710s] Read in 491 macros, 68 used
[04/04 17:23:48 710s] Read in 68 components
[04/04 17:23:48 710s] 64 core components: 64 unplaced, 0 placed, 0 fixed
[04/04 17:23:48 710s] 4 block/ring components: 0 unplaced, 0 placed, 4 fixed
[04/04 17:23:48 710s] Read in 164 physical pins
[04/04 17:23:48 710s] 164 physical pins: 0 unplaced, 0 placed, 164 fixed
[04/04 17:23:48 710s] Read in 144 nets
[04/04 17:23:48 710s] Read in 2 special nets, 2 routed
[04/04 17:23:48 710s] Read in 303 terminals
[04/04 17:23:48 710s] 2 nets selected.
[04/04 17:23:48 710s]
[04/04 17:23:48 710s] Begin power routing ...
[04/04 17:23:48 710s] CPU time for FollowPin 0 seconds
[04/04 17:23:48 710s] CPU time for FollowPin 0 seconds
[04/04 17:23:48 710s] Number of Core ports routed: 0 open: 215
[04/04 17:23:48 710s] Number of Followpin connections: 122

[04/04 17:23:48 710s] End power routing: cpu: 0:00:00, real: 0:00:00, peak:
1892.00 megs.
[04/04 17:23:48 710s]
[04/04 17:23:48 710s]
[04/04 17:23:48 710s]
[04/04 17:23:48 710s] Begin updating DB with routing results ...
[04/04 17:23:48 710s] Updating DB with 160 via definition ...
[04/04 17:23:48 710s] Updating DB with 164 io pins ...
[04/04 17:23:48 710s]
sroute post-processing starts at Mon Apr 4 17:23:48 2016
The viaGen is rebuilding shadow vias for net gnd.
[04/04 17:23:48 710s] sroute post-processing ends at Mon Apr 4 17:23:48
2016

sroute post-processing starts at Mon Apr 4 17:23:48 2016

The viaGen is rebuilding shadow vias for net vdd.
[04/04 17:23:48 710s] sroute post-processing ends at Mon Apr 4 17:23:48
2016
sroute: Total CPU time used = 0:0:0
[04/04 17:23:48 710s] sroute: Total Real time used = 0:0:1
[04/04 17:23:48 710s] sroute: Total Memory used = 0.00 megs
[04/04 17:23:48 710s] sroute: Total Peak Memory used = 1128.29 megs
[04/04 17:23:50 710s] <CMD> setLayerPreference violation -isVisible 1
[04/04 17:23:50 710s] <CMD> violationBrowser -all -no_display_false
[04/04 17:23:52 711s] <CMD> clearDrc
[04/04 17:24:01 712s] <CMD> setPlaceMode -fp false
[04/04 17:24:01 712s] <CMD> placeDesign
[04/04 17:24:01 712s] *** Starting placeDesign default flow ***
[04/04 17:24:01 712s] **INFO: Enable pre-place timing setting for timing
analysis

[04/04 17:24:01 712s] Set Using Default Delay Limit as 101.

[04/04 17:24:01 712s] **WARN: (ENCDC-1629):
The default delay limit was
set to 101. This is less than the default of 1000 and may result in inaccurate
delay calculation for nets with a fanout higher than the setting. If needed, the
default delay limit may be adjusted by running the command 'set
delaycal_use_default_delay_limit'.
[04/04 17:24:01 712s] Set Default Net Delay as 0 ps.
[04/04 17:24:01 712s] Set Default Net Load as 0 pF.
[04/04 17:24:01 712s] **INFO: Analyzing IO path groups for slack adjustment
[04/04 17:24:02 712s] Effort level <high> specified for reg2reg_tmp.12308
path_group
[04/04 17:24:02 712s]
################################################
#################################
[04/04 17:24:02 712s] # Design Stage: PreRoute
[04/04 17:24:02 712s] # Design Mode: 90nm
[04/04 17:24:02 712s] # Analysis Mode: MMMC non-OCV
[04/04 17:24:02 712s] # Extraction Mode: default
[04/04 17:24:02 712s] # Delay Calculation Options: engine=aae
SIAware=false(opt_signoff)
[04/04 17:24:02 712s] # Switching Delay Calculation Engine to AAE
[04/04 17:24:02 712s]
################################################
#################################
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...

[04/04 17:24:02 712s] Calculate delays in BcWc mode...

[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Calculate delays in BcWc mode...
[04/04 17:24:02 712s] Topological Sorting (CPU = 0:00:00.0, MEM = 1138.1M,
InitMEM = 1138.1M)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:24:09 719s] AAE_THRD: End delay calculation. (MEM=1434
CPU=0:00:05.1 REAL=0:00:05.0)
[04/04 17:24:09 719s] *** CDM Built up (cpu=0:00:06.9 real=0:00:07.0 mem=
1434.0M) ***
[04/04 17:24:11 721s] *** Start deleteBufferTree ***
[04/04 17:24:11 721s] Info: Detect buffers to remove automatically.
[04/04 17:24:11 721s] Analyzing netlist ...
[04/04 17:24:11 721s] All-RC-Corners-Per-Net-In-Memory is turned ON...
[04/04 17:24:11 721s] Updating netlist
[04/04 17:24:11 721s]
[04/04 17:24:11 721s] *summary: 49 instances (buffers/inverters) removed
[04/04 17:24:11 721s] *** Finish deleteBufferTree (0:00:00.1) ***
[04/04 17:24:11 721s] **INFO: Disable pre-place timing setting for timing
analysis
[04/04 17:24:11 721s] Set Using Default Delay Limit as 1000.
[04/04 17:24:11 721s] Set Default Net Delay as 1000 ps.
[04/04 17:24:11 721s] Set Default Net Load as 0.5 pF.
[04/04 17:24:11 721s] *** Starting "NanoPlace(TM) placement v#1
(mem=1249.9M)" ...
[04/04 17:24:25 735s] *** Build Buffered Sizing Timing Model
[04/04 17:24:25 735s] (cpu=0:00:14.4 mem=1249.9M) ***
[04/04 17:24:26 736s] *** Build Virtual Sizing Timing Model

[04/04 17:24:26 736s] (cpu=0:00:14.7 mem=1249.9M) ***

[04/04 17:24:26 736s] Options: timingDriven clkGateAware ignoreScan
pinGuide congEffort=auto gpeffort=medium
[04/04 17:24:26 736s] **WARN: (ENCSP-9042):
defined, -ignoreScan option will be ignored.

Scan chains were not

[04/04 17:24:26 736s] Define the scan chains before using this option.
[04/04 17:24:26 736s] Type 'man ENCSP-9042' for more detail.
[04/04 17:24:27 737s] #std cell=2185 (0 fixed + 2185 movable) #block=4 (0
floating + 4 preplaced)
[04/04 17:24:27 737s] #ioInst=0 #net=2274 #term=8764 #term/net=3.85,
#fixedIo=144, #floatIo=0, #fixedPin=117, #floatPin=0
[04/04 17:24:27 737s] stdCell: 2185 single + 0 double + 0 multi
[04/04 17:24:27 737s] Total standard cell length = 5.9666 (mm), area = 0.0102
(mm^2)
[04/04 17:24:27 737s] Core basic site is CoreSite
[04/04 17:24:27 737s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:24:27 737s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:24:27 737s] Average module density = 0.738.
[04/04 17:24:27 737s] Density for the design = 0.738.
[04/04 17:24:27 737s]
= stdcell_area 29833 sites (10203 um^2) /
alloc_area 40419 sites (13823 um^2).
[04/04 17:24:27 737s] Pin Density = 0.069.
[04/04 17:24:27 737s]
127119.

= total # of pins 8764 / total Instance area

[04/04 17:24:27 737s] === lastAutoLevel = 8

Est. stn bbox = 7.737e+04 (4.10e+04

[04/04 17:24:39 749s]

1403.7M

cpu = 0:00:01.5 real = 0:00:01.0 mem =

[04/04 17:24:41 751s] Congestion driven padding in post-place stage.

[04/04 17:24:41 751s] Congestion driven padding increases utilization from

0.738 to 0.845
[04/04 17:24:41 751s] Congestion driven padding runtime: cpu = 0:00:00.0 real
= 0:00:00.0 mem = 1403.7M
[04/04 17:24:41 751s] Iteration 9: Total net bbox = 6.319e+04 (3.33e+04
2.99e+04)
[04/04 17:24:41 751s]
3.67e+04)

Est. stn bbox = 7.773e+04 (4.10e+04

[04/04 17:24:41 751s]

1403.7M

cpu = 0:00:01.6 real = 0:00:02.0 mem =

35.80 um

[04/04 17:24:47 757s] inst (EXECUTE_INST/g3350) with max move: (108.065,

148.285) -> (98.4, 174.42)
[04/04 17:24:47 757s] mean

(X+Y) =

1.34 um

[04/04 17:24:47 757s] Summary Report:

[04/04 17:24:47 757s] Instances move: 2185 (out of 2185 movable)
[04/04 17:24:47 757s] Mean displacement: 1.34 um
[04/04 17:24:47 757s] Max displacement: 35.80 um (Instance:
EXECUTE_INST/g3350) (108.065, 148.285) -> (98.4, 174.42)
[04/04 17:24:47 757s]
cell type: INVXL

Length: 3 sites, height: 1 rows, site name: CoreSite,

[04/04 17:24:47 757s] Total instances moved : 2185

[04/04 17:24:47 757s] Total net length = 5.648e+04 (2.973e+04 2.675e+04)
(ext = 8.598e+03)
[04/04 17:24:47 757s] Runtime: CPU: 0:00:02.6 REAL: 0:00:03.0 MEM:
1206.2MB

[04/04 17:24:47 757s] [CPU] RefinePlace/total (cpu=0:00:02.6, real=0:00:03.0,

mem=1206.2MB) @(0:12:33 - 0:12:35).
[04/04 17:24:47 757s] *** Finished refinePlace (0:12:35 mem=1206.2M) ***
[04/04 17:24:47 757s] Total net length = 5.647e+04 (2.973e+04 2.674e+04)
(ext = 8.587e+03)
[04/04 17:24:47 757s] *** End of Placement (cpu=0:00:35.9, real=0:00:36.0,
mem=1206.2M) ***
[04/04 17:24:47 757s] Core basic site is CoreSite
[04/04 17:24:47 757s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:24:47 757s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:24:47 757s] default core: bins with density > 0.75 = 77.5 % ( 131 /
169 )
[04/04 17:24:47 757s] Density distribution unevenness ratio = 6.364%
[04/04 17:24:47 757s] *** Free Virtual Timing Model ...(mem=1206.2M)
[04/04 17:24:47 757s] Starting IO pin assignment...
[04/04 17:24:47 757s] Starting congestion repair ...
[04/04 17:24:47 757s] congRepair options: -clkGateAware 1
-rplaceIncrNPClkGateAwareMode 4.
[04/04 17:24:47 757s] *** Starting trialRoute (mem=1206.2M) ***
[04/04 17:24:47 757s]
[04/04 17:24:47 757s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:24:47 757s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:24:47 757s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:24:47 757s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:24:47 757s]
[04/04 17:24:47 757s] Nr of prerouted/Fixed nets = 0
[04/04 17:24:47 757s] routingBox: (-200 -330) (210200 207240)
[04/04 17:24:47 757s] coreBox:

(0 0) (210000 206910)

[04/04 17:24:47 757s] Number of multi-gpin terms=2413, multi-gpins=5699,

moved blk term=63/63
[04/04 17:24:47 757s]
[04/04 17:24:47 757s] Phase 1a route (0:00:00.0 1206.2M):
[04/04 17:24:47 757s] Est net length = 6.393e+04um = 3.303e+04H +
3.089e+04V
[04/04 17:24:47 757s] Usage: (10.3%H 12.3%V) = (3.617e+04um
4.325e+04um) = (36164 25285)
[04/04 17:24:47 757s] Obstruct: 8394 = 4197 (16.5%H) + 4197 (16.5%V)
[04/04 17:24:47 757s] Overflow: 53 = 19 (0.09% H) + 34 (0.16% V)
[04/04 17:24:47 757s]
[04/04 17:24:47 757s] Phase 1b route (0:00:00.0 1206.2M):
[04/04 17:24:47 757s] Usage: (10.3%H 12.3%V) = (3.606e+04um
4.324e+04um) = (36062 25280)
[04/04 17:24:47 757s] Overflow: 34 = 0 (0.00% H) + 34 (0.16% V)
[04/04 17:24:47 757s]
[04/04 17:24:47 757s] Phase 1c route (0:00:00.0 1206.2M):
[04/04 17:24:47 757s] Usage: (10.3%H 12.3%V) = (3.601e+04um
4.321e+04um) = (36009 25263)
[04/04 17:24:47 757s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:24:47 757s]
[04/04 17:24:47 757s] Phase 1d route (0:00:00.0 1206.2M):
[04/04 17:24:47 757s] Usage: (10.3%H 12.3%V) = (3.601e+04um
4.321e+04um) = (36009 25263)
[04/04 17:24:47 757s] Overflow: 0 = 0 (0.00% H) + 0 (0.00% V)
[04/04 17:24:47 757s]
[04/04 17:24:47 757s] Phase 1a-1d Overflow: 0.00% H + 0.00% V (0:00:00.1
1206.2M)

[04/04 17:24:47 757s]

[04/04 17:24:47 757s] Phase 1e route (0:00:00.0 1206.2M):

0.01%

924

4.36%

[04/04 17:24:48 757s] 5:

2121099.99%

2018495.15%

[04/04 17:24:48 757s]

[04/04 17:24:48 757s] Global route (cpu=0.1s real=0.1s 1206.2M)
[04/04 17:24:48 757s] Updating RC grid for preRoute extraction ...
[04/04 17:24:48 757s] Initializing multi-corner capacitance tables ...
[04/04 17:24:48 757s] Initializing multi-corner resistance tables ...
[04/04 17:24:48 758s]
[04/04 17:24:48 758s]
[04/04 17:24:48 758s] *** After '-updateRemainTrks' operation:

0.00%

0.18%

[04/04 17:24:48 758s] 3:

0.00%

138

0.65%

[04/04 17:24:48 758s] 4:

0.02%

962

4.53%

[04/04 17:24:48 758s] 5:

2120999.98%

2004394.48%

[04/04 17:24:48 758s]

[04/04 17:24:48 758s]
[04/04 17:24:48 758s] *** Completed Phase 1 route (0:00:00.4 1214.2M) ***
[04/04 17:24:48 758s]
[04/04 17:24:48 758s]
[04/04 17:24:48 758s] ** np local hotspot detection info verbose **

[04/04 17:24:48 758s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:24:48 758s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:24:48 758s]
[04/04 17:24:48 758s]
[04/04 17:24:48 758s] Total length: 6.581e+04um, number of vias: 19702
[04/04 17:24:48 758s] M1(H) length: 1.898e+01um, number of vias: 8391
[04/04 17:24:48 758s] M2(V) length: 1.702e+04um, number of vias: 8010
[04/04 17:24:48 758s] M3(H) length: 2.501e+04um, number of vias: 1421
[04/04 17:24:48 758s] M4(V) length: 8.668e+03um, number of vias: 796
[04/04 17:24:48 758s] M5(H) length: 4.708e+03um, number of vias: 582
[04/04 17:24:48 758s] M6(V) length: 2.954e+03um, number of vias: 251
[04/04 17:24:48 758s] M7(H) length: 2.780e+03um, number of vias: 220
[04/04 17:24:48 758s] M8(V) length: 3.851e+03um, number of vias: 31
[04/04 17:24:48 758s] M9(H) length: 8.022e+02um
[04/04 17:24:48 758s] *** Completed Phase 2 route (0:00:00.2 1214.2M) ***
[04/04 17:24:48 758s]
[04/04 17:24:48 758s] *** Finished all Phases (cpu=0:00:00.6 mem=1214.2M)
***
[04/04 17:24:48 758s] dbSprFixZeroViaCodes runtime= 0:00:00.0
[04/04 17:24:48 758s] Peak Memory Usage was 1214.2M
[04/04 17:24:48 758s] TrialRoute+GlbRouteEst total runtime= +0:00:00.7 =
0:00:09.5
[04/04 17:24:48 758s] TrialRoute full (called 12x) runtime= 0:00:08.7
[04/04 17:24:48 758s] TrialRoute check only (called 4x) runtime= 0:00:00.1
[04/04 17:24:48 758s] GlbRouteEst (called 21x) runtime= 0:00:00.6
[04/04 17:24:48 758s] *** Finished trialRoute (cpu=0:00:00.7 mem=1214.2M)
***
[04/04 17:24:48 758s]

[04/04 17:24:48 758s] Local HotSpot Analysis: normalized max congestion

hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in
unit of 4 std-cell row bins)
[04/04 17:24:48 758s]
[04/04 17:24:48 758s] ** np local hotspot detection info verbose **
[04/04 17:24:48 758s] level 0: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 88.00 (area is in unit of 4 std-cell row bins)
[04/04 17:24:48 758s] level 1: max group area = 0.00 (0.00%) total group area
= 0.00 (0.00%) threshold area = 80.00 (area is in unit of 4 std-cell row bins)
[04/04 17:24:48 758s]
[04/04 17:24:48 758s] describeCongestion: hCong = 0.00 vCong = 0.00
[04/04 17:24:48 758s] Trial Route Overflow 0.000000(H) 0.059666(V).
[04/04 17:24:48 758s] Start repairing congestion with level 1.
[04/04 17:24:48 758s] Skipped repairing congestion.
[04/04 17:24:48 758s] End of congRepair (cpu=0:00:00.7, real=0:00:01.0)
[04/04 17:24:48 758s] *** Finishing placeDesign default flow ***
[04/04 17:24:48 758s] **placeDesign ... cpu = 0: 0:46, real = 0: 0:47, mem =
1203.3M **
[04/04 17:24:48 758s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12

Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:24:48 758s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:24:48 758s]
[04/04 17:24:48 758s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:24:48 758s] Severity ID

Count Summary

[04/04 17:24:48 758s] WARNING ENCDC-1629

was set to %d. T...

1 The default delay limit

[04/04 17:24:48 758s] WARNING ENCSP-9025

specified/traced.

1 No scan chain

[04/04 17:24:48 758s] WARNING ENCSP-9042

defined, -ignoreSca...

1 Scan chains were not

[04/04 17:24:48 758s] *** Message Summary: 3 warning(s), 0 error(s)

[04/04 17:24:48 758s]

[04/04 17:24:57 758s] <CMD> setLayerPreference allM0 -isVisible 0

[04/04 17:24:57 758s] <CMD> setLayerPreference allM1Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM1 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM2Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM2 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM3Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM3 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM4Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM4 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM5Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM5 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM6Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM6 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM7Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM7 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM8Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM8 -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM9Cont -isVisible 0
[04/04 17:24:57 758s] <CMD> setLayerPreference allM9 -isVisible 0
[04/04 17:25:10 759s] <CMD> reportGateCount
[04/04 17:25:10 759s] Gate area 1.0260 um^2
[04/04 17:25:10 759s] [0] tdsp_core Gates=38188 Cells=2189 Area=39181.9
um^2
[04/04 17:25:17 760s] <CMD> zoomBox 67.066 118.207 90.549 75.757
[04/04 17:25:18 760s] <CMD> fit
[04/04 17:25:27 761s] <CMD> clockDesign -specFile ../../DATA/clock.ctstch
-outDir clock_report -fixedInstBeforeCTS
[04/04 17:25:27 761s] -engine auto
ccopt_from_edi_spec}, default=auto

# enums={ck ccopt auto

[04/04 17:25:27 761s] **WARN: (ENCCK-9000):

supported when setCTSMode -engine is not ck.

Option -outDir is partially

[04/04 17:25:27 761s] **ERROR: (ENCCK-9000):

Option -fixedInstBeforeCTS is
not supported when setCTSMode -engine is not ck, please use
changeClockStatus command before clockDesign.
[04/04 17:25:27 761s]
[04/04 17:25:27 761s] clockDesign
[04/04 17:25:27 761s]

[-specFile {filename1 filename2 ...}]

2 %s

[04/04 17:25:27 761s] *** Message Summary: 0 warning(s), 2 error(s)

[04/04 17:25:27 761s]

[04/04 17:25:35 761s] <CMD> setCTSMode -engine ck

[04/04 17:25:57 761s] invalid command name "AutoCTSRootPin"
[04/04 17:26:08 762s] <CMD> clockDesign -specFile ../../DATA/clock.ctstch
-outDir clock_report -fixedInstBeforeCTS
[04/04 17:26:08 762s] -engine ck
ccopt_from_edi_spec}, default=auto, user setting

# enums={ck ccopt auto

[04/04 17:26:08 762s] **clockDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1203.3M **
[04/04 17:26:08 762s] setCTSMode -engine ck -moveGateLimit 25
[04/04 17:26:08 762s] <clockDesign INFO> 'setCTSMode -routeClkNet true' is
set inside clockDesign.
[04/04 17:26:08 762s]
[04/04 17:26:08 762s] <clockDesign CMD> cleanupSpecifyClockTree
[04/04 17:26:08 762s] <clockDesign CMD> specifyClockTree -file
../../DATA/clock.ctstch
[04/04 17:26:08 762s] Checking spec file integrity...
[04/04 17:26:08 762s]
[04/04 17:26:08 762s] Reading clock tree spec file '../../DATA/clock.ctstch' ...
[04/04 17:26:08 762s]
[04/04 17:26:08 762s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:26:08 762s] Updating RC grid for preRoute extraction ...

[04/04 17:26:08 762s] Initializing multi-corner capacitance tables ...
[04/04 17:26:08 762s] Initializing multi-corner resistance tables ...
[04/04 17:26:08 762s] RouteType

: FE_CTS_DEFAULT

[04/04 17:26:08 762s] PreferredExtraSpace

[04/04 17:26:08 762s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:26:08 762s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:26:08 762s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:26:08 762s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:26:08 762s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)

: 0.0937833(V=0.0937833

[04/04 17:26:08 762s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 17:26:08 762s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:26:08 762s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:26:08 762s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:26:08 762s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)

cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 17:26:08 762s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:26:08 762s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:26:08 762s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 17:26:08 762s]
[04/04 17:26:08 762s] RC Information for View
Arise_analysis_view_test_min_cmax_Tm20V15 :
[04/04 17:26:08 762s] Est. Cap
H=0.0937833) (ff/um) [9.37833e-05]

: 0.0937833(V=0.0937833

[04/04 17:26:08 762s] Est. Res

(ohm/um) [0.000862857]

: 0.862857(V=0.862857 H=0.862857)

[04/04 17:26:08 762s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:26:08 762s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:26:08 762s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:26:08 762s] Est. Via Res

: 4.8575(ohm) [8.90542]

[04/04 17:26:08 762s] Est. Via Cap

: 0.0480942(ff)

[04/04 17:26:08 762s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:26:08 762s] M1(H) w=0.06(um) s=0.06(um) p=0.19(um)

[04/04 17:26:08 762s] M5(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)

cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=4.60625(ohm)
viaCap=0.0513155(ff)
[04/04 17:26:08 762s] M6(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm)
viaCap=0.0810791(ff)
[04/04 17:26:08 762s] M7(H) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.863(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:26:08 762s] M8(V) w=0.07(um) s=0.07(um) p=0.2(um) es=0.33(um)
cap=0.0938(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm) viaCap=0.24015(ff)
[04/04 17:26:08 762s] M9(H) w=0.07(um) s=0.07(um) p=0.33(um)
es=0.59(um) cap=0.244(ff/um) res=0.306(ohm/um) viaRes=1.675(ohm)
viaCap=0.478584(ff)
[04/04 17:26:08 762s]
[04/04 17:26:08 762s] Switching off Advanced RC Correlation modes in AAE
mode.
[04/04 17:26:08 762s] Active Analysis Views for CTS are,
[04/04 17:26:08 762s] #1 Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:08 762s] #2 Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:26:08 762s] #3 Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:26:08 762s] #4 Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:26:08 762s] #5 Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:26:08 762s] #6 Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:26:08 762s] #7 Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:26:08 762s] #8 Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:26:08 762s] #9 Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:26:08 762s] #10 Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:26:08 762s] #11 Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:26:08 762s] #12 Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:26:08 762s] #13 Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:26:08 762s] #14 Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:26:08 762s] #15 Arise_analysis_view_test_max_cmin_T140V102

[04/04 17:26:08 762s] #16 Arise_analysis_view_func_max_cmin_T125V108

[04/04 17:26:08 762s] #17 Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:26:08 762s] #18 Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:26:08 762s] #19 Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:26:08 762s] #20 Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:26:08 762s] #21 Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:26:08 762s] #22 Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:26:08 762s] #23 Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:26:08 762s] #24 Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:26:08 762s] #25 Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:26:08 762s] #26 Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:26:08 762s] #27 Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:26:08 762s] #28 Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:26:08 762s] #29 Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:26:08 762s] #30 Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:26:08 762s] #31 Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:26:08 762s] #32 Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:26:08 762s] #33 Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:26:08 762s] #34 Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:26:08 762s] #35 Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:26:08 762s] Default Analysis Views is
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:08 762s]
[04/04 17:26:08 762s]
[04/04 17:26:08 762s] ****** AutoClockRootPin ******
[04/04 17:26:08 762s] AutoClockRootPin 1: clk
[04/04 17:26:08 762s] # NoGating
[04/04 17:26:08 762s] # SetDPinAsSync

NO
NO

[04/04 17:26:08 762s] # SetIoPinAsSync NO

[04/04 17:26:08 762s] # SetAsyncSRPinAsSync NO

[04/04 17:26:08 762s] # SetTriStEnPinAsSync NO
[04/04 17:26:08 762s] # SetBBoxPinAsSync NO
[04/04 17:26:08 762s] # RouteClkNet
[04/04 17:26:08 762s] # PostOpt

[04/04 17:26:09 762s] Checking spec file integrity...

[04/04 17:26:09 762s] List of dont use cells: HOLDX1
[04/04 17:26:09 762s] List of dont touch cells:
[04/04 17:26:09 762s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 17:26:09 763s] ***** Allocate Placement Memory Finished (MEM:
1213.340M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Start to trace clock trees ...
[04/04 17:26:09 763s] *** Begin Tracer (mem=1213.3M) ***

[04/04 17:26:09 763s] Tracing Clock clk ...

[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Reconvergent mux Check for spec:clk
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Reconvergent mux Checks Finished, CPU=0:00:00.0
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s] *** End Tracer (mem=1213.3M) ***
[04/04 17:26:09 763s] ***** Allocate Obstruction Memory Finished (MEM:
1213.340M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s]
################################################
#############################
[04/04 17:26:09 763s] #
[04/04 17:26:09 763s] # Pre-Synthesis Checks and Parameters
[04/04 17:26:09 763s] #
[04/04 17:26:09 763s]
################################################
#############################
[04/04 17:26:09 763s]
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Types of Check
Disabled

Enabled|

[04/04 17:26:09 763s] ---------------------------------------------------------------------------[04/04 17:26:09 763s]

[04/04 17:26:09 763s] Check cell drive strength

enabled
:

enabled

[04/04 17:26:09 763s]

[04/04 17:26:09 763s] Parameters of checking :
[04/04 17:26:09 763s] CTS uses following values to determine if diagnostic
checks are successful.
[04/04 17:26:09 763s] Use setCTSMode to change default values.
[04/04 17:26:09 763s] ---------------------------------------------------------------------------[04/04 17:26:09 763s]
[04/04 17:26:09 763s] 1) Pin capacitance check
[04/04 17:26:09 763s]
of constraint (default)

Threshold for MaxCap check

90%

[04/04 17:26:09 763s] 2) Gating depth check

[04/04 17:26:09 763s]
levels (default)

Maximum gating depth

[04/04 17:26:09 763s] 3) Placement near clock pin check

[04/04 17:26:09 763s]
5.13(um) (default)

Threshold distance for placeable location

[04/04 17:26:09 763s] 4) Clock gating location check

[04/04 17:26:09 763s]
(default)

Allowed clock gate detour

290(um)

[04/04 17:26:09 763s]

0.5 (default)

180(ps) derived from 90% (default) MaxSinkTran constraint

[04/04 17:26:09 763s] Root Input Transition

0.1(ps)]

[0.1(ps)

[04/04 17:26:09 763s]

[04/04 17:26:09 763s]
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Max Cap Limit Checks
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Max Cap Limit Checks Finished, CPU=0:00:00.0
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]

[04/04 17:26:09 763s] Deep Gating Level Checks

[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s] ** INFO Clock clk has a maximum of 1 levels of logic
before synthesis.
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Deep Gating Level Checks Finished, CPU=0:00:00.0
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Max placement distance Checks
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Max placement distance Checks Finished,
CPU=0:00:00.0
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Root input tran Checks
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Root input tran Checks Finished, CPU=0:00:00.0
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Routing OBS checks

[04/04 17:26:09 763s]

================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Routing OBS Checks Finished, CPU=0:00:00.1
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] MacroModel Debugging Check
[04/04 17:26:09 763s] ==========================
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] MacroModel Debugging Check Finished, CPU=0:00:00.0
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Clock gating checks
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Clock gating Checks Finished, CPU=0:00:00.0
[04/04 17:26:09 763s]
================================================
============
[04/04 17:26:09 763s]
[04/04 17:26:09 763s]
################################################
#############################
[04/04 17:26:09 763s] #
[04/04 17:26:09 763s] # Summary of Pre-Synthesis Checks
[04/04 17:26:09 763s] #

[04/04 17:26:09 763s]

################################################
#############################
[04/04 17:26:09 763s]
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Types of Check
warnings

Number of

[04/04 17:26:09 763s] ---------------------------------------------------------------------------[04/04 17:26:09 763s]

[04/04 17:26:09 763s] Check cell drive strength
0(disabled)

[04/04 17:26:09 763s] Check root input transition

[04/04 17:26:09 763s] Check pin capacitance

[04/04 17:26:09 763s] Check multiple path through MUX

[04/04 17:26:09 763s] Check gating depth

:
:

[04/04 17:26:09 763s] Check placement near clock pins

0
0

[04/04 17:26:09 763s] Check route blockages over clock pins

0
:

[04/04 17:26:09 763s] Report FIXED, DontUse and DontTouch

0(disabled)
[04/04 17:26:09 763s] clock gating checks
[04/04 17:26:09 763s] MacroModel checks

:
:

0
:

(default)

Delay threshold

:
:

10(ps)

[04/04 17:26:09 763s] 3) Saving intermediate database

[04/04 17:26:09 763s]
0(min) (default)

Save long-running subtrees time

[04/04 17:26:09 763s]

(default)

Maximum number of saved databases

[04/04 17:26:09 763s] 4) Clock gating location check

[04/04 17:26:09 763s]
(default)

Allowed clock gate detour

290(um)

[04/04 17:26:09 763s] 5) Wire resistance check

[04/04 17:26:09 763s]
(default)

Allowed resistance deviation

[04/04 17:26:09 763s]

Ohm (user set)

Resistance threshold

0.2

97.15

[04/04 17:26:09 763s] Net length threshold for resistance checks

um (derived 200*M2 layer pitch)

[04/04 17:26:09 763s]

[04/04 17:26:09 763s]
[04/04 17:26:09 763s] ****** Clock (clk) Diagnostic check Parameters
[04/04 17:26:09 763s] Assumed driver input transition
28.4(ps) (derived from BUFX8)

[04/04 17:26:09 763s] Threshold for MaxBufTran check

180(ps) derived from 90% (default) MaxBufTran constraint

[04/04 17:26:09 763s] Threshold for MaxSinkTran check

180(ps) derived from 90% (default) MaxSinkTran constraint

[04/04 17:26:09 763s] Movement threshold

5.172750(um) (derived 5% of MaxBuf strength)
[04/04 17:26:09 763s] Root Input Transition
0.1(ps)]
[04/04 17:26:09 763s]
[04/04 17:26:09 763s]

:
:

[0.1(ps)

[04/04 17:26:09 763s]

[04/04 17:26:09 763s] ****** Clock Tree (clk) Structure
[04/04 17:26:09 763s] Max. Skew

: 20(ps)

[04/04 17:26:09 763s] Max. Sink Transition: 200(ps)

[04/04 17:26:09 763s] Max. Buf Transition : 200(ps)
[04/04 17:26:09 763s] Max. Delay

: 950(ps)

[04/04 17:26:09 763s] Min. Delay

: 950(ps)

[04/04 17:26:09 763s] Buffer

(BUFX8)

: (BUFX2) (BUFX3) (BUFX4) (BUFX6)

[04/04 17:26:09 763s] Nr. Subtrees

[04/04 17:26:09 763s] Nr. Sinks
[04/04 17:26:09 763s] Nr.

: 13
: 258

Rising Sync Pins : 258

[04/04 17:26:09 763s] Nr. Inverter Rising Sync Pins : 0

[04/04 17:26:09 763s] Nr.

Falling Sync Pins : 0

[04/04 17:26:09 763s] Nr. Inverter Falling Sync Pins : 0

[04/04 17:26:09 763s] Nr. Unsync Pins

[04/04 17:26:09 763s]

***********************************************************
[04/04 17:26:09 763s] SubTree No: 0
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(TDSP_CORE_MACH_INST/RC_CG_HIER_INST29/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(TDSP_CORE_MACH_INST/RC_CG_HIER_INST29/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (TDSP_CORE_MACH_INST/rc_gclk)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=0[249,249]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)

[04/04 17:26:09 763s] SubTree No: 1

[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(PROG_BUS_MACH_INST/RC_CG_HIER_INST28/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(PROG_BUS_MACH_INST/RC_CG_HIER_INST28/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (PROG_BUS_MACH_INST/rc_gclk)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=1[259,260]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 2
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(PORT_BUS_MACH_INST/RC_CG_HIER_INST27/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(PORT_BUS_MACH_INST/RC_CG_HIER_INST27/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (PORT_BUS_MACH_INST/rc_gclk)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=0[258,259]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 3
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH/ECK)

[04/04 17:26:09 763s] Output_Net: (EXECUTE_INST/rc_gclk_11928)

[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=1[261,262]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 4
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST25/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST25/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (EXECUTE_INST/rc_gclk_11925)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=0[251,251]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 5
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (EXECUTE_INST/rc_gclk_11922)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=0[254,254]ps N1 inTran=0/0ps.

[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,

real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 6
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST23/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST23/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (EXECUTE_INST/rc_gclk_11919)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=2[273,275]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 7
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST22/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST22/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (EXECUTE_INST/rc_gclk_11916)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=1[263,264]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 8
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST21/RC_CGIC_INST/LATCH/CK)

[04/04 17:26:09 763s] Output_Pin:

(EXECUTE_INST/RC_CG_HIER_INST21/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (EXECUTE_INST/rc_gclk_11913)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=1[261,262]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 9
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(EXECUTE_INST/RC_CG_HIER_INST20/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(EXECUTE_INST/RC_CG_HIER_INST20/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (EXECUTE_INST/rc_gclk)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=2[277,280]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 10
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(DECODE_INST/RC_CG_HIER_INST19/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(DECODE_INST/RC_CG_HIER_INST19/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (DECODE_INST/rc_gclk)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]

[04/04 17:26:09 763s] Macro model: Skew=1[276,277]ps N1 inTran=0/0ps.

[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 11
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin:
(DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/LATCH/CK)
[04/04 17:26:09 763s] Output_Pin:
(DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/LATCH/ECK)
[04/04 17:26:09 763s] Output_Net: (DATA_BUS_MACH_INST/rc_gclk)
[04/04 17:26:09 763s] **** CK_START: Macro Models Generation
(mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Macro model: Skew=0[259,259]ps N1 inTran=0/0ps.
[04/04 17:26:09 763s] **** CK_END: Macro Models Generation (cpu=0:00:00.0,
real=0:00:00.0, mem=1225.4M)
[04/04 17:26:09 763s] SubTree No: 12
[04/04 17:26:09 763s]
[04/04 17:26:09 763s] Input_Pin: (NULL)
[04/04 17:26:09 763s] Output_Pin: (clk)
[04/04 17:26:09 763s] Output_Net: (clk)
[04/04 17:26:09 763s] **** CK_START: TopDown Tree Construction for clk (58leaf) (12 macro model) (mem=1225.4M)
[04/04 17:26:09 763s]
[04/04 17:26:10 764s] Total 3 topdown clustering.
[04/04 17:26:10 764s] Trig. Edge Skew=*34[377,410*] N58 B4 G13 A7(6.6)
L[2,5] C1/3 score=62550 cpu=0:00:01.0 mem=1223M
[04/04 17:26:10 764s]
[04/04 17:26:10 764s] **** CK_END: TopDown Tree Construction for clk
(cpu=0:00:01.2, real=0:00:01.0, mem=1223.4M)
[04/04 17:26:10 764s]

[04/04 17:26:10 764s]

[04/04 17:26:10 764s]
[04/04 17:26:10 764s] **** CK_START: Update Database (mem=1223.4M)
[04/04 17:26:10 764s] 4 Clock Buffers/Inverters inserted.
[04/04 17:26:10 764s] **** CK_END: Update Database (cpu=0:00:00.0,
real=0:00:00.0, mem=1223.4M)
[04/04 17:26:10 764s]
[04/04 17:26:10 764s] Refine place movement check
[04/04 17:26:10 764s]
================================================
============
[04/04 17:26:10 764s]
[04/04 17:26:10 764s]
[04/04 17:26:10 764s] **INFO: The distance threshold for maximum refine
placement move is 5.172750 microns (5% of max driving distance).
[04/04 17:26:10 764s]
[04/04 17:26:10 764s] ***** Start Refine Placement.....
[04/04 17:26:10 764s] *** Starting refinePlace (0:12:42 mem=1223.4M) ***
[04/04 17:26:10 764s] Total net length = 5.668e+04 (2.979e+04 2.688e+04)
(ext = 8.325e+03)
[04/04 17:26:10 764s] Starting refinePlace ...
[04/04 17:26:10 764s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:26:11 765s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:26:11 765s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.8,
real=0:00:01.0, mem=1226.2MB) @(0:12:42 - 0:12:43).
[04/04 17:26:11 765s] Move report: preRPlace moves 167 insts, mean move:
0.05 um, max move: 1.50 um
[04/04 17:26:11 765s]
(103.58, 201.86)

Max move on inst (clk__L1_I0): (105.00, 201.78) -->

[04/04 17:26:11 765s]

cell type: BUFX8

Length: 11 sites, height: 1 rows, site name: CoreSite,

[04/04 17:26:11 765s] wireLenOptFixPriorityInst 4 inst fixed

[04/04 17:26:11 765s] Move report: legalization moves 186 insts, mean move:
0.88 um, max move: 4.91 um
[04/04 17:26:11 765s] Max move on inst (TDSP_CORE_GLUE_INST/g8521):
(156.60, 112.86) --> (159.80, 111.15)
[04/04 17:26:11 765s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1226.2MB) @(0:12:43 - 0:12:43).
[04/04 17:26:11 765s] Move report: Detail placement moves 111 insts, mean
move: 1.49 um, max move: 4.91 um
[04/04 17:26:11 765s] Max move on inst (TDSP_CORE_GLUE_INST/g8521):
(156.60, 112.86) --> (159.80, 111.15)
[04/04 17:26:11 765s]
1226.2MB

Runtime: CPU: 0:00:00.8 REAL: 0:00:01.0 MEM:

[04/04 17:26:11 765s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:26:11 765s] maximum (X+Y) =

4.91 um

[04/04 17:26:11 765s] inst (TDSP_CORE_GLUE_INST/g8521) with max move:

(156.6, 112.86) -> (159.8, 111.15)
[04/04 17:26:11 765s] mean

(X+Y) =

1.49 um

[04/04 17:26:11 765s] Summary Report:

[04/04 17:26:11 765s] Instances move: 111 (out of 1919 movable)
[04/04 17:26:11 765s] Mean displacement: 1.49 um
[04/04 17:26:11 765s] Max displacement: 4.91 um (Instance:
TDSP_CORE_GLUE_INST/g8521) (156.6, 112.86) -> (159.8, 111.15)
[04/04 17:26:11 765s]
cell type: NOR2BX4

Length: 11 sites, height: 1 rows, site name: CoreSite,

[04/04 17:26:11 765s] Total instances moved : 111

[04/04 17:26:11 765s] Total net length = 5.668e+04 (2.979e+04 2.688e+04)
(ext = 8.325e+03)
[04/04 17:26:11 765s] Runtime: CPU: 0:00:00.8 REAL: 0:00:01.0 MEM:
1226.2MB
[04/04 17:26:11 765s] [CPU] RefinePlace/total (cpu=0:00:00.8, real=0:00:01.0,
mem=1226.2MB) @(0:12:42 - 0:12:43).
[04/04 17:26:11 765s] *** Finished refinePlace (0:12:43 mem=1226.2M) ***

[04/04 17:26:11 765s] ***** Refine Placement Finished (CPU Time: 0:00:01.0
MEM: 1226.207M)
[04/04 17:26:11 765s]
[04/04 17:26:11 765s]
[04/04 17:26:11 765s] **INFO: Total instances moved beyond threshold limit
during refinePlace are 0...
[04/04 17:26:11 765s]
[04/04 17:26:11 765s]
[04/04 17:26:11 765s] Refine place movement check finished, CPU=0:00:01.1
[04/04 17:26:11 765s]
================================================
============
[04/04 17:26:12 765s]
[04/04 17:26:12 765s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:12 765s] ********** Clock clk Pre-Route Timing Analysis **********
[04/04 17:26:12 765s] Nr. of Subtrees

: 13

[04/04 17:26:12 765s] Nr. of Sinks

: 258

[04/04 17:26:12 765s] Nr. of Buffer

[04/04 17:26:12 765s] Nr. of Level (including gates) : 4

[04/04 17:26:12 765s] Root Rise Input Tran

: 0.1(ps)

[04/04 17:26:12 765s] Root Fall Input Tran

: 0.1(ps)

[04/04 17:26:12 765s] No Driving Cell Specified!

[04/04 17:26:12 765s] Max trig. edge delay at sink(R):
EXECUTE_INST/acc_reg[10]/state_remap/DFF/CK 411.2(ps)
[04/04 17:26:12 765s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_6_reg/state_remap/DFF/CK 377.5(ps)
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]

(Actual)

(Required)

[04/04 17:26:12 765s] Rise Phase Delay

950~950(ps)

: 377.5~411.2(ps)

[04/04 17:26:12 765s] Fall Phase Delay

950~950(ps)

: 354.9~418.3(ps)

[04/04 17:26:12 765s] Trig. Edge Skew

: 33.7(ps)

[04/04 17:26:12 765s] Rise Skew

[04/04 17:26:12 765s] Fall Skew

20(ps)

: 33.7(ps)
: 63.4(ps)

[04/04 17:26:12 765s] Max. Rise Buffer Tran.

: 90.8(ps)

200(ps)

[04/04 17:26:12 765s] Max. Fall Buffer Tran.

: 101.2(ps)

200(ps)

[04/04 17:26:12 765s] Max. Rise Sink Tran.

: 121.3(ps)

200(ps)

[04/04 17:26:12 765s] Max. Fall Sink Tran.

[04/04 17:26:12 765s] Min. Rise Buffer Tran.

: 137.1(ps)
: 21.5(ps)

200(ps)
0(ps)

[04/04 17:26:12 765s] Min. Fall Buffer Tran.

: 21.8(ps)

0(ps)

[04/04 17:26:12 765s] Min. Rise Sink Tran.

: 41.2(ps)

0(ps)

[04/04 17:26:12 765s] Min. Fall Sink Tran.

: 30.8(ps)

0(ps)

[04/04 17:26:12 765s]

[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 21.9ps (required = 20ps)

[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew

= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 19.7ps (required = 20ps)

[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmin_Tm20V15 :

skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]
[04/04 17:26:12 765s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]
[04/04 17:26:12 765s] Switching to the default view
'Arise_analysis_view_test_max_cmax_T150V08'...
[04/04 17:26:12 765s] *** Look For Reconvergent Clock Component ***
[04/04 17:26:12 765s] The clock tree clk has no reconvergent cell.
[04/04 17:26:12 765s] Reducing the latency of clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 17:26:12 765s]
[04/04 17:26:12 765s] Calculating pre-route downstream delay for clock tree
'clk'...
[04/04 17:26:12 765s] *** Look For PreservePin And Optimized CrossOver Root
Pin ***

[04/04 17:26:12 765s] MaxTriggerDelay: 411.2 (ps)

[04/04 17:26:12 765s] MinTriggerDelay: 377.5 (ps)
[04/04 17:26:12 765s] Skew: 33.7 (ps)
[04/04 17:26:12 765s] *** Finished Latency Reduction ((cpu=0:00:00.0
real=0:00:00.0 mem=1226.2M) ***
[04/04 17:26:12 765s] Reducing the skew of clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 17:26:12 765s]
[04/04 17:26:12 765s] MaxTriggerDelay: 411.2 (ps)
[04/04 17:26:12 765s] MinTriggerDelay: 377.5 (ps)
[04/04 17:26:12 765s] Skew: 33.7 (ps)
[04/04 17:26:12 765s] *** Finished Skew Reduction ((cpu=0:00:00.0
real=0:00:00.0 mem=1226.2M) ***
[04/04 17:26:12 765s] resized 0 standard cell(s).
[04/04 17:26:12 765s] inserted 0 standard cell(s).
[04/04 17:26:12 765s] deleted 0 standard cell(s).
[04/04 17:26:12 765s] moved 0 standard cell(s).
[04/04 17:26:12 765s] *** Optimized Clock Tree Latency (cpu=0:00:00.0
real=0:00:00.0 mem=1226.2M) ***
[04/04 17:26:12 765s]
[04/04 17:26:12 765s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:12 765s] ********** Clock clk Pre-Route Timing Analysis **********
[04/04 17:26:12 765s] Nr. of Subtrees

: 13

[04/04 17:26:12 765s] Nr. of Sinks

: 258

[04/04 17:26:12 765s] Nr. of Buffer

[04/04 17:26:12 765s] Nr. of Level (including gates) : 4

[04/04 17:26:12 765s] Root Rise Input Tran
[04/04 17:26:12 765s] Root Fall Input Tran
[04/04 17:26:12 765s] No Driving Cell Specified!

: 0.1(ps)
: 0.1(ps)

[04/04 17:26:12 765s] Max trig. edge delay at sink(R):

EXECUTE_INST/acc_reg[10]/state_remap/DFF/CK 411.2(ps)
[04/04 17:26:12 765s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_6_reg/state_remap/DFF/CK 377.5(ps)
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]

(Actual)

[04/04 17:26:12 765s] Rise Phase Delay

950~950(ps)

(Required)

: 377.5~411.2(ps)

[04/04 17:26:12 765s] Fall Phase Delay

950~950(ps)

: 354.9~418.3(ps)

[04/04 17:26:12 765s] Trig. Edge Skew

: 33.7(ps)

[04/04 17:26:12 765s] Rise Skew

[04/04 17:26:12 765s] Fall Skew

20(ps)

: 33.7(ps)
: 63.4(ps)

[04/04 17:26:12 765s] Max. Rise Buffer Tran.

: 90.8(ps)

200(ps)

[04/04 17:26:12 765s] Max. Fall Buffer Tran.

: 101.2(ps)

200(ps)

[04/04 17:26:12 765s] Max. Rise Sink Tran.

: 121.3(ps)

200(ps)

[04/04 17:26:12 765s] Max. Fall Sink Tran.

[04/04 17:26:12 765s] Min. Rise Buffer Tran.

: 137.1(ps)
: 21.5(ps)

200(ps)
0(ps)

[04/04 17:26:12 765s] Min. Fall Buffer Tran.

: 21.8(ps)

0(ps)

[04/04 17:26:12 765s] Min. Rise Sink Tran.

: 41.2(ps)

0(ps)

[04/04 17:26:12 765s] Min. Fall Sink Tran.

: 30.8(ps)

0(ps)

[04/04 17:26:12 765s]

[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmax_T125V108 :

skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 33.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 21.9ps (required = 20ps)

[04/04 17:26:12 765s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew

= 21.9ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 19.7ps (required = 20ps)
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]
[04/04 17:26:12 765s] Generating Clock Analysis Report
clock_report/clock.report ....
[04/04 17:26:12 765s] Clock Analysis (CPU Time 0:00:00.1)
[04/04 17:26:12 765s]
[04/04 17:26:12 765s]

[04/04 17:26:12 765s] *** ckSynthesis Opt Latency (cpu=0:00:00.4

real=0:00:01.0 mem=1226.2M) ***
[04/04 17:26:12 766s] ***** Start Refine Placement.....
[04/04 17:26:12 766s] *** Starting refinePlace (0:12:44 mem=1226.2M) ***
[04/04 17:26:12 766s] Total net length = 5.706e+04 (2.989e+04 2.717e+04)
(ext = 8.335e+03)
[04/04 17:26:12 766s] Starting refinePlace ...
[04/04 17:26:12 766s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:26:12 766s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:26:12 766s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.1,
real=0:00:00.0, mem=1226.2MB) @(0:12:44 - 0:12:44).
[04/04 17:26:12 766s] Move report: preRPlace moves 67 insts, mean move:
0.01 um, max move: 0.04 um
[04/04 17:26:12 766s] Max move on inst (EXECUTE_INST/g16510): (130.20,
123.12) --> (130.23, 123.13)
[04/04 17:26:12 766s]
cell type: AOI221X4

Length: 23 sites, height: 1 rows, site name: CoreSite,

[04/04 17:26:12 766s] wireLenOptFixPriorityInst 10 inst fixed

[04/04 17:26:12 766s] Move report: legalization moves 85 insts, mean move:
0.67 um, max move: 3.71 um
[04/04 17:26:12 766s] Max move on inst
(TDSP_CORE_GLUE_INST/lsh_120_82/g2921): (71.60, 80.37) --> (73.60, 78.66)
[04/04 17:26:12 766s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1226.2MB) @(0:12:44 - 0:12:44).
[04/04 17:26:12 766s] Move report: Detail placement moves 50 insts, mean
move: 1.13 um, max move: 3.71 um
[04/04 17:26:12 766s] Max move on inst
(TDSP_CORE_GLUE_INST/lsh_120_82/g2921): (71.60, 80.37) --> (73.60, 78.66)
[04/04 17:26:12 766s]
1226.2MB

Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM:

[04/04 17:26:12 766s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:26:12 766s] maximum (X+Y) =

3.71 um

[04/04 17:26:12 766s] inst (TDSP_CORE_GLUE_INST/lsh_120_82/g2921) with

max move: (71.6, 80.37) -> (73.6, 78.66)
[04/04 17:26:12 766s] mean

(X+Y) =

1.13 um

[04/04 17:26:12 766s] Summary Report:

[04/04 17:26:12 766s] Instances move: 50 (out of 1925 movable)
[04/04 17:26:12 766s] Mean displacement: 1.13 um
[04/04 17:26:12 766s] Max displacement: 3.71 um (Instance:
TDSP_CORE_GLUE_INST/lsh_120_82/g2921) (71.6, 80.37) -> (73.6, 78.66)
[04/04 17:26:12 766s]
cell type: AO21X4

Length: 10 sites, height: 1 rows, site name: CoreSite,

[04/04 17:26:12 766s] Total instances moved : 50

[04/04 17:26:12 766s] Total net length = 5.706e+04 (2.989e+04 2.717e+04)
(ext = 8.335e+03)
[04/04 17:26:12 766s] Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM:
1226.2MB
[04/04 17:26:12 766s] [CPU] RefinePlace/total (cpu=0:00:00.1, real=0:00:00.0,
mem=1226.2MB) @(0:12:44 - 0:12:44).
[04/04 17:26:12 766s] *** Finished refinePlace (0:12:44 mem=1226.2M) ***
[04/04 17:26:13 766s] ***** Refine Placement Finished (CPU Time: 0:00:00.4
MEM: 1226.207M)
[04/04 17:26:13 766s]
[04/04 17:26:13 766s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:13 766s] ********** Clock clk Pre-Route Timing Analysis **********
[04/04 17:26:13 766s] Nr. of Subtrees

: 13

[04/04 17:26:13 766s] Nr. of Sinks

: 258

[04/04 17:26:13 766s] Nr. of Buffer

: 10

[04/04 17:26:13 766s] Nr. of Level (including gates) : 10

[04/04 17:26:13 766s] Root Rise Input Tran
[04/04 17:26:13 766s] Root Fall Input Tran
[04/04 17:26:13 766s] No Driving Cell Specified!

: 0.1(ps)
: 0.1(ps)

[04/04 17:26:13 766s] Max trig. edge delay at sink(R):

EXECUTE_INST/acc_reg[10]/state_remap/DFF/CK 952.5(ps)
[04/04 17:26:13 766s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_6_reg/state_remap/DFF/CK 921.6(ps)
[04/04 17:26:13 766s]
[04/04 17:26:13 766s]
[04/04 17:26:13 766s]

(Actual)

[04/04 17:26:13 766s] Rise Phase Delay

950~950(ps)

(Required)

: 921.6~952.5(ps)

[04/04 17:26:13 766s] Fall Phase Delay

950~950(ps)

: 898.5~962.5(ps)

[04/04 17:26:13 766s] Trig. Edge Skew

: 30.9(ps)

[04/04 17:26:13 766s] Rise Skew

[04/04 17:26:13 766s] Fall Skew

20(ps)

: 30.9(ps)
: 64(ps)

[04/04 17:26:13 766s] Max. Rise Buffer Tran.

: 92.5(ps)

200(ps)

[04/04 17:26:13 766s] Max. Fall Buffer Tran.

: 103.3(ps)

200(ps)

[04/04 17:26:13 766s] Max. Rise Sink Tran.

: 121.3(ps)

200(ps)

[04/04 17:26:13 766s] Max. Fall Sink Tran.

[04/04 17:26:13 766s] Min. Rise Buffer Tran.

: 137.1(ps)
: 21.5(ps)

200(ps)
0(ps)

[04/04 17:26:13 766s] Min. Fall Buffer Tran.

: 21.8(ps)

0(ps)

[04/04 17:26:13 766s] Min. Rise Sink Tran.

: 41.2(ps)

0(ps)

[04/04 17:26:13 766s] Min. Fall Sink Tran.

: 30.8(ps)

0(ps)

[04/04 17:26:13 766s]

[04/04 17:26:13 766s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 30.9ps (required = 20ps)

[04/04 17:26:13 766s] view Arise_analysis_view_test_max_cmax_T125V108 :

skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 30.9ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 22ps (required = 20ps)

[04/04 17:26:13 766s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew

= 22ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 20.4ps (required = 20ps)
[04/04 17:26:13 766s]
[04/04 17:26:13 766s]
[04/04 17:26:13 766s] Clock Analysis (CPU Time 0:00:00.1)
[04/04 17:26:13 766s]
[04/04 17:26:13 766s]
[04/04 17:26:13 766s]
[04/04 17:26:13 766s] globalDetailRoute
[04/04 17:26:13 766s]

[04/04 17:26:13 766s] #setNanoRouteMode -drouteAutoStop false

[04/04 17:26:13 766s] #setNanoRouteMode -drouteEndIteration 5
[04/04 17:26:13 766s] #setNanoRouteMode -drouteStartIteration 0
[04/04 17:26:13 766s] #setNanoRouteMode -routeSelectedNetOnly true
[04/04 17:26:13 766s] #setNanoRouteMode -routeWithEco true
[04/04 17:26:13 766s] #setNanoRouteMode -routeWithTimingDriven false
[04/04 17:26:13 766s] #Start globalDetailRoute on Mon Apr 4 17:26:13 2016
[04/04 17:26:13 766s] #
[04/04 17:26:13 766s] ### Ignoring a total of 1 master slice layers:
[04/04 17:26:13 766s] ### Oxide
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[0] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[1] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[2] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[3] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[4] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[5] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[6] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[7] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[8] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[9] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[10] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.

[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[11] in CELL_VIEW

mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[12] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[13] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[14] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[15] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[16] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[17] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[18] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (NRDB-728) PIN result[19] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:26:13 766s] #WARNING (EMS-27) Message (NRDB-728) has exceeded
the current message display limit of 20.
[04/04 17:26:13 766s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 17:26:13 767s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 17:26:13 767s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:13 767s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:13 767s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.

[04/04 17:26:13 767s] #WARNING (NRIG-34) Power/Ground pin V_Core of

instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:13 767s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:13 767s] #WARNING (NRDB-976) The TRACK STEP 0.1900 for
preferred direction tracks is smaller than the PITCH 0.2000 for LAYER Metal3. This
will cause routability problems for NanoRoute.
[04/04 17:26:13 767s] #WARNING (NRDB-976) The TRACK STEP 0.1900 for
preferred direction tracks is smaller than the PITCH 0.2000 for LAYER Metal5. This
will cause routability problems for NanoRoute.
[04/04 17:26:13 767s] #NanoRoute Version v14.28-s005 NR1603131959/14_28-UB
[04/04 17:26:13 767s] #Bottom routing layer is M1, bottom routing layer for
shielding is M1, bottom shield layer is M1
[04/04 17:26:13 767s] #Start routing data preparation.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal3 is not specified for width 0.070.

[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal5 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal4 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal5 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal5 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal5 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal7 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal6 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal7 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal7 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal7 is not specified for width 0.070.

[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal9 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal8 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal9 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal1 is not specified for width 0.060.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2077) The below via enclosure for
LAYER Metal2 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (NRDB-2078) The above via enclosure for
LAYER Metal3 is not specified for width 0.070.
[04/04 17:26:13 767s] #WARNING (EMS-27) Message (NRDB-2077) has
exceeded the current message display limit of 20.
[04/04 17:26:13 767s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 17:26:13 767s] #WARNING (EMS-27) Message (NRDB-2078) has
exceeded the current message display limit of 20.
[04/04 17:26:13 767s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 17:26:13 767s] #WARNING (NRDB-812) Cuts within VIA VIA12_4C violate
adjacent cut spacing rule.

0.445

H Track-Pitch = 0.285

Line-2-Via Pitch =

[04/04 17:26:16 770s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:26:16 770s] # Metal8
0.385

V Track-Pitch = 0.200

Line-2-Via Pitch =

[04/04 17:26:16 770s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:26:16 770s] # Metal9
0.385

H Track-Pitch = 0.380

Line-2-Via Pitch =

[04/04 17:26:16 770s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:26:16 770s] #Regenerating Ggrids automatically.
[04/04 17:26:16 770s] #Auto generating G-grids with size=15 tracks, using
layer Metal2's pitch = 0.200.
[04/04 17:26:16 770s] #Using automatically generated G-grids.
[04/04 17:26:16 770s] #Done routing data preparation.
[04/04 17:26:16 770s] #cpu time = 00:00:03, elapsed time = 00:00:03,
memory = 1041.90 (MB), peak = 1407.81 (MB)
[04/04 17:26:16 770s] #Merging special wires...
[04/04 17:26:16 770s] #reading routing guides ......
[04/04 17:26:16 770s] #Number of eco nets is 0
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Start data preparation...
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Data preparation is done on Mon Apr 4 17:26:16 2016
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Analyzing routing resource...
[04/04 17:26:16 770s] #Routing resource analysis is done on Mon Apr 4
17:26:16 2016
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] # Resource Analysis:
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] # Layer
Blocked

Routing #Avail
Direction Track

379

111

4900

18.98%

[04/04 17:26:16 770s] # Metal 9

452

4900

16.12%

[04/04 17:26:16 770s] # -------------------------------------------------------------[04/04 17:26:16 770s] # Total

3222

52.59% 44100

50.28%

[04/04 17:26:16 770s] #

[04/04 17:26:16 770s] # 23 nets (0.88%) with 1 preferred extra spacing.
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Routing guide is on.
[04/04 17:26:16 770s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1042.98 (MB), peak = 1407.81 (MB)
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #start global routing iteration 1...
[04/04 17:26:16 770s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1045.19 (MB), peak = 1407.81 (MB)
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #start global routing iteration 2...
[04/04 17:26:16 770s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1045.20 (MB), peak = 1407.81 (MB)
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Total number of trivial nets (e.g. < 2 pins) = 322
(skipped).
[04/04 17:26:16 770s] #Total number of selected nets for routing = 23.
[04/04 17:26:16 770s] #Total number of unselected nets (but routable) for
routing = 2261 (skipped).

[04/04 17:26:16 770s] #Total number of nets in the design = 2606.

[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #2261 skipped nets do not have any wires.
[04/04 17:26:16 770s] #23 routable nets have only global wires.
[04/04 17:26:16 770s] #23 global routed or unrouted (routable) nets have been
constrained (e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Routed net constraints summary:
[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

Rules Pref Extra Space Unconstrained

[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

Default

[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

Total

[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

[04/04 17:26:16 770s] #Routing constraints summary of the whole design:
[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

Rules Pref Extra Space Unconstrained

[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

Default

2261

[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

Total

2261

[04/04 17:26:16 770s] #-----------------------------------------------[04/04 17:26:16 770s] #

[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] # Congestion Analysis: (blocked Gcells are excluded)
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #

OverCon

[04/04 17:26:16 770s] #

#Gcell
Layer

(1)

#Gcell

(2)

%Gcell

(3) OverCon

[04/04 17:26:16 770s] # -----------------------------------------------------------[04/04 17:26:16 770s] # Metal 1

(0.00%)

0(0.00%)

[04/04 17:26:16 770s] # Metal 2

(0.23%)

3(0.18%)

[04/04 17:26:16 770s] # The worst congested Gcell overcon (routing demand
over resource in number of tracks) = 3
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Complete Global Routing.
[04/04 17:26:16 770s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:26:16 770s] #Total wire length = 2139 um.
[04/04 17:26:16 770s] #Total half perimeter of net bounding box = 1550 um.

[04/04 17:26:16 770s] #Total wire length on LAYER Metal1 = 0 um.

[04/04 17:26:16 770s] #Total wire length on LAYER Metal2 = 32 um.
[04/04 17:26:16 770s] #Total wire length on LAYER Metal3 = 1061 um.
[04/04 17:26:16 770s] #Total wire length on LAYER Metal4 = 1005 um.
[04/04 17:26:16 770s] #Total wire length on LAYER Metal5 = 15 um.
[04/04 17:26:16 770s] #Total wire length on LAYER Metal6 = 27 um.
[04/04 17:26:16 770s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:26:16 770s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:26:16 770s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:26:16 770s] #Total number of vias = 774
[04/04 17:26:16 770s] #Up-Via Summary (total 774):
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #----------------------[04/04 17:26:16 770s] # Metal 1

305

[04/04 17:26:16 770s] # Metal 2

251

[04/04 17:26:16 770s] # Metal 3

208

[04/04 17:26:16 770s] # Metal 4

[04/04 17:26:16 770s] # Metal 5

[04/04 17:26:16 770s] #----------------------[04/04 17:26:16 770s] #

774

[04/04 17:26:16 770s] #

[04/04 17:26:16 770s] #Max overcon = 3 tracks.
[04/04 17:26:16 770s] #Total overcon = 0.02%.
[04/04 17:26:16 770s] #Worst layer Gcell overcon rate = 0.00%.
[04/04 17:26:16 770s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1045.30 (MB), peak = 1407.81 (MB)
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #Start data preparation for track assignment...

[04/04 17:26:16 770s] #

[04/04 17:26:16 770s] #Data preparation is done on Mon Apr 4 17:26:16 2016
[04/04 17:26:16 770s] #
[04/04 17:26:16 770s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1045.31 (MB), peak = 1407.81 (MB)
[04/04 17:26:16 770s] #Start Track Assignment.
[04/04 17:26:17 770s] #Done with 182 horizontal wires in 1 hboxes and 160
vertical wires in 1 hboxes.
[04/04 17:26:17 770s] #Done with 7 horizontal wires in 1 hboxes and 7 vertical
wires in 1 hboxes.
[04/04 17:26:17 770s] #Complete Track Assignment.
[04/04 17:26:17 770s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:26:17 770s] #Total wire length = 2131 um.
[04/04 17:26:17 770s] #Total half perimeter of net bounding box = 1550 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal1 = 0 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal2 = 28 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal3 = 1058 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal4 = 1005 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal5 = 13 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal6 = 27 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:26:17 770s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:26:17 770s] #Total number of vias = 774
[04/04 17:26:17 770s] #Up-Via Summary (total 774):
[04/04 17:26:17 770s] #
[04/04 17:26:17 770s] #----------------------[04/04 17:26:17 770s] # Metal 1

305

[04/04 17:26:17 770s] # Metal 2

251

[04/04 17:26:17 770s] # Metal 3

208

[04/04 17:26:17 770s] # Metal 4

[04/04 17:26:17 770s] # Metal 5

[04/04 17:26:17 770s] #----------------------[04/04 17:26:17 770s] #

774

[04/04 17:26:17 770s] #

[04/04 17:26:17 770s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1010.97 (MB), peak = 1407.81 (MB)
[04/04 17:26:17 770s] #
[04/04 17:26:17 770s] #Cpu time = 00:00:03
[04/04 17:26:17 770s] #Elapsed time = 00:00:04
[04/04 17:26:17 770s] #Increased memory = 11.90 (MB)
[04/04 17:26:17 770s] #Total memory = 1010.97 (MB)
[04/04 17:26:17 770s] #Peak memory = 1407.81 (MB)
[04/04 17:26:18 771s] #
[04/04 17:26:18 771s] #Start Detail Routing..
[04/04 17:26:18 771s] #start initial detail routing ...
[04/04 17:26:21 774s] # ECO: 4.2% of the total area was rechecked for DRC,
and 32.6% required routing.
[04/04 17:26:21 774s] #

number of violations = 0

[04/04 17:26:21 774s] #cpu time = 00:00:03, elapsed time = 00:00:03,

memory = 1079.80 (MB), peak = 1407.81 (MB)
[04/04 17:26:21 774s] #start 1st optimization iteration ...
[04/04 17:26:21 774s] #

number of violations = 0

[04/04 17:26:21 774s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1080.06 (MB), peak = 1407.81 (MB)
[04/04 17:26:21 774s] #Complete Detail Routing.
[04/04 17:26:21 774s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:26:21 774s] #Total wire length = 2150 um.

[04/04 17:26:21 774s] #Total half perimeter of net bounding box = 1550 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal1 = 14 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal2 = 95 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal3 = 989 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal4 = 1052 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal5 = 0 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:26:21 774s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:26:21 774s] #Total number of vias = 891
[04/04 17:26:21 774s] #Up-Via Summary (total 891):
[04/04 17:26:21 774s] #
[04/04 17:26:21 774s] #----------------------[04/04 17:26:21 774s] # Metal 1

309

[04/04 17:26:21 774s] # Metal 2

266

[04/04 17:26:21 774s] # Metal 3

316

[04/04 17:26:21 774s] #----------------------[04/04 17:26:21 774s] #

891

[04/04 17:26:21 774s] #

[04/04 17:26:21 774s] #Total number of DRC violations = 0
[04/04 17:26:21 774s] #Cpu time = 00:00:04
[04/04 17:26:21 774s] #Elapsed time = 00:00:04
[04/04 17:26:21 774s] #Increased memory = 69.09 (MB)
[04/04 17:26:21 774s] #Total memory = 1080.06 (MB)
[04/04 17:26:21 774s] #Peak memory = 1407.81 (MB)
[04/04 17:26:21 774s] #detailRoute Statistics:
[04/04 17:26:21 774s] #Cpu time = 00:00:04

[04/04 17:26:21 774s] #Elapsed time = 00:00:04

[04/04 17:26:21 774s] #Increased memory = 69.09 (MB)
[04/04 17:26:21 774s] #Total memory = 1080.06 (MB)
[04/04 17:26:21 774s] #Peak memory = 1407.81 (MB)
[04/04 17:26:21 774s] #
[04/04 17:26:21 774s] #globalDetailRoute statistics:
[04/04 17:26:21 774s] #Cpu time = 00:00:08
[04/04 17:26:21 774s] #Elapsed time = 00:00:08
[04/04 17:26:21 774s] #Increased memory = 75.45 (MB)
[04/04 17:26:21 774s] #Total memory = 1080.06 (MB)
[04/04 17:26:21 774s] #Peak memory = 1407.81 (MB)
[04/04 17:26:21 774s] #Number of warnings = 78
[04/04 17:26:21 774s] #Total number of warnings = 234
[04/04 17:26:21 774s] #Number of fails = 0
[04/04 17:26:21 774s] #Total number of fails = 0
[04/04 17:26:21 774s] #Complete globalDetailRoute on Mon Apr 4 17:26:21
2016
[04/04 17:26:21 774s] #
[04/04 17:26:21 774s] *** Look For Un-Routed Clock Tree Net ***
[04/04 17:26:21 774s]
[04/04 17:26:21 774s] Routing correlation check
[04/04 17:26:21 774s]
================================================
============
[04/04 17:26:21 774s]
[04/04 17:26:21 774s] Min length threshold value is :: 40 microns
[04/04 17:26:21 774s]
[04/04 17:26:21 774s] Allowed deviation from route guide is 50%
[04/04 17:26:21 774s]

[04/04 17:26:21 774s]

[04/04 17:26:21 774s] Routing correlation check finished, CPU=0:00:00.0
[04/04 17:26:21 774s]
================================================
============
[04/04 17:26:21 774s]
[04/04 17:26:21 774s] Wire resistance checks
[04/04 17:26:21 774s]
================================================
============
[04/04 17:26:21 774s] Calculating clock delays in preRoute mode...
[04/04 17:26:21 774s] Calculating clock delays in clkRouteOnly mode...
[04/04 17:26:21 774s] Updating RC grid for preRoute extraction ...
[04/04 17:26:21 774s] Initializing multi-corner capacitance tables ...
[04/04 17:26:21 774s] Initializing multi-corner resistance tables ...
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11922 has 53.7195 percent resistance deviation between
preRoute resistance (109.534 ohm) and after route resistance (236.673 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
PORT_BUS_MACH_INST/rc_gclk has 49.9286 percent resistance deviation between
preRoute resistance (175.736 ohm) and after route resistance (350.97 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
DATA_BUS_MACH_INST/rc_gclk has 46.2272 percent resistance deviation between
preRoute resistance (180.456 ohm) and after route resistance (335.589 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11916 has 44.3716 percent resistance deviation between
preRoute resistance (239.198 ohm) and after route resistance (429.993 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk has 43.8166 percent resistance deviation between
preRoute resistance (491.338 ohm) and after route resistance (874.526 ohm)
values. This may indicate correlation issues like jogging in routing for this net.

[04/04 17:26:21 774s] **WARN: (ENCCK-6350):

Clock net
DECODE_INST/rc_gclk has 42.1873 percent resistance deviation between
preRoute resistance (455.549 ohm) and after route resistance (787.973 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11913 has 41.8411 percent resistance deviation between
preRoute resistance (221.061 ohm) and after route resistance (380.098 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
PROG_BUS_MACH_INST/rc_gclk has 40.8929 percent resistance deviation
between preRoute resistance (194.036 ohm) and after route resistance (328.279
ohm) values. This may indicate correlation issues like jogging in routing for this
net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11919 has 40.7613 percent resistance deviation between
preRoute resistance (427.065 ohm) and after route resistance (720.922 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
EXECUTE_INST/rc_gclk_11928 has 40.3172 percent resistance deviation between
preRoute resistance (209.387 ohm) and after route resistance (350.833 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net clk__L4_N0 has
40.3007 percent resistance deviation between preRoute resistance (654.324
ohm) and after route resistance (1096.03 ohm) values. This may indicate
correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s] **WARN: (ENCCK-6350):
Clock net
clk__L1_N0__CASCADE_L7_N0 has 22.0193 percent resistance deviation between
preRoute resistance (426.664 ohm) and after route resistance (547.141 ohm)
values. This may indicate correlation issues like jogging in routing for this net.
[04/04 17:26:21 774s]
[04/04 17:26:21 774s] Wire resistance checks Finished, CPU=0:00:00.1
[04/04 17:26:21 774s]
================================================
============
[04/04 17:26:21 775s]
[04/04 17:26:21 775s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:21 775s] ********** Clock clk Clk-Route-Only Timing Analysis
**********

[04/04 17:26:21 775s] Nr. of Subtrees

: 13

[04/04 17:26:21 775s] Nr. of Sinks

: 258

[04/04 17:26:21 775s] Nr. of Buffer

: 10

[04/04 17:26:21 775s] Nr. of Level (including gates) : 10

[04/04 17:26:21 775s] Root Rise Input Tran

: 0.1(ps)

[04/04 17:26:21 775s] Root Fall Input Tran

: 0.1(ps)

[04/04 17:26:21 775s] No Driving Cell Specified!

[04/04 17:26:21 775s] Max trig. edge delay at sink(R):
EXECUTE_INST/acc_reg[10]/state_remap/DFF/CK 957.9(ps)
[04/04 17:26:21 775s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 926.8(ps)
[04/04 17:26:21 775s]
[04/04 17:26:21 775s]
[04/04 17:26:21 775s]

(Actual)

[04/04 17:26:21 775s] Rise Phase Delay

950~950(ps)

(Required)

: 926.8~957.9(ps)

[04/04 17:26:21 775s] Fall Phase Delay

950~950(ps)

: 904.3~970(ps)

[04/04 17:26:21 775s] Trig. Edge Skew

: 31.1(ps)

[04/04 17:26:21 775s] Rise Skew

[04/04 17:26:21 775s] Fall Skew

20(ps)

: 31.1(ps)
: 65.7(ps)

[04/04 17:26:21 775s] Max. Rise Buffer Tran.

: 94.7(ps)

200(ps)

[04/04 17:26:21 775s] Max. Fall Buffer Tran.

: 105.2(ps)

200(ps)

[04/04 17:26:21 775s] Max. Rise Sink Tran.

: 123.1(ps)

200(ps)

[04/04 17:26:21 775s] Max. Fall Sink Tran.

[04/04 17:26:21 775s] Min. Rise Buffer Tran.

: 139.1(ps)
: 21.4(ps)

200(ps)
0(ps)

[04/04 17:26:21 775s] Min. Fall Buffer Tran.

: 21.7(ps)

0(ps)

[04/04 17:26:21 775s] Min. Rise Sink Tran.

: 41.2(ps)

0(ps)

[04/04 17:26:21 775s] Min. Fall Sink Tran.

[04/04 17:26:21 775s]

: 30.7(ps)

0(ps)

[04/04 17:26:21 775s] view Arise_analysis_view_test_max_cmax_T150V08 :

skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 23.2ps (required = 20ps)

[04/04 17:26:21 775s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew

= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:21 775s]

[04/04 17:26:21 775s]

[04/04 17:26:21 775s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 17:26:21 775s]
[04/04 17:26:21 775s]
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_max_cmax_T150V08'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_max_cmax_T150V08'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_max_cmax_T140V102'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_max_cmax_T125V108'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_max_cmax_T125V108'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_nom_cmax_T25V12'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_nom_cmax_T50V13'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_nom_cmax_T25V12'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_nom_cmax_T50V13'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_nom_cmax_T15V11'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_nom_cmax_T15V11'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_max_cmin_T150V08'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_max_cmin_T150V08'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_max_cmin_T140V102'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_max_cmin_T140V102'...

[04/04 17:26:21 775s] setting up for view

'Arise_analysis_view_func_max_cmin_T125V108'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_max_cmin_T125V108'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_nom_cmin_T25V12'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_nom_cmin_T25V12'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_nom_cmin_T20V13'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_nom_cmin_T20V13'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_nom_cmin_T15V11'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_nom_cmin_T15V11'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_min_cmin_T0V132'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_min_cmin_T0V132'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_min_cmin_Tm20V15'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_min_cmin_Tm20V15'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_min_cmin_Tm40V18'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_min_cmin_Tm40V18'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_min_cmax_T0V132'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_min_cmax_T0V132'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm20V15'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm40V15'...

[04/04 17:26:21 775s] setting up for view

'Arise_analysis_view_test_min_cmax_Tm40V15'...
[04/04 17:26:21 775s] setting up for view
'Arise_analysis_view_test_min_cmax_Tm20V15'...
[04/04 17:26:21 775s] View 'Arise_analysis_view_func_max_cmax_T150V08' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_max_cmax_T125V108' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_nom_cmax_T25V12' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_nom_cmax_T50V13' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_nom_cmax_T15V11' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_max_cmin_T150V08' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_max_cmin_T140V102' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_max_cmin_T125V108' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_nom_cmin_T25V12' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_nom_cmin_T20V13' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_nom_cmin_T15V11' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_min_cmin_T0V132' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_min_cmin_Tm20V15' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_min_cmin_Tm40V18' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_test_min_cmax_T0V132' in
clock tree 'clk' is redundant
[04/04 17:26:21 775s] View 'Arise_analysis_view_func_min_cmax_Tm40V15' in
clock tree 'clk' is redundant

[04/04 17:26:21 775s] View 'Arise_analysis_view_test_min_cmax_Tm20V15' in

clock tree 'clk' is redundant
[04/04 17:26:21 775s] Selecting the worst MMMC view of clock tree 'clk' ...
[04/04 17:26:21 775s] Optimizing clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 17:26:21 775s]
[04/04 17:26:21 775s] Calculating clk-route-only downstream delay for clock
tree 'clk' ...
[04/04 17:26:21 775s] *** Look For Reconvergent Clock Component ***
[04/04 17:26:21 775s] The clock tree clk has no reconvergent cell.
[04/04 17:26:21 775s] *** Look For PreservePin And Optimized CrossOver Root
Pin ***
[04/04 17:26:21 775s] resized 0 standard cell(s).
[04/04 17:26:21 775s] inserted 0 standard cell(s).
[04/04 17:26:21 775s] *** Gated Clock Tree Optimization (cpu=0:00:00.1
real=0:00:00.0 mem=1287.1M) ***
[04/04 17:26:21 775s] *** Finished Clock Tree Skew Optimization
(cpu=0:00:00.1 real=0:00:00.0 mem=1287.1M) ***
[04/04 17:26:21 775s]
[04/04 17:26:21 775s] None of the clock tree buffers/gates are modified by the
skew optimization.
[04/04 17:26:21 775s]
[04/04 17:26:21 775s] Switching to the default view
'Arise_analysis_view_test_max_cmax_T150V08' ...
[04/04 17:26:21 775s] Tuning the min phase delay of clock tree 'clk' ...
[04/04 17:26:21 775s]
[04/04 17:26:21 775s] Calculating clk-route-only downstream delay for clock
tree 'clk' ...
[04/04 17:26:22 775s] resized 0 standard cell(s).
[04/04 17:26:22 775s] inserted 0 standard cell(s).
[04/04 17:26:22 775s] *** Tuned Min Phase Delay (cpu=0:00:00.1
mem=1287.1M) ***

[04/04 17:26:22 775s]

[04/04 17:26:22 775s] *** None of the buffer chains at roots are modified by the
fine-tune process.
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]
[04/04 17:26:22 775s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:22 775s] ********** Clock clk Clk-Route-Only Timing Analysis
**********
[04/04 17:26:22 775s] Nr. of Subtrees

: 13

[04/04 17:26:22 775s] Nr. of Sinks

: 258

[04/04 17:26:22 775s] Nr. of Buffer

: 10

[04/04 17:26:22 775s] Nr. of Level (including gates) : 10

[04/04 17:26:22 775s] Root Rise Input Tran

: 0.1(ps)

[04/04 17:26:22 775s] Root Fall Input Tran

: 0.1(ps)

[04/04 17:26:22 775s] No Driving Cell Specified!

[04/04 17:26:22 775s] Max trig. edge delay at sink(R):
EXECUTE_INST/acc_reg[10]/state_remap/DFF/CK 957.9(ps)
[04/04 17:26:22 775s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 926.8(ps)
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]

(Actual)

[04/04 17:26:22 775s] Rise Phase Delay

950~950(ps)

(Required)

: 926.8~957.9(ps)

[04/04 17:26:22 775s] Fall Phase Delay

950~950(ps)

: 904.3~970(ps)

[04/04 17:26:22 775s] Trig. Edge Skew

: 31.1(ps)

[04/04 17:26:22 775s] Rise Skew

[04/04 17:26:22 775s] Fall Skew
[04/04 17:26:22 775s] Max. Rise Buffer Tran.

20(ps)

: 31.1(ps)
: 65.7(ps)
: 94.7(ps)

200(ps)

[04/04 17:26:22 775s] Max. Fall Buffer Tran.

: 105.2(ps)

200(ps)

[04/04 17:26:22 775s] Max. Rise Sink Tran.

: 123.1(ps)

200(ps)

[04/04 17:26:22 775s] Max. Fall Sink Tran.

[04/04 17:26:22 775s] Min. Rise Buffer Tran.

: 139.1(ps)
: 21.4(ps)

200(ps)
0(ps)

[04/04 17:26:22 775s] Min. Fall Buffer Tran.

: 21.7(ps)

0(ps)

[04/04 17:26:22 775s] Min. Rise Sink Tran.

: 41.2(ps)

0(ps)

[04/04 17:26:22 775s] Min. Fall Sink Tran.

: 30.7(ps)

0(ps)

[04/04 17:26:22 775s]

[04/04 17:26:22 775s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 31.1ps (required = 20ps)

[04/04 17:26:22 775s] view Arise_analysis_view_func_max_cmin_T140V102 :

skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 31.1ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 23.2ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 21.4ps (required = 20ps)

[04/04 17:26:22 775s] view Arise_analysis_view_func_min_cmax_Tm20V15 :

skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 21.4ps (required = 20ps)
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]
[04/04 17:26:22 775s] Clock clk has been routed. Routing guide will not be
generated.
[04/04 17:26:22 775s] Generating Clock Analysis Report
clock_report/clock.report ....
[04/04 17:26:22 775s] Generating Clock Routing Guide tdsp_core.rguide ....
[04/04 17:26:22 775s] Clock Analysis (CPU Time 0:00:00.2)
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]
[04/04 17:26:22 775s] Clock gating checks
[04/04 17:26:22 775s]
================================================
============
[04/04 17:26:22 775s]
[04/04 17:26:22 775s] Clock gating Checks Finished, CPU=0:00:00.0
[04/04 17:26:22 775s]
================================================
============
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]
################################################
#############################
[04/04 17:26:22 775s] #

[04/04 17:26:22 775s] # Summary of During-Synthesis Checks

[04/04 17:26:22 775s] #
[04/04 17:26:22 775s]
################################################
#############################
[04/04 17:26:22 775s]
[04/04 17:26:22 775s]
[04/04 17:26:22 775s] Types of Check
warnings

Number of

[04/04 17:26:22 775s] ---------------------------------------------------------------------------[04/04 17:26:22 775s]

[04/04 17:26:22 775s] Check RefinePlacement move distance

[04/04 17:26:22 775s] Check route layer follows preference

[04/04 17:26:22 775s] Check route follows guide

[04/04 17:26:22 775s] clock gating checks

[04/04 17:26:22 775s] Wire resistance checks

0
0

[04/04 17:26:22 775s]

[04/04 17:26:22 776s] *** End ckSynthesis (cpu=0:00:13.6, real=0:00:13.0,
mem=1287.1M) ***
[04/04 17:26:22 776s] <clockDesign CMD> specifyClockTree -update
{AutoCTSRootPin * PostOpt YES}
[04/04 17:26:22 776s] <clockDesign CMD> ckECO -postCTS
-useSpecFileCellsOnly -report clock_report/clock.postCTS.report
[04/04 17:26:22 776s] Redoing specifyClockTree ...
[04/04 17:26:22 776s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:26:22 776s] Checking spec file integrity...

[04/04 17:26:22 776s] List of dont use cells: HOLDX1
[04/04 17:26:22 776s] List of dont touch cells:
[04/04 17:26:22 776s] List of valid cells: BUFX2 BUFX3 BUFX4 BUFX6 BUFX8
[04/04 17:26:22 776s] ***** Doing trialRoute -handlePreroute.

[04/04 17:26:22 776s]

[04/04 17:26:22 776s] *** Starting trialRoute (mem=1287.1M) ***
[04/04 17:26:22 776s]
[04/04 17:26:22 776s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:26:22 776s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:26:22 776s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:26:22 776s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:26:22 776s]
[04/04 17:26:22 776s] Nr of prerouted/Fixed nets = 23
[04/04 17:26:22 776s] There are 23 nets with 1 extra space.
[04/04 17:26:22 776s] routingBox: (-200 -330) (210200 207240)
[04/04 17:26:22 776s] coreBox:

(0 0) (210000 206910)

[04/04 17:26:22 776s] There are 23 prerouted nets with extraSpace.

[04/04 17:26:22 776s] Number of multi-gpin terms=2387, multi-gpins=5648,
moved blk term=63/63
[04/04 17:26:22 776s]
[04/04 17:26:22 776s] Phase 1a route (0:00:00.0 1287.1M):
[04/04 17:26:22 776s] Est net length = 6.248e+04um = 3.226e+04H +
3.022e+04V
[04/04 17:26:22 776s] Usage: (11.1%H 13.4%V) = (3.888e+04um
4.703e+04um) = (38881 27493)
[04/04 17:26:22 776s] Obstruct: 8394 = 4197 (16.5%H) + 4197 (16.5%V)
[04/04 17:26:22 776s] Overflow: 51 = 14 (0.07% H) + 36 (0.17% V)
[04/04 17:26:22 776s]
[04/04 17:26:23 776s] Phase 1b route (0:00:00.0 1287.1M):
[04/04 17:26:23 776s] Usage: (11.0%H 13.4%V) = (3.879e+04um
4.702e+04um) = (38784 27487)
[04/04 17:26:23 776s] Overflow: 36 = 0 (0.00% H) + 36 (0.17% V)

[04/04 17:26:23 776s]

[04/04 17:26:23 776s] Phase 1c route (0:00:00.0 1287.1M):
[04/04 17:26:23 776s] Usage: (11.0%H 13.4%V) = (3.874e+04um
4.700e+04um) = (38735 27474)
[04/04 17:26:23 776s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Phase 1d route (0:00:00.0 1287.1M):
[04/04 17:26:23 776s] Usage: (11.0%H 13.4%V) = (3.874e+04um
4.700e+04um) = (38735 27474)
[04/04 17:26:23 776s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Phase 1a-1d Overflow: 0.00% H + 0.01% V (0:00:00.1
1287.1M)

[04/04 17:26:23 776s]

[04/04 17:26:23 776s] Phase 1e route (0:00:00.0 1287.1M):
[04/04 17:26:23 776s] Usage: (11.0%H 13.4%V) = (3.874e+04um
4.700e+04um) = (38735 27474)
[04/04 17:26:23 776s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Overflow: 0.00% H + 0.01% V (0:00:00.0 1287.1M)

[04/04 17:26:23 776s] Usage: (11.0%H 13.4%V) = (3.874e+04um

4.700e+04um) = (38735 27474)
[04/04 17:26:23 776s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Congestion distribution:
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Remain cntH

0.02%

1007

4.75%

[04/04 17:26:23 776s] 5:

2120799.97%

2010494.77%

[04/04 17:26:23 776s]

[04/04 17:26:23 776s] Global route (cpu=0.1s real=0.1s 1287.1M)
[04/04 17:26:23 776s] Updating RC grid for preRoute extraction ...
[04/04 17:26:23 776s] Initializing multi-corner capacitance tables ...
[04/04 17:26:23 776s] Initializing multi-corner resistance tables ...
[04/04 17:26:23 776s] There are 23 prerouted nets with extraSpace.
[04/04 17:26:23 776s]
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] *** After '-updateRemainTrks' operation:
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Usage: (11.3%H 14.0%V) = (3.975e+04um
4.931e+04um) = (39742 28823)
[04/04 17:26:23 776s] Overflow: 12 = 0 (0.00% H) + 12 (0.06% V)
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Phase 1l Overflow: 0.00% H + 0.06% V (0:00:00.3
1287.1M)

[04/04 17:26:23 776s]

[04/04 17:26:23 776s] Congestion distribution:
[04/04 17:26:23 776s]
[04/04 17:26:23 776s] Remain cntH

cntV

0.01%

114

0.54%

[04/04 17:26:23 776s] 4:

0.02%

1040

4.90%

[04/04 17:26:23 776s] 5:

: 1.00000

[04/04 17:26:23 777s] PreRoute extraction is honoring

NDR/Shielding/ExtraSpace for clock nets.
[04/04 17:26:23 777s] Using capacitance table file ...
[04/04 17:26:23 777s] Updating RC grid for preRoute extraction ...

[04/04 17:26:23 777s] Initializing multi-corner capacitance tables ...

[04/04 17:26:23 777s] Initializing multi-corner resistance tables ...
[04/04 17:26:23 777s] PreRoute RC Extraction DONE (CPU Time: 0:00:00.1 Real
Time: 0:00:00.0 MEM: 1287.082M)
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_max_cmax_T150V08'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_max_cmax_T150V08'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_max_cmax_T140V102'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_max_cmax_T125V108'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_max_cmax_T125V108'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_nom_cmax_T25V12'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_nom_cmax_T50V13'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_nom_cmax_T25V12'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_nom_cmax_T50V13'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_nom_cmax_T15V11'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_nom_cmax_T15V11'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_max_cmin_T150V08'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_max_cmin_T150V08'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_max_cmin_T140V102'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_max_cmin_T140V102'...

[04/04 17:26:23 777s] setting up for view

'Arise_analysis_view_func_max_cmin_T125V108'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_max_cmin_T125V108'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_nom_cmin_T25V12'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_nom_cmin_T25V12'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_nom_cmin_T20V13'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_nom_cmin_T20V13'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_nom_cmin_T15V11'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_nom_cmin_T15V11'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_min_cmin_T0V132'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_min_cmin_T0V132'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_min_cmin_Tm20V15'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_min_cmin_Tm20V15'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_min_cmin_Tm40V18'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_min_cmin_Tm40V18'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_min_cmax_T0V132'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_min_cmax_T0V132'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm20V15'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_func_min_cmax_Tm40V15'...

[04/04 17:26:23 777s] setting up for view

'Arise_analysis_view_test_min_cmax_Tm40V15'...
[04/04 17:26:23 777s] setting up for view
'Arise_analysis_view_test_min_cmax_Tm20V15'...
[04/04 17:26:23 777s] View 'Arise_analysis_view_func_max_cmax_T150V08' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_max_cmax_T125V108' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_nom_cmax_T25V12' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_nom_cmax_T50V13' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_nom_cmax_T15V11' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_max_cmin_T150V08' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_max_cmin_T140V102' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_max_cmin_T125V108' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_nom_cmin_T25V12' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_nom_cmin_T20V13' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_nom_cmin_T15V11' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_min_cmin_T0V132' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_min_cmin_Tm20V15' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_min_cmin_Tm40V18' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_test_min_cmax_T0V132' in
clock tree 'clk' is redundant
[04/04 17:26:23 777s] View 'Arise_analysis_view_func_min_cmax_Tm40V15' in
clock tree 'clk' is redundant

[04/04 17:26:23 777s] View 'Arise_analysis_view_test_min_cmax_Tm20V15' in

clock tree 'clk' is redundant
[04/04 17:26:24 777s]
[04/04 17:26:24 777s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:24 777s] ********** Clock clk Post-CTS Timing Analysis **********
[04/04 17:26:24 777s] Nr. of Subtrees

: 13

[04/04 17:26:24 777s] Nr. of Sinks

: 258

[04/04 17:26:24 777s] Nr. of Buffer

: 10

[04/04 17:26:24 777s] Nr. of Level (including gates) : 10

[04/04 17:26:24 777s] Root Rise Input Tran

: 0.1(ps)

[04/04 17:26:24 777s] Root Fall Input Tran

: 0.1(ps)

[04/04 17:26:24 777s] No Driving Cell Specified!

[04/04 17:26:24 777s] Max trig. edge delay at sink(R):
EXECUTE_INST/alu_cmd_reg[0]/state_remap/DFF/CK 985.1(ps)
[04/04 17:26:24 777s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 947.7(ps)
[04/04 17:26:24 777s]
[04/04 17:26:24 777s]
[04/04 17:26:24 777s]

(Actual)

(Required)

[04/04 17:26:24 777s] Rise Phase Delay

950~950(ps)

: 947.7~985.1(ps)

[04/04 17:26:24 777s] Fall Phase Delay

950~950(ps)

: 927.4~1001.2(ps)

[04/04 17:26:24 777s] Trig. Edge Skew

: 37.4(ps)

[04/04 17:26:24 777s] Rise Skew

[04/04 17:26:24 777s] Fall Skew
[04/04 17:26:24 777s] Max. Rise Buffer Tran.

20(ps)

[04/04 17:26:24 777s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 37.4ps (required = 20ps)

[04/04 17:26:24 777s] view Arise_analysis_view_test_max_cmin_T140V102 :

skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 37.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 26.4ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 23.7ps (required = 20ps)

[04/04 17:26:24 777s] view Arise_analysis_view_func_min_cmax_Tm40V15 :

skew = 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 23.7ps (required = 20ps)
[04/04 17:26:24 777s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 23.7ps (required = 20ps)
[04/04 17:26:24 777s]
[04/04 17:26:24 777s]
[04/04 17:26:24 777s] Clock Analysis (CPU Time 0:00:00.4)
[04/04 17:26:24 777s]
[04/04 17:26:24 777s]
[04/04 17:26:24 777s] Switching to the default view
'Arise_analysis_view_test_max_cmax_T150V08' ...
[04/04 17:26:24 777s] *** Finished Rebuilding Buffer Chain (cpu=0:00:00.0
real=0:00:00.0 mem=1287.1M) ***
[04/04 17:26:24 777s]
[04/04 17:26:24 777s] *** None of the buffer chains at roots are modified by the
re-build process.
[04/04 17:26:24 777s]
[04/04 17:26:24 777s] Selecting the worst MMMC view of clock tree 'clk' ...
[04/04 17:26:24 778s] Optimizing clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...
[04/04 17:26:24 778s]
[04/04 17:26:24 778s] Calculating post-route downstream delay for clock tree
'clk' ...
[04/04 17:26:24 778s] *** Look For Reconvergent Clock Component ***
[04/04 17:26:24 778s] The clock tree clk has no reconvergent cell.
[04/04 17:26:24 778s] *** Look For PreservePin And Optimized CrossOver Root
Pin ***
[04/04 17:26:24 778s] Selecting the worst MMMC view of clock tree 'clk' ...
[04/04 17:26:24 778s] Optimizing clock tree 'clk' in
'Arise_analysis_view_test_max_cmax_T150V08' view ...

[04/04 17:26:24 778s]

[04/04 17:26:24 778s] Calculating post-route downstream delay for clock tree
'clk' ...
[04/04 17:26:25 778s] Resized (BUFX2->BUFX3): clk__L3_I0
[04/04 17:26:25 778s] resized 1 standard cell(s).
[04/04 17:26:25 778s] inserted 0 standard cell(s).
[04/04 17:26:25 778s] *** Gated Clock Tree Optimization (cpu=0:00:00.5
real=0:00:01.0 mem=1287.1M) ***
[04/04 17:26:25 778s] *** Finished Clock Tree Skew Optimization
(cpu=0:00:00.5 real=0:00:01.0 mem=1287.1M) ***
[04/04 17:26:25 778s] Doing the final refine placement ...
[04/04 17:26:25 778s] ***** Start Refine Placement.....
[04/04 17:26:25 778s] *** Starting refinePlace (0:12:57 mem=1287.1M) ***
[04/04 17:26:25 778s] Total net length = 5.776e+04 (3.001e+04 2.775e+04)
(ext = 8.376e+03)
[04/04 17:26:25 778s] Starting refinePlace ...
[04/04 17:26:25 778s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:26:25 778s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:26:25 778s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.1,
real=0:00:00.0, mem=1287.1MB) @(0:12:57 - 0:12:57).
[04/04 17:26:25 778s] Move report: preRPlace moves 320 insts, mean move:
0.02 um, max move: 0.14 um
[04/04 17:26:25 778s] Max move on inst (TDSP_CORE_GLUE_INST/g8440):
(97.60, 54.72) --> (97.47, 54.72)
[04/04 17:26:25 778s]
cell type: AO21X4

Length: 10 sites, height: 1 rows, site name: CoreSite,

[04/04 17:26:25 778s] wireLenOptFixPriorityInst 280 inst fixed

[04/04 17:26:25 778s] Move report: legalization moves 432 insts, mean move:
1.07 um, max move: 6.84 um
[04/04 17:26:25 778s] Max move on inst (TDSP_CORE_GLUE_INST/g8370):
(113.00, 70.11) --> (113.00, 76.95)

[04/04 17:26:25 778s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,

real=0:00:00.0, mem=1287.1MB) @(0:12:57 - 0:12:57).
[04/04 17:26:25 778s] Move report: Detail placement moves 298 insts, mean
move: 1.55 um, max move: 6.84 um
[04/04 17:26:25 778s] Max move on inst (TDSP_CORE_GLUE_INST/g8370):
(113.00, 70.11) --> (113.00, 76.95)
[04/04 17:26:25 778s]
1287.1MB

Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM:

[04/04 17:26:25 778s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:26:25 778s] maximum (X+Y) =

6.84 um

[04/04 17:26:25 778s] inst (TDSP_CORE_GLUE_INST/g8370) with max move:

(113, 70.11) -> (113, 76.95)
[04/04 17:26:25 778s] mean

(X+Y) =

1.55 um

[04/04 17:26:25 778s] Summary Report:

[04/04 17:26:25 778s] Instances move: 298 (out of 2195 movable)
[04/04 17:26:25 778s] Mean displacement: 1.55 um
[04/04 17:26:25 778s] Max displacement: 6.84 um (Instance:
TDSP_CORE_GLUE_INST/g8370) (113, 70.11) -> (113, 76.95)
[04/04 17:26:25 778s]
cell type: AOI221X4

Length: 23 sites, height: 1 rows, site name: CoreSite,

[04/04 17:26:25 778s] Total instances moved : 298

[04/04 17:26:25 778s] Total net length = 5.776e+04 (3.001e+04 2.775e+04)
(ext = 8.376e+03)
[04/04 17:26:25 778s] Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM:
1287.1MB
[04/04 17:26:25 778s] [CPU] RefinePlace/total (cpu=0:00:00.1, real=0:00:00.0,
mem=1287.1MB) @(0:12:57 - 0:12:57).
[04/04 17:26:25 778s] *** Finished refinePlace (0:12:57 mem=1287.1M) ***
[04/04 17:26:25 778s] ***** Refine Placement Finished (CPU Time: 0:00:00.4
MEM: 1287.082M)
[04/04 17:26:25 778s]
[04/04 17:26:25 778s] globalDetailRoute

[04/04 17:26:25 778s]

[04/04 17:26:25 778s] #setNanoRouteMode -drouteStartIteration 0
[04/04 17:26:25 778s] #setNanoRouteMode -routeSelectedNetOnly true
[04/04 17:26:25 778s] #setNanoRouteMode -routeWithEco true
[04/04 17:26:25 778s] #Start globalDetailRoute on Mon Apr 4 17:26:25 2016
[04/04 17:26:25 778s] #
[04/04 17:26:25 778s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 17:26:25 778s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:25 778s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:25 778s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 17:26:25 778s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:25 778s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:26:25 779s] #WARNING (NRDB-976) The TRACK STEP 0.1900 for
preferred direction tracks is smaller than the PITCH 0.2000 for LAYER Metal3. This
will cause routability problems for NanoRoute.
[04/04 17:26:25 779s] #WARNING (NRDB-976) The TRACK STEP 0.1900 for
preferred direction tracks is smaller than the PITCH 0.2000 for LAYER Metal5. This
will cause routability problems for NanoRoute.
[04/04 17:26:25 779s] #NanoRoute Version v14.28-s005 NR1603131959/14_28-UB

0.445

H Track-Pitch = 0.285

Line-2-Via Pitch =

[04/04 17:26:25 779s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:26:25 779s] # Metal8
0.385

V Track-Pitch = 0.200

Line-2-Via Pitch =

[04/04 17:26:25 779s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:26:25 779s] # Metal9
0.385

H Track-Pitch = 0.380

Line-2-Via Pitch =

[04/04 17:26:25 779s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:26:25 779s] #Regenerating Ggrids automatically.

[04/04 17:26:25 779s] #Auto generating G-grids with size=15 tracks, using
layer Metal2's pitch = 0.200.
[04/04 17:26:25 779s] #Using automatically generated G-grids.
[04/04 17:26:25 779s] #Done routing data preparation.
[04/04 17:26:25 779s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1137.17 (MB), peak = 1407.81 (MB)
[04/04 17:26:25 779s] #Merging special wires...
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (153.500 101.740) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (153.900 100.040) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (152.700 91.480) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (152.700 94.900) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (154.300 98.320) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (98.300 147.920) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (100.100 144.500) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the

wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (144.900 142.780) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (160.500 91.480) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (161.700 93.200) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (160.700 94.900) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (107.700 146.200) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (144.900 144.500) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (125.700 52.160) on Metal1 for NET EXECUTE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (121.900 55.580) on Metal1 for NET EXECUTE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.

[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to

PIN CK at (116.100 48.740) on Metal1 for NET EXECUTE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (110.500 47.020) on Metal1 for NET EXECUTE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (108.100 48.740) on Metal1 for NET EXECUTE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (60.900 100.040) on Metal1 for NET EXECUTE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (104.700 52.160) on Metal1 for NET EXECUTE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:26:25 779s] #WARNING (EMS-27) Message (NRDB-1005) has
exceeded the current message display limit of 20.
[04/04 17:26:25 779s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 17:26:25 779s] #19 routed nets are extracted.
[04/04 17:26:25 779s] #

19 (0.73%) extracted nets are partially routed.

[04/04 17:26:25 779s] #4 routed nets are imported.

[04/04 17:26:25 779s] #2261 (86.76%) nets are without wires.
[04/04 17:26:25 779s] #322 nets are fixed|skipped|trivial (not extracted).
[04/04 17:26:25 779s] #Total number of nets = 2606.
[04/04 17:26:25 779s] #Number of eco nets is 19
[04/04 17:26:25 779s] #

[04/04 17:26:25 779s] #Start data preparation...

[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #Data preparation is done on Mon Apr 4 17:26:25 2016
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #Analyzing routing resource...
[04/04 17:26:25 779s] #Routing resource analysis is done on Mon Apr 4
17:26:25 2016
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] # Resource Analysis:
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] # Layer
Blocked

Routing #Avail
Direction Track

379

111

4900

18.98%

[04/04 17:26:25 779s] # Metal 9

452

4900

16.12%

[04/04 17:26:25 779s] # -------------------------------------------------------------[04/04 17:26:25 779s] # Total

3222

52.59% 44100

50.28%

[04/04 17:26:25 779s] #

[04/04 17:26:25 779s] # 23 nets (0.88%) with 1 preferred extra spacing.
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #

[04/04 17:26:25 779s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1137.22 (MB), peak = 1407.81 (MB)
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #start global routing iteration 1...
[04/04 17:26:25 779s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1137.22 (MB), peak = 1407.81 (MB)
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #start global routing iteration 2...
[04/04 17:26:25 779s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1137.22 (MB), peak = 1407.81 (MB)
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #Total number of trivial nets (e.g. < 2 pins) = 322
(skipped).
[04/04 17:26:25 779s] #Total number of selected nets for routing = 23.
[04/04 17:26:25 779s] #Total number of unselected nets (but routable) for
routing = 2261 (skipped).
[04/04 17:26:25 779s] #Total number of nets in the design = 2606.
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #2261 skipped nets do not have any wires.
[04/04 17:26:25 779s] #19 routable nets have only global wires.
[04/04 17:26:25 779s] #4 routable nets have only detail routed wires.
[04/04 17:26:25 779s] #19 global routed or unrouted (routable) nets have been
constrained (e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:26:25 779s] #4 detail routed (routable) nets have been constrained
(e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:26:25 779s] #
[04/04 17:26:25 779s] #Routed net constraints summary:
[04/04 17:26:25 779s] #-----------------------------------------------[04/04 17:26:25 779s] #

Rules Pref Extra Space Unconstrained

[04/04 17:26:25 779s] #------------------------------------------------

[04/04 17:26:25 779s] #

Default

[04/04 17:26:25 779s] #-----------------------------------------------[04/04 17:26:25 779s] #

Total

[04/04 17:26:25 779s] #-----------------------------------------------[04/04 17:26:25 779s] #

[04/04 17:26:25 779s] #Routing constraints summary of the whole design:
[04/04 17:26:25 779s] #-----------------------------------------------[04/04 17:26:25 779s] #

Rules Pref Extra Space Unconstrained

[04/04 17:26:25 779s] #-----------------------------------------------[04/04 17:26:25 779s] #

Default

2261

[04/04 17:26:25 779s] #-----------------------------------------------[04/04 17:26:26 779s] #

Total

2261

[04/04 17:26:26 779s] #-----------------------------------------------[04/04 17:26:26 779s] #

[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] # Congestion Analysis: (blocked Gcells are excluded)
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #

[04/04 17:26:26 779s] #

[04/04 17:26:26 779s] # The worst congested Gcell overcon (routing demand
over resource in number of tracks) = 1
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #Complete Global Routing.
[04/04 17:26:26 779s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:26:26 779s] #Total wire length = 2168 um.
[04/04 17:26:26 779s] #Total half perimeter of net bounding box = 1565 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal1 = 11 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal2 = 87 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal3 = 1002 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal4 = 1068 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal5 = 0 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:26:26 779s] #Total number of vias = 882
[04/04 17:26:26 779s] #Up-Via Summary (total 882):
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #----------------------[04/04 17:26:26 779s] # Metal 1

302

[04/04 17:26:26 779s] # Metal 2

267

[04/04 17:26:26 779s] # Metal 3

313

[04/04 17:26:26 779s] #----------------------[04/04 17:26:26 779s] #

882

[04/04 17:26:26 779s] #

[04/04 17:26:26 779s] #Max overcon = 0 track.
[04/04 17:26:26 779s] #Total overcon = 0.00%.
[04/04 17:26:26 779s] #Worst layer Gcell overcon rate = 0.00%.
[04/04 17:26:26 779s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1137.23 (MB), peak = 1407.81 (MB)
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #Start data preparation for track assignment...
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #Data preparation is done on Mon Apr 4 17:26:26 2016
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1137.23 (MB), peak = 1407.81 (MB)
[04/04 17:26:26 779s] #Start Track Assignment.
[04/04 17:26:26 779s] #Done with 9 horizontal wires in 1 hboxes and 7 vertical
wires in 1 hboxes.
[04/04 17:26:26 779s] #Done with 0 horizontal wires in 1 hboxes and 0 vertical
wires in 1 hboxes.
[04/04 17:26:26 779s] #Complete Track Assignment.
[04/04 17:26:26 779s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:26:26 779s] #Total wire length = 2171 um.
[04/04 17:26:26 779s] #Total half perimeter of net bounding box = 1565 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal1 = 11 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal2 = 87 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal3 = 1002 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal4 = 1071 um.

[04/04 17:26:26 779s] #Total wire length on LAYER Metal5 = 0 um.

[04/04 17:26:26 779s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:26:26 779s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:26:26 779s] #Total number of vias = 872
[04/04 17:26:26 779s] #Up-Via Summary (total 872):
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #----------------------[04/04 17:26:26 779s] # Metal 1

298

[04/04 17:26:26 779s] # Metal 2

263

[04/04 17:26:26 779s] # Metal 3

311

[04/04 17:26:26 779s] #----------------------[04/04 17:26:26 779s] #

872

[04/04 17:26:26 779s] #

[04/04 17:26:26 779s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1052.79 (MB), peak = 1407.81 (MB)
[04/04 17:26:26 779s] #
[04/04 17:26:26 779s] #Cpu time = 00:00:01
[04/04 17:26:26 779s] #Elapsed time = 00:00:01
[04/04 17:26:26 779s] #Increased memory = -51.82 (MB)
[04/04 17:26:26 779s] #Total memory = 1052.79 (MB)
[04/04 17:26:26 779s] #Peak memory = 1407.81 (MB)
[04/04 17:26:27 780s] #
[04/04 17:26:27 780s] #Start Detail Routing..
[04/04 17:26:27 780s] #start initial detail routing ...
[04/04 17:26:29 782s] # ECO: 22.9% of the total area was rechecked for DRC,
and 14.6% required routing.
[04/04 17:26:29 782s] #

number of violations = 0

[04/04 17:26:29 782s] #432 out of 2199 instances need to be verified(marked

ipoed).
[04/04 17:26:29 782s] #22.6% of the total area is being checked for drcs
[04/04 17:26:29 783s] #22.6% of the total area was checked
[04/04 17:26:29 783s] #

number of violations = 0

[04/04 17:26:29 783s] #cpu time = 00:00:02, elapsed time = 00:00:02,

memory = 1111.93 (MB), peak = 1407.81 (MB)
[04/04 17:26:29 783s] #start 1st optimization iteration ...
[04/04 17:26:29 783s] #

number of violations = 0

[04/04 17:26:29 783s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1111.93 (MB), peak = 1407.81 (MB)
[04/04 17:26:29 783s] #Complete Detail Routing.
[04/04 17:26:29 783s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:26:29 783s] #Total wire length = 2177 um.
[04/04 17:26:29 783s] #Total half perimeter of net bounding box = 1565 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal1 = 12 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal2 = 93 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal3 = 1012 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal4 = 1060 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal5 = 0 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:26:29 783s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:26:29 783s] #Total number of vias = 902
[04/04 17:26:29 783s] #Up-Via Summary (total 902):
[04/04 17:26:29 783s] #
[04/04 17:26:29 783s] #----------------------[04/04 17:26:29 783s] # Metal 1

308

[04/04 17:26:29 783s] # Metal 2

273

[04/04 17:26:29 783s] # Metal 3

321

[04/04 17:26:29 783s] #----------------------[04/04 17:26:29 783s] #

902

[04/04 17:26:29 783s] #

[04/04 17:26:29 783s] #Total number of DRC violations = 0
[04/04 17:26:29 783s] #Cpu time = 00:00:04
[04/04 17:26:29 783s] #Elapsed time = 00:00:04
[04/04 17:26:29 783s] #Increased memory = 59.14 (MB)
[04/04 17:26:29 783s] #Total memory = 1111.93 (MB)
[04/04 17:26:29 783s] #Peak memory = 1407.81 (MB)
[04/04 17:26:29 783s] #
[04/04 17:26:29 783s] #start routing for process antenna violation fix ...
[04/04 17:26:30 784s] #cpu time = 00:00:01, elapsed time = 00:00:01,
memory = 1056.46 (MB), peak = 1407.81 (MB)
[04/04 17:26:30 784s] #
[04/04 17:26:30 784s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:26:30 784s] #Total wire length = 2177 um.
[04/04 17:26:30 784s] #Total half perimeter of net bounding box = 1565 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal1 = 12 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal2 = 93 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal3 = 1012 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal4 = 1060 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal5 = 0 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:26:30 784s] #Total wire length on LAYER Metal9 = 0 um.

[04/04 17:26:30 784s] #Total number of vias = 902

[04/04 17:26:30 784s] #Up-Via Summary (total 902):
[04/04 17:26:30 784s] #
[04/04 17:26:30 784s] #----------------------[04/04 17:26:30 784s] # Metal 1

308

[04/04 17:26:30 784s] # Metal 2

273

[04/04 17:26:30 784s] # Metal 3

321

[04/04 17:26:30 784s] #----------------------[04/04 17:26:30 784s] #

902

[04/04 17:26:30 784s] #

[04/04 17:26:30 784s] #Total number of DRC violations = 0
[04/04 17:26:30 784s] #Total number of net violated process antenna rule = 0
[04/04 17:26:30 784s] #
[04/04 17:26:30 784s] #detailRoute Statistics:
[04/04 17:26:30 784s] #Cpu time = 00:00:05
[04/04 17:26:30 784s] #Elapsed time = 00:00:05
[04/04 17:26:30 784s] #Increased memory = 3.69 (MB)
[04/04 17:26:30 784s] #Total memory = 1056.47 (MB)
[04/04 17:26:30 784s] #Peak memory = 1407.81 (MB)
[04/04 17:26:30 784s] #
[04/04 17:26:30 784s] #globalDetailRoute statistics:
[04/04 17:26:30 784s] #Cpu time = 00:00:05
[04/04 17:26:30 784s] #Elapsed time = 00:00:05
[04/04 17:26:30 784s] #Increased memory = -48.05 (MB)
[04/04 17:26:30 784s] #Total memory = 1056.47 (MB)
[04/04 17:26:30 784s] #Peak memory = 1407.81 (MB)
[04/04 17:26:30 784s] #Number of warnings = 32
[04/04 17:26:30 784s] #Total number of warnings = 266

[04/04 17:26:30 784s] #Number of fails = 0

[04/04 17:26:30 784s] #Total number of fails = 0
[04/04 17:26:30 784s] #Complete globalDetailRoute on Mon Apr 4 17:26:30
2016
[04/04 17:26:30 784s] #
[04/04 17:26:30 784s] *** Re-Route Steiner Clock Tree/Signal Net
(cpu=0:00:05.3 mem=1257.4M) ***
[04/04 17:26:30 784s] *** Look For Un-Routed Clock Tree Net ***
[04/04 17:26:30 784s] Extraction called for design 'tdsp_core' of
instances=2199 and nets=2606 using extraction engine 'preRoute' .
[04/04 17:26:30 784s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:26:30 784s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:26:30 784s] PreRoute RC Extraction called for design tdsp_core.
[04/04 17:26:30 784s] RC Extraction called in multi-corner(2) mode.
[04/04 17:26:30 784s] RCMode: PreRoute
[04/04 17:26:30 784s]

RC Corner Indexes

[04/04 17:26:30 784s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:26:30 784s] Resistance Scaling Factor

[04/04 17:26:31 784s] Nr. of Sinks

: 258

[04/04 17:26:31 784s] Nr. of Buffer

: 10

[04/04 17:26:31 784s] Nr. of Level (including gates) : 10

[04/04 17:26:31 784s] Root Rise Input Tran

: 0.1(ps)

[04/04 17:26:31 784s] Root Fall Input Tran

: 0.1(ps)

[04/04 17:26:31 784s] No Driving Cell Specified!

[04/04 17:26:31 784s] Max trig. edge delay at sink(R):
EXECUTE_INST/acc_reg[10]/state_remap/DFF/CK 982.4(ps)
[04/04 17:26:31 784s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 950.9(ps)
[04/04 17:26:31 784s]
[04/04 17:26:31 784s]
[04/04 17:26:31 784s]

(Actual)

[04/04 17:26:31 784s] Rise Phase Delay

950~950(ps)

(Required)

: 950.9~982.4(ps)

[04/04 17:26:31 784s] Fall Phase Delay

950~950(ps)

: 931.2~980.8(ps)

[04/04 17:26:31 784s] Trig. Edge Skew

: 31.5(ps)

[04/04 17:26:31 784s] Rise Skew

[04/04 17:26:31 784s] Fall Skew
[04/04 17:26:31 784s] Max. Rise Buffer Tran.

20(ps)

: 31.5(ps)
: 49.6(ps)
: 102.1(ps)

200(ps)

[04/04 17:26:31 784s] Max. Fall Buffer Tran.

: 114.3(ps)

200(ps)

[04/04 17:26:31 784s] Max. Rise Sink Tran.

: 133.6(ps)

200(ps)

[04/04 17:26:31 784s] Max. Fall Sink Tran.

[04/04 17:26:31 784s] Min. Rise Buffer Tran.
[04/04 17:26:31 784s] Min. Fall Buffer Tran.

: 151.1(ps)
: 23.8(ps)
: 24.2(ps)

200(ps)
0(ps)
0(ps)

[04/04 17:26:31 784s] Min. Rise Sink Tran.

: 42(ps)

0(ps)

[04/04 17:26:31 784s] Min. Fall Sink Tran.

: 31.6(ps)

0(ps)

[04/04 17:26:31 784s]

[04/04 17:26:31 784s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_max_cmax_T125V108 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 31.6ps (required = 20ps)

[04/04 17:26:31 784s] view Arise_analysis_view_test_max_cmin_T125V108 :

skew = 31.6ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:31 784s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 17.1ps (required = 20ps)

[04/04 17:26:31 784s] view Arise_analysis_view_test_min_cmax_Tm20V15 :

skew = 17.1ps (required = 20ps)
[04/04 17:26:31 784s]
[04/04 17:26:31 784s]
[04/04 17:26:31 784s] Clock Analysis (CPU Time 0:00:00.4)
[04/04 17:26:31 784s]
[04/04 17:26:31 784s]
[04/04 17:26:31 784s] Switching to the default view
'Arise_analysis_view_test_max_cmax_T150V08' ...
[04/04 17:26:31 784s] Tuning the min phase delay of clock tree 'clk' ...
[04/04 17:26:31 784s]
[04/04 17:26:31 784s] Calculating post-route downstream delay for clock tree
'clk' ...
[04/04 17:26:31 785s] resized 0 standard cell(s).
[04/04 17:26:31 785s] inserted 0 standard cell(s).
[04/04 17:26:31 785s] *** Tuned Min Phase Delay (cpu=0:00:00.3
mem=1257.4M) ***
[04/04 17:26:31 785s]
[04/04 17:26:31 785s] *** None of the buffer chains at roots are modified by the
fine-tune process.
[04/04 17:26:31 785s]
[04/04 17:26:32 785s]
[04/04 17:26:32 785s] # Analysis View:
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:26:32 785s] ********** Clock clk Post-CTS Timing Analysis **********
[04/04 17:26:32 785s] Nr. of Subtrees

: 13

[04/04 17:26:32 785s] Nr. of Sinks

: 258

[04/04 17:26:32 785s] Nr. of Buffer

: 10

[04/04 17:26:32 785s] Nr. of Level (including gates) : 10

[04/04 17:26:32 785s] Root Rise Input Tran
[04/04 17:26:32 785s] Root Fall Input Tran

: 0.1(ps)
: 0.1(ps)

[04/04 17:26:32 785s] No Driving Cell Specified!

[04/04 17:26:32 785s] Max trig. edge delay at sink(R):
EXECUTE_INST/acc_reg[10]/state_remap/DFF/CK 982.4(ps)
[04/04 17:26:32 785s] Min trig. edge delay at sink(R):
TDSP_CORE_MACH_INST/phi_1_reg/state_remap/DFF/CK 950.9(ps)
[04/04 17:26:32 785s]
[04/04 17:26:32 785s]
[04/04 17:26:32 785s]

(Actual)

[04/04 17:26:32 785s] Rise Phase Delay

950~950(ps)

(Required)

: 950.9~982.4(ps)

[04/04 17:26:32 785s] Fall Phase Delay

950~950(ps)

: 931.2~980.8(ps)

[04/04 17:26:32 785s] Trig. Edge Skew

: 31.5(ps)

[04/04 17:26:32 785s] Rise Skew

[04/04 17:26:32 785s] Fall Skew
[04/04 17:26:32 785s] Max. Rise Buffer Tran.

20(ps)

: 31.5(ps)
: 49.6(ps)
: 102.1(ps)

200(ps)

[04/04 17:26:32 785s] Max. Fall Buffer Tran.

: 114.3(ps)

200(ps)

[04/04 17:26:32 785s] Max. Rise Sink Tran.

: 133.6(ps)

200(ps)

[04/04 17:26:32 785s] Max. Fall Sink Tran.

[04/04 17:26:32 785s] Min. Rise Buffer Tran.

: 151.1(ps)
: 23.8(ps)

200(ps)
0(ps)

[04/04 17:26:32 785s] Min. Fall Buffer Tran.

: 24.2(ps)

0(ps)

[04/04 17:26:32 785s] Min. Rise Sink Tran.

: 42(ps)

0(ps)

[04/04 17:26:32 785s] Min. Fall Sink Tran.

: 31.6(ps)

0(ps)

[04/04 17:26:32 785s]

[04/04 17:26:32 785s] view Arise_analysis_view_test_max_cmax_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_max_cmax_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_max_cmax_T140V102 :
skew = 31.6ps (required = 20ps)

[04/04 17:26:32 785s] view Arise_analysis_view_func_max_cmax_T125V108 :

skew = 31.6ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_max_cmax_T125V108 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_nom_cmax_T25V12 :
skew = 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_nom_cmax_T50V13 :
skew = 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_nom_cmax_T25V12 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_nom_cmax_T50V13 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_nom_cmax_T15V11 :
skew = 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_nom_cmax_T15V11 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_max_cmin_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_max_cmin_T150V08 :
skew = 31.5ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_max_cmin_T140V102 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_max_cmin_T140V102 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_max_cmin_T125V108 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_max_cmin_T125V108 :
skew = 31.6ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_nom_cmin_T25V12 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_nom_cmin_T25V12 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_nom_cmin_T20V13 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_nom_cmin_T20V13 : skew
= 18.1ps (required = 20ps)

[04/04 17:26:32 785s] view Arise_analysis_view_func_nom_cmin_T15V11 : skew

= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_nom_cmin_T15V11 : skew
= 18.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_min_cmin_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_min_cmin_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_min_cmin_Tm20V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_min_cmin_Tm20V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_min_cmin_Tm40V18 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_min_cmin_Tm40V18 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_min_cmax_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_min_cmax_T0V132 : skew
= 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_min_cmax_Tm20V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_func_min_cmax_Tm40V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_min_cmax_Tm40V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s] view Arise_analysis_view_test_min_cmax_Tm20V15 :
skew = 17.1ps (required = 20ps)
[04/04 17:26:32 785s]
[04/04 17:26:32 785s]
[04/04 17:26:32 785s] Generating Clock Analysis Report
clock_report/clock.postCTS.report ....
[04/04 17:26:32 785s] Clock Analysis (CPU Time 0:00:00.4)
[04/04 17:26:32 785s]

[04/04 17:26:32 785s]

[04/04 17:26:32 785s] *** End ckECO (cpu=0:00:09.5, real=0:00:10.0,
mem=1257.4M) ***
[04/04 17:26:32 785s] **clockDesign ... cpu = 0:00:24, real = 0:00:24, mem =
1255.4M **
[04/04 17:26:32 785s]
[04/04 17:26:32 785s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:26:32 785s] Severity ID

Count Summary

[04/04 17:26:32 785s] WARNING ENCEXT-3530

not set. Use the com...

2 The process node is

[04/04 17:26:32 785s] WARNING ENCCK-2070

option is obsolete.

5 The PadBufAfterGate

[04/04 17:26:32 785s] WARNING ENCCK-6350

percent resistance d...

12 Clock net %s has %g

[04/04 17:26:32 785s] *** Message Summary: 19 warning(s), 0 error(s)

[04/04 17:26:32 785s]
[04/04 17:27:19 786s] <CMD> timeDesign -postCTS -outDir gopi/postcts
[04/04 17:27:19 786s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but
to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".
[04/04 17:27:19 786s] **WARN: (ENCEXT-3493): The design extraction status
has been reset by the setExtractRCMode command. The parasitic data can be
regenerated either by extracting the design using the extractRC command or by
loading the SPEF or RCDB file(s).
[04/04 17:27:19 786s] Type 'man ENCEXT-3493' for more detail.
[04/04 17:27:19 786s] *** Starting trialRoute (mem=1255.4M) ***
[04/04 17:27:19 786s]
[04/04 17:27:19 786s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:27:19 786s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.

[04/04 17:27:19 786s] Start to check current routing status for nets...
[04/04 17:27:19 786s] Net ACCUM_STAT_INST/n_101 is not routed.
[04/04 17:27:19 786s] All nets will be rerouted.
[04/04 17:27:19 786s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:27:19 786s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:27:19 786s]
[04/04 17:27:19 786s] Nr of prerouted/Fixed nets = 23
[04/04 17:27:19 786s] There are 23 nets with 1 extra space.
[04/04 17:27:19 786s] routingBox: (-200 -330) (210200 207240)
[04/04 17:27:19 786s] coreBox:

(0 0) (210000 206910)

[04/04 17:27:19 786s] There are 23 prerouted nets with extraSpace.

[04/04 17:27:19 786s] Number of multi-gpin terms=2389, multi-gpins=5650,
moved blk term=63/63
[04/04 17:27:19 786s]
[04/04 17:27:19 786s] Phase 1a route (0:00:00.0 1255.4M):
[04/04 17:27:19 786s] Est net length = 6.274e+04um = 3.235e+04H +
3.039e+04V
[04/04 17:27:19 786s] Usage: (11.1%H 13.4%V) = (3.904e+04um
4.724e+04um) = (39042 27618)
[04/04 17:27:19 786s] Obstruct: 8394 = 4197 (16.5%H) + 4197 (16.5%V)
[04/04 17:27:19 786s] Overflow: 52 = 14 (0.07% H) + 37 (0.18% V)
[04/04 17:27:19 786s]
[04/04 17:27:19 786s] Phase 1b route (0:00:00.0 1255.4M):
[04/04 17:27:19 786s] Usage: (11.1%H 13.4%V) = (3.894e+04um
4.723e+04um) = (38940 27610)
[04/04 17:27:19 786s] Overflow: 37 = 0 (0.00% H) + 37 (0.18% V)
[04/04 17:27:19 786s]
[04/04 17:27:19 786s] Phase 1c route (0:00:00.0 1255.4M):
[04/04 17:27:19 786s] Usage: (11.1%H 13.4%V) = (3.889e+04um
4.721e+04um) = (38886 27598)

[04/04 17:27:19 786s] Overflow: 3 = 0 (0.00% H) + 3 (0.01% V)

[04/04 17:27:19 786s]
[04/04 17:27:19 787s] Phase 1d route (0:00:00.0 1255.4M):
[04/04 17:27:19 787s] Usage: (11.1%H 13.4%V) = (3.889e+04um
4.721e+04um) = (38886 27598)
[04/04 17:27:19 787s] Overflow: 3 = 0 (0.00% H) + 3 (0.01% V)
[04/04 17:27:19 787s]
[04/04 17:27:19 787s] Phase 1a-1d Overflow: 0.00% H + 0.01% V (0:00:00.1
1255.4M)

0.00%

0.31%

[04/04 17:27:19 787s] 4:

0.01%

1016

4.79%

[04/04 17:27:19 787s] 5:

2121199.99%

2008494.68%

[04/04 17:27:19 787s]

[04/04 17:27:19 787s] Global route (cpu=0.1s real=0.1s 1255.4M)
[04/04 17:27:19 787s] Updating RC grid for preRoute extraction ...
[04/04 17:27:19 787s] Initializing multi-corner capacitance tables ...
[04/04 17:27:19 787s] Initializing multi-corner resistance tables ...
[04/04 17:27:19 787s] There are 23 prerouted nets with extraSpace.
[04/04 17:27:19 787s]
[04/04 17:27:19 787s]
[04/04 17:27:19 787s] *** After '-updateRemainTrks' operation:
[04/04 17:27:19 787s]
[04/04 17:27:19 787s] Usage: (11.4%H 14.1%V) = (3.997e+04um
4.965e+04um) = (39961 29017)
[04/04 17:27:19 787s] Overflow: 13 = 0 (0.00% H) + 13 (0.06% V)
[04/04 17:27:19 787s]
[04/04 17:27:19 787s] Phase 1l Overflow: 0.00% H + 0.06% V (0:00:00.3
1263.4M)

[04/04 17:27:19 787s]

[04/04 17:27:19 787s] Congestion distribution:
[04/04 17:27:19 787s]
[04/04 17:27:19 787s] Remain cntH

cntV

[04/04 17:27:19 787s] -------------------------------------[04/04 17:27:19 787s] -2:

0.00%

0.01%

[04/04 17:27:19 787s] -1:

0.00%

0.05%

[04/04 17:27:19 787s] --------------------------------------

[04/04 17:27:19 787s] 0:

0.00%

0.06%

[04/04 17:27:19 787s] 1:

0.00%

0.13%

[04/04 17:27:19 787s] 2:

0.00%

0.25%

[04/04 17:27:19 787s] 3:

0.00%

133

0.63%

[04/04 17:27:19 787s] 4:

0.03%

1034

4.87%

[04/04 17:27:19 787s] 5:

: 1.00000

[04/04 17:27:20 787s] PreRoute extraction is honoring

NDR/Shielding/ExtraSpace for clock nets.
[04/04 17:27:20 787s] Using capacitance table file ...
[04/04 17:27:20 787s] Updating RC grid for preRoute extraction ...
[04/04 17:27:20 787s] Initializing multi-corner capacitance tables ...
[04/04 17:27:20 787s] Initializing multi-corner resistance tables ...
[04/04 17:27:20 787s] PreRoute RC Extraction DONE (CPU Time: 0:00:00.1 Real
Time: 0:00:00.0 MEM: 1255.379M)
[04/04 17:27:20 787s] Effort level <high> specified for reg2reg path_group
[04/04 17:27:20 788s] Effort level <high> specified for reg2cgate path_group

[04/04 17:27:20 788s] Found active setup analysis view

Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12

[04/04 17:27:20 788s] Found active setup analysis view

Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:27:20 788s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132

[04/04 17:27:20 788s] Found active hold analysis view

Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:27:20 788s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:27 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:28 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:01.0)
[04/04 17:27:28 795s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:27:28 795s] AAE_THRD: End delay calculation. (MEM=1472.46
CPU=0:00:06.3 REAL=0:00:07.0)
[04/04 17:27:30 798s]
-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -6.570 | -2.503 | -0.212 | -6.570 |

TNS (ns):| -1076.5 | -85.518 | -0.212 |-990.817 |

|
|

Violating Paths:| 593 | 43

| 549 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+

| max_cap

| max_tran

4 (4)

| -0.324 |

40 (665)

| -10.784 |

4 (4)

40 (665)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 73.998%
Routing Overflow: 0.00% H and 0.06% V
-----------------------------------------------------------Reported timing to dir gopi/postcts
[04/04 17:27:30 798s] Total CPU time: 11.29 sec
[04/04 17:27:30 798s] Total Real time: 11.0 sec
[04/04 17:27:30 798s] Total Memory Usage: 1436.304688 Mbytes
[04/04 17:28:09 798s] <CMD> timeDesign -postCTS -hold -outDir gopi/postcts
[04/04 17:28:09 798s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but
to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".
[04/04 17:28:10 798s] **WARN: (ENCEXT-3493): The design extraction status
has been reset by the setExtractRCMode command. The parasitic data can be
regenerated either by extracting the design using the extractRC command or by
loading the SPEF or RCDB file(s).
[04/04 17:28:10 798s] Type 'man ENCEXT-3493' for more detail.
[04/04 17:28:10 798s] *** Starting trialRoute (mem=1241.8M) ***
[04/04 17:28:10 798s]
[04/04 17:28:10 798s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:28:10 798s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:28:10 798s] Start to check current routing status for nets...
[04/04 17:28:10 798s] All nets are already routed correctly.

[04/04 17:28:10 798s] TrialRoute+GlbRouteEst total runtime= +0:00:00.0 =

0:00:11.1
[04/04 17:28:10 798s] TrialRoute full (called 14x) runtime= 0:00:10.3
[04/04 17:28:10 798s] TrialRoute check only (called 5x) runtime= 0:00:00.1
[04/04 17:28:10 798s] GlbRouteEst (called 21x) runtime= 0:00:00.6
[04/04 17:28:10 798s] *** Finishing trialRoute (mem=1241.8M) ***
[04/04 17:28:10 798s]
[04/04 17:28:10 798s] Extraction called for design 'tdsp_core' of
instances=2199 and nets=2606 using extraction engine 'preRoute' .
[04/04 17:28:10 798s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:28:10 798s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:28:10 798s] PreRoute RC Extraction called for design tdsp_core.
[04/04 17:28:10 798s] RC Extraction called in multi-corner(2) mode.
[04/04 17:28:10 798s] RCMode: PreRoute
[04/04 17:28:10 798s]

RC Corner Indexes

[04/04 17:28:10 798s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:28:10 798s] Resistance Scaling Factor

: 1.00000 1.00000

[04/04 17:28:10 798s] Clock Cap. Scaling Factor

: 1.00000 1.00000

[04/04 17:28:10 798s] Clock Res. Scaling Factor

: 1.00000 1.00000

[04/04 17:28:10 798s] Shrink Factor

: 1.00000

[04/04 17:28:10 798s] PreRoute extraction is honoring

NDR/Shielding/ExtraSpace for clock nets.
[04/04 17:28:10 798s] Using capacitance table file ...
[04/04 17:28:10 798s] Updating RC grid for preRoute extraction ...
[04/04 17:28:10 798s] Initializing multi-corner capacitance tables ...
[04/04 17:28:10 799s] Initializing multi-corner resistance tables ...
[04/04 17:28:10 799s] PreRoute RC Extraction DONE (CPU Time: 0:00:00.2 Real
Time: 0:00:00.0 MEM: 1241.844M)
[04/04 17:28:10 799s] Effort level <high> specified for reg2reg path_group

[04/04 17:28:10 799s] Effort level <high> specified for reg2cgate path_group
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108

[04/04 17:28:10 799s] Found active setup analysis view

Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:28:10 799s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11

[04/04 17:28:10 799s] Found active hold analysis view

Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:28:10 799s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:17 806s] AAE_THRD: End delay calculation. (MEM=1481.08
CPU=0:00:06.4 REAL=0:00:06.0)
[04/04 17:28:18 807s]
-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.059 | 0.076 | 0.258 | -0.059 |

TNS (ns):| -0.507 | 0.000 | 0.000 | -0.507 |

|
|

Violating Paths:| 17

| 17

All Paths:| 521 | 432 | 12

| 82

+--------------------+---------+---------+---------+---------+

Density: 73.998%
Routing Overflow: 0.00% H and 0.06% V
------------------------------------------------------------

Reported timing to dir gopi/postcts

[04/04 17:28:18 807s] Total CPU time: 9.04 sec
[04/04 17:28:18 807s] Total Real time: 9.0 sec
[04/04 17:28:18 807s] Total Memory Usage: 1241.84375 Mbytes
[04/04 17:28:35 808s] <CMD> setOptMode -fixCap true -fixTran true
-fixFanoutLoad false
[04/04 17:28:35 808s] <CMD> optDesign -postCTS
[04/04 17:28:35 808s] Core basic site is CoreSite
[04/04 17:28:35 808s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:28:35 808s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:28:36 809s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:28:36 809s] GigaOpt running with 1 threads.
[04/04 17:28:40 813s] **optDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1253.9M, totSessionCpu=0:13:31 **
[04/04 17:28:40 813s] *** optDesign -postCTS ***
[04/04 17:28:40 813s] DRC Margin: user margin 0.0; extra margin 0.2
[04/04 17:28:40 813s] Hold Target Slack: user slack 0
[04/04 17:28:40 813s] Setup Target Slack: user slack 0; extra slack 0.1
[04/04 17:28:41 813s] Multi-VT timing optimization disabled based on library
information.
[04/04 17:28:41 814s] *** Starting trialRoute (mem=1253.9M) ***
[04/04 17:28:41 814s]
[04/04 17:28:41 814s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:28:41 814s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:28:41 814s] Start to check current routing status for nets...
[04/04 17:28:41 814s] All nets are already routed correctly.
[04/04 17:28:41 814s] TrialRoute+GlbRouteEst total runtime= +0:00:00.0 =
0:00:11.1
[04/04 17:28:41 814s] TrialRoute full (called 14x) runtime= 0:00:10.3

[04/04 17:28:41 814s] TrialRoute check only (called 6x) runtime= 0:00:00.2
[04/04 17:28:41 814s] GlbRouteEst (called 21x) runtime= 0:00:00.6
[04/04 17:28:41 814s] *** Finishing trialRoute (mem=1253.9M) ***
[04/04 17:28:41 814s]
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102

[04/04 17:28:42 814s] Found active setup analysis view

Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:28:42 814s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13

[04/04 17:28:42 814s] Found active hold analysis view

Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:28:42 814s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:28:48 821s] AAE_THRD: End delay calculation. (MEM=1543.03
CPU=0:00:06.2 REAL=0:00:06.0)
[04/04 17:28:50 822s]
-----------------------------------------------------------Initial Summary
------------------------------------------------------------

+--------------------+---------+
|

Setup mode

| all |

+--------------------+---------+
|

WNS (ns):| -6.570 |

TNS (ns):| -1076.5 |

Violating Paths:| 593 |

All Paths:| 1055 |

+--------------------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

| max_tran

4 (4)

| -0.324 |

40 (665)

| -10.784 |

4 (4)

40 (665)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 73.998%
-----------------------------------------------------------**optDesign ... cpu = 0:00:10, real = 0:00:10, mem = 1506.9M,
totSessionCpu=0:13:41 **
[04/04 17:28:50 822s] ** INFO : this run is activating placeOpt flow focusing on
WNS only...
[04/04 17:28:50 822s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:28:50 823s] Active setup views:
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:28:50 823s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15

[04/04 17:28:50 823s] *** Starting optimizing excluded clock nets MEM=
1508.9M) ***
[04/04 17:28:50 823s] *info: No excluded clock nets to be optimized.
*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM=
1508.9M) ***
[04/04 17:28:50 823s] *** Starting optimizing excluded clock nets MEM=
1508.9M) ***
[04/04 17:28:50 823s] *info: No excluded clock nets to be optimized.
*** Finished optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM=
1508.9M) ***
[04/04 17:28:50 823s] Begin: GigaOpt Global Optimization
[04/04 17:28:50 823s] Info: 23 nets with fixed/cover wires excluded.
[04/04 17:28:50 823s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:28:50 823s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:28:55 827s] *info: 23 clock nets excluded
[04/04 17:28:55 827s] *info: 2 special nets excluded.
[04/04 17:28:55 827s] *info: 32 multi-driver nets excluded.
[04/04 17:28:55 827s] *info: 319 no-driver nets excluded.
[04/04 17:28:55 827s] *info: 23 nets with fixed/cover wires excluded.
[04/04 17:28:56 829s] ** GigaOpt Global Opt WNS Slack -6.567 TNS Slack
-1076.087
[04/04 17:28:56 829s] +--------+---------+----------+------------+-------+------------------------------------------+---------+----------------------------------------------------+
[04/04 17:28:56 829s] | WNS | TNS | Density | Real
Worst View
|Pathgroup|
End Point

| Mem |
|

[04/04 17:28:56 829s] +--------+---------+----------+------------+-------+------------------------------------------+---------+----------------------------------------------------+

[04/04 17:28:56 829s] | -6.567|-1076.087| 74.00%| 0:00:00.0| 1648.6M|
Arise_analysis_view_func_max_cmax_T125V108| default|
EXECUTE_INST/top_reg[1]/state_remap/DFF/RN
|
[04/04 17:29:00 833s] | -0.795| -42.714| 76.67%| 0:00:04.0| 1648.6M|
Arise_analysis_view_func_max_cmax_T125V108| default|
EXECUTE_INST/ar0_reg[15]/state_remap/DFF/D
|

[04/04 17:29:03 836s] | -0.155| -18.181| 72.48%| 0:00:03.0| 1662.3M|

|
|

[04/04 17:29:04 836s] | -0.150| -16.906| 72.43%| 0:00:01.0| 1662.3M|

|
|

[04/04 17:29:04 836s] +--------+---------+----------+------------+-------+------------------------------------------+---------+----------------------------------------------------+

[04/04 17:29:04 836s]
[04/04 17:29:04 836s] *** Finish post-CTS Global Setup Fixing (cpu=0:00:07.5
real=0:00:08.0 mem=1662.3M) ***
[04/04 17:29:04 836s]
[04/04 17:29:04 836s] *** Finish post-CTS Setup Fixing (cpu=0:00:07.5
real=0:00:08.0 mem=1662.3M) ***
[04/04 17:29:04 836s] ** GigaOpt Global Opt End WNS Slack -0.150 TNS Slack
-16.906
[04/04 17:29:04 837s] End: GigaOpt Global Optimization
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13

[04/04 17:29:04 837s] Found active setup analysis view

Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:29:04 837s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132

[04/04 17:29:04 837s] Found active hold analysis view

Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12

[04/04 17:29:04 837s] Found active hold analysis view

Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:29:04 837s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:29:04 837s]
-----------------------------------------------------------Summary (cpu=0.22min real=0.23min mem=1545.9M)
------------------------------------------------------------

+--------------------+---------+
|

Setup mode

| all |

+--------------------+---------+
|

WNS (ns):| -0.150 |

TNS (ns):| -16.906 |

Violating Paths:| 276 |

All Paths:| 1055 |

+--------------------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

| max_tran

| max_fanout |

0 (0)

| 0.000

18 (236)
0 (0)

| -0.612 |
|

0 (0)

18 (236)
0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

[04/04 17:29:29 862s] Reclaim Optimization End WNS Slack -0.149 TNS Slack
-16.985 Density 51.96
[04/04 17:29:29 862s]
[04/04 17:29:29 862s] ** Summary: Restruct = 0 Buffer Deletion = 8 Declone =
2 Resize = 1788 **
[04/04 17:29:29 862s] -------------------------------------------------------------[04/04 17:29:29 862s] |

| Total

| Sequential |

[04/04 17:29:29 862s] -------------------------------------------------------------[04/04 17:29:29 862s] | Num insts resized

[04/04 17:29:29 862s] | Num insts undone

|
|

1672 |

57 |

[04/04 17:29:29 862s] | Num insts Downsized

1672 |

[04/04 17:29:29 862s] | Num insts Samesized

0 |

[04/04 17:29:29 862s] | Num insts Upsized

0 |

[04/04 17:29:29 862s] | Num multiple commits+uncommits

96
0
0

|
|

122 |

[04/04 17:29:29 862s] -------------------------------------------------------------[04/04 17:29:29 862s] ** Finished Core Area Reclaim Optimization (cpu =
0:00:24.7) (real = 0:00:25.0) **
[04/04 17:29:29 862s] Executing incremental physical updates
[04/04 17:29:29 862s] Executing incremental physical updates
[04/04 17:29:29 862s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:29:29 862s] *** Starting refinePlace (0:14:20 mem=1599.8M) ***
[04/04 17:29:29 862s] Total net length = 6.228e+04 (3.309e+04 2.919e+04)
(ext = 7.887e+03)
[04/04 17:29:29 862s] default core: bins with density > 0.75 = 1.18 % ( 2 / 169
)
[04/04 17:29:29 862s] Density distribution unevenness ratio = 7.167%
[04/04 17:29:29 862s] RPlace IncrNP: Rollback Lev = -3
[04/04 17:29:29 862s] RPlace: Density =1.030233, incremental np is triggered.

[04/04 17:29:29 862s] nrCritNet: 1.84% ( 43 / 2338 ) cutoffSlk: -98.6ps

stdDelay: 11.6ps
[04/04 17:29:29 862s] default core: bins with density > 0.75 =

0 % ( 0 / 169 )

[04/04 17:29:29 862s] Density distribution unevenness ratio = 7.323%

[04/04 17:29:29 862s] RPlace postIncrNP: Density = 1.030233 -> 0.689755.
[04/04 17:29:29 862s] RPlace postIncrNP Info: Density distribution changes:
[04/04 17:29:29 862s] [1.10+

0 (0.00%) -> 0 (0.00%)

[04/04 17:29:29 862s] [1.05 - 1.10] : 0 (0.00%) -> 0 (0.00%)

[04/04 17:29:29 862s] [1.00 - 1.05] : 1 (0.59%) -> 0 (0.00%)
[04/04 17:29:29 862s] [0.95 - 1.00] : 0 (0.00%) -> 0 (0.00%)
[04/04 17:29:29 862s] [0.90 - 0.95] : 0 (0.00%) -> 0 (0.00%)
[04/04 17:29:29 862s] [0.85 - 0.90] : 0 (0.00%) -> 0 (0.00%)
[04/04 17:29:29 862s] [0.80 - 0.85] : 0 (0.00%) -> 0 (0.00%)
[04/04 17:29:29 862s] [CPU] RefinePlace/IncrNP (cpu=0:00:00.1,
real=0:00:00.0, mem=1599.8MB) @(0:14:20 - 0:14:20).
[04/04 17:29:29 862s] Move report: incrNP moves 27 insts, mean move: 5.35
um, max move: 31.58 um
[04/04 17:29:29 862s] Max move on inst (FE_OFC36_DFT_sen): (105.20,
205.20) --> (106.00, 174.42)
[04/04 17:29:29 862s] Move report: Timing Driven Placement moves 27 insts,
mean move: 5.35 um, max move: 31.58 um
[04/04 17:29:29 862s] Max move on inst (FE_OFC36_DFT_sen): (105.20,
205.20) --> (106.00, 174.42)
[04/04 17:29:29 862s]
1599.8MB

Runtime: CPU: 0:00:00.1 REAL: 0:00:00.0 MEM:

[04/04 17:29:29 862s] Starting refinePlace ...

[04/04 17:29:29 862s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:29:30 862s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:29:30 862s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.6,
real=0:00:01.0, mem=1599.8MB) @(0:14:20 - 0:14:21).

[04/04 17:29:30 862s] Move report: preRPlace moves 136 insts, mean move:
0.67 um, max move: 3.31 um
[04/04 17:29:30 862s] Max move on inst (EXECUTE_INST/FE_OFC21_n_787):
(99.60, 174.42) --> (98.00, 176.13)
[04/04 17:29:30 862s]
cell type: BUFX6

Length: 9 sites, height: 1 rows, site name: CoreSite,

[04/04 17:29:30 862s] wireLenOptFixPriorityInst 258 inst fixed

[04/04 17:29:30 862s] Placement tweakage begins.
[04/04 17:29:30 862s] wire length = 7.053e+04
[04/04 17:29:30 863s] wire length = 7.026e+04
[04/04 17:29:30 863s] Placement tweakage ends.
[04/04 17:29:30 863s] Move report: tweak moves 370 insts, mean move: 2.13
um, max move: 9.79 um
[04/04 17:29:30 863s] Max move on inst (TDSP_CORE_GLUE_INST/g8350):
(115.40, 94.05) --> (125.19, 94.05)
[04/04 17:29:30 863s] [CPU] RefinePlace/TweakPlacement (cpu=0:00:00.1,
real=0:00:00.0, mem=1599.8MB) @(0:14:21 - 0:14:21).
[04/04 17:29:30 863s] Move report: legalization moves 138 insts, mean move:
0.22 um, max move: 1.90 um
[04/04 17:29:30 863s] Max move on inst (EXECUTE_INST/FE_OFC48_DFT_sen):
(108.19, 123.12) --> (108.00, 124.83)
[04/04 17:29:30 863s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1599.8MB) @(0:14:21 - 0:14:21).
[04/04 17:29:30 863s] Move report: Detail placement moves 445 insts, mean
move: 1.86 um, max move: 9.40 um
[04/04 17:29:30 863s] Max move on inst (TDSP_CORE_GLUE_INST/g8350):
(115.60, 94.05) --> (125.00, 94.05)
[04/04 17:29:30 863s]
1599.8MB

Runtime: CPU: 0:00:00.8 REAL: 0:00:01.0 MEM:

[04/04 17:29:30 863s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:29:30 863s] maximum (X+Y) =

31.58 um

[04/04 17:29:30 863s] inst (FE_OFC36_DFT_sen) with max move: (105.2,

205.2) -> (106, 174.42)

[04/04 17:29:30 863s] mean

(X+Y) =

2.08 um

[04/04 17:29:30 863s] Total instances flipped for legalization: 6

[04/04 17:29:30 863s] Summary Report:
[04/04 17:29:30 863s] Instances move: 463 (out of 2225 movable)
[04/04 17:29:30 863s] Mean displacement: 2.08 um
[04/04 17:29:30 863s] Max displacement: 31.58 um (Instance:
FE_OFC36_DFT_sen) (105.2, 205.2) -> (106, 174.42)
[04/04 17:29:30 863s]
cell type: INVX16

Length: 16 sites, height: 1 rows, site name: CoreSite,

[04/04 17:29:30 863s] Total instances moved : 463

[04/04 17:29:30 863s] Total net length = 6.272e+04 (3.347e+04 2.924e+04)
(ext = 7.909e+03)
[04/04 17:29:30 863s] Runtime: CPU: 0:00:00.9 REAL: 0:00:01.0 MEM:
1599.8MB
[04/04 17:29:30 863s] [CPU] RefinePlace/total (cpu=0:00:00.9, real=0:00:01.0,
mem=1599.8MB) @(0:14:20 - 0:14:21).
[04/04 17:29:30 863s] *** Finished refinePlace (0:14:21 mem=1599.8M) ***
[04/04 17:29:30 863s] Ripped up 8 affected routes.
[04/04 17:29:30 863s] *** Finished Area Reclaim Optimization (cpu=0:00:26,
real=0:00:26, mem=1561.61M, totSessionCpu=0:14:21).
[04/04 17:29:30 863s] *** Starting trialRoute (mem=1561.6M) ***
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:29:30 863s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:29:30 863s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:29:30 863s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Nr of prerouted/Fixed nets = 23
[04/04 17:29:30 863s] There are 23 nets with 1 extra space.

[04/04 17:29:30 863s] routingBox: (-200 -330) (210200 207240)

[04/04 17:29:30 863s] coreBox:

(0 0) (210000 206910)

[04/04 17:29:30 863s] There are 23 prerouted nets with extraSpace.

[04/04 17:29:30 863s] Number of multi-gpin terms=805, multi-gpins=1719,
moved blk term=63/63
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Phase 1a route (0:00:00.0 1561.6M):
[04/04 17:29:30 863s] Est net length = 6.461e+04um = 3.339e+04H +
3.122e+04V
[04/04 17:29:30 863s] Usage: (11.4%H 13.8%V) = (4.019e+04um
4.838e+04um) = (40185 28286)
[04/04 17:29:30 863s] Obstruct: 8394 = 4197 (16.5%H) + 4197 (16.5%V)
[04/04 17:29:30 863s] Overflow: 48 = 6 (0.03% H) + 42 (0.20% V)
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Phase 1b route (0:00:00.0 1561.6M):
[04/04 17:29:30 863s] Usage: (11.4%H 13.8%V) = (4.008e+04um
4.837e+04um) = (40082 28277)
[04/04 17:29:30 863s] Overflow: 42 = 0 (0.00% H) + 42 (0.20% V)
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Phase 1c route (0:00:00.0 1561.6M):
[04/04 17:29:30 863s] Usage: (11.4%H 13.8%V) = (4.005e+04um
4.835e+04um) = (40049 28267)
[04/04 17:29:30 863s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Phase 1d route (0:00:00.0 1561.6M):
[04/04 17:29:30 863s] Usage: (11.4%H 13.8%V) = (4.005e+04um
4.835e+04um) = (40049 28267)
[04/04 17:29:30 863s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Phase 1a-1d Overflow: 0.00% H + 0.01% V (0:00:00.1
1561.6M)

0.00%

0.38%

[04/04 17:29:30 863s] 4:

0.03%

1105

5.21%

[04/04 17:29:30 863s] 5:

2120799.97%

1998594.21%

[04/04 17:29:30 863s]

[04/04 17:29:30 863s] Global route (cpu=0.1s real=0.1s 1561.6M)
[04/04 17:29:30 863s] There are 23 prerouted nets with extraSpace.
[04/04 17:29:30 863s]

[04/04 17:29:30 863s]

[04/04 17:29:30 863s] *** After '-updateRemainTrks' operation:
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Usage: (11.8%H 14.5%V) = (4.127e+04um
5.106e+04um) = (41268 29846)
[04/04 17:29:30 863s] Overflow: 10 = 0 (0.00% H) + 10 (0.05% V)
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Phase 1l Overflow: 0.00% H + 0.05% V (0:00:00.2
1569.6M)

[04/04 17:29:30 863s]

[04/04 17:29:30 863s] Congestion distribution:
[04/04 17:29:30 863s]
[04/04 17:29:30 863s] Remain cntH

cntV

0.01%

125

0.59%

[04/04 17:29:30 863s] 4:

0.03%

1130

5.33%

[04/04 17:29:30 863s] 5:

2120399.95%

1984893.57%

[04/04 17:29:30 863s]

[04/04 17:29:30 863s]
[04/04 17:29:30 863s] *** Completed Phase 1 route (0:00:00.4 1569.6M) ***
[04/04 17:29:30 863s]

[04/04 17:29:31 863s]

[04/04 17:29:31 863s] Total length: 6.893e+04um, number of vias: 20766
[04/04 17:29:31 863s] M1(H) length: 8.089e+01um, number of vias: 8521
[04/04 17:29:31 863s] M2(V) length: 1.633e+04um, number of vias: 8193
[04/04 17:29:31 863s] M3(H) length: 2.583e+04um, number of vias: 1994
[04/04 17:29:31 863s] M4(V) length: 9.728e+03um, number of vias: 864
[04/04 17:29:31 863s] M5(H) length: 5.350e+03um, number of vias: 645
[04/04 17:29:31 863s] M6(V) length: 3.681e+03um, number of vias: 272
[04/04 17:29:31 863s] M7(H) length: 2.743e+03um, number of vias: 246
[04/04 17:29:31 863s] M8(V) length: 4.429e+03um, number of vias: 31
[04/04 17:29:31 863s] M9(H) length: 7.592e+02um
[04/04 17:29:31 863s] *** Completed Phase 2 route (0:00:00.2 1569.6M) ***
[04/04 17:29:31 863s]
[04/04 17:29:31 863s] *** Finished all Phases (cpu=0:00:00.7 mem=1569.6M)
***
[04/04 17:29:31 863s] dbSprFixZeroViaCodes runtime= 0:00:00.0
[04/04 17:29:31 863s] Peak Memory Usage was 1569.6M
[04/04 17:29:31 863s] TrialRoute+GlbRouteEst total runtime= +0:00:00.7 =
0:00:11.8
[04/04 17:29:31 863s] TrialRoute full (called 15x) runtime= 0:00:11.0
[04/04 17:29:31 863s] TrialRoute check only (called 6x) runtime= 0:00:00.2
[04/04 17:29:31 863s] GlbRouteEst (called 21x) runtime= 0:00:00.6
[04/04 17:29:31 863s] *** Finished trialRoute (cpu=0:00:00.7 mem=1569.6M)
***
[04/04 17:29:31 863s]
[04/04 17:29:31 863s] Extraction called for design 'tdsp_core' of
instances=2251 and nets=2661 using extraction engine 'preRoute' .
[04/04 17:29:31 863s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:29:31 863s] Type 'man ENCEXT-3530' for more detail.

[04/04 17:29:31 863s] PreRoute RC Extraction called for design tdsp_core.

[04/04 17:29:31 863s] RC Extraction called in multi-corner(2) mode.
[04/04 17:29:31 863s] RCMode: PreRoute
[04/04 17:29:31 863s]

RC Corner Indexes

[04/04 17:29:31 863s] Capacitance Scaling Factor : 1.00000 1.00000

+--------------------+---------+
|

Setup mode

| all |

+--------------------+---------+
|

WNS (ns):| -0.159 |

TNS (ns):| -17.423 |

Violating Paths:| 280 |

All Paths:| 1055 |

+--------------------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

| max_tran

1 (33)

| -0.133 |

0 (0)

1 (33)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 51.961%
Routing Overflow: 0.00% H and 0.05% V
------------------------------------------------------------

**optDesign ... cpu = 0:00:53, real = 0:00:53, mem = 1540.6M,

totSessionCpu=0:14:24 **
[04/04 17:29:33 866s] Begin: GigaOpt DRV Optimization
[04/04 17:29:33 866s] Info: 23 nets with fixed/cover wires excluded.
[04/04 17:29:33 866s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:29:33 866s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:29:38 870s]
+-------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:29:38 870s] |
max-tran
max-length |
|
|
|

|
|

max-cap
|

max-fanout

[04/04 17:29:38 870s]

+-------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:29:38 870s] | nets | terms | nets | terms | nets | terms |
nets | terms | WNS | #Buffer | #Resize | Density | Real | Mem |
[04/04 17:29:38 870s]
+-------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:29:38 870s] |
7 |
-0.16 |
0|
0| 51.96 |

73 |
|

0 |

[04/04 17:29:38 871s] |

0 |
0 |
0 |
0 |
0 |
-0.16 |
1|
7| 51.97 | 0:00:00.0| 1672.3M|

0 |

[04/04 17:29:38 871s] |

0 |
0 |
0 |
0 |
0 |
-0.16 |
0|
0| 51.97 | 0:00:00.0| 1672.3M|

0 |

[04/04 17:29:38 871s]

[04/04 17:29:38 871s] Total net length = 6.050e+04 (3.147e+04 2.903e+04)

(ext = 7.726e+03)
[04/04 17:29:38 871s] default core: bins with density > 0.75 =

0 % ( 0 / 169 )

[04/04 17:29:38 871s] Density distribution unevenness ratio = 7.281%

[04/04 17:29:38 871s] [CPU] RefinePlace/IncrNP (cpu=0:00:00.0,
real=0:00:00.0, mem=1672.3MB) @(0:14:29 - 0:14:29).
[04/04 17:29:38 871s] Starting refinePlace ...
[04/04 17:29:38 871s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:29:38 871s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:29:38 871s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.0,
real=0:00:00.0, mem=1672.3MB) @(0:14:29 - 0:14:29).
[04/04 17:29:38 871s] Move report: preRPlace moves 0 insts, mean move: 0.00
um, max move: 0.00 um
[04/04 17:29:38 871s] wireLenOptFixPriorityInst 258 inst fixed
[04/04 17:29:38 871s] Move report: legalization moves 4 insts, mean move:
1.05 um, max move: 1.71 um
[04/04 17:29:38 871s] Max move on inst (ALU_32_INST/FE_OFC88_n_326):
(47.80, 100.89) --> (47.80, 102.60)
[04/04 17:29:38 871s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1672.3MB) @(0:14:29 - 0:14:29).
[04/04 17:29:38 871s] Move report: Detail placement moves 4 insts, mean
move: 1.05 um, max move: 1.71 um
[04/04 17:29:38 871s] Max move on inst (ALU_32_INST/FE_OFC88_n_326):
(47.80, 100.89) --> (47.80, 102.60)
[04/04 17:29:38 871s]
1672.3MB

Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:

[04/04 17:29:38 871s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:29:38 871s] maximum (X+Y) =

1.71 um

[04/04 17:29:38 871s] inst (ALU_32_INST/FE_OFC88_n_326) with max move:

(47.8, 100.89) -> (47.8, 102.6)
[04/04 17:29:38 871s] mean

(X+Y) =

[04/04 17:29:38 871s] Summary Report:

1.05 um

[04/04 17:29:38 871s] Instances move: 4 (out of 2226 movable)

[04/04 17:29:38 871s] Mean displacement: 1.05 um
[04/04 17:29:38 871s] Max displacement: 1.71 um (Instance:
ALU_32_INST/FE_OFC88_n_326) (47.8, 100.89) -> (47.8, 102.6)
[04/04 17:29:38 871s]
cell type: CLKBUFX2

Length: 5 sites, height: 1 rows, site name: CoreSite,

[04/04 17:29:38 871s] Total instances moved : 4

[04/04 17:29:38 871s] Total net length = 6.050e+04 (3.147e+04 2.903e+04)
(ext = 7.726e+03)
[04/04 17:29:38 871s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
1672.3MB
[04/04 17:29:38 871s] [CPU] RefinePlace/total (cpu=0:00:00.0, real=0:00:00.0,
mem=1672.3MB) @(0:14:29 - 0:14:29).
[04/04 17:29:38 871s] *** Finished refinePlace (0:14:29 mem=1672.3M) ***
[04/04 17:29:38 871s] *** maximum move = 1.71 um ***
[04/04 17:29:38 871s] *** Finished refinePlace (0:14:29 mem=1672.3M) ***
[04/04 17:29:38 871s] *** Finished re-routing un-routed nets (1672.3M) ***
[04/04 17:29:39 871s]
[04/04 17:29:39 871s] *** Finish Physical Update (cpu=0:00:00.4
real=0:00:01.0 mem=1672.3M) ***
[04/04 17:29:39 871s] End: GigaOpt DRV Optimization
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12

[04/04 17:29:39 871s] Found active setup analysis view

Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:29:39 871s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132

[04/04 17:29:39 871s] Found active hold analysis view

Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12

[04/04 17:29:39 871s] Found active hold analysis view

Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:29:39 871s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:29:39 872s]
-----------------------------------------------------------Summary (cpu=0.09min real=0.10min mem=1555.9M)
------------------------------------------------------------

+--------------------+---------+
|

Setup mode

| all |

+--------------------+---------+
|

WNS (ns):| -0.159 |

TNS (ns):| -17.394 |

Violating Paths:| 273 |

All Paths:| 1055 |

+--------------------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 51.968%
Routing Overflow: 0.00% H and 0.05% V
**optDesign ... cpu = 0:00:59, real = 0:00:59, mem = 1555.9M,
totSessionCpu=0:14:30 **
[04/04 17:29:39 872s] Begin: GigaOpt Optimization in WNS mode
[04/04 17:29:39 872s] Info: 23 nets with fixed/cover wires excluded.
[04/04 17:29:39 872s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:29:39 872s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:29:43 876s] *info: 23 clock nets excluded
[04/04 17:29:43 876s] *info: 2 special nets excluded.
[04/04 17:29:43 876s] *info: 32 multi-driver nets excluded.
[04/04 17:29:43 876s] *info: 322 no-driver nets excluded.
[04/04 17:29:43 876s] *info: 23 nets with fixed/cover wires excluded.
[04/04 17:29:43 876s] Effort level <high> specified for reg2reg path_group
[04/04 17:29:44 876s] Effort level <high> specified for reg2cgate path_group
[04/04 17:29:44 877s] ** GigaOpt Optimizer WNS Slack -0.159 TNS Slack
-17.394 Density 51.97
[04/04 17:29:44 877s] Optimizer WNS Pass 0
[04/04 17:29:44 877s] Active Path Group: reg2cgate reg2reg
[04/04 17:29:44 877s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:29:44 877s] | WNS | All WNS | TNS | All TNS | Density | Real
Mem |
Worst View
|Pathgroup|
End Point
|

[04/04 17:29:44 877s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:29:44 877s] | -0.008| -0.159| -0.017| -17.394| 51.97%|
0:00:00.0| 1670.3M|Arise_analysis_view_func_max_cmax_T125V108| reg2reg|
EXECUTE_INST/acc_reg[21]/state_remap/DFF/D
|
[04/04 17:29:44 877s] | 0.014| -0.159| 0.000| -17.378| 51.98%|
0:00:00.0| 1685.8M|Arise_analysis_view_func_max_cmax_T125V108| reg2reg|
EXECUTE_INST/acc_reg[15]/state_remap/DFF/D
|
[04/04 17:29:44 877s] | 0.014| -0.159| 0.000| -17.378| 51.98%|
0:00:00.0| 1685.8M|Arise_analysis_view_func_max_cmax_T125V108| reg2reg|
EXECUTE_INST/acc_reg[15]/state_remap/DFF/D
|
[04/04 17:29:44 877s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:29:44 877s]
[04/04 17:29:44 877s] *** Finish Optimize Step (cpu=0:00:00.2 real=0:00:00.0
mem=1685.8M) ***
[04/04 17:29:44 877s] Active Path Group: default
[04/04 17:29:44 877s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:29:44 877s] | WNS | All WNS | TNS | All TNS | Density | Real
Mem |
Worst View
|Pathgroup|
End Point
|
[04/04 17:29:44 877s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:29:44 877s] | -0.159| -0.159| -17.378| -17.378| 51.98%|
0:00:00.0| 1685.8M|Arise_analysis_view_func_max_cmax_T125V108| default|
TDSP_CORE_MACH_INST/tdsp_state_reg[2]/state_remap/ |
[04/04 17:29:44 877s] |
|
| DFF/D

[04/04 17:29:45 877s] | -0.109| -0.109| -17.185| -17.185| 52.07%|

0:00:01.0| 1685.8M| Arise_analysis_view_func_nom_cmax_T50V13| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:29:45 877s] |
|
| LATCH/SE

|
|

[04/04 17:29:45 878s] | -0.109| -0.109| -17.185| -17.185| 52.07%|

0:00:00.0| 1685.8M| Arise_analysis_view_func_nom_cmax_T50V13| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:29:45 878s] |
|
| LATCH/SE

[04/04 17:29:45 878s] | -0.109| -0.109| -17.185| -17.185| 52.07%|

0:00:00.0| 1685.8M|Arise_analysis_view_func_max_cmax_T125V108| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:29:45 878s] |
|
| LATCH/SE

[04/04 17:29:45 878s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:29:45 878s]
[04/04 17:29:45 878s] *** Finish Optimize Step (cpu=0:00:00.9 real=0:00:01.0
mem=1685.8M) ***
[04/04 17:29:45 878s] ** GigaOpt Optimizer WNS Slack -0.109 TNS Slack
-17.185 Density 52.07
[04/04 17:29:45 878s] *** Starting refinePlace (0:14:36 mem=1685.8M) ***
[04/04 17:29:46 878s] *** Starting refinePlace (0:14:36 mem=1685.8M) ***
[04/04 17:29:46 878s] Total net length = 6.054e+04 (3.149e+04 2.906e+04)
(ext = 7.722e+03)
[04/04 17:29:46 878s] default core: bins with density > 0.75 =

0 % ( 0 / 169 )

[04/04 17:29:46 878s] Density distribution unevenness ratio = 7.342%

[04/04 17:29:46 878s] [CPU] RefinePlace/IncrNP (cpu=0:00:00.0,
real=0:00:00.0, mem=1685.8MB) @(0:14:36 - 0:14:36).
[04/04 17:29:46 878s] Starting refinePlace ...
[04/04 17:29:46 878s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:29:47 879s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:29:47 879s] [CPU] RefinePlace/preRPlace (cpu=0:00:01.0,
real=0:00:01.0, mem=1688.6MB) @(0:14:36 - 0:14:37).
[04/04 17:29:47 879s] Move report: preRPlace moves 55 insts, mean move:
0.22 um, max move: 1.01 um

[04/04 17:29:47 879s] Max move on inst

(TDSP_CORE_MACH_INST/FE_RC_15_0): (101.80, 200.07) --> (102.80, 200.08)
[04/04 17:29:47 879s]
cell type: NAND2X8

Length: 16 sites, height: 1 rows, site name: CoreSite,

[04/04 17:29:47 879s] wireLenOptFixPriorityInst 258 inst fixed

[04/04 17:29:47 879s] Move report: legalization moves 57 insts, mean move:
1.67 um, max move: 4.99 um
[04/04 17:29:47 879s] Max move on inst (DATA_BUS_MACH_INST/g278):
(104.88, 198.21) --> (106.60, 194.94)
[04/04 17:29:47 879s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=1688.6MB) @(0:14:37 - 0:14:37).
[04/04 17:29:47 879s] Move report: Detail placement moves 50 insts, mean
move: 2.03 um, max move: 5.42 um
[04/04 17:29:47 879s] Max move on inst (DATA_BUS_MACH_INST/g278):
(104.60, 198.36) --> (106.60, 194.94)
[04/04 17:29:47 879s]
1688.6MB

Runtime: CPU: 0:00:01.0 REAL: 0:00:01.0 MEM:

[04/04 17:29:47 879s] Statistics of distance of Instance movement in refine

placement:
[04/04 17:29:47 879s] maximum (X+Y) =

5.42 um

[04/04 17:29:47 879s] inst (DATA_BUS_MACH_INST/g278) with max move:

(104.6, 198.36) -> (106.6, 194.94)
[04/04 17:29:47 879s] mean

(X+Y) =

2.03 um

[04/04 17:29:47 879s] Summary Report:

[04/04 17:29:47 879s] Instances move: 50 (out of 2236 movable)
[04/04 17:29:47 879s] Mean displacement: 2.03 um
[04/04 17:29:47 879s] Max displacement: 5.42 um (Instance:
DATA_BUS_MACH_INST/g278) (104.6, 198.36) -> (106.6, 194.94)
[04/04 17:29:47 879s]
cell type: OR2X1

Length: 5 sites, height: 1 rows, site name: CoreSite,

[04/04 17:29:47 879s] Total instances moved : 50

[04/04 17:29:47 879s] Total net length = 6.054e+04 (3.149e+04 2.906e+04)
(ext = 7.722e+03)

[04/04 17:29:47 879s] Runtime: CPU: 0:00:01.0 REAL: 0:00:01.0 MEM:

1688.6MB
[04/04 17:29:47 879s] [CPU] RefinePlace/total (cpu=0:00:01.0, real=0:00:01.0,
mem=1688.6MB) @(0:14:36 - 0:14:37).
[04/04 17:29:47 879s] *** Finished refinePlace (0:14:37 mem=1688.6M) ***
[04/04 17:29:47 879s] *** maximum move = 5.42 um ***
[04/04 17:29:47 879s] *** Finished refinePlace (0:14:37 mem=1688.6M) ***
[04/04 17:29:47 879s] *** Finished re-routing un-routed nets (1688.6M) ***
[04/04 17:29:47 879s]
[04/04 17:29:47 879s] *** Finish Physical Update (cpu=0:00:01.3
real=0:00:02.0 mem=1688.6M) ***
[04/04 17:29:47 879s] ** GigaOpt Optimizer WNS Slack -0.109 TNS Slack
-17.185 Density 52.07
[04/04 17:29:47 879s] Optimizer WNS Pass 1
[04/04 17:29:47 879s] Active Path Group: default
[04/04 17:29:47 879s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:29:47 879s] | WNS | All WNS | TNS | All TNS | Density | Real
Mem |
Worst View
|Pathgroup|
End Point
|
[04/04 17:29:47 879s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:29:47 879s] | -0.109| -0.109| -17.185| -17.185| 52.07%|
0:00:00.0| 1688.6M|Arise_analysis_view_func_max_cmax_T125V108| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:29:47 879s] |
|
| LATCH/SE

[04/04 17:29:47 880s] | -0.109| -0.109| -17.185| -17.185| 52.07%|

0:00:00.0| 1688.6M| Arise_analysis_view_func_nom_cmax_T50V13| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:29:47 880s] |
|
| LATCH/SE

|
|

[04/04 17:29:47 880s] | -0.109| -0.109| -17.185| -17.185| 52.07%|

0:00:00.0| 1688.6M|Arise_analysis_view_func_max_cmax_T125V108| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:29:47 880s] |
|
| LATCH/SE

[04/04 17:29:47 880s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:29:47 880s]
[04/04 17:29:47 880s] *** Finish Optimize Step (cpu=0:00:00.4 real=0:00:00.0
mem=1688.6M) ***
[04/04 17:29:47 880s]
[04/04 17:29:47 880s] *** Finish post-CTS Setup Fixing (cpu=0:00:03.7
real=0:00:04.0 mem=1688.6M) ***
[04/04 17:29:47 880s]
[04/04 17:29:47 880s] End: GigaOpt Optimization in WNS mode
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13

[04/04 17:29:47 880s] Found active setup analysis view

Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:29:47 880s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15

[04/04 17:29:47 880s] Found active hold analysis view

Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13

[04/04 17:29:47 880s] Found active hold analysis view

Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:29:47 880s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:29:48 880s]
-----------------------------------------------------------Summary (cpu=0.13min real=0.13min mem=1567.8M)
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.109 | 0.014 | 0.038 | -0.109 |

TNS (ns):| -17.185 | 0.000 | 0.000 | -17.185 |

|
|

Violating Paths:| 270 |

| 270 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.066%
Routing Overflow: 0.00% H and 0.05% V
-----------------------------------------------------------**optDesign ... cpu = 0:01:07, real = 0:01:08, mem = 1567.8M,
totSessionCpu=0:14:38 **
[04/04 17:29:48 880s] Info: 23 nets with fixed/cover wires excluded.
[04/04 17:29:48 880s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:29:48 880s] *** Starting trialRoute (mem=1567.8M) ***
[04/04 17:29:48 880s]
[04/04 17:29:48 880s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:29:48 880s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:29:48 880s] triMarkNetsWithAllFixedWires runtime= 0:00:00.0
[04/04 17:29:48 880s] Options: -handlePreroute -keepMarkedOptRoutes
-noPinGuide
[04/04 17:29:48 880s]
[04/04 17:29:48 880s] Nr of prerouted/Fixed nets = 23
[04/04 17:29:48 880s] There are 23 nets with 1 extra space.
[04/04 17:29:48 880s] routingBox: (-200 -330) (210200 207240)
[04/04 17:29:48 880s] coreBox:

(0 0) (210000 206910)

[04/04 17:29:48 880s] There are 23 prerouted nets with extraSpace.

[04/04 17:29:48 880s] Number of multi-gpin terms=811, multi-gpins=1733,
moved blk term=63/63
[04/04 17:29:48 880s]
[04/04 17:29:48 880s] Phase 1a route (0:00:00.0 1567.8M):
[04/04 17:29:48 880s] Est net length = 6.466e+04um = 3.343e+04H +
3.123e+04V
[04/04 17:29:48 880s] Usage: (11.5%H 13.8%V) = (4.024e+04um
4.843e+04um) = (40239 28317)
[04/04 17:29:48 880s] Obstruct: 8394 = 4197 (16.5%H) + 4197 (16.5%V)

[04/04 17:29:48 880s] Overflow: 48 = 6 (0.03% H) + 42 (0.20% V)

[04/04 17:29:48 880s]
[04/04 17:29:48 880s] Phase 1b route (0:00:00.0 1569.8M):
[04/04 17:29:48 880s] Usage: (11.4%H 13.8%V) = (4.014e+04um
4.842e+04um) = (40140 28308)
[04/04 17:29:48 880s] Overflow: 42 = 0 (0.00% H) + 42 (0.20% V)
[04/04 17:29:48 880s]
[04/04 17:29:48 880s] Phase 1c route (0:00:00.0 1569.8M):
[04/04 17:29:48 880s] Usage: (11.4%H 13.8%V) = (4.011e+04um
4.840e+04um) = (40107 28300)
[04/04 17:29:48 880s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:29:48 880s]
[04/04 17:29:48 880s] Phase 1d route (0:00:00.0 1569.8M):
[04/04 17:29:48 880s] Usage: (11.4%H 13.8%V) = (4.011e+04um
4.840e+04um) = (40107 28300)
[04/04 17:29:48 880s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:29:48 880s]
[04/04 17:29:48 880s] Phase 1a-1d Overflow: 0.00% H + 0.01% V (0:00:00.1
1569.8M)

[04/04 17:29:48 880s]

[04/04 17:29:48 880s] Phase 1e route (0:00:00.0 1569.8M):
[04/04 17:29:48 880s] Usage: (11.4%H 13.8%V) = (4.011e+04um
4.840e+04um) = (40107 28300)
[04/04 17:29:48 880s] Overflow: 2 = 0 (0.00% H) + 2 (0.01% V)
[04/04 17:29:48 880s]
[04/04 17:29:48 880s] Overflow: 0.00% H + 0.01% V (0:00:00.0 1569.8M)

0.00%

0.38%

[04/04 17:29:48 880s] 4:

0.03%

1046

4.93%

[04/04 17:29:48 880s] 5:

2120699.97%

2004294.48%

[04/04 17:29:48 880s]

[04/04 17:29:48 880s] Global route (cpu=0.1s real=0.1s 1569.8M)
[04/04 17:29:48 881s] There are 23 prerouted nets with extraSpace.
[04/04 17:29:48 881s]
[04/04 17:29:48 881s]
[04/04 17:29:48 881s] *** After '-updateRemainTrks' operation:
[04/04 17:29:48 881s]
[04/04 17:29:48 881s] Usage: (11.8%H 14.5%V) = (4.133e+04um
5.112e+04um) = (41329 29881)
[04/04 17:29:48 881s] Overflow: 10 = 0 (0.00% H) + 10 (0.05% V)
[04/04 17:29:48 881s]
[04/04 17:29:48 881s] Phase 1l Overflow: 0.00% H + 0.05% V (0:00:00.2
1577.8M)

[04/04 17:29:48 881s]

[04/04 17:29:48 881s] Congestion distribution:

[04/04 17:29:48 881s]

[04/04 17:29:48 881s] Remain cntH

cntV

0.00%

[04/04 17:29:49 882s] Calculate delays in BcWc mode...

[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Calculate delays in BcWc mode...
[04/04 17:29:49 882s] Topological Sorting (CPU = 0:00:00.0, MEM = 1430.0M,
InitMEM = 1430.0M)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:29:56 888s] AAE_THRD: End delay calculation. (MEM=1586.73
CPU=0:00:06.3 REAL=0:00:07.0)
[04/04 17:29:56 888s] *** CDM Built up (cpu=0:00:06.7 real=0:00:07.0 mem=
1586.7M) ***
[04/04 17:29:57 889s] Begin: GigaOpt postEco DRV Optimization
[04/04 17:29:57 889s] Info: 23 nets with fixed/cover wires excluded.
[04/04 17:29:57 889s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:29:57 889s] Core basic site is CoreSite
[04/04 17:29:57 889s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:29:57 889s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:30:03 895s]
+-------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:30:03 895s] |
max-tran
max-length |
|
|
|

|
|

max-cap
|

max-fanout

[04/04 17:30:03 895s]

+-------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:30:03 895s] | nets | terms | nets | terms | nets | terms |
nets | terms | WNS | #Buffer | #Resize | Density | Real | Mem |
[04/04 17:30:03 895s]
+-------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:30:03 895s] |
0 |
-0.11 |
0|
0| 52.07 |

0 |

[04/04 17:30:03 896s] |

0 |
0 |
0 |
0 |
0 |
-0.11 |
0|
0| 52.07 | 0:00:00.0| 1697.4M|

0 |

0 |
|

[04/04 17:30:03 896s]

+-------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:30:03 896s]
[04/04 17:30:03 896s] *** Finish DRV Fixing (cpu=0:00:01.2 real=0:00:01.0
mem=1697.4M) ***
[04/04 17:30:03 896s]
[04/04 17:30:04 896s] End: GigaOpt postEco DRV Optimization
[04/04 17:30:04 896s] GigaOpt: WNS changes after routing: 0.008 -> 0.008
(bump = 0.0)
[04/04 17:30:04 896s] Begin: GigaOpt postEco optimization
[04/04 17:30:04 896s] Info: 23 nets with fixed/cover wires excluded.
[04/04 17:30:04 896s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:30:04 896s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:30:04 896s] *info: 23 clock nets excluded
[04/04 17:30:04 896s] *info: 2 special nets excluded.
[04/04 17:30:04 896s] *info: 32 multi-driver nets excluded.
[04/04 17:30:04 896s] *info: 322 no-driver nets excluded.
[04/04 17:30:04 896s] *info: 23 nets with fixed/cover wires excluded.
[04/04 17:30:04 896s] ** GigaOpt Optimizer WNS Slack -0.109 TNS Slack
-17.358 Density 52.07
[04/04 17:30:04 896s] Optimizer WNS Pass 0
[04/04 17:30:04 896s] Active Path Group: default
[04/04 17:30:04 896s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:30:04 896s] | WNS | All WNS | TNS | All TNS | Density | Real
Mem |
Worst View
|Pathgroup|
End Point
|
[04/04 17:30:04 896s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:30:04 896s] | -0.109| -0.109| -17.358| -17.358| 52.07%|

0:00:00.0| 1682.3M| Arise_analysis_view_test_max_cmax_T150V08| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:30:04 896s] |
|
| LATCH/SE

[04/04 17:30:04 896s] | -0.109| -0.109| -17.358| -17.358| 52.07%|

0:00:00.0| 1698.8M| Arise_analysis_view_test_max_cmax_T150V08| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:30:04 896s] |
|
| LATCH/SE

[04/04 17:30:04 896s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:30:04 896s]
[04/04 17:30:04 896s] *** Finish Optimize Step (cpu=0:00:00.2 real=0:00:00.0
mem=1698.8M) ***
[04/04 17:30:04 896s]
[04/04 17:30:04 896s] *** Finish post-CTS Setup Fixing (cpu=0:00:00.2
real=0:00:00.0 mem=1698.8M) ***
[04/04 17:30:04 896s]
[04/04 17:30:04 897s] End: GigaOpt postEco optimization
[04/04 17:30:04 897s] GigaOpt: WNS changes after postEco optimization: 0.008
-> 0.008 (bump = 0.0)
[04/04 17:30:04 897s] GigaOpt: Skipping nonLegal postEco optimization
[04/04 17:30:04 897s] *** Steiner Routed Nets: 0.0%; Threshold: 100; Threshold
for Hold: 100
[04/04 17:30:04 897s] Re-routed 0 nets
[04/04 17:30:04 897s] Extraction called for design 'tdsp_core' of
instances=2262 and nets=2672 using extraction engine 'preRoute' .
[04/04 17:30:04 897s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:30:04 897s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:30:04 897s] PreRoute RC Extraction called for design tdsp_core.

[04/04 17:30:04 897s] RC Extraction called in multi-corner(2) mode.

[04/04 17:30:04 897s] RCMode: PreRoute
[04/04 17:30:04 897s]

RC Corner Indexes

[04/04 17:30:04 897s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:30:13 905s] Found active hold analysis view

Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:30:13 905s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:30:13 905s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:30:13 905s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:30:13 905s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:30:13 905s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:30:15 907s]
-----------------------------------------------------------optDesign Final Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.109 | 0.014 | 0.041 | -0.109 |

TNS (ns):| -17.358 | 0.000 | 0.000 | -17.358 |

|
|

Violating Paths:| 270 |

| 270 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+

| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.066%
Routing Overflow: 0.00% H and 0.05% V
-----------------------------------------------------------**optDesign ... cpu = 0:01:35, real = 0:01:35, mem = 1564.6M,
totSessionCpu=0:15:06 **
[04/04 17:30:15 907s] *** Finished optDesign ***
[04/04 17:30:15 907s]
[04/04 17:30:15 907s]
0:01:49 real= 0:01:50)

OPT_RUNTIME:

optDesign (count = 3): (cpu=

[04/04 17:30:15 907s] OPT_RUNTIME:

(cpu=0:00:13.8 real=0:00:13.8)

ofo (count = 1):

[04/04 17:30:15 907s] OPT_RUNTIME:

(cpu=0:00:25.9 real=0:00:26.0)

reclaim (count = 2):

[04/04 17:30:15 907s] OPT_RUNTIME:

(cpu=0:00:01.7 real=0:00:01.7)

phyUpdate (count = 2):

[04/04 17:30:15 907s] OPT_RUNTIME:

(cpu=0:00:12.8 real=0:00:13.1)

wns (count = 2):

[04/04 17:30:15 907s] OPT_RUNTIME:

(cpu=0:00:01.7 real=0:00:01.8)

wnsOpt (count = 3):

[04/04 17:30:15 907s] OPT_RUNTIME:

(cpu=0:00:30.3 real=0:00:30.5)

postTROpt (count = 2):

[04/04 17:31:23 908s] <CMD> timeDesign -postCTS -hold -outDir

gopi/postcts_optimization/
[04/04 17:31:23 908s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but
to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".

[04/04 17:31:23 908s] **WARN: (ENCEXT-3493): The design extraction status

has been reset by the setExtractRCMode command. The parasitic data can be
regenerated either by extracting the design using the extractRC command or by
loading the SPEF or RCDB file(s).
[04/04 17:31:23 908s] Type 'man ENCEXT-3493' for more detail.
[04/04 17:31:23 908s] *** Starting trialRoute (mem=1303.2M) ***
[04/04 17:31:23 908s]
[04/04 17:31:23 908s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:31:23 908s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:31:23 908s] Start to check current routing status for nets...
[04/04 17:31:23 908s] All nets are already routed correctly.
[04/04 17:31:23 908s] TrialRoute+GlbRouteEst total runtime= +0:00:00.0 =
0:00:12.6
[04/04 17:31:23 908s] TrialRoute full (called 16x) runtime= 0:00:11.7
[04/04 17:31:23 908s] TrialRoute check only (called 7x) runtime= 0:00:00.2
[04/04 17:31:23 908s] GlbRouteEst (called 21x) runtime= 0:00:00.6
[04/04 17:31:23 908s] *** Finishing trialRoute (mem=1303.2M) ***
[04/04 17:31:23 908s]
[04/04 17:31:23 908s] Extraction called for design 'tdsp_core' of
instances=2262 and nets=2672 using extraction engine 'preRoute' .
[04/04 17:31:23 908s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:31:23 908s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:31:23 908s] PreRoute RC Extraction called for design tdsp_core.
[04/04 17:31:23 908s] RC Extraction called in multi-corner(2) mode.
[04/04 17:31:23 908s] RCMode: PreRoute
[04/04 17:31:23 908s]

RC Corner Indexes

[04/04 17:31:23 908s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:31:23 908s] Resistance Scaling Factor

: 1.00000 1.00000

[04/04 17:31:23 908s] Clock Cap. Scaling Factor

: 1.00000 1.00000

[04/04 17:31:23 908s] Clock Res. Scaling Factor

: 1.00000 1.00000

[04/04 17:31:23 908s] Shrink Factor

: 1.00000

[04/04 17:31:23 908s] PreRoute extraction is honoring

NDR/Shielding/ExtraSpace for clock nets.
[04/04 17:31:23 908s] Using capacitance table file ...
[04/04 17:31:23 908s] Initializing multi-corner capacitance tables ...
[04/04 17:31:23 908s] Initializing multi-corner resistance tables ...
[04/04 17:31:23 908s] PreRoute RC Extraction DONE (CPU Time: 0:00:00.1 Real
Time: 0:00:00.0 MEM: 1303.164M)
[04/04 17:31:23 908s] Effort level <high> specified for reg2reg path_group
[04/04 17:31:24 908s] Effort level <high> specified for reg2cgate path_group
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11

[04/04 17:31:24 908s] Found active setup analysis view

Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:31:24 908s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18

[04/04 17:31:24 908s] Found active hold analysis view

Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:31:24 908s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11

[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:31:32 916s] AAE_THRD: End delay calculation. (MEM=1542.4
CPU=0:00:06.7 REAL=0:00:07.0)
[04/04 17:31:33 917s]
-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+

WNS (ns):| -0.061 | 0.080 | 0.261 | -0.061 |

TNS (ns):| -0.240 | 0.000 | 0.000 | -0.240 |

|
|

Violating Paths:|

All Paths:| 521 | 432 | 12

5
| 82

|
|

+--------------------+---------+---------+---------+---------+

Density: 52.066%
Routing Overflow: 0.00% H and 0.05% V
-----------------------------------------------------------Reported timing to dir gopi/postcts_optimization/
[04/04 17:31:33 917s] Total CPU time: 9.33 sec
[04/04 17:31:33 917s] Total Real time: 10.0 sec
[04/04 17:31:33 917s] Total Memory Usage: 1303.164062 Mbytes
[04/04 17:32:14 918s] <CMD> setOptMode -fixCap true -fixTran true
-fixFanoutLoad false
[04/04 17:32:14 918s] <CMD> optDesign -postCTS -hold
[04/04 17:32:14 918s] GigaOpt running with 1 threads.
[04/04 17:32:14 918s] Core basic site is CoreSite
[04/04 17:32:14 918s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:32:14 918s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:32:15 918s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:32:19 922s] **optDesign ... cpu = 0:00:00, real = 0:00:00, mem =
1315.2M, totSessionCpu=0:15:21 **
[04/04 17:32:19 922s] *** optDesign -postCTS ***
[04/04 17:32:19 922s] DRC Margin: user margin 0.0
[04/04 17:32:19 922s] Hold Target Slack: user slack 0
[04/04 17:32:19 922s] Setup Target Slack: user slack 0;
[04/04 17:32:19 923s] *** Starting trialRoute (mem=1315.2M) ***
[04/04 17:32:19 923s]

[04/04 17:32:19 923s] There are 0 guide points passed to trialRoute for fixed
pins.
[04/04 17:32:19 923s] There are 0 guide points passed to trialRoute for
pinGroup/netGroup/pinGuide pins.
[04/04 17:32:19 923s] Start to check current routing status for nets...
[04/04 17:32:19 923s] All nets are already routed correctly.
[04/04 17:32:19 923s] TrialRoute+GlbRouteEst total runtime= +0:00:00.0 =
0:00:12.6
[04/04 17:32:19 923s] TrialRoute full (called 16x) runtime= 0:00:11.7
[04/04 17:32:19 923s] TrialRoute check only (called 8x) runtime= 0:00:00.2
[04/04 17:32:19 923s] GlbRouteEst (called 21x) runtime= 0:00:00.6
[04/04 17:32:19 923s] *** Finishing trialRoute (mem=1315.2M) ***
[04/04 17:32:19 923s]
[04/04 17:32:20 923s] *info: All cells identified as Buffer and Delay cells:
[04/04 17:32:20 923s] *info: with footprint "DLY1X4" or "BUFX2":
[04/04 17:32:20 923s] *info: -----------------------------------------------------------------[04/04 17:32:20 923s] *info: (dly) DLY2X1

[04/04 17:32:20 923s] *info: (buf) BUFX2
[04/04 17:32:20 923s] *info: (buf) CLKBUFX3
[04/04 17:32:20 923s] *info: (buf) BUFX3
[04/04 17:32:20 923s] *info: (buf) CLKBUFX4

- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc

[04/04 17:32:20 923s] *info: (buf) BUFX4

- gpdk045wc

[04/04 17:32:20 923s] *info: (buf) BUFX6

- gpdk045wc

04/04 17:32:20 923s] *info: (buf) CLKBUFX6

[04/04 17:32:20 923s] *info: (buf) BUFX8
[04/04 17:32:20 923s] *info: (buf) CLKBUFX8
[04/04 17:32:20 923s] *info: (buf) CLKBUFX12
[04/04 17:32:20 923s] *info: (buf) BUFX12
[04/04 17:32:20 923s] *info: (buf) CLKBUFX16
[04/04 17:32:20 923s] *info: (buf) BUFX16
[04/04 17:32:20 923s] *info: (buf) CLKBUFX20
[04/04 17:32:20 923s] *info: (buf) BUFX20
[04/04 17:32:20 923s] *info: (buf) CLKBUFX2
[04/04 17:32:20 923s] *info: (buf) BUFX2
[04/04 17:32:20 923s] *info: (buf) CLKBUFX3
[04/04 17:32:20 923s] *info: (buf) BUFX3
[04/04 17:32:20 923s] *info: (buf) CLKBUFX4

- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc

[04/04 17:32:20 923s] *info: (buf) BUFX4

- gpdk045wc

[04/04 17:32:20 923s] *info: (buf) BUFX6

- gpdk045wc

[04/04 17:32:20 923s] *info: (buf) CLKBUFX6

[04/04 17:32:20 923s] *info: (buf) BUFX8

- gpdk045wc
- gpdk045wc

[04/04 17:32:20 923s] *info: (buf) CLKBUFX8

[04/04 17:32:20 923s] *info: (buf) CLKBUFX12
[04/04 17:32:20 923s] *info: (buf) BUFX12
[04/04 17:32:20 923s] *info: (buf) CLKBUFX16
[04/04 17:32:20 923s] *info: (buf) BUFX16
[04/04 17:32:20 923s] *info: (buf) CLKBUFX20
[04/04 17:32:20 923s] *info: (buf) BUFX20

- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc

[04/04 17:32:20 923s] Core basic site is CoreSite

[04/04 17:32:20 923s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:32:20 924s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:32:20 924s] GigaOpt Hold Optimizer is used
[04/04 17:32:25 928s] gigaOpt Hold fixing search radius: 68.400000 Microns
(40 stdCellHgt)
[04/04 17:32:25 928s] *info: Run optDesign holdfix with 1 thread.
[04/04 17:32:25 928s] Starting initialization (fixHold) cpu=0:00:04.1
real=0:00:05.0 totSessionCpu=0:15:26 mem=1528.3M ***
[04/04 17:32:25 928s] Effort level <high> specified for reg2reg path_group
[04/04 17:32:25 928s] Effort level <high> specified for reg2cgate path_group
[04/04 17:32:25 928s] *info: Starting Blocking QThread with 1 CPU
[04/04 17:32:25 928s]
################################################
#################################
[04/04 17:32:25 928s] # Design Stage: PreRoute
[04/04 17:32:25 928s] # Design Mode: 90nm
[04/04 17:32:25 928s] # Analysis Mode: MMMC non-OCV
[04/04 17:32:25 928s] # Extraction Mode: default
[04/04 17:32:25 928s] # Delay Calculation Options: engine=aae
SIAware=false(opt_signoff)
[04/04 17:32:25 928s] # Switching Delay Calculation Engine to AAE

[04/04 17:32:25 928s]

################################################
#################################
[04/04 17:32:25 928s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:25 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...
[04/04 17:32:26 928s] Calculate delays in BcWc mode...

[04/04 17:32:26 928s] Topological Sorting (CPU = 0:00:00.0, MEM = 0.0M,

InitMEM = 0.0M)
[04/04 17:32:26 928s] *** Calculating scaling factor for
Arise_min_library_T0V132_set libraries using the default operating condition of
each library.
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:32 928s] AAE_THRD: End delay calculation. (MEM=109.355
CPU=0:00:06.5 REAL=0:00:06.0)
[04/04 17:32:32 928s] *** CDM Built up (cpu=0:00:07.4 real=0:00:07.0 mem=
109.4M) ***
[04/04 17:32:34 928s]
[04/04 17:32:34 928s] Active hold views:

[04/04 17:32:34 928s] Arise_analysis_view_func_min_cmin_T0V132

[04/04 17:32:34 928s] Dominating endpoints: 442
[04/04 17:32:34 928s] Dominating TNS: -25.239
[04/04 17:32:34 928s]
[04/04 17:32:34 928s] Done building cte hold timing graph (fixHold)
cpu=0:00:08.8 real=0:00:09.0 totSessionCpu=0:00:08.8 mem=109.4M ***
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102

[04/04 17:32:34 928s] Found active setup analysis view

Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:32:34 928s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13

[04/04 17:32:34 928s] Found active hold analysis view

Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:32:34 928s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:32:35 928s] Done building hold timer [1446 node(s), 1528 edge(s), 1
view(s)] (fixHold) cpu=0:00:09.8 real=0:00:10.0 totSessionCpu=0:00:09.8
mem=75.2M ***
[04/04 17:32:35 938s]
################################################
#################################

[04/04 17:32:35 938s] # Design Stage: PreRoute

[04/04 17:32:35 938s] # Design Mode: 90nm
[04/04 17:32:35 938s] # Analysis Mode: MMMC non-OCV
[04/04 17:32:35 938s] # Extraction Mode: default
[04/04 17:32:35 938s] # Delay Calculation Options: engine=aae
SIAware=false(opt_signoff)
[04/04 17:32:35 938s] # Switching Delay Calculation Engine to AAE
[04/04 17:32:35 938s]
################################################
#################################
[04/04 17:32:35 938s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...

[04/04 17:32:35 938s] Calculate delays in BcWc mode...

[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Calculate delays in BcWc mode...
[04/04 17:32:35 938s] Topological Sorting (CPU = 0:00:00.0, MEM = 1545.4M,
InitMEM = 1545.4M)
[04/04 17:32:35 938s] *** Calculating scaling factor for
Arise_max_library_T150V08_set libraries using the default operating condition of
each library.
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:42 945s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:32:42 945s] AAE_THRD: End delay calculation. (MEM=1745.32

CPU=0:00:06.5 REAL=0:00:06.0)
[04/04 17:32:42 945s] *** CDM Built up (cpu=0:00:07.2 real=0:00:07.0 mem=
1745.3M) ***
[04/04 17:32:43 946s] Done building cte setup timing graph (fixHold)
cpu=0:00:21.6 real=0:00:23.0 totSessionCpu=0:15:44 mem=1745.3M ***
[04/04 17:32:44 947s] *info: category slack lower bound [L -109.0] default
[04/04 17:32:44 947s] *info: category slack lower bound [H 0.0] reg2cgate
[04/04 17:32:44 947s] *info: category slack lower bound [H 0.0] reg2reg
[04/04 17:32:44 947s] --------------------------------------------------[04/04 17:32:44 947s]

Setup Violation Summary with Target Slack (0.000 ns)

[04/04 17:32:44 947s] --------------------------------------------------[04/04 17:32:44 947s]

[04/04 17:32:44 947s]

WNS
-0.109 ns

reg2regWNS
0.014 ns

[04/04 17:32:44 947s] --------------------------------------------------[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13

[04/04 17:32:44 947s] Found active setup analysis view

Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:32:44 947s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15

[04/04 17:32:44 947s] Found active hold analysis view

Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13

[04/04 17:32:44 947s] Found active hold analysis view

Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:32:44 947s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:32:45 948s]
-----------------------------------------------------------Initial Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.109 | 0.014 | 0.041 | -0.109 |

TNS (ns):| -17.358 | 0.000 | 0.000 | -17.358 |

|
|

Violating Paths:| 270 |

| 270 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.061 | 0.080 | 0.261 | -0.061 |

TNS (ns):| -0.240 | 0.000 | 0.000 | -0.240 |

|
|

Violating Paths:|

All Paths:| 521 | 432 | 12

| 82

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|

Real

Total

|
|

DRVs

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.066%
Routing Overflow: 0.00% H and 0.05% V
------------------------------------------------------------

[04/04 17:32:45 948s] *Info: minBufDelay = 0.060900 ns ; LibStdDelay =

0.011600 ns; minBufSize = 1710000 (5); worstDelayView:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11

[04/04 17:32:45 948s] Footprint list for hold buffering

[04/04 17:32:45 948s]
================================================
=================
[04/04 17:32:45 948s] *Info: holdDelay delayRatio IGArea drvRes
cellname(iterm,oterm)
[04/04 17:32:45 948s] -----------------------------------------------------------------[04/04 17:32:45 948s] *Info:

2.80 20.0 5.11 CLKBUFX16 (A,Y)

[04/04 17:32:45 948s] *Info:

23.3

2.80 20.0 5.11 BUFX16 (A,Y)

[04/04 17:32:45 948s] *Info:

109.5

[04/04 17:32:45 948s] *Info:

24.0

2.77 24.0 4.10 CLKBUFX20 (A,Y)

[04/04 17:32:45 948s] *Info:

24.0

2.77 24.0 4.10 BUFX20 (A,Y)

[04/04 17:32:45 948s] *Info:

153.0

3.27 24.0 77.11 DLY3X1 (A,Y)

[04/04 17:32:45 948s] *Info:

153.6

3.30 26.0 19.43 DLY3X4 (A,Y)

3.31 17.0 77.12 DLY2X1 (A,Y)

3.24 20.0 19.41 DLY2X4 (A,Y)

[04/04 17:32:45 948s] *Info:

196.1

3.30 29.0 76.73 DLY4X1 (A,Y)

[04/04 17:32:45 948s] *Info:

198.5

3.35 31.0 19.53 DLY4X4 (A,Y)

[04/04 17:32:45 948s]

================================================
=================
[04/04 17:32:45 948s] Info: 23 nets with fixed/cover wires excluded.
[04/04 17:32:45 948s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:32:46 949s] --------------------------------------------------[04/04 17:32:46 949s]

Hold Timing Summary - Initial

[04/04 17:32:46 949s] --------------------------------------------------[04/04 17:32:46 949s] Target slack: 0.000 ns

[04/04 17:32:46 949s] View: Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:32:46 949s]

WNS: -0.061

[04/04 17:32:46 949s]

TNS: -0.240

[04/04 17:32:46 949s]

VP: 5

[04/04 17:32:46 949s]

Worst hold path end point: read

[04/04 17:32:46 949s]

VP: 270

[04/04 17:32:46 949s] Worst setup path end

point:PROG_BUS_MACH_INST/RC_CG_HIER_INST28/RC_CGIC_INST/LATCH/SE
[04/04 17:32:46 949s] View: Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:32:46 949s]

WNS: -0.109

[04/04 17:32:46 949s]

TNS: -17.358

[04/04 17:32:46 949s]

VP: 270

[04/04 17:32:46 949s] Worst setup path end

point:PROG_BUS_MACH_INST/RC_CG_HIER_INST28/RC_CGIC_INST/LATCH/SE
[04/04 17:32:46 949s] --------------------------------------------------[04/04 17:32:46 949s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:32:46 949s]
[04/04 17:32:46 949s] *** Starting Core Fixing (fixHold) cpu=0:00:24.9
real=0:00:26.0 totSessionCpu=0:15:47 mem=1712.9M density=52.066% ***
[04/04 17:32:46 949s] Optimizer Target Slack 0.000 StdDelay is 0.012
[04/04 17:32:47 949s] Phase I ......
[04/04 17:32:47 949s] Executing transform: ECO Safe Resize
[04/04 17:32:47 949s]
+-----------------------------------------------------------------------------------------------+
[04/04 17:32:47 949s] Worst hold path end point: read net read nrTerm=3
[04/04 17:32:47 949s] | 0| -0.061|
52.07%| 0:00:27.0| 1713.9M|

-0.24|

0)|

[04/04 17:32:47 949s] Worst hold path end point: read net read nrTerm=3
[04/04 17:32:47 949s] | 1| -0.061|
52.07%| 0:00:27.0| 1714.9M|

-0.24|

0)|

[04/04 17:32:47 949s]

+-----------------------------------------------------------------------------------------------+
[04/04 17:32:47 949s] Executing transform: AddBuffer + LegalResize
[04/04 17:32:47 949s]
+-----------------------------------------------------------------------------------------------+

[04/04 17:32:47 949s] |Iter| WNS | TNS

Density | Real Time | Mem |

| #VP | #Buffer | #Resize(F/F) |

[04/04 17:32:47 949s]

+-----------------------------------------------------------------------------------------------+
[04/04 17:32:47 949s] Worst hold path end point: read net read nrTerm=3
[04/04 17:32:47 949s] | 0| -0.061|
52.07%| 0:00:27.0| 1714.9M|

-0.24|

0)|

[04/04 17:32:47 950s] Worst hold path end point: FE_PHC94_as/A net
FE_PHN93_as nrTerm=3
[04/04 17:32:47 950s] | 1| -0.001|
52.17%| 0:00:27.0| 1733.4M|

-0.00|

0)|

[04/04 17:32:47 950s] | 2| 0.000|

52.19%| 0:00:27.0| 1733.4M|

0.00|

0)|

[04/04 17:32:47 950s]

+-----------------------------------------------------------------------------------------------+
[04/04 17:32:47 950s]
[04/04 17:32:47 950s] *info:

Total 5 cells added for Phase I

[04/04 17:32:47 950s] *info:

Total 2 instances resized for Phase I

[04/04 17:32:47 950s] *info:

in which 0 FF resizing

[04/04 17:32:47 950s] --------------------------------------------------[04/04 17:32:47 950s]

Hold Timing Summary - Phase I

[04/04 17:32:47 950s] --------------------------------------------------[04/04 17:32:47 950s] Target slack: 0.000 ns

[04/04 17:32:47 950s] View: Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:32:47 950s]

WNS: 0.000

[04/04 17:32:47 950s]

TNS: 0.000

[04/04 17:32:47 950s]

VP: 0

[04/04 17:32:47 950s]

Worst hold path end point: port_as

[04/04 17:32:47 950s] --------------------------------------------------[04/04 17:32:47 950s]

in which 0 FF resizing

[04/04 17:32:47 950s] *info:

[04/04 17:32:48 950s] *** Starting refinePlace (0:15:48 mem=1733.4M) ***
[04/04 17:32:48 951s] *** Starting refinePlace (0:15:48 mem=1733.4M) ***
[04/04 17:32:48 951s] Total net length = 6.061e+04 (3.154e+04 2.907e+04)
(ext = 7.441e+03)
[04/04 17:32:48 951s] Starting refinePlace ...
[04/04 17:32:48 951s] Move report: placeLevelShifters moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:32:48 951s] Spread Effort: high, pre-route mode, useDDP on.
[04/04 17:32:48 951s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.0,
real=0:00:00.0, mem=1733.4MB) @(0:15:48 - 0:15:48).
[04/04 17:32:48 951s] Move report: preRPlace moves 0 insts, mean move: 0.00
um, max m
[04/04 17:32:48 951s] **optDesign ... cpu = 0:00:28, real = 0:00:29, mem =
1616.1M, totSessionCpu=0:15:49 **
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108

[04/04 17:32:48 951s] Found active setup analysis view

Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:32:48 951s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11

[04/04 17:32:48 951s] Found active hold analysis view

Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15

[04/04 17:32:48 951s] Found active hold analysis view

Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:32:48 951s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:32:48 951s] *info: Starting Blocking QThread with 1 CPU
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:32:56 951s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:32:56 951s] AAE_THRD: End delay calculation. (MEM=0
CPU=0:00:06.6 REAL=0:00:07.0)
[04/04 17:33:00 962s]
-----------------------------------------------------------optDesign Final Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.109 | 0.014 | 0.041 | -0.109 |

TNS (ns):| -17.358 | 0.000 | 0.000 | -17.358 |

|
|

Violating Paths:| 270 |

| 270 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| 0.001 | 0.080 | 0.261 | 0.001 |

TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 |

|
|

Violating Paths:|

All Paths:| 521 | 432 | 12

| 82

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|

Real

Total

|
|

DRVs

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.192%
Routing Overflow: 0.00% H and 0.05% V
-----------------------------------------------------------*** Final Summary (holdfix) CPU=0:00:10.2, REAL=0:00:12.0, MEM=1616.1M
[04/04 17:33:00 962s] **optDesign ... cpu = 0:00:38, real = 0:00:41, mem =
1614.1M, totSessionCpu=0:15:59 **
[04/04 17:33:00 962s] *** Finished optDesign ***
[04/04 17:33:00 962s]
[04/04 17:33:00 962s]
0:01:09 real= 0:01:13)

OPT_RUNTIME:

[04/04 17:33:00 962s] OPT_RUNTIME:

(cpu=0:00:00.4 real=0:00:00.4)

optDesign (count = 3): (cpu=

phyUpdate (count = 1):

[04/04 17:33:21 963s] <CMD> selectInst gopi_MPY_32

[04/04 17:33:22 963s] <CMD> deselectAll
[04/04 17:34:23 965s] <CMD> setNanoRouteMode -quiet -timingEngine {}
[04/04 17:34:23 965s] <CMD> setNanoRouteMode -quiet
-routeWithSiPostRouteFix 0
[04/04 17:34:23 965s] <CMD> setNanoRouteMode -quiet
-routeTopRoutingLayer 3
[04/04 17:34:23 965s] <CMD> setNanoRouteMode -quiet
-routeBottomRoutingLayer 1

[04/04 17:34:23 965s] <CMD> setNanoRouteMode -quiet -drouteEndIteration

default
[04/04 17:34:23 965s] <CMD> setNanoRouteMode -quiet
-routeWithTimingDriven false
[04/04 17:34:23 965s] <CMD> setNanoRouteMode -quiet -routeWithSiDriven
false
[04/04 17:34:23 965s] Running Native NanoRoute ...
[04/04 17:34:23 965s] <CMD> routeDesign -globalDetail
[04/04 17:34:23 965s] #routeDesign: cpu time = 00:00:00, elapsed time =
00:00:00, memory = 1430.98 (MB), peak = 1432.06 (MB)
[04/04 17:34:23 965s] #WARNING (NRIG-96) Selected single pass global detail
route "-globalDetail". Clock eco and post optimizations will not be run. See "man
NRIG-96" for more details.
[04/04 17:34:23 965s] Core basic site is CoreSite
[04/04 17:34:23 965s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:34:23 965s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:34:23 965s] Begin checking placement ... (start mem=1614.1M, init
mem=1614.1M)
[04/04 17:34:23 966s] *info: Placed = 2267

(Fixed = 284)

[04/04 17:34:23 966s] *info: Unplaced = 0

[04/04 17:34:23 966s] Placement Density:51.92%(7215/13897)
[04/04 17:34:23 966s] Finished checkPlace (cpu: total=0:00:00.1, vio
checks=0:00:00.0; mem=1614.1M)
[04/04 17:34:23 966s] #**INFO: honoring user setting for
routeWithTimingDriven set to false
[04/04 17:34:23 966s] #**INFO: honoring user setting for routeWithSiDriven set
to false
[04/04 17:34:23 966s]
[04/04 17:34:23 966s] changeUseClockNetStatus Option : -noFixedNetWires
[04/04 17:34:23 966s] *** Changed status on (23) nets in Clock.
[04/04 17:34:23 966s] *** End changeUseClockNetStatus (cpu=0:00:00.0,
real=0:00:00.0, mem=1614.1M) ***
[04/04 17:34:23 966s]

[04/04 17:34:23 966s] globalDetailRoute

[04/04 17:34:23 966s]
[04/04 17:34:23 966s] #setNanoRouteMode -drouteStartIteration 0
[04/04 17:34:23 966s] #setNanoRouteMode -routeBottomRoutingLayer 1
[04/04 17:34:23 966s] #setNanoRouteMode -routeTopRoutingLayer 3
[04/04 17:34:23 966s] #setNanoRouteMode -routeWithSiDriven false
[04/04 17:34:23 966s] #setNanoRouteMode -routeWithTimingDriven false
[04/04 17:34:23 966s] #Start globalDetailRoute on Mon Apr 4 17:34:23 2016
[04/04 17:34:23 966s] #
[04/04 17:34:23 966s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 17:34:23 966s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:23 966s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:23 966s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 17:34:23 966s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:23 966s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DATA_BUS_MACH_INST/as_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (102.300 205.865) on LAYER Metal1. The location is not
inside the pin geometry extraction.

[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK

of INST DATA_BUS_MACH_INST/write_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (111.500 204.535) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DATA_BUS_MACH_INST/present_state_reg[1]/state_remap/DFF connects to
NET clk__L4_N0 at location (111.900 197.695) on LAYER Metal1. The location is
not inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DATA_BUS_MACH_INST/read_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (110.700 205.865) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DATA_BUS_MACH_INST/bus_request_reg/state_remap/DFF connects to
NET clk__L4_N0 at location (101.900 204.535) on LAYER Metal1. The location is
not inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DATA_BUS_MACH_INST/present_state_reg[2]/state_remap/DFF connects to
NET clk__L4_N0 at location (102.100 201.115) on LAYER Metal1. The location is
not inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DATA_BUS_MACH_INST/present_state_reg[0]/state_remap/DFF connects to
NET clk__L4_N0 at location (103.300 192.185) on LAYER Metal1. The location is
not inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST PORT_BUS_MACH_INST/present_state_reg[0]/state_remap/DFF connects
to NET clk__L4_N0 at location (104.300 180.595) on LAYER Metal1. The location
is not inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST PORT_BUS_MACH_INST/as_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (102.500 177.175) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DECODE_INST/read_port_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (101.300 172.045) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DECODE_INST/go_data_reg/state_remap/DFF connects to NET clk__L4_N0
at location (93.300 171.665) on LAYER Metal1. The location is not inside the pin
geometry extraction.

[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK

of INST DECODE_INST/go_port_reg/state_remap/DFF connects to NET clk__L4_N0
at location (93.100 168.245) on LAYER Metal1. The location is not inside the pin
geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DECODE_INST/go_prog_reg/state_remap/DFF connects to NET clk__L4_N0
at location (96.100 164.825) on LAYER Metal1. The location is not inside the pin
geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST DECODE_INST/two_cycle_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (93.100 163.495) on LAYER Metal1. The location is not
inside the pin geometry extraction.

[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK

of INST PROG_BUS_MACH_INST/present_state_reg[1]/state_remap/DFF connects
to NET clk__L4_N0 at location (93.300 157.985) on LAYER Metal1. The location is
not inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST EXECUTE_INST/read_prog_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (91.500 144.305) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST EXECUTE_INST/branch_stall_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (88.700 137.465) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST EXECUTE_INST/update_it_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (86.300 136.135) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST EXECUTE_INST/two_cycle_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (72.700 132.715) on LAYER Metal1. The location is not
inside the pin geometry extraction.
[04/04 17:34:23 966s] #WARNING (NRDB-682) Connectivity is broken at PIN CK
of INST EXECUTE_INST/skip_one_reg/state_remap/DFF connects to NET
clk__L4_N0 at location (60.100 130.625) on LAYER Metal1. The location is not
inside the pin geometry extraction.

[04/04 17:34:23 966s] #WARNING (EMS-27) Message (NRDB-682) has exceeded

the current message display limit of 20.

[04/04 17:34:23 966s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET clk__L4_N0 has LVS
problem. The integrity of the wires will be checked. NanoRoute will continue.
Check the net for FIXED or misaligned routing connections. If necessary, skip this
net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
DATA_BUS_MACH_INST/rc_gclk has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
DECODE_INST/rc_gclk has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11913 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11916 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11919 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11922 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11925 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:23 966s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11928 has LVS problem. The integrity of the wires will be

0.445

H Track-Pitch = 0.285

Line-2-Via Pitch =

[04/04 17:34:26 969s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:34:26 969s] # Metal8
0.385

V Track-Pitch = 0.200

Line-2-Via Pitch =

[04/04 17:34:26 969s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:34:26 969s] # Metal9
0.385

H Track-Pitch = 0.380

Line-2-Via Pitch =

[04/04 17:34:26 969s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:34:26 969s] #ERROR (NRDB-954) Invalid option value
-routeTopRoutingLayer 3. It is in conflict with already existing routed wires on
layer 4. The option must specify a layer equal to or above the top-most layer for
existing routes.
[04/04 17:34:26 969s] ### Ignoring a total of 1 master slice layers:
[04/04 17:34:26 969s] ### Oxide
[04/04 17:34:26 969s] #Cpu time = 00:00:04
[04/04 17:34:26 969s] #Elapsed time = 00:00:04
[04/04 17:34:26 969s] #Increased memory = -151.29 (MB)
[04/04 17:34:26 969s] #Total memory = 1279.74 (MB)
[04/04 17:34:26 969s] #Peak memory = 1463.79 (MB)
[04/04 17:34:26 969s] #WARNING (NRIF-19) Failed to complete
globalDetailRoute on Mon Apr 4 17:34:26 2016
[04/04 17:34:26 969s] #
[04/04 17:34:26 969s] #routeDesign: cpu time = 00:00:04, elapsed time =
00:00:04, memory = 1279.74 (MB), peak = 1463.79 (MB)

[04/04 17:34:26 969s] *** Message Summary: 0 warning(s), 0 error(s)

[04/04 17:34:26 969s]
[04/04 17:34:26 969s] 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM0 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM1Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM1 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM2Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM2 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM3Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM3 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM4Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM4 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM5Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM5 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM6Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM6 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM7Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM7 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM8Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM8 -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM9Cont -isVisible 1
[04/04 17:34:38 969s] <CMD> setLayerPreference allM9 -isVisible 1
[04/04 17:34:40 970s] <CMD> zoomBox 138.418 134.464 145.944 115.196
[04/04 17:34:44 970s] <CMD> fit
[04/04 17:34:56 971s] <CMD> setNanoRouteMode -quiet
-routeTopRoutingLayer 5
[04/04 17:34:56 971s] <CMD> setNanoRouteMode -quiet -drouteEndIteration
default

[04/04 17:34:56 971s] <CMD> setNanoRouteMode -quiet

-routeWithTimingDriven false
[04/04 17:34:56 971s] <CMD> setNanoRouteMode -quiet -routeWithSiDriven
false
[04/04 17:34:56 971s] Running Native NanoRoute ...
[04/04 17:34:56 971s] <CMD> routeDesign -globalDetail
[04/04 17:34:56 971s] #routeDesign: cpu time = 00:00:00, elapsed time =
00:00:00, memory = 1279.74 (MB), peak = 1463.79 (MB)
[04/04 17:34:56 971s] #WARNING (NRIG-96) Selected single pass global detail
route "-globalDetail". Clock eco and post optimizations will not be run. See "man
NRIG-96" for more details.
[04/04 17:34:56 971s] Core basic site is CoreSite
[04/04 17:34:56 971s] **Info: (ENCSP-307): Design contains fractional 153 cells.
[04/04 17:34:56 971s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:34:56 971s] Begin checking placement ... (start mem=1462.0M, init
mem=1462.0M)
[04/04 17:34:56 971s] *info: Placed = 2267

(Fixed = 284)

[04/04 17:34:56 971s] *info: Unplaced = 0

[04/04 17:34:56 971s] Placement Density:51.92%(7215/13897)
[04/04 17:34:56 971s] Finished checkPlace (cpu: total=0:00:00.1, vio
checks=0:00:00.0; mem=1462.0M)
[04/04 17:34:56 971s] #**INFO: honoring user setting for
routeWithTimingDriven set to false
[04/04 17:34:56 971s] #**INFO: honoring user setting for routeWithSiDriven set
to false
[04/04 17:34:56 971s]
[04/04 17:34:56 971s] changeUseClockNetStatus Option : -noFixedNetWires
[04/04 17:34:56 971s] *** Changed status on (0) nets in Clock.
[04/04 17:34:56 971s] *** End changeUseClockNetStatus (cpu=0:00:00.0,
real=0:00:00.0, mem=1462.0M) ***
[04/04 17:34:56 971s]
[04/04 17:34:56 971s] globalDetailRoute

[04/04 17:34:56 971s]

[04/04 17:34:56 971s] #setNanoRouteMode -drouteStartIteration 0
[04/04 17:34:56 971s] #setNanoRouteMode -routeBottomRoutingLayer 1
[04/04 17:34:56 971s] #setNanoRouteMode -routeTopRoutingLayer 5
[04/04 17:34:56 971s] #setNanoRouteMode -routeWithSiDriven false
[04/04 17:34:56 971s] #setNanoRouteMode -routeWithTimingDriven false
[04/04 17:34:56 971s] #Start globalDetailRoute on Mon Apr 4 17:34:56 2016
[04/04 17:34:56 971s] #
[04/04 17:34:56 971s] ### Ignoring a total of 1 master slice layers:
[04/04 17:34:56 971s] ### Oxide
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[0] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[1] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[2] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[3] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[4] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[5] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[6] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[7] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[8] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[9] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[10] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.

[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[11] in CELL_VIEW

mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[12] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[13] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[14] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[15] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[16] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[17] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[18] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (NRDB-728) PIN result[19] in CELL_VIEW
mult_32_pg3 does not have antenna diff area.
[04/04 17:34:56 971s] #WARNING (EMS-27) Message (NRDB-728) has exceeded
the current message display limit of 20.
[04/04 17:34:56 971s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 17:34:56 972s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.
[04/04 17:34:56 972s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:56 972s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:56 972s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance gopi_MPY_32 is not connected to any power/ground net. Use command
globalNetConnect to connect the power/ground pin to a power/ground net.

[04/04 17:34:56 972s] #WARNING (NRIG-34) Power/Ground pin V_Core of

instance suraj_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:56 972s] #WARNING (NRIG-34) Power/Ground pin V_Core of
instance ashok_MPY_32_INST is not connected to any power/ground net. Use
command globalNetConnect to connect the power/ground pin to a power/ground
net.
[04/04 17:34:56 972s] #WARNING (NRIG-44) Imported NET clk__L4_N0 has LVS
problem. The integrity of the wires will be checked. NanoRoute will continue.
Check the net for FIXED or misaligned routing connections. If necessary, skip this
net or delete the net routing.
[04/04 17:34:56 972s] #WARNING (NRIG-44) Imported NET
DATA_BUS_MACH_INST/rc_gclk has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:56 972s] #WARNING (NRIG-44) Imported NET
DECODE_INST/rc_gclk has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:56 972s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:56 972s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11913 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:56 972s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11916 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:56 972s] #WARNING (NRIG-44) Imported NET
EXECUTE_INST/rc_gclk_11919 has LVS problem. The integrity of the wires will be
checked. NanoRoute will continue. Check the net for FIXED or misaligned routing
connections. If necessary, skip this net or delete the net routing.
[04/04 17:34:56 972s] #WARNING (EMS-27) Message (NRIG-44) has exceeded
the current message display limit of 20.
[04/04 17:34:56 972s] #To increase the message display limit, refer to the
product command reference manual.

V Track-Pitch = 0.200

Line-2-Via Pitch =

[04/04 17:34:59 975s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:34:59 975s] # Metal9
0.385

H Track-Pitch = 0.380

Line-2-Via Pitch =

[04/04 17:34:59 975s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:34:59 975s] #Regenerating Ggrids automatically.
[04/04 17:34:59 975s] #Auto generating G-grids with size=15 tracks, using
layer Metal2's pitch = 0.200.
[04/04 17:34:59 975s] #Using automatically generated G-grids.
[04/04 17:34:59 975s] #Done routing data preparation.

[04/04 17:34:59 975s] #cpu time = 00:00:03, elapsed time = 00:00:03,

memory = 1155.07 (MB), peak = 1463.79 (MB)
[04/04 17:34:59 975s] #Merging special wires...
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (203.135 100.130) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk.
The NET is considered partially routed. Visually verify wiring at the specified
location as the wire/via origin may not touch the PIN. This NET will be rerouted
with same or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (203.135 93.290) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk. The
NET is considered partially routed. Visually verify wiring at the specified location
as the wire/via origin may not touch the PIN. This NET will be rerouted with same
or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (202.335 98.225) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk. The
NET is considered partially routed. Visually verify wiring at the specified location
as the wire/via origin may not touch the PIN. This NET will be rerouted with same
or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (202.935 91.385) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk. The
NET is considered partially routed. Visually verify wiring at the specified location
as the wire/via origin may not touch the PIN. This NET will be rerouted with same
or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (194.735 101.645) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk.
The NET is considered partially routed. Visually verify wiring at the specified
location as the wire/via origin may not touch the PIN. This NET will be rerouted
with same or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (186.735 101.645) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk.
The NET is considered partially routed. Visually verify wiring at the specified
location as the wire/via origin may not touch the PIN. This NET will be rerouted
with same or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (183.935 98.225) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk. The
NET is considered partially routed. Visually verify wiring at the specified location
as the wire/via origin may not touch the PIN. This NET will be rerouted with same
or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (184.535 94.805) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk. The
NET is considered partially routed. Visually verify wiring at the specified location

as the wire/via origin may not touch the PIN. This NET will be rerouted with same
or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (185.935 91.385) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk. The
NET is considered partially routed. Visually verify wiring at the specified location
as the wire/via origin may not touch the PIN. This NET will be rerouted with same
or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (186.335 100.130) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk.
The NET is considered partially routed. Visually verify wiring at the specified
location as the wire/via origin may not touch the PIN. This NET will be rerouted
with same or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (184.735 103.550) on Metal1 for NET DATA_BUS_MACH_INST/rc_gclk.
The NET is considered partially routed. Visually verify wiring at the specified
location as the wire/via origin may not touch the PIN. This NET will be rerouted
with same or different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (159.735 113.810) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (158.535 110.390) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (152.735 91.385) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (153.935 93.290) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (154.335 98.225) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.

[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to

PIN CK at (98.335 148.010) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (146.135 113.810) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (159.935 108.775) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (NRDB-1005) Cannot establish connection to
PIN CK at (161.135 101.935) on Metal1 for NET DECODE_INST/rc_gclk. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:34:59 975s] #WARNING (EMS-27) Message (NRDB-1005) has
exceeded the current message display limit of 20.
[04/04 17:34:59 975s] #To increase the message display limit, refer to the
product command reference manual.
[04/04 17:34:59 975s] #13 routed nets are extracted.
[04/04 17:34:59 975s] #

13 (0.49%) extracted nets are partially routed.

[04/04 17:34:59 975s] #10 routed nets are imported.

[04/04 17:34:59 975s] #2329 (87.00%) nets are without wires.
[04/04 17:34:59 975s] #325 nets are fixed|skipped|trivial (not extracted).
[04/04 17:34:59 975s] #Total number of nets = 2677.
[04/04 17:34:59 975s] #Number of eco nets is 13
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] #Start data preparation...
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] #Data preparation is done on Mon Apr 4 17:34:59 2016
[04/04 17:34:59 975s] #

[04/04 17:34:59 975s] #Analyzing routing resource...

[04/04 17:34:59 975s] #Routing resource analysis is done on Mon Apr 4
17:34:59 2016
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] # Resource Analysis:
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] # Layer
Blocked

Routing #Avail
Direction Track

379

111

4900

18.98%

[04/04 17:34:59 975s] # -------------------------------------------------------------[04/04 17:34:59 975s] # Total

2770

57.07% 39200

54.52%

[04/04 17:34:59 975s] #

[04/04 17:34:59 975s] # 23 nets (0.86%) with 1 preferred extra spacing.
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1155.91 (MB), peak = 1463.79 (MB)
[04/04 17:34:59 975s] #
[04/04 17:34:59 975s] #start global routing iteration 1...
[04/04 17:35:01 976s] #cpu time = 00:00:01, elapsed time = 00:00:01,
memory = 1165.56 (MB), peak = 1463.79 (MB)

[04/04 17:35:01 976s] #

[04/04 17:35:01 976s] #start global routing iteration 2...
[04/04 17:35:01 977s] #cpu time = 00:00:01, elapsed time = 00:00:01,
memory = 1165.63 (MB), peak = 1463.79 (MB)
[04/04 17:35:01 977s] #
[04/04 17:35:01 977s] #
[04/04 17:35:01 977s] #Total number of trivial nets (e.g. < 2 pins) = 325
(skipped).
[04/04 17:35:01 977s] #Total number of routable nets = 2352.
[04/04 17:35:01 977s] #Total number of nets in the design = 2677.
[04/04 17:35:01 977s] #
[04/04 17:35:01 977s] #2342 routable nets have only global wires.
[04/04 17:35:01 977s] #10 routable nets have only detail routed wires.
[04/04 17:35:01 977s] #13 global routed or unrouted (routable) nets have been
constrained (e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:35:01 977s] #10 detail routed (routable) nets have been constrained
(e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:35:01 977s] #
[04/04 17:35:01 977s] #Routed nets constraints summary:
[04/04 17:35:01 977s] #-----------------------------------------------[04/04 17:35:01 977s] #

Rules Pref Extra Space Unconstrained

(1-2)

OverCon
#Gcell

(3-4)

0(0.00%) (0.00%)

0(0.00%)

30(1.75%)

0(0.00%)
22(1.29%)

[04/04 17:35:01 977s] # --------------------------------------------------------------------------

[04/04 17:35:01 977s] #

14(0.08%) (0.65%)

Total

50(0.28%)

30(0.17%)

1576

[04/04 17:35:02 978s] # Metal 4

623

[04/04 17:35:02 978s] #----------------------[04/04 17:35:02 978s] #

16822

[04/04 17:35:02 978s] #

[04/04 17:35:02 978s] #cpu time = 00:00:01, elapsed time = 00:00:01,
memory = 1133.65 (MB), peak = 1463.79 (MB)
[04/04 17:35:02 978s] #
[04/04 17:35:02 978s] #Cpu time = 00:00:06
[04/04 17:35:02 978s] #Elapsed time = 00:00:06
[04/04 17:35:02 978s] #Increased memory = 13.25 (MB)
[04/04 17:35:02 978s] #Total memory = 1133.65 (MB)
[04/04 17:35:02 978s] #Peak memory = 1463.79 (MB)
[04/04 17:35:03 979s] #
[04/04 17:35:03 979s] #Start Detail Routing..
[04/04 17:35:03 979s] #start initial detail routing ...
[04/04 17:35:20 995s] #

number of violations = 3

[04/04 17:35:20 995s] #

By Layer and Type :

[04/04 17:35:20 995s] #

Short

Loop Totals

[04/04 17:35:20 995s] #Metal1

[04/04 17:35:20 995s] #Metal2

[04/04 17:35:20 995s] #Totals

[04/04 17:35:20 995s] #1992 out of 2267 instances need to be verified(marked

ipoed).
[04/04 17:35:21 997s] #

number of violations = 3

[04/04 17:35:21 997s] #

By Layer and Type :

[04/04 17:35:21 997s] #

Short

Loop Totals

[04/04 17:35:22 997s] #Totals

[04/04 17:35:22 997s] #

number of process antenna violations = 10

[04/04 17:35:22 997s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1202.84 (MB), peak = 1463.79 (MB)
[04/04 17:35:22 997s] #start 7th optimization iteration ...
[04/04 17:35:22 998s] #

number of violations = 2

[04/04 17:35:22 998s] #

[04/04 17:35:22 998s] #
[04/04 17:35:22 998s] #

By Layer and Type :

Short Totals

[04/04 17:35:22 998s] #Metal1

[04/04 17:35:22 998s] #Metal2

[04/04 17:35:22 998s] #Totals

[04/04 17:35:23 998s] #

number of violations = 2

[04/04 17:35:23 998s] #

By Layer and Type :

[04/04 17:35:23 998s] #

Short Totals

[04/04 17:35:23 998s] #Metal1

[04/04 17:35:23 998s] #Metal2

[04/04 17:35:23 998s] #Totals

single-cut

multi-cut

Total

[04/04 17:35:23 998s] #----------------------------------------------------------[04/04 17:35:23 998s] # Metal 1

9086 ( 95.8%)

399 ( 4.2%)

[04/04 17:35:23 998s] # Metal 2

6175 (100.0%)

0 ( 0.0%)

6175

[04/04 17:35:23 998s] # Metal 3

1435 (100.0%)

0 ( 0.0%)

1435

[04/04 17:35:23 998s] # Metal 4

613 (100.0%)

0 ( 0.0%)

9485

613

[04/04 17:35:23 998s] #----------------------------------------------------------[04/04 17:35:23 998s] #

17309 ( 97.7%)

399 ( 2.3%)

17708

[04/04 17:35:23 998s] #

[04/04 17:35:23 998s] #Total number of DRC violations = 2
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal1 = 0
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:35:23 998s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:35:23 998s] #Cpu time = 00:00:21
[04/04 17:35:23 998s] #Elapsed time = 00:00:21
[04/04 17:35:23 998s] #Increased memory = 80.05 (MB)
[04/04 17:35:23 998s] #Total memory = 1213.70 (MB)
[04/04 17:35:23 998s] #Peak memory = 1463.79 (MB)
[04/04 17:35:23 998s] #
[04/04 17:35:23 998s] #Start Post Routing Optimization.
[04/04 17:35:23 999s] #start 1st post routing optimization iteration ...
[04/04 17:35:24 1000s] #

number of DRC violations = 2

[04/04 17:35:24 1000s] #

By Layer and Type :

single-cut

multi-cut

Total

[04/04 17:35:24 1000s] #----------------------------------------------------------[04/04 17:35:24 1000s] # Metal 1

9086 ( 95.8%)

399 ( 4.2%)

[04/04 17:35:24 1000s] # Metal 2

6175 (100.0%)

0 ( 0.0%)

6175

[04/04 17:35:24 1000s] # Metal 3

1435 (100.0%)

0 ( 0.0%)

1435

[04/04 17:35:24 1000s] # Metal 4

613 (100.0%)

0 ( 0.0%)

[04/04 17:35:24 1000s] #-----------------------------------------------------------

9485

613

[04/04 17:35:24 1000s] #

17309 ( 97.7%)

399 ( 2.3%)

17708

[04/04 17:35:24 1000s] #

[04/04 17:35:24 1000s] #Total number of DRC violations = 2
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal1 = 0
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:35:24 1000s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:35:24 1000s] #
[04/04 17:35:24 1000s] #start routing for process antenna violation fix ...
[04/04 17:35:26 1001s] #
[04/04 17:35:26 1001s] #

By Layer and Type :

[04/04 17:35:26 1001s] #

Short Totals

[04/04 17:35:26 1001s] #

Metal1

[04/04 17:35:26 1001s] #

Metal2

[04/04 17:35:26 1001s] #

Totals

[04/04 17:35:26 1001s] #cpu time = 00:00:02, elapsed time = 00:00:02,

memory = 1136.40 (MB), peak = 1463.79 (MB)
[04/04 17:35:26 1001s] #
[04/04 17:35:26 1001s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:35:26 1001s] #Total wire length = 69961 um.
[04/04 17:35:26 1001s] #Total half perimeter of net bounding box = 61163 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal1 = 4843 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal2 = 17516 um.

[04/04 17:35:26 1001s] #Total wire length on LAYER Metal3 = 21640 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal4 = 15421 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal5 = 10541 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:35:26 1001s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:35:26 1001s] #Total number of vias = 17708
[04/04 17:35:26 1001s] #Total number of multi-cut vias = 399 ( 2.3%)
[04/04 17:35:26 1001s] #Total number of single cut vias = 17309 ( 97.7%)
[04/04 17:35:26 1001s] #Up-Via Summary (total 17708):
[04/04 17:35:26 1001s] #

[04/04 17:35:26 1001s] #Total number of DRC violations = 2
[04/04 17:35:26 1001s] #Total number of net violated process antenna rule = 2
[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal1 = 0
[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal6 = 0

[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal7 = 0

[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:35:26 1001s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:35:26 1001s] #
[04/04 17:35:26 1001s] #
[04/04 17:35:26 1001s] #start delete and reroute for process antenna violation
fix ...
[04/04 17:35:33 1009s] #cpu time = 00:00:07, elapsed time = 00:00:08,
memory = 1137.36 (MB), peak = 1463.79 (MB)
[04/04 17:35:33 1009s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:35:33 1009s] #Total wire length = 69952 um.
[04/04 17:35:33 1009s] #Total half perimeter of net bounding box = 61163 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal1 = 4851 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal2 = 17505 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal3 = 22031 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal4 = 15427 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal5 = 10138 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:35:33 1009s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:35:33 1009s] #Total number of vias = 17732
[04/04 17:35:33 1009s] #Total number of multi-cut vias = 399 ( 2.3%)
[04/04 17:35:33 1009s] #Total number of single cut vias = 17333 ( 97.7%)
[04/04 17:35:33 1009s] #Up-Via Summary (total 17732):
[04/04 17:35:33 1009s] #

[04/04 17:35:33 1009s] #Total number of DRC violations = 2
[04/04 17:35:33 1009s] #Total number of net violated process antenna rule = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal1 = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:35:33 1009s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:35:33 1009s] #
[04/04 17:35:34 1010s] #
[04/04 17:35:34 1010s] #Start Post Route wire spreading..
[04/04 17:35:34 1010s] #
[04/04 17:35:34 1010s] #Start data preparation for wire spreading...
[04/04 17:35:34 1010s] #
[04/04 17:35:34 1010s] #Data preparation is done on Mon Apr 4 17:35:34 2016
[04/04 17:35:34 1010s] #
[04/04 17:35:34 1010s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1137.36 (MB), peak = 1463.79 (MB)
[04/04 17:35:34 1010s] #

[04/04 17:35:34 1010s] #Spread distance (# of tracks): min = 0.500000; max =

2.000000
[04/04 17:35:35 1010s] #
[04/04 17:35:35 1010s] #Start Post Route Wire Spread.
[04/04 17:35:35 1010s] #Done with 1965 horizontal wires in 2 hboxes and 1580
vertical wires in 2 hboxes.
[04/04 17:35:35 1010s] #Complete Post Route Wire Spread.
[04/04 17:35:35 1010s] #
[04/04 17:35:35 1010s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:35:35 1010s] #Total wire length = 71376 um.
[04/04 17:35:35 1010s] #Total half perimeter of net bounding box = 61163 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal1 = 4899 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal2 = 17908 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal3 = 22710 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal4 = 15643 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal5 = 10216 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:35:35 1010s] #Total number of vias = 17732
[04/04 17:35:35 1010s] #Total number of multi-cut vias = 399 ( 2.3%)
[04/04 17:35:35 1010s] #Total number of single cut vias = 17333 ( 97.7%)
[04/04 17:35:35 1010s] #Up-Via Summary (total 17732):
[04/04 17:35:35 1010s] #

single-cut

multi-cut

Total

[04/04 17:35:35 1010s] #----------------------------------------------------------[04/04 17:35:35 1010s] # Metal 1

9092 ( 95.8%)

[04/04 17:35:35 1010s] # Metal 2

6199 (100.0%)

399 ( 4.2%)
0 ( 0.0%)

9491
6199

[04/04 17:35:35 1010s] # Metal 3

1444 (100.0%)

[04/04 17:35:35 1010s] # Metal 4

598 (100.0%)

0 ( 0.0%)

1444

0 ( 0.0%)

598

[04/04 17:35:35 1010s] #----------------------------------------------------------[04/04 17:35:35 1010s] #

17333 ( 97.7%)

399 ( 2.3%)

17732

[04/04 17:35:35 1010s] #

[04/04 17:35:35 1010s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1147.84 (MB), peak = 1463.79 (MB)
[04/04 17:35:35 1010s] #
[04/04 17:35:35 1010s] #Post Route wire spread is done.
[04/04 17:35:35 1010s] #Total number of nets with non-default rule or having
extra spacing = 23
[04/04 17:35:35 1010s] #Total wire length = 71376 um.
[04/04 17:35:35 1010s] #Total half perimeter of net bounding box = 61163 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal1 = 4899 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal2 = 17908 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal3 = 22710 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal4 = 15643 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal5 = 10216 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:35:35 1010s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:35:35 1010s] #Total number of vias = 17732
[04/04 17:35:35 1010s] #Total number of multi-cut vias = 399 ( 2.3%)
[04/04 17:35:35 1010s] #Total number of single cut vias = 17333 ( 97.7%)
[04/04 17:35:35 1010s] #Up-Via Summary (total 17732):
[04/04 17:35:35 1010s] #

[04/04 17:35:36 1011s] #
[04/04 17:35:36 1011s] #Start DRC checking..
[04/04 17:35:38 1013s] #

number of violations = 2

[04/04 17:35:38 1013s] #

By Layer and Type :

[04/04 17:35:38 1013s] #

Short Totals

[04/04 17:35:38 1013s] #

Metal1

[04/04 17:35:38 1013s] #

Metal2

[04/04 17:35:38 1013s] #

Totals

[04/04 17:35:38 1013s] #cpu time = 00:00:02, elapsed time = 00:00:02,

memory = 1202.60 (MB), peak = 1463.79 (MB)
[04/04 17:35:38 1013s] #

number of violations = 2

[04/04 17:35:38 1013s] #

By Layer and Type :

RC Corner Indexes

[04/04 17:36:52 1017s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:36:52 1017s] Coupling Cap. Scaling Factor : 1.00000 1.00000
[04/04 17:36:52 1017s] Resistance Scaling Factor

[04/04 17:36:53 1018s] Number of Extracted Ground Cap. : 54904

[04/04 17:36:53 1018s] Number of Extracted Coupling Cap. : 98936
[04/04 17:36:53 1018s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:36:53 1018s] Filtering XCap in 'relativeOnly' mode using values
relative_c_threshold=0.03 and total_c_threshold=5fF.
[04/04 17:36:53 1018s] Corner: Arise_rc_corner_cmax
[04/04 17:36:53 1018s] Corner: Arise_rc_corner_cmin
[04/04 17:36:53 1018s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
1396.8M)
[04/04 17:36:53 1018s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb_Filter.rcdb.d' for storing RC.
[04/04 17:36:53 1018s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2352 times net's RC data read were
performed.
[04/04 17:36:53 1018s] Lumped Parasitic Loading Started (total cpu=0:00:00.0,
real=0:00:00.0, current mem=1394.594M)
[04/04 17:36:53 1018s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.

[04/04 17:36:53 1018s] Lumped Parasitic Loading Completed (total

cpu=0:00:00.0, real=0:00:00.0, current mem=1390.594M)
[04/04 17:36:53 1018s] PostRoute (effortLevel low) RC Extraction DONE (CPU
Time: 0:00:01.0 Real Time: 0:00:01.0 MEM: 1390.594M)
[04/04 17:36:53 1018s] Generate Setup TimingWindows
[04/04 17:36:53 1018s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:36:53 1018s] SI iteration 1 ...
[04/04 17:36:53 1018s]
################################################
#################################
[04/04 17:36:53 1018s] # Design Stage: PostRoute
[04/04 17:36:53 1018s] # Design Mode: 90nm
[04/04 17:36:53 1018s] # Analysis Mode: MMMC OCV
[04/04 17:36:53 1018s] # Extraction Mode: detail/spef
[04/04 17:36:53 1018s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:36:53 1018s] # Switching Delay Calculation Engine to AAE-SI
[04/04 17:36:53 1018s]
################################################
#################################
[04/04 17:36:54 1019s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:36:54 1019s] Setting infinite Tws ...
[04/04 17:36:54 1019s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1404.2M)
[04/04 17:36:54 1019s]

First Iteration Infinite Tw...

[04/04 17:36:54 1019s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1404.2M)
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...

[04/04 17:36:54 1019s] Calculate early delays in OCV mode...

[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...

[04/04 17:36:54 1019s] Calculate early delays in OCV mode...

[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Calculate early delays in OCV mode...
[04/04 17:36:54 1019s] Calculate late delays in OCV mode...
[04/04 17:36:54 1019s] Topological Sorting (CPU = 0:00:00.0, MEM = 1404.2M,
InitMEM = 1404.2M)
[04/04 17:36:54 1019s] Initializing multi-corner capacitance tables ...
[04/04 17:36:54 1019s] Initializing multi-corner resistance tables ...
[04/04 17:36:54 1019s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:36:54 1019s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1776.2M)
[04/04 17:36:54 1019s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:36:56 1021s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:36:57 1022s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:36:58 1023s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:36:59 1024s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis

[04/04 17:37:00 1025s] AAE_INFO-618: Total number of nets in the design is

2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:01 1026s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:02 1027s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:03 1028s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:04 1029s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:05 1030s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:06 1031s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:07 1032s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:07 1032s] AAE_THRD: End delay calculation. (MEM=1816.04
CPU=0:00:12.1 REAL=0:00:12.0)
[04/04 17:37:07 1032s] *** CDM Built up (cpu=0:00:13.9 real=0:00:14.0
mem= 1816.0M) ***
[04/04 17:37:09 1033s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1816.0M)
[04/04 17:37:09 1033s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:37:09 1034s] Loading CTE timing window is completed (CPU =
0:00:00.1, REAL = 0:00:00.0, MEM = 1777.9M)
[04/04 17:37:09 1034s] SI iteration 2 ...
[04/04 17:37:09 1034s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...

[04/04 17:37:09 1034s] Calculate late delays in OCV mode...

[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:09 1034s] Calculate early delays in OCV mode...

[04/04 17:37:09 1034s] Calculate late delays in OCV mode...

[04/04 17:37:09 1034s] Calculate early delays in OCV mode...
[04/04 17:37:09 1034s] Calculate late delays in OCV mode...
[04/04 17:37:11 1035s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:12 1036s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:13 1038s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:14 1039s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:15 1040s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:16 1041s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:18 1042s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:19 1044s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:20 1045s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:21 1046s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:22 1047s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:23 1048s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:23 1048s] AAE_THRD: End delay calculation. (MEM=2003.09
CPU=0:00:14.0 REAL=0:00:14.0)
[04/04 17:37:23 1048s] *** CDM Built up (cpu=0:00:14.3 real=0:00:14.0
mem= 2003.1M) ***
[04/04 17:37:24 1049s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but
to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".
[04/04 17:37:24 1049s] Effort level <high> specified for reg2reg path_group
[04/04 17:37:24 1049s] Effort level <high> specified for reg2cgate path_group
[04/04 17:37:24 1049s] Begin: glitch net info
[04/04 17:37:24 1049s] glitch slack range: number of glitch nets
[04/04 17:37:24 1049s] glitch slack < -0.32 : 0
[04/04 17:37:24 1049s] -0.32 < glitch slack < -0.28 : 0
[04/04 17:37:24 1049s] -0.28 < glitch slack < -0.24 : 0
[04/04 17:37:24 1049s] -0.24 < glitch slack < -0.2 : 0
[04/04 17:37:24 1049s] -0.2 < glitch slack < -0.16 : 0

[04/04 17:37:24 1049s] -0.16 < glitch slack < -0.12 : 0

[04/04 17:37:24 1049s] -0.12 < glitch slack < -0.08 : 0
[04/04 17:37:24 1049s] -0.08 < glitch slack < -0.04 : 0
[04/04 17:37:24 1049s] -0.04 < glitch slack : 0
[04/04 17:37:24 1049s] End: glitch net info
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102

[04/04 17:37:24 1049s] Found active setup analysis view

Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:37:24 1049s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13

[04/04 17:37:24 1049s] Found active hold analysis view

Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:37:24 1049s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:37:27 1052s]
-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.116 | 0.064 | 0.074 | -0.116 |

TNS (ns):| -19.921 | 0.000 | 0.000 | -19.921 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.192%
Total number of glitch violations: 0
-----------------------------------------------------------Reported timing to dir gopi/postroute
[04/04 17:37:27 1052s] Total CPU time: 34.73 sec
[04/04 17:37:27 1052s] Total Real time: 35.0 sec
[04/04 17:37:27 1052s] Total Memory Usage: 1964.929688 Mbytes

[04/04 17:37:27 1052s] Reset AAE Options

[04/04 17:37:44 1052s] <CMD> timeDesign -postRoute -hold -outDir
gopi/postroute
[04/04 17:37:44 1052s] Reset EOS DB
[04/04 17:37:44 1052s] Resetting the settings
[04/04 17:37:44 1052s] Ignoring AAE DB Resetting ...
[04/04 17:37:44 1052s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 4704 times net's RC data read were
performed.
[04/04 17:37:44 1052s] Extraction called for design 'tdsp_core' of
instances=2267 and nets=2677 using extraction engine 'postRoute' at effort
level 'low' .
[04/04 17:37:44 1052s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:37:44 1052s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:37:44 1052s] PostRoute (effortLevel low) RC Extraction called for
design tdsp_core.
[04/04 17:37:44 1052s] RC Extraction called in multi-corner(2) mode.
[04/04 17:37:44 1052s] Process corner(s) are loaded.
[04/04 17:37:44 1052s] Corner: Arise_rc_corner_cmax
[04/04 17:37:44 1052s] Corner: Arise_rc_corner_cmin
[04/04 17:37:44 1052s] Metal density calculation for erosion effect completed
(CPU=0:00:00.1 MEM=1964.93M)
[04/04 17:37:44 1052s] extractDetailRC Option : -outfile
./tdsp_core_12308_nnzBe5.rcdb.d -maxResLength 200 -extended
[04/04 17:37:44 1052s] RC Mode: PostRoute effortLevel low [Extended CapTable,
RC Table Resistances]
[04/04 17:37:44 1052s]

RC Corner Indexes

[04/04 17:37:44 1052s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:37:44 1052s] Coupling Cap. Scaling Factor : 1.00000 1.00000
[04/04 17:37:44 1052s] Resistance Scaling Factor

: 1.00000 1.00000

[04/04 17:37:44 1052s] Clock Cap. Scaling Factor

: 1.00000 1.00000

[04/04 17:37:44 1052s] Clock Res. Scaling Factor

[04/04 17:37:44 1052s] Shrink Factor

: 1.00000 1.00000

: 1.00000

[04/04 17:37:44 1052s] Initializing multi-corner capacitance tables ...

[04/04 17:37:44 1052s] Initializing multi-corner resistance tables ...
[04/04 17:37:44 1052s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
1964.9M)
[04/04 17:37:44 1052s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for storing RC.
[04/04 17:37:44 1052s] Extracted 10.0057% (CPU Time= 0:00:00.2 MEM=
2013.6M)
[04/04 17:37:44 1052s] Extracted 20.0057% (CPU Time= 0:00:00.3 MEM=
2041.6M)
[04/04 17:37:44 1052s] Extracted 30.0057% (CPU Time= 0:00:00.3 MEM=
2041.6M)
[04/04 17:37:44 1052s] Extracted 40.0057% (CPU Time= 0:00:00.3 MEM=
2041.6M)
[04/04 17:37:44 1052s] Extracted 50.0057% (CPU Time= 0:00:00.4 MEM=
2041.6M)
[04/04 17:37:44 1052s] Extracted 60.0057% (CPU Time= 0:00:00.4 MEM=
2041.6M)
[04/04 17:37:44 1052s] Extracted 70.0057% (CPU Time= 0:00:00.5 MEM=
2041.6M)
[04/04 17:37:44 1053s] Extracted 80.0057% (CPU Time= 0:00:00.5 MEM=
2041.6M)
[04/04 17:37:44 1053s] Extracted 90.0057% (CPU Time= 0:00:00.6 MEM=
2041.6M)
[04/04 17:37:45 1053s] Extracted 100% (CPU Time= 0:00:00.8 MEM= 2041.6M)
[04/04 17:37:45 1053s] Number of Extracted Resistors

: 52552

[04/04 17:37:45 1053s] Number of Extracted Ground Cap. : 54904

[04/04 17:37:45 1053s] Number of Extracted Coupling Cap. : 98936
[04/04 17:37:45 1053s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:37:45 1053s] Filtering XCap in 'relativeOnly' mode using values
relative_c_threshold=0.03 and total_c_threshold=5fF.

[04/04 17:37:45 1053s] Corner: Arise_rc_corner_cmax

[04/04 17:37:45 1053s] Corner: Arise_rc_corner_cmin
[04/04 17:37:45 1053s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
1999.6M)
[04/04 17:37:45 1053s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb_Filter.rcdb.d' for storing RC.
[04/04 17:37:45 1053s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2352 times net's RC data read were
performed.
[04/04 17:37:45 1053s] Lumped Parasitic Loading Started (total cpu=0:00:00.0,
real=0:00:00.0, current mem=1997.375M)
[04/04 17:37:45 1053s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:37:45 1053s] Lumped Parasitic Loading Completed (total
cpu=0:00:00.0, real=0:00:00.0, current mem=1993.375M)
[04/04 17:37:45 1053s] PostRoute (effortLevel low) RC Extraction DONE (CPU
Time: 0:00:01.1 Real Time: 0:00:01.0 MEM: 1993.375M)
[04/04 17:37:45 1053s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:37:45 1053s] SI iteration 1 ...
[04/04 17:37:45 1053s]
################################################
#################################
[04/04 17:37:45 1053s] # Design Stage: PostRoute
[04/04 17:37:45 1053s] # Design Mode: 90nm
[04/04 17:37:45 1053s] # Analysis Mode: MMMC OCV
[04/04 17:37:45 1053s] # Extraction Mode: detail/spef
[04/04 17:37:45 1053s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:37:45 1053s] # Switching Delay Calculation Engine to AAE-SI
[04/04 17:37:45 1053s]
################################################
#################################
[04/04 17:37:46 1054s] AAE_INFO: 1 threads acquired from CTE.

[04/04 17:37:46 1054s] Setting infinite Tws ...

[04/04 17:37:46 1054s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1439.3M)
[04/04 17:37:46 1054s]

First Iteration Infinite Tw...

[04/04 17:37:46 1054s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1439.3M)
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...

[04/04 17:37:46 1054s] Calculate late delays in OCV mode...

[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Calculate early delays in OCV mode...
[04/04 17:37:46 1054s] Calculate late delays in OCV mode...
[04/04 17:37:46 1054s] Topological Sorting (CPU = 0:00:00.0, MEM = 1439.3M,
InitMEM = 1439.3M)
[04/04 17:37:46 1054s] Initializing multi-corner capacitance tables ...
[04/04 17:37:46 1054s] Initializing multi-corner resistance tables ...
[04/04 17:37:46 1054s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.

[04/04 17:37:46 1055s] RC Database In Completed (CPU Time= 0:00:00.0 Real

Time=0:00:00.0 MEM= 1809.3M)
[04/04 17:37:46 1055s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:37:48 1056s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:49 1057s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:50 1058s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:51 1059s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:52 1060s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:53 1061s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:54 1062s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:55 1063s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:56 1064s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:57 1065s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:58 1066s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:59 1067s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:37:59 1067s] AAE_THRD: End delay calculation. (MEM=1819.48
CPU=0:00:12.3 REAL=0:00:12.0)
[04/04 17:37:59 1067s] *** CDM Built up (cpu=0:00:14.1 real=0:00:14.0
mem= 1819.5M) ***
[04/04 17:38:01 1069s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1819.5M)
[04/04 17:38:01 1069s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:38:01 1069s] Loading CTE timing window is completed (CPU =
0:00:00.1, REAL = 0:00:00.0, MEM = 1781.3M)
[04/04 17:38:01 1069s] SI iteration 2 ...
[04/04 17:38:01 1069s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...

[04/04 17:38:01 1069s] Calculate early delays in OCV mode...

[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1069s] Calculate early delays in OCV mode...
[04/04 17:38:01 1069s] Calculate late delays in OCV mode...
[04/04 17:38:01 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...

[04/04 17:38:02 1070s] Calculate early delays in OCV mode...

[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:02 1070s] Calculate early delays in OCV mode...
[04/04 17:38:02 1070s] Calculate late delays in OCV mode...
[04/04 17:38:03 1071s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:04 1072s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:05 1073s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:06 1074s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:07 1075s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:09 1077s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:10 1078s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:11 1079s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:12 1080s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:13 1081s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis

[04/04 17:38:15 1083s] AAE_INFO-618: Total number of nets in the design is

2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:16 1084s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:16 1084s] AAE_THRD: End delay calculation. (MEM=2003.52
CPU=0:00:14.1 REAL=0:00:14.0)
[04/04 17:38:16 1084s] *** CDM Built up (cpu=0:00:14.5 real=0:00:15.0
mem= 2003.5M) ***
[04/04 17:38:16 1084s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but

to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".
[04/04 17:38:16 1084s] Effort level <high> specified for reg2reg path_group
[04/04 17:38:17 1085s] Effort level <high> specified for reg2cgate path_group
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102

[04/04 17:38:17 1085s] Found active setup analysis view

Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:38:17 1085s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13

[04/04 17:38:17 1085s] Found active hold analysis view

Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:38:17 1085s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:38:20 1087s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:21 1088s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:22 1090s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:23 1091s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis

[04/04 17:38:24 1092s] AAE_INFO-618: Total number of nets in the design is

2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:25 1093s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:26 1094s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:27 1095s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:28 1096s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:29 1097s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:30 1098s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:31 1099s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:31 1099s] AAE_THRD: End delay calculation. (MEM=1836.36
CPU=0:00:12.4 REAL=0:00:12.0)
[04/04 17:38:35 1102s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:36 1103s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:37 1104s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:38 1105s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:39 1107s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:40 1107s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:41 1108s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:42 1109s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:43 1110s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:44 1112s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:45 1113s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:46 1114s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:38:46 1114s] AAE_THRD: End delay calculation. (MEM=2022.39
CPU=0:00:12.1 REAL=0:00:12.0)
[04/04 17:38:47 1115s]
-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.005 | 0.078 | 0.256 | -0.005 |

TNS (ns):| -0.009 | 0.000 | 0.000 | -0.009 |

|
|

Violating Paths:|

All Paths:| 521 | 432 | 12

2
| 82

|
|

+--------------------+---------+---------+---------+---------+

Density: 52.192%
-----------------------------------------------------------Reported timing to dir gopi/postroute
[04/04 17:38:47 1115s] Total CPU time: 62.57 sec
[04/04 17:38:47 1115s] Total Real time: 63.0 sec
[04/04 17:38:47 1115s] Total Memory Usage: 1387.101562 Mbytes
[04/04 17:38:47 1115s] Reset AAE Options
[04/04 17:39:06 1116s] <CMD> zoomBox 204.049 106.466 214.285 98.036
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM0 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM1Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM1 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM2Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM2 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM3Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM3 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM4Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM4 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM5Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM5 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM6Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM6 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM7Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM7 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM8Cont -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM8 -isVisible 0
[04/04 17:39:21 1116s] <CMD> setLayerPreference allM9Cont -isVisible 0

[04/04 17:39:21 1116s] <CMD> setLayerPreference allM9 -isVisible 0

[04/04 17:39:22 1116s] <CMD> setLayerPreference allM0 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM1Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM1 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM2Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM2 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM3Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM3 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM4Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM4 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM5Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM5 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM6Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM6 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM7Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM7 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM8Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM8 -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM9Cont -isVisible 1
[04/04 17:39:22 1116s] <CMD> setLayerPreference allM9 -isVisible 1
[04/04 17:39:26 1117s] <CMD> fit
[04/04 17:39:36 1117s] <CMD> setOptMode -fixCap true -fixTran true
-fixFanoutLoad false
[04/04 17:39:36 1117s] <CMD> optDesign -postRoute
[04/04 17:39:36 1117s] Disable merging buffers from different footprints for
postRoute code for non-MSV designs
[04/04 17:39:36 1117s] Core basic site is CoreSite
[04/04 17:39:36 1118s] **Info: (ENCSP-307): Design contains fractional 153
cells.

: 1.00000

[04/04 17:39:42 1124s] Initializing multi-corner capacitance tables ...

[04/04 17:39:42 1124s] Initializing multi-corner resistance tables ...
[04/04 17:39:42 1124s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
1408.1M)
[04/04 17:39:43 1124s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for storing RC.
[04/04 17:39:43 1124s] Extracted 10.0057% (CPU Time= 0:00:00.2 MEM=
1444.8M)
[04/04 17:39:43 1124s] Extracted 20.0057% (CPU Time= 0:00:00.3 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 30.0057% (CPU Time= 0:00:00.3 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 40.0057% (CPU Time= 0:00:00.3 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 50.0057% (CPU Time= 0:00:00.4 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 60.0057% (CPU Time= 0:00:00.4 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 70.0057% (CPU Time= 0:00:00.5 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 80.0057% (CPU Time= 0:00:00.5 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 90.0057% (CPU Time= 0:00:00.6 MEM=
1472.8M)
[04/04 17:39:43 1124s] Extracted 100% (CPU Time= 0:00:00.8 MEM= 1472.8M)
[04/04 17:39:43 1124s] Number of Extracted Resistors

: 52552

[04/04 17:39:43 1124s] Number of Extracted Ground Cap. : 54904

[04/04 17:39:43 1124s] Number of Extracted Coupling Cap. : 98936

[04/04 17:39:43 1124s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:39:43 1124s] Filtering XCap in 'relativeOnly' mode using values
relative_c_threshold=0.03 and total_c_threshold=5fF.
[04/04 17:39:43 1124s] Corner: Arise_rc_corner_cmax
[04/04 17:39:43 1124s] Corner: Arise_rc_corner_cmin
[04/04 17:39:43 1124s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
1430.8M)
[04/04 17:39:43 1124s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb_Filter.rcdb.d' for storing RC.
[04/04 17:39:43 1124s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2352 times net's RC data read were
performed.
[04/04 17:39:43 1125s] Lumped Parasitic Loading Started (total cpu=0:00:00.0,
real=0:00:00.0, current mem=1430.789M)
[04/04 17:39:43 1125s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:39:43 1125s] Lumped Parasitic Loading Completed (total
cpu=0:00:00.0, real=0:00:00.0, current mem=1426.773M)
[04/04 17:39:43 1125s] PostRoute (effortLevel low) RC Extraction DONE (CPU
Time: 0:00:01.0 Real Time: 0:00:01.0 MEM: 1426.773M)
[04/04 17:39:43 1125s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:39:43 1125s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1428.8M)
[04/04 17:39:43 1125s] Initializing multi-corner capacitance tables ...
[04/04 17:39:44 1125s] Initializing multi-corner resistance tables ...
[04/04 17:39:44 1125s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:39:44 1125s] SI iteration 1 ...
[04/04 17:39:44 1125s]
################################################
#################################

[04/04 17:39:44 1125s] # Design Stage: PostRoute

[04/04 17:39:44 1125s] # Design Mode: 90nm
[04/04 17:39:44 1125s] # Analysis Mode: MMMC OCV
[04/04 17:39:44 1125s] # Extraction Mode: detail/spef
[04/04 17:39:44 1125s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:39:44 1125s] # Switching Delay Calculation Engine to AAE-SI
[04/04 17:39:44 1125s]
################################################
#################################
[04/04 17:39:44 1125s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:39:44 1125s] Setting infinite Tws ...
[04/04 17:39:44 1125s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1426.8M)
[04/04 17:39:44 1125s]

First Iteration Infinite Tw...

[04/04 17:39:44 1125s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1426.8M)
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...

[04/04 17:39:44 1125s] Calculate late delays in OCV mode...

[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...

[04/04 17:39:44 1125s] Calculate late delays in OCV mode...

[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Calculate early delays in OCV mode...
[04/04 17:39:44 1125s] Calculate late delays in OCV mode...
[04/04 17:39:44 1125s] Topological Sorting (CPU = 0:00:00.0, MEM = 1426.8M,
InitMEM = 1426.8M)
[04/04 17:39:44 1125s] *** Calculating scaling factor for
Arise_max_library_T150V08_set libraries using the default operating condition of
each library.
[04/04 17:39:46 1127s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:47 1128s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:48 1129s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:49 1130s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:50 1131s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:51 1132s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:52 1133s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:53 1134s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:54 1135s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:55 1136s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:56 1137s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:39:57 1138s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis

[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:39:57 1138s] AAE_THRD: End delay calculation. (MEM=1823.12
CPU=0:00:12.0 REAL=0:00:12.0)
[04/04 17:39:57 1138s] *** CDM Built up (cpu=0:00:13.4 real=0:00:13.0
mem= 1823.1M) ***
[04/04 17:40:00 1141s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1823.1M)
[04/04 17:40:00 1141s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:40:00 1141s] Loading CTE timing window is completed (CPU =
0:00:00.2, REAL = 0:00:00.0, MEM = 1785.0M)
[04/04 17:40:00 1141s]

[04/04 17:40:00 1141s] Executing IPO callback for view pruning ..

[04/04 17:40:00 1142s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:00 1142s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:40:00 1142s] SI iteration 2 ...
[04/04 17:40:01 1142s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:40:01 1142s] Calculate early delays in OCV mode...
[04/04 17:40:01 1142s] Calculate late delays in OCV mode...
[04/04 17:40:01 1142s] Calculate early delays in OCV mode...
[04/04 17:40:01 1142s] Calculate late delays in OCV mode...
[04/04 17:40:02 1143s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:03 1144s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:03 1144s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:03 1144s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:03 1144s] AAE_THRD: End delay calculation. (MEM=2007.16
CPU=0:00:01.8 REAL=0:00:02.0)
[04/04 17:40:03 1144s] *** CDM Built up (cpu=0:00:01.9 real=0:00:02.0
mem= 2007.2M) ***

[04/04 17:40:03 1144s] *** Done Building Timing Graph (cpu=0:00:19,

real=0:00:19, mem=1969.01M, totSessionCpu=0:19:00).
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108

[04/04 17:40:03 1144s] Found active setup analysis view

Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:03 1144s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11

[04/04 17:40:03 1144s] Found active hold analysis view

Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:03 1144s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:03 1144s]
-----------------------------------------------------------Initial SI Timing Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.116 | 0.064 | 0.074 | -0.116 |

|
|
|

TNS (ns):| -19.915 | 0.000 | 0.000 | -19.915 |

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.192%
Total number of glitch violations: 0
-----------------------------------------------------------**optDesign ... cpu = 0:00:22, real = 0:00:22, mem = 1971.0M,
totSessionCpu=0:19:00 **
[04/04 17:40:03 1145s] Setting latch borrow mode to budget during
optimization.
[04/04 17:40:04 1145s] Glitch fixing enabled
[04/04 17:40:04 1145s] **INFO: Start fixing DRV (Mem = 2028.24M) ...
[04/04 17:40:04 1145s] **INFO: Options = -postRoute -maxCap -maxTran
-noMaxFanout -noSensitivity -backward -maxIter 1
[04/04 17:40:04 1145s] **INFO: Start fixing DRV iteration 1 ...
[04/04 17:40:04 1145s] Begin: GigaOpt DRV Optimization

[04/04 17:40:04 1145s] Glitch fixing enabled

[04/04 17:40:04 1145s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:40:04 1145s] DRV pessimism of 5.00% is used.
[04/04 17:40:04 1145s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:08 1149s]
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:40:08 1149s] |
max-length |
glitch

max-tran
|
|

|
|

max-cap
|
|

max-fanout
|
|

[04/04 17:40:08 1149s]

1 |
7 |
0 |
0| 52.19 |

0 |
|

0 |

[04/04 17:40:09 1150s] |

0 |
0 | -0.12 |
0|

0 |
0 |
0 |
0 |
0 |
0 |
1| 52.20 | 0:00:01.0| 2231.5M|

0 |

[04/04 17:40:09 1150s] |

0 |
0 | -0.12 |
0|

0 |
0 |
0 |
0 |
0 |
0 |
0| 52.20 | 0:00:00.0| 2231.5M|

0 |

[04/04 17:40:09 1150s]

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
[04/04 17:40:09 1150s]
[04/04 17:40:09 1150s] *** Finish DRV Fixing (cpu=0:00:00.7 real=0:00:01.0
mem=2231.5M) ***
[04/04 17:40:09 1150s]
[04/04 17:40:09 1150s] Begin: glitch net info
[04/04 17:40:09 1150s] glitch slack range: number of glitch nets
[04/04 17:40:09 1150s] glitch slack < -0.32 : 0

[04/04 17:40:09 1150s] -0.32 < glitch slack < -0.28 : 0

[04/04 17:40:09 1150s] -0.28 < glitch slack < -0.24 : 0
[04/04 17:40:09 1150s] -0.24 < glitch slack < -0.2 : 0
[04/04 17:40:09 1150s] -0.2 < glitch slack < -0.16 : 0
[04/04 17:40:09 1150s] -0.16 < glitch slack < -0.12 : 0
[04/04 17:40:09 1150s] -0.12 < glitch slack < -0.08 : 0
[04/04 17:40:09 1150s] -0.08 < glitch slack < -0.04 : 0
[04/04 17:40:09 1150s] -0.04 < glitch slack : 0
[04/04 17:40:09 1150s] End: glitch net info
[04/04 17:40:09 1150s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:09 1150s] *** Starting refinePlace (0:19:06 mem=2146.0M) ***
[04/04 17:40:09 1150s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:09 1150s] Starting refinePlace ...
[04/04 17:40:09 1150s] Spread Effort: high, post-route mode, useDDP on.
[04/04 17:40:09 1150s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.0,
real=0:00:00.0, mem=2146.0MB) @(0:19:06 - 0:19:06).
[04/04 17:40:09 1150s] Move report: preRPlace moves 0 insts, mean move: 0.00
um, max move: 0.00 um
[04/04 17:40:09 1150s] wireLenOptFixPriorityInst 258 inst fixed
[04/04 17:40:09 1150s] Move report: legalization moves 0 insts, mean move:
0.00 um, max move: 0.00 um
[04/04 17:40:09 1150s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=2146.0MB) @(0:19:06 - 0:19:06).
[04/04 17:40:09 1150s] Move report: Detail placement moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:40:09 1150s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2146.0MB
[04/04 17:40:09 1150s] Statistics of distance of Instance movement in refine
placement:
[04/04 17:40:09 1150s] maximum (X+Y) =

0.00 um

[04/04 17:40:09 1150s] mean

(X+Y) =

0.00 um

[04/04 17:40:09 1150s] Summary Report:

[04/04 17:40:09 1150s] Instances move: 0 (out of 2241 movable)
[04/04 17:40:09 1150s] Mean displacement: 0.00 um
[04/04 17:40:09 1150s] Max displacement: 0.00 um
[04/04 17:40:09 1150s] Total instances moved : 0
[04/04 17:40:09 1150s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:09 1150s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2146.0MB
[04/04 17:40:09 1150s] [CPU] RefinePlace/total (cpu=0:00:00.0, real=0:00:00.0,
mem=2146.0MB) @(0:19:06 - 0:19:06).
[04/04 17:40:09 1150s] *** Finished refinePlace (0:19:06 mem=2146.0M) ***
[04/04 17:40:09 1150s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:09 1150s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:09 1150s] default core: bins with density > 0.75 = 59.2 % ( 100 /
169 )
[04/04 17:40:09 1150s] Density distribution unevenness ratio = 11.389%
[04/04 17:40:09 1150s] End: GigaOpt DRV Optimization
[04/04 17:40:09 1150s] **optDesign ... cpu = 0:00:28, real = 0:00:28, mem =
2105.8M, totSessionCpu=0:19:06 **
[04/04 17:40:09 1150s] *info:
[04/04 17:40:09 1150s] **INFO: Completed fixing DRV (CPU Time = 0:00:06,
Mem = 2105.80M).
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102

[04/04 17:40:09 1150s] Found active setup analysis view

Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13

[04/04 17:40:09 1150s] Found active setup analysis view

Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:09 1150s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15

[04/04 17:40:09 1150s] Found active hold analysis view

Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:09 1150s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:10 1151s]
-----------------------------------------------------------SI Timing Summary (cpu=0.09min real=0.08min mem=2105.8M)
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.116 | 0.064 | 0.074 | -0.116 |

TNS (ns):| -19.913 | 0.000 | 0.000 | -19.913 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+

|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.195%
Total number of glitch violations: 0
-----------------------------------------------------------**optDesign ... cpu = 0:00:28, real = 0:00:29, mem = 2105.8M,
totSessionCpu=0:19:07 **
[04/04 17:40:10 1151s] *** Timing NOT met, worst failing slack is -0.116
[04/04 17:40:10 1151s] *** Check timing (0:00:00.0)
[04/04 17:40:10 1151s] Begin: GigaOpt Optimization in WNS mode
[04/04 17:40:10 1151s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:40:10 1151s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:14 1155s] *info: 23 clock nets excluded
[04/04 17:40:14 1155s] *info: 2 special nets excluded.
[04/04 17:40:14 1155s] *info: 32 multi-driver nets excluded.
[04/04 17:40:14 1155s] *info: 322 no-driver nets excluded.
[04/04 17:40:14 1155s] ** GigaOpt Optimizer WNS Slack -0.116 TNS Slack
-19.913 Density 52.20
[04/04 17:40:14 1155s] Optimizer WNS Pass 0
[04/04 17:40:14 1155s] Active Path Group: default

[04/04 17:40:14 1155s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:14 1155s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:14 1155s] | -0.116| -0.116| -19.913| -19.913| 52.20%|
0:00:00.0| 2182.1M| Arise_analysis_view_test_max_cmax_T150V08| default|
EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/ |
[04/04 17:40:14 1155s] |
|
| SE

[04/04 17:40:14 1155s] | -0.116| -0.116| -19.913| -19.913| 52.20%|

0:00:00.0| 2195.8M| Arise_analysis_view_test_max_cmax_T150V08| default|
EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/ |
[04/04 17:40:14 1155s] |
|
| SE

[04/04 17:40:14 1155s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:14 1155s]
[04/04 17:40:14 1155s] *** Finish Optimize Step (cpu=0:00:00.3 real=0:00:00.0
mem=2195.8M) ***
[04/04 17:40:14 1155s]
[04/04 17:40:14 1155s] *** Finish Post Route Setup Fixing (cpu=0:00:00.3
real=0:00:00.0 mem=2195.8M) ***
[04/04 17:40:14 1155s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:14 1156s] *** Starting refinePlace (0:19:11 mem=2110.8M) ***
[04/04 17:40:14 1156s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:14 1156s] Starting refinePlace ...
[04/04 17:40:14 1156s] Spread Effort: high, post-route mode, useDDP on.

[04/04 17:40:14 1156s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.0,

real=0:00:00.0, mem=2110.8MB) @(0:19:11 - 0:19:11).
[04/04 17:40:14 1156s] Move report: preRPlace moves 0 insts, mean move: 0.00
um, max move: 0.00 um
[04/04 17:40:14 1156s] wireLenOptFixPriorityInst 258 inst fixed
[04/04 17:40:14 1156s] Move report: legalization moves 0 insts, mean move:
0.00 um, max move: 0.00 um
[04/04 17:40:14 1156s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=2110.8MB) @(0:19:11 - 0:19:11).
[04/04 17:40:14 1156s] Move report: Detail placement moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:40:14 1156s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2110.8MB
[04/04 17:40:14 1156s] Statistics of distance of Instance movement in refine
placement:
[04/04 17:40:14 1156s] maximum (X+Y) =
[04/04 17:40:14 1156s] mean

(X+Y) =

0.00 um
0.00 um

[04/04 17:40:14 1156s] Summary Report:

[04/04 17:40:14 1156s] Instances move: 0 (out of 2241 movable)
[04/04 17:40:14 1156s] Mean displacement: 0.00 um
[04/04 17:40:14 1156s] Max displacement: 0.00 um
[04/04 17:40:14 1156s] Total instances moved : 0
[04/04 17:40:14 1156s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:14 1156s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2110.8MB
[04/04 17:40:14 1156s] [CPU] RefinePlace/total (cpu=0:00:00.0, real=0:00:00.0,
mem=2110.8MB) @(0:19:11 - 0:19:11).
[04/04 17:40:14 1156s] *** Finished refinePlace (0:19:11 mem=2110.8M) ***
[04/04 17:40:14 1156s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:14 1156s] **Info: (ENCSP-307): Design contains fractional 153
cells.

[04/04 17:40:15 1156s] default core: bins with density > 0.75 = 59.2 % ( 100 /
169 )
[04/04 17:40:15 1156s] Density distribution unevenness ratio = 11.389%
[04/04 17:40:15 1156s] End: GigaOpt Optimization in WNS mode
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102

[04/04 17:40:15 1156s] Found active setup analysis view

Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:15 1156s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13

[04/04 17:40:15 1156s] Found active hold analysis view

Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:15 1156s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:15 1156s]
-----------------------------------------------------------SI Timing Summary (cpu=0.08min real=0.08min mem=2068.7M)
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.116 | 0.064 | 0.074 | -0.116 |

TNS (ns):| -19.913 | 0.000 | 0.000 | -19.913 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.195%
Total number of glitch violations: 0
-----------------------------------------------------------**optDesign ... cpu = 0:00:34, real = 0:00:34, mem = 2068.7M,
totSessionCpu=0:19:12 **
[04/04 17:40:15 1156s] Begin: GigaOpt Optimization in TNS mode
[04/04 17:40:15 1156s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:40:15 1156s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:19 1160s] *info: 23 clock nets excluded

[04/04 17:40:19 1160s] *info: 2 special nets excluded.

[04/04 17:40:19 1160s] *info: 32 multi-driver nets excluded.
[04/04 17:40:19 1160s] *info: 322 no-driver nets excluded.
[04/04 17:40:19 1160s] ** GigaOpt Optimizer WNS Slack -0.116 TNS Slack
-19.913 Density 52.20
[04/04 17:40:19 1160s] Optimizer TNS Opt
[04/04 17:40:19 1160s] Active Path Group: default
[04/04 17:40:19 1160s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+
[04/04 17:40:19 1160s] | WNS | All WNS | TNS | All TNS | Density | Real
Mem |
Worst View
|Pathgroup|
End Point
|

[04/04 17:40:19 1160s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:19 1160s] | -0.116| -0.116| -19.913| -19.913| 52.20%|
0:00:00.0| 2191.3M| Arise_analysis_view_test_max_cmax_T150V08| default|
EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/ |
[04/04 17:40:19 1160s] |
|
| SE

[04/04 17:40:21 1162s] | -0.116| -0.116| -19.138| -19.138| 52.21%|

0:00:02.0| 2250.9M| Arise_analysis_view_func_nom_cmax_T25V12| default|
DECODE_INST/go_data_reg/state_remap/DFF/SE
|
[04/04 17:40:21 1162s] | -0.116| -0.116| -19.138| -19.138| 52.21%|
0:00:00.0| 2250.9M| Arise_analysis_view_test_max_cmax_T150V08| default|
EXECUTE_INST/RC_CG_HIER_INST24/RC_CGIC_INST/LATCH/ |
[04/04 17:40:21 1162s] |
|
| SE

[04/04 17:40:21 1162s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:21 1162s]
[04/04 17:40:21 1162s] *** Finish Optimize Step (cpu=0:00:01.7 real=0:00:02.0
mem=2250.9M) ***

[04/04 17:40:21 1162s] ** GigaOpt Optimizer WNS Slack -0.116 TNS Slack
-19.138 Density 52.21
[04/04 17:40:21 1162s] Update Timing Windows (Threshold 0.012) ...
[04/04 17:40:21 1162s] Re Calculate Delays on 0 Nets
[04/04 17:40:21 1162s]
[04/04 17:40:21 1162s] *** Finish Post Route Setup Fixing (cpu=0:00:01.8
real=0:00:02.0 mem=2250.9M) ***
[04/04 17:40:21 1162s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:21 1162s] *** Starting refinePlace (0:19:18 mem=2136.4M) ***
[04/04 17:40:21 1162s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:21 1162s] Starting refinePlace ...
[04/04 17:40:21 1162s] Spread Effort: high, post-route mode, useDDP on.
[04/04 17:40:21 1162s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.0,
real=0:00:00.0, mem=2136.4MB) @(0:19:18 - 0:19:18).
[04/04 17:40:21 1162s] Move report: preRPlace moves 0 insts, mean move: 0.00
um, max move: 0.00 um
[04/04 17:40:21 1162s] wireLenOptFixPriorityInst 258 inst fixed
[04/04 17:40:21 1162s] Move report: legalization moves 0 insts, mean move:
0.00 um, max move: 0.00 um
[04/04 17:40:21 1162s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=2136.4MB) @(0:19:18 - 0:19:18).
[04/04 17:40:21 1162s] Move report: Detail placement moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:40:21 1162s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2136.4MB
[04/04 17:40:21 1162s] Statistics of distance of Instance movement in refine
placement:
[04/04 17:40:21 1162s] maximum (X+Y) =
[04/04 17:40:21 1162s] mean

(X+Y) =

0.00 um
0.00 um

[04/04 17:40:21 1162s] Summary Report:

[04/04 17:40:21 1162s] Instances move: 0 (out of 2241 movable)

[04/04 17:40:21 1162s] Mean displacement: 0.00 um

[04/04 17:40:21 1162s] Max displacement: 0.00 um
[04/04 17:40:21 1162s] Total instances moved : 0
[04/04 17:40:21 1162s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:21 1162s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2136.4MB
[04/04 17:40:21 1162s] [CPU] RefinePlace/total (cpu=0:00:00.0, real=0:00:00.0,
mem=2136.4MB) @(0:19:18 - 0:19:18).
[04/04 17:40:21 1162s] *** Finished refinePlace (0:19:18 mem=2136.4M) ***
[04/04 17:40:21 1162s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.440e+03)
[04/04 17:40:21 1162s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:21 1162s] default core: bins with density > 0.75 = 59.2 % ( 100 /
169 )
[04/04 17:40:21 1162s] Density distribution unevenness ratio = 11.385%
[04/04 17:40:21 1163s] End: GigaOpt Optimization in TNS mode
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12

[04/04 17:40:21 1163s] Found active setup analysis view

Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:21 1163s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15

[04/04 17:40:21 1163s] Found active hold analysis view

Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13

[04/04 17:40:21 1163s] Found active hold analysis view

Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:40:21 1163s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:40:22 1163s]
-----------------------------------------------------------SI Timing Summary (cpu=0.11min real=0.10min mem=2093.9M)
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.116 | 0.064 | 0.074 | -0.116 |

TNS (ns):| -19.138 | 0.000 | 0.000 | -19.138 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.210%
Total number of glitch violations: 0
-----------------------------------------------------------**optDesign ... cpu = 0:00:40, real = 0:00:41, mem = 2093.9M,
totSessionCpu=0:19:19 **
[04/04 17:40:22 1163s] Timing Snapshot:
[04/04 17:40:22 1163s]

Weighted WNS: -0.006

[04/04 17:40:22 1163s]

All PG WNS: -0.116

[04/04 17:40:22 1163s]

High PG WNS: 0.000

[04/04 17:40:22 1163s]

All PG TNS: -19.138

[04/04 17:40:22 1163s]

High PG TNS: 0.000

WNS (ns):| -0.116 | 0.064 | 0.074 | -0.116 |

TNS (ns):| -19.138 | 0.000 | 0.000 | -19.138 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

setting

# int, default=0, user

[04/04 17:40:22 1164s] -drouteStartIteration 0

# int, default=0

[04/04 17:40:22 1164s]

Line-2-Via Pitch =

[04/04 17:40:23 1164s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:40:23 1164s] # Metal8
0.385

V Track-Pitch = 0.200

Line-2-Via Pitch =

[04/04 17:40:23 1164s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.

[04/04 17:40:23 1164s] # Metal9

0.385

H Track-Pitch = 0.380

Line-2-Via Pitch =

[04/04 17:40:23 1164s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:40:23 1164s] #60/2352 = 2% of signal nets have been set as priority
nets
[04/04 17:40:23 1164s] #Regenerating Ggrids automatically.
[04/04 17:40:23 1164s] #Auto generating G-grids with size=15 tracks, using
layer Metal2's pitch = 0.200.
[04/04 17:40:23 1164s] #Using automatically generated G-grids.
[04/04 17:40:23 1164s] #Done routing data preparation.
[04/04 17:40:23 1164s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1844.45 (MB), peak = 2198.33 (MB)
[04/04 17:40:23 1164s] #Merging special wires...
[04/04 17:40:23 1164s] #WARNING (NRDB-1005) Cannot establish connection to
PIN A at (107.310 124.035) on Metal1 for NET FE_OFN36_DFT_sen. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:40:23 1164s] #WARNING (NRDB-1005) Cannot establish connection to
PIN A at (105.910 142.725) on Metal1 for NET FE_OFN36_DFT_sen. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:40:23 1164s] #WARNING (NRDB-1005) Cannot establish connection to
PIN A at (104.910 146.145) on Metal1 for NET FE_OFN36_DFT_sen. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:40:23 1164s] #WARNING (NRDB-1005) Cannot establish connection to
PIN Y at (105.915 146.110) on Metal1 for NET FE_OFN44_DFT_sen. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:40:23 1164s] #WARNING (NRDB-1005) Cannot establish connection to
PIN Y at (107.325 142.690) on Metal1 for NET FE_OFN45_DFT_sen. The NET is
considered partially routed. Visually verify wiring at the specified location as the

wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:40:23 1164s] #WARNING (NRDB-1005) Cannot establish connection to
PIN Y at (108.315 124.070) on Metal1 for NET FE_OFN47_DFT_sen. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:40:23 1164s] #WARNING (NRDB-1005) Cannot establish connection to
PIN Y at (133.500 91.255) on Metal1 for NET opa\[0\]\[10\]. The NET is considered
partially routed. Visually verify wiring at the specified location as the wire/via
origin may not touch the PIN. This NET will be rerouted with same or different
wiring.
[04/04 17:40:23 1164s] #396 routed nets are extracted.
[04/04 17:40:23 1164s] #

5 (0.19%) extracted nets are partially routed.

[04/04 17:40:23 1164s] #1956 routed nets are imported.

[04/04 17:40:23 1164s] #325 nets are fixed|skipped|trivial (not extracted).
[04/04 17:40:23 1164s] #Total number of nets = 2677.
[04/04 17:40:23 1164s] #Found 0 nets for post-route si or timing fixing.
[04/04 17:40:23 1164s] #Number of eco nets is 5
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Start data preparation...
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Data preparation is done on Mon Apr 4 17:40:23 2016
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Analyzing routing resource...
[04/04 17:40:23 1164s] #Routing resource analysis is done on Mon Apr 4
17:40:23 2016
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] # Resource Analysis:
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] # Layer
Blocked

379

111

4900

18.98%

[04/04 17:40:23 1164s] # -------------------------------------------------------------[04/04 17:40:23 1164s] # Total

2770

57.07% 39200

54.52%

[04/04 17:40:23 1164s] #

[04/04 17:40:23 1164s] # 24 nets (0.90%) with 1 preferred extra spacing.
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1844.83 (MB), peak = 2198.33 (MB)
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #start global routing iteration 1...
[04/04 17:40:23 1164s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1845.13 (MB), peak = 2198.33 (MB)
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #start global routing iteration 2...
[04/04 17:40:23 1164s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1845.13 (MB), peak = 2198.33 (MB)
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Total number of trivial nets (e.g. < 2 pins) = 325
(skipped).
[04/04 17:40:23 1164s] #Total number of routable nets = 2352.

[04/04 17:40:23 1164s] #Total number of nets in the design = 2677.

[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #5 routable nets have only global wires.
[04/04 17:40:23 1164s] #2347 routable nets have only detail routed wires.
[04/04 17:40:23 1164s] #4 global routed or unrouted (routable) nets have been
constrained (e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:40:23 1164s] #79 detail routed (routable) nets have been constrained
(e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Routed net constraints summary:
[04/04 17:40:23 1164s] #Miscellaneous constraints include nets with expansionratio, avoid-detour, preferred-bottom-layer or preferred-top-layer etc. attributes
[04/04 17:40:23 1164s] #-----------------------------------------------[04/04 17:40:23 1164s] #

Rules Misc Constraints Unconstrained

[04/04 17:40:23 1164s] #-----------------------------------------------[04/04 17:40:23 1164s] #

Default

[04/04 17:40:23 1164s] #-----------------------------------------------[04/04 17:40:23 1164s] #

Total

[04/04 17:40:23 1164s] #-----------------------------------------------[04/04 17:40:23 1164s] #

[04/04 17:40:23 1164s] #Routing constraints summary of the whole design:
[04/04 17:40:23 1164s] #Miscellaneous constraints include nets with expansionratio, avoid-detour, preferred-bottom-layer or preferred-top-layer etc. attributes
[04/04 17:40:23 1164s] #------------------------------------------------------------------[04/04 17:40:23 1164s] #
Unconstrained

Rules Pref Extra Space Misc Constraints

[04/04 17:40:23 1164s] #------------------------------------------------------------------[04/04 17:40:23 1164s] #

Default

2269

[04/04 17:40:23 1164s] #------------------------------------------------------------------[04/04 17:40:23 1164s] #

Total

2269

[04/04 17:40:23 1164s] #------------------------------------------------------------------[04/04 17:40:23 1164s] #

[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] # Congestion Analysis: (blocked Gcells are excluded)
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #

Total

1(0.01%) (0.01%)

[04/04 17:40:23 1164s] #

[04/04 17:40:23 1164s] # The worst congested Gcell overcon (routing demand
over resource in number of tracks) = 1
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Complete Global Routing.
[04/04 17:40:23 1164s] #Total number of nets with non-default rule or having
extra spacing = 24
[04/04 17:40:23 1164s] #Total wire length = 71387 um.
[04/04 17:40:23 1164s] #Total half perimeter of net bounding box = 61162 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal1 = 4898 um.

[04/04 17:40:23 1164s] #Total wire length on LAYER Metal2 = 17914 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal3 = 22716 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal4 = 15643 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal5 = 10216 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:40:23 1164s] #Total number of vias = 17735
[04/04 17:40:23 1164s] #Total number of multi-cut vias = 396 ( 2.2%)
[04/04 17:40:23 1164s] #Total number of single cut vias = 17339 ( 97.8%)
[04/04 17:40:23 1164s] #Up-Via Summary (total 17735):
[04/04 17:40:23 1164s] #

[04/04 17:40:23 1164s] #Max overcon = 1 tracks.
[04/04 17:40:23 1164s] #Total overcon = 0.01%.
[04/04 17:40:23 1164s] #Worst layer Gcell overcon rate = 0.00%.
[04/04 17:40:23 1164s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1845.13 (MB), peak = 2198.33 (MB)
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Start data preparation for track assignment...

[04/04 17:40:23 1164s] #

[04/04 17:40:23 1164s] #Data preparation is done on Mon Apr 4 17:40:23 2016
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1845.13 (MB), peak = 2198.33 (MB)
[04/04 17:40:23 1164s] #Start Track Assignment.
[04/04 17:40:23 1164s] #Done with 2 horizontal wires in 1 hboxes and 3 vertical
wires in 1 hboxes.
[04/04 17:40:23 1164s] #Done with 0 horizontal wires in 1 hboxes and 0 vertical
wires in 1 hboxes.
[04/04 17:40:23 1164s] #Complete Track Assignment.
[04/04 17:40:23 1164s] #Total number of nets with non-default rule or having
extra spacing = 24
[04/04 17:40:23 1164s] #Total wire length = 71388 um.
[04/04 17:40:23 1164s] #Total half perimeter of net bounding box = 61162 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal1 = 4898 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal2 = 17916 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal3 = 22715 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal4 = 15643 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal5 = 10216 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:40:23 1164s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:40:23 1164s] #Total number of vias = 17735
[04/04 17:40:23 1164s] #Total number of multi-cut vias = 396 ( 2.2%)
[04/04 17:40:23 1164s] #Total number of single cut vias = 17339 ( 97.8%)
[04/04 17:40:23 1164s] #Up-Via Summary (total 17735):
[04/04 17:40:23 1164s] #

single-cut

[04/04 17:40:23 1164s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1812.50 (MB), peak = 2198.33 (MB)
[04/04 17:40:23 1164s] #
[04/04 17:40:23 1164s] #Cpu time = 00:00:01
[04/04 17:40:23 1164s] #Elapsed time = 00:00:01
[04/04 17:40:23 1164s] #Increased memory = -7.18 (MB)
[04/04 17:40:23 1164s] #Total memory = 1812.50 (MB)
[04/04 17:40:23 1164s] #Peak memory = 2198.33 (MB)
[04/04 17:40:24 1165s] #
[04/04 17:40:24 1165s] #Start Detail Routing..
[04/04 17:40:24 1165s] #start initial detail routing ...
[04/04 17:40:25 1166s] # ECO: 0.0% of the total area was rechecked for DRC,
and 2.8% required routing.
[04/04 17:40:25 1166s] #

number of violations = 2

[04/04 17:40:25 1166s] #

By Layer and Type :

[04/04 17:40:26 1167s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1845.32 (MB), peak = 2198.33 (MB)
[04/04 17:40:26 1167s] #start 8th optimization iteration ...
[04/04 17:40:26 1167s] #

number of violations = 2

[04/04 17:40:26 1167s] #

[04/04 17:40:26 1167s] #
[04/04 17:40:26 1167s] #
[04/04 17:40:26 1167s] #

By Layer and Type :

Short Totals
Metal1

[04/04 17:40:26 1167s] #

Metal2

[04/04 17:40:26 1167s] #

Totals

memory = 1862.27 (MB), peak = 2198.33 (MB)
[04/04 17:40:27 1168s] #start 12th optimization iteration ...
[04/04 17:40:27 1168s] #

number of violations = 2

[04/04 17:40:27 1168s] #

By Layer and Type :

[04/04 17:40:27 1168s] #Total number of DRC violations = 2
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal1 = 0
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:40:27 1168s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:40:27 1168s] #Cpu time = 00:00:04
[04/04 17:40:27 1168s] #Elapsed time = 00:00:04
[04/04 17:40:27 1168s] #Increased memory = 49.84 (MB)
[04/04 17:40:27 1168s] #Total memory = 1862.34 (MB)
[04/04 17:40:27 1168s] #Peak memory = 2198.33 (MB)

[04/04 17:40:27 1168s] #

[04/04 17:40:27 1168s] #Start Post Routing Optimization.
[04/04 17:40:27 1168s] #start 1st post routing optimization iteration ...
[04/04 17:40:28 1169s] #

number of DRC violations = 2

[04/04 17:40:28 1169s] #

By Layer and Type :

multi-cut

Total

[04/04 17:40:29 1170s] #----------------------------------------------------------[04/04 17:40:29 1170s] # Metal 1

9097 ( 95.8%)

[04/04 17:40:29 1170s] # Metal 2

6195 (100.0%)

400 ( 4.2%)
0 ( 0.0%)

9497
6195

[04/04 17:40:29 1170s] # Metal 3

1445 (100.0%)

[04/04 17:40:29 1170s] # Metal 4

598 (100.0%)

0 ( 0.0%)

1445

0 ( 0.0%)

598

[04/04 17:40:29 1170s] #----------------------------------------------------------[04/04 17:40:29 1170s] #

17335 ( 97.7%)

400 ( 2.3%)

17735

[04/04 17:40:29 1170s] #

[04/04 17:40:29 1170s] #Total number of DRC violations = 2
[04/04 17:40:29 1170s] #Total number of net violated process antenna rule = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal1 = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:40:29 1170s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:40:29 1170s] #
[04/04 17:40:29 1170s] #detailRoute Statistics:
[04/04 17:40:29 1170s] #Cpu time = 00:00:06
[04/04 17:40:29 1170s] #Elapsed time = 00:00:06
[04/04 17:40:29 1170s] #Increased memory = 6.12 (MB)
[04/04 17:40:29 1170s] #Total memory = 1818.62 (MB)
[04/04 17:40:29 1170s] #Peak memory = 2198.33 (MB)
[04/04 17:40:29 1170s] #Updating routing design signature
[04/04 17:40:29 1170s] #Created 492 library cell signatures
[04/04 17:40:29 1170s] #Created 2677 NETS and 0 SPECIALNETS signatures
[04/04 17:40:29 1170s] #Created 2268 instance signatures
[04/04 17:40:30 1171s] #

[04/04 17:40:30 1171s] #globalDetailRoute statistics:

[04/04 17:40:30 1171s] #Cpu time = 00:00:07
[04/04 17:40:30 1171s] #Elapsed time = 00:00:07
[04/04 17:40:30 1171s] #Increased memory = -554.70 (MB)
[04/04 17:40:30 1171s] #Total memory = 1264.80 (MB)
[04/04 17:40:30 1171s] #Peak memory = 2198.33 (MB)
[04/04 17:40:30 1171s] #Number of warnings = 30
[04/04 17:40:30 1171s] #Total number of warnings = 451
[04/04 17:40:30 1171s] #Number of fails = 0
[04/04 17:40:30 1171s] #Total number of fails = 1
[04/04 17:40:30 1171s] #Complete globalDetailRoute on Mon Apr 4 17:40:30
2016
[04/04 17:40:30 1171s] #
[04/04 17:40:30 1171s] **optDesign ... cpu = 0:00:48, real = 0:00:49, mem =
1469.6M, totSessionCpu=0:19:27 **
[04/04 17:40:30 1171s] -routeWithEco false

# bool, default=false

[04/04 17:40:30 1171s] -routeSelectedNetOnly false

default=false

# bool,

[04/04 17:40:30 1171s] -routeWithTimingDriven false

default=false, user setting

# bool,

[04/04 17:40:30 1171s] -routeWithSiDriven false

default=false, user setting
[04/04 17:40:30 1171s] -drouteStartIteration 0
setting

# bool,
# int, default=0, user

[04/04 17:40:30 1171s] Extraction called for design 'tdsp_core' of

instances=2267 and nets=2677 using extraction engine 'postRoute' at effort
level 'low' .
[04/04 17:40:30 1171s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:40:30 1171s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:40:30 1171s] PostRoute (effortLevel low) RC Extraction called for
design tdsp_core.

[04/04 17:40:30 1171s] RC Extraction called in multi-corner(2) mode.

[04/04 17:40:30 1171s] Process corner(s) are loaded.
[04/04 17:40:30 1171s] Corner: Arise_rc_corner_cmax
[04/04 17:40:30 1171s] Corner: Arise_rc_corner_cmin
[04/04 17:40:30 1171s] Metal density calculation for erosion effect completed
(CPU=0:00:00.1 MEM=1469.58M)
[04/04 17:40:30 1171s] extractDetailRC Option : -outfile
./tdsp_core_12308_nnzBe5.rcdb.d -maxResLength 200 -extended
[04/04 17:40:30 1171s] RC Mode: PostRoute effortLevel low [Extended CapTable,
RC Table Resistances]
[04/04 17:40:30 1171s]

RC Corner Indexes

[04/04 17:40:30 1171s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:40:30 1171s] Coupling Cap. Scaling Factor : 1.00000 1.00000
[04/04 17:40:30 1171s] Resistance Scaling Factor

[04/04 17:40:31 1172s] Number of Extracted Ground Cap. : 54877

[04/04 17:40:31 1172s] Number of Extracted Coupling Cap. : 98888
[04/04 17:40:31 1172s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:40:31 1172s] Filtering XCap in 'relativeOnly' mode using values
relative_c_threshold=0.03 and total_c_threshold=5fF.
[04/04 17:40:31 1172s] Corner: Arise_rc_corner_cmax
[04/04 17:40:31 1172s] Corner: Arise_rc_corner_cmin
[04/04 17:40:31 1172s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
1493.0M)
[04/04 17:40:31 1172s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb_Filter.rcdb.d' for storing RC.
[04/04 17:40:31 1172s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2352 times net's RC data read were
performed.
[04/04 17:40:31 1172s] Lumped Parasitic Loading Started (total cpu=0:00:00.0,
real=0:00:00.0, current mem=1490.766M)
[04/04 17:40:31 1172s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:40:31 1172s] Lumped Parasitic Loading Completed (total
cpu=0:00:00.0, real=0:00:00.0, current mem=1486.766M)

[04/04 17:40:31 1172s] PostRoute (effortLevel low) RC Extraction DONE (CPU

Time: 0:00:01.0 Real Time: 0:00:01.0 MEM: 1486.766M)
[04/04 17:40:31 1172s] Finished Generating Timing Windows
[04/04 17:40:31 1172s] **optDesign ... cpu = 0:00:49, real = 0:00:50, mem =
1484.8M, totSessionCpu=0:19:28 **
[04/04 17:40:31 1172s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:40:31 1172s] SI iteration 1 ...
[04/04 17:40:31 1172s] Begin IPO call back ...
[04/04 17:40:31 1172s] End IPO call back ...
[04/04 17:40:31 1172s]
################################################
#################################
[04/04 17:40:31 1172s] # Design Stage: PostRoute
[04/04 17:40:31 1172s] # Design Mode: 90nm
[04/04 17:40:31 1172s] # Analysis Mode: MMMC OCV
[04/04 17:40:31 1172s] # Extraction Mode: detail/spef
[04/04 17:40:31 1172s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:40:31 1172s] # Switching Delay Calculation Engine to AAE-SI
[04/04 17:40:31 1172s]
################################################
#################################
[04/04 17:40:31 1172s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:40:31 1172s] Setting infinite Tws ...
[04/04 17:40:31 1173s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1488.8M)
[04/04 17:40:31 1173s]

First Iteration Infinite Tw...

[04/04 17:40:31 1173s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1488.8M)
[04/04 17:40:31 1173s] Calculate early delays in OCV mode...
[04/04 17:40:31 1173s] Calculate late delays in OCV mode...

[04/04 17:40:31 1173s] Calculate early delays in OCV mode...

[04/04 17:40:31 1173s] Calculate late delays in OCV mode...
[04/04 17:40:31 1173s] Topological Sorting (CPU = 0:00:00.0, MEM = 1488.8M,
InitMEM = 1488.8M)
[04/04 17:40:31 1173s] Initializing multi-corner capacitance tables ...
[04/04 17:40:32 1173s] Initializing multi-corner resistance tables ...
[04/04 17:40:32 1173s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:40:32 1173s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1858.8M)
[04/04 17:40:32 1173s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:40:33 1174s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:34 1175s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:34 1175s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:34 1175s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:34 1175s] AAE_THRD: End delay calculation. (MEM=1889.13
CPU=0:00:01.6 REAL=0:00:02.0)
[04/04 17:40:34 1175s] *** CDM Built up (cpu=0:00:02.7 real=0:00:03.0
mem= 1889.1M) ***
[04/04 17:40:34 1175s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1889.1M)
[04/04 17:40:34 1175s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:40:34 1175s] Loading CTE timing window is completed (CPU =
0:00:00.1, REAL = 0:00:00.0, MEM = 1851.0M)
[04/04 17:40:34 1175s] SI iteration 2 ...
[04/04 17:40:35 1176s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:40:35 1176s] Calculate early delays in OCV mode...
[04/04 17:40:35 1176s] Calculate late delays in OCV mode...

[04/04 17:40:35 1176s] Calculate early delays in OCV mode...

[04/04 17:40:35 1176s] Calculate late delays in OCV mode...
[04/04 17:40:36 1177s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:36 1178s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:36 1178s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:36 1178s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:36 1178s] AAE_THRD: End delay calculation. (MEM=2073.18
CPU=0:00:01.9 REAL=0:00:01.0)
[04/04 17:40:36 1178s] *** CDM Built up (cpu=0:00:01.9 real=0:00:01.0
mem= 2073.2M) ***
[04/04 17:40:37 1178s] *** Done Building Timing Graph (cpu=0:00:06,
real=0:00:06, mem=2035.02M, totSessionCpu=0:19:33).
[04/04 17:40:37 1178s] Setting latch borrow mode to budget during
optimization.
[04/04 17:40:37 1178s] *** Timing NOT met, worst failing slack is -0.116
[04/04 17:40:37 1178s] *** Check timing (0:00:00.0)
[04/04 17:40:37 1178s] Begin: GigaOpt Optimization in post-eco TNS mode
[04/04 17:40:37 1178s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:40:37 1178s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:40:37 1179s] *info: 23 clock nets excluded
[04/04 17:40:37 1179s] *info: 2 special nets excluded.
[04/04 17:40:37 1179s] *info: 32 multi-driver nets excluded.
[04/04 17:40:37 1179s] *info: 322 no-driver nets excluded.
[04/04 17:40:38 1179s] ** GigaOpt Optimizer WNS Slack -0.116 TNS Slack
-19.243 Density 52.21
[04/04 17:40:38 1179s] Optimizer TNS Opt
[04/04 17:40:38 1179s] Active Path Group: default

[04/04 17:40:38 1179s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:38 1179s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:38 1179s] | -0.116| -0.116| -19.243| -19.243| 52.21%|
0:00:00.0| 2236.3M| Arise_analysis_view_test_max_cmax_T150V08| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:40:38 1179s] |
|
| LATCH/SE

[04/04 17:40:38 1179s] | -0.116| -0.116| -19.243| -19.243| 52.21%|

0:00:00.0| 2236.3M| Arise_analysis_view_test_max_cmax_T150V08| default|
DATA_BUS_MACH_INST/RC_CG_HIER_INST18/RC_CGIC_INST/ |
[04/04 17:40:38 1179s] |
|
| LATCH/SE

[04/04 17:40:38 1179s] +--------+---------+--------+---------+----------+-----------+--------+------------------------------------------+--------+----------------------------------------------------+

[04/04 17:40:38 1179s]
[04/04 17:40:38 1179s] *** Finish Optimize Step (cpu=0:00:00.2 real=0:00:00.0
mem=2236.3M) ***
[04/04 17:40:38 1179s]
[04/04 17:40:38 1179s] *** Finish Post Route Setup Fixing (cpu=0:00:00.2
real=0:00:00.0 mem=2236.3M) ***
[04/04 17:40:38 1179s] End: GigaOpt Optimization in post-eco TNS mode
[04/04 17:40:38 1179s] Running setup recovery post routing.
[04/04 17:40:38 1179s] Timing Snapshot:
[04/04 17:40:38 1179s]

Weighted WNS: -0.006

[04/04 17:40:38 1179s]

All PG WNS: -0.116

[04/04 17:40:38 1179s]

High PG WNS: 0.000

[04/04 17:40:38 1179s]

All PG TNS: -19.243

[04/04 17:40:38 1179s]

High PG TNS: 0.000

First Iteration Infinite Tw...

[04/04 17:40:39 1180s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1553.7M)
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...

[04/04 17:40:39 1180s] Calculate late delays in OCV mode...

[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...

[04/04 17:40:39 1180s] Calculate late delays in OCV mode...

[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Calculate early delays in OCV mode...
[04/04 17:40:39 1180s] Calculate late delays in OCV mode...
[04/04 17:40:39 1180s] Topological Sorting (CPU = 0:00:00.0, MEM = 1553.7M,
InitMEM = 1553.7M)
[04/04 17:40:41 1182s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:42 1183s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:43 1184s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:44 1185s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:45 1186s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:46 1187s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis

[04/04 17:40:47 1188s] AAE_INFO-618: Total number of nets in the design is

2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:48 1189s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:49 1190s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:50 1191s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:51 1192s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:52 1193s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:40:52 1193s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:40:52 1193s] AAE_THRD: End delay calculation. (MEM=1944.61

CPU=0:00:12.1 REAL=0:00:12.0)
[04/04 17:40:52 1193s] *** CDM Built up (cpu=0:00:13.7 real=0:00:14.0
mem= 1944.6M) ***
[04/04 17:40:55 1196s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1944.6M)
[04/04 17:40:55 1196s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:40:55 1196s] Loading CTE timing window is completed (CPU =
0:00:00.1, REAL = 0:00:00.0, MEM = 1906.5M)
[04/04 17:40:55 1196s] SI iteration 2 ...
[04/04 17:40:55 1196s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...

[04/04 17:40:55 1196s] Calculate early delays in OCV mode...

[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...
[04/04 17:40:55 1196s] Calculate early delays in OCV mode...
[04/04 17:40:55 1196s] Calculate late delays in OCV mode...

[04/04 17:40:57 1198s] AAE_INFO-618: Total number of nets in the design is

2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:58 1199s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:40:59 1200s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:00 1201s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:01 1202s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:02 1203s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:04 1205s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:05 1206s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:06 1207s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:07 1208s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:08 1209s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:10 1211s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:10 1211s] AAE_THRD: End delay calculation. (MEM=2128.66
CPU=0:00:14.1 REAL=0:00:15.0)
[04/04 17:41:10 1211s] *** CDM Built up (cpu=0:00:14.4 real=0:00:15.0
mem= 2128.7M) ***
[04/04 17:41:10 1212s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11

[04/04 17:41:10 1212s] Active hold views:

Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:41:10 1212s] Reported timing to dir ./timingReports
[04/04 17:41:10 1212s] **optDesign ... cpu = 0:01:29, real = 0:01:29, mem =
2090.5M, totSessionCpu=0:20:07 **
[04/04 17:41:10 1212s] Begin: glitch net info
[04/04 17:41:11 1212s] glitch slack range: number of glitch nets
[04/04 17:41:11 1212s] glitch slack < -0.32 : 0
[04/04 17:41:11 1212s] -0.32 < glitch slack < -0.28 : 0
[04/04 17:41:11 1212s] -0.28 < glitch slack < -0.24 : 0
[04/04 17:41:11 1212s] -0.24 < glitch slack < -0.2 : 0
[04/04 17:41:11 1212s] -0.2 < glitch slack < -0.16 : 0
[04/04 17:41:11 1212s] -0.16 < glitch slack < -0.12 : 0
[04/04 17:41:11 1212s] -0.12 < glitch slack < -0.08 : 0
[04/04 17:41:11 1212s] -0.08 < glitch slack < -0.04 : 0

[04/04 17:41:11 1212s] -0.04 < glitch slack : 0

[04/04 17:41:11 1212s] End: glitch net info
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108

[04/04 17:41:11 1212s] Found active setup analysis view

Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:41:11 1212s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11

[04/04 17:41:11 1212s] Found active hold analysis view

Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:41:11 1212s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:41:12 1213s]
-----------------------------------------------------------optDesign Final SI Timing Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+

WNS (ns):| -0.116 | 0.064 | 0.066 | -0.116 |

TNS (ns):| -19.247 | 0.000 | 0.000 | -19.247 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.210%
Total number of glitch violations: 0
-----------------------------------------------------------**optDesign ... cpu = 0:01:31, real = 0:01:31, mem = 2090.5M,
totSessionCpu=0:20:09 **
[04/04 17:41:12 1213s] ReSet Options after AAE Based Opt flow
[04/04 17:41:13 1214s] *** Finished optDesign ***
[04/04 17:41:13 1214s]
[04/04 17:41:13 1214s] OPT_RUNTIME:
0:01:36 real= 0:01:37)
[04/04 17:41:13 1214s] OPT_RUNTIME:
(cpu=0:00:00.0 real=0:00:00.0)

optDesign (count = 3): (cpu=

Init (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:02.2 real=0:00:02.6)
[04/04 17:41:13 1214s] OPT_RUNTIME:
(cpu=0:00:20.0 real=0:00:20.1)

Extraction (count = 2):

TimingGraph (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:05.9 real=0:00:05.9)

DRVOpt (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:04.3 real=0:00:04.3)

setupOpt (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:00.3 real=0:00:00.3)

wnsOpt (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:01.9 real=0:00:01.9)

tnsOpt (count = 2):

[04/04 17:41:13 1214s] OPT_RUNTIME: RouterDirectives (count = 1):

(cpu=0:00:00.6 real=0:00:00.6)
[04/04 17:41:13 1214s] OPT_RUNTIME:
(cpu=0:00:07.1 real=0:00:07.1)

ecoRoute (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:06.2 real=0:00:06.2)

TimingGraph (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:00.6 real=0:00:00.6)

LefSafeOpt (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:32.6 real=0:00:32.6)

Recovery (count = 1):

[04/04 17:41:13 1214s] OPT_RUNTIME:

(cpu=0:00:00.0 real=0:00:00.0)

Final (count = 0):

[04/04 17:41:13 1214s] <CMD> optDesign -postRoute -hold

[04/04 17:41:13 1214s] Disable merging buffers from different footprints for
postRoute code for non-MSV designs
[04/04 17:41:13 1214s] GigaOpt running with 1 threads.
[04/04 17:41:13 1214s] Core basic site is CoreSite
[04/04 17:41:13 1214s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:41:13 1214s] Layer info - lib-1st H=1, V=2. Cell-FPin=1. Top-pin=2
[04/04 17:41:13 1214s] **Info: (ENCSP-307): Design contains fractional 153
cells.

[04/04 17:41:17 1218s] **optDesign ... cpu = 0:00:00, real = 0:00:00, mem =
2053.0M, totSessionCpu=0:20:14 **
[04/04 17:41:17 1218s] #Created 492 library cell signatures
[04/04 17:41:17 1218s] #Created 2677 NETS and 0 SPECIALNETS signatures
[04/04 17:41:17 1218s] #Created 2268 instance signatures
[04/04 17:41:17 1218s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:41:17 1218s] Begin checking placement ... (start mem=2063.0M, init
mem=2063.0M)
[04/04 17:41:17 1218s] *info: Placed = 2267

(Fixed = 26)

[04/04 17:41:17 1218s] *info: Unplaced = 0

[04/04 17:41:17 1218s] Placement Density:51.93%(7217/13897)
[04/04 17:41:17 1218s] Finished checkPlace (cpu: total=0:00:00.1, vio
checks=0:00:00.0; mem=2063.0M)
[04/04 17:41:17 1218s] Limited Access feature "encUseAAEForPostRouteOpt" is
Set. Starting AAE Based SI Opt
[04/04 17:41:17 1218s] Initial DC engine is -> aae
[04/04 17:41:17 1218s]
[04/04 17:41:17 1218s] AAE-Opt:: Current number of nets in RC Memory -> 100
K
[04/04 17:41:17 1218s]
[04/04 17:41:17 1218s]
[04/04 17:41:17 1218s] AAE-Opt:: New number of nets in RC Memory -> 100 K
[04/04 17:41:17 1218s]
[04/04 17:41:17 1218s] Reset EOS DB
[04/04 17:41:17 1218s] Resetting the settings
[04/04 17:41:17 1218s] Ignoring AAE DB Resetting ...
[04/04 17:41:17 1218s] Set Options for AAE Based Opt flow
[04/04 17:41:17 1218s] *** optDesign -postRoute ***
[04/04 17:41:17 1218s] DRC Margin: user margin 0.0; extra margin 0
[04/04 17:41:17 1218s] Setup Target Slack: user slack 0

[04/04 17:41:17 1218s] Hold Target Slack: user slack 0

[04/04 17:41:18 1219s] ** INFO : this run is activating 'postRoute' automaton
[04/04 17:41:18 1219s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 4704 times net's RC data read were
performed.
[04/04 17:41:18 1219s] Extraction called for design 'tdsp_core' of
instances=2267 and nets=2677 using extraction engine 'postRoute' at effort
level 'low' .
[04/04 17:41:18 1219s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:41:18 1219s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:41:18 1219s] PostRoute (effortLevel low) RC Extraction called for
design tdsp_core.
[04/04 17:41:18 1219s] RC Extraction called in multi-corner(2) mode.
[04/04 17:41:18 1219s] Process corner(s) are loaded.
[04/04 17:41:18 1219s] Corner: Arise_rc_corner_cmax
[04/04 17:41:18 1219s] Corner: Arise_rc_corner_cmin
[04/04 17:41:18 1219s] Metal density calculation for erosion effect completed
(CPU=0:00:00.1 MEM=1510.91M)
[04/04 17:41:18 1219s] extractDetailRC Option : -outfile
./tdsp_core_12308_nnzBe5.rcdb.d -maxResLength 200 -extended
[04/04 17:41:18 1219s] RC Mode: PostRoute effortLevel low [Extended CapTable,
RC Table Resistances]
[04/04 17:41:18 1219s]

RC Corner Indexes

[04/04 17:41:18 1219s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:41:18 1219s] Coupling Cap. Scaling Factor : 1.00000 1.00000
[04/04 17:41:18 1219s] Resistance Scaling Factor

: 1.00000 1.00000

[04/04 17:41:19 1220s] *info: (buf) CLKBUFX2

[04/04 17:41:19 1220s] *info: (buf) BUFX2
[04/04 17:41:19 1220s] *info: (buf) CLKBUFX3
[04/04 17:41:19 1220s] *info: (buf) BUFX3
[04/04 17:41:19 1220s] *info: (buf) CLKBUFX4

- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc

[04/04 17:41:19 1220s] *info: (buf) BUFX4

- gpdk045wc

[04/04 17:41:19 1220s] *info: (buf) CLKBUFX3
[04/04 17:41:19 1220s] *info: (buf) BUFX3
[04/04 17:41:19 1220s] *info: (buf) CLKBUFX4

- gpdk045wc
- gpdk045wc

[04/04 17:41:19 1220s] *info: (buf) CLKBUFX8

- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc
- gpdk045wc

[04/04 17:41:20 1221s] GigaOpt Hold Optimizer is used

[04/04 17:41:20 1221s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:41:20 1221s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1501.8M)
[04/04 17:41:20 1221s] Initializing multi-corner capacitance tables ...
[04/04 17:41:20 1221s] Initializing multi-corner resistance tables ...
[04/04 17:41:25 1226s] gigaOpt Hold fixing search radius: 68.400000 Microns
(40 stdCellHgt)
[04/04 17:41:25 1226s] *info: Run optDesign holdfix with 1 thread.
[04/04 17:41:25 1226s] Starting initialization (fixHold) cpu=0:00:04.8
real=0:00:05.0 totSessionCpu=0:20:21 mem=1634.4M ***
[04/04 17:41:25 1226s] Effort level <high> specified for reg2reg path_group
[04/04 17:41:25 1226s] Effort level <high> specified for reg2cgate path_group
[04/04 17:41:25 1226s] *info: Starting Blocking QThread with 1 CPU
[04/04 17:41:25 1226s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:41:25 1226s] SI iteration 1 ...
[04/04 17:41:25 1226s] Begin IPO call back ...
[04/04 17:41:25 1226s] End IPO call back ...
[04/04 17:41:25 1226s]
################################################
#################################
[04/04 17:41:25 1226s] # Design Stage: PostRoute

[04/04 17:41:25 1226s] # Design Mode: 90nm

[04/04 17:41:25 1226s] # Analysis Mode: MMMC OCV
[04/04 17:41:25 1226s] # Extraction Mode: detail/spef
[04/04 17:41:25 1226s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:41:25 1226s] # Switching Delay Calculation Engine to AAE-SI
[04/04 17:41:25 1226s]
################################################
#################################
[04/04 17:41:26 1226s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:41:26 1226s] Setting infinite Tws ...
[04/04 17:41:26 1226s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 0.0M)
[04/04 17:41:26 1226s]

First Iteration Infinite Tw...

[04/04 17:41:26 1226s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 0.0M)
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...

[04/04 17:41:26 1226s] Calculate late delays in OCV mode...

[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...

[04/04 17:41:26 1226s] Calculate late delays in OCV mode...

[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Calculate late delays in OCV mode...
[04/04 17:41:26 1226s] Calculate early delays in OCV mode...
[04/04 17:41:26 1226s] Topological Sorting (CPU = 0:00:00.0, MEM = 0.0M,
InitMEM = 0.0M)
[04/04 17:41:26 1226s] *** Calculating scaling factor for
Arise_min_library_T0V132_set libraries using the default operating condition of
each library.
[04/04 17:41:28 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:29 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:30 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:31 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:32 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:33 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis

[04/04 17:41:34 1226s] AAE_INFO-618: Total number of nets in the design is

2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:35 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:36 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:37 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:38 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis

[04/04 17:41:39 1226s] AAE_INFO-618: Total number of nets in the design is

2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:39 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:40 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:01.0)
[04/04 17:41:40 1226s] AAE_THRD: End delay calculation. (MEM=301.844
CPU=0:00:12.7 REAL=0:00:13.0)
[04/04 17:41:40 1226s] *** CDM Built up (cpu=0:00:14.4 real=0:00:15.0
mem= 301.8M) ***
[04/04 17:41:42 1226s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 301.8M)
[04/04 17:41:42 1226s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:41:42 1226s] Loading CTE timing window is completed (CPU =
0:00:00.2, REAL = 0:00:00.0, MEM = 267.4M)

[04/04 17:41:42 1226s]

[04/04 17:41:42 1226s] Executing IPO callback for view pruning ..
[04/04 17:41:43 1226s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:41:43 1226s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:41:43 1226s] SI iteration 2 ...
[04/04 17:41:43 1226s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:41:43 1226s] Calculate late delays in OCV mode...
[04/04 17:41:43 1226s] Calculate early delays in OCV mode...
[04/04 17:41:44 1226s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:44 1226s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:44 1226s] AAE_THRD: End delay calculation. (MEM=490.625
CPU=0:00:00.8 REAL=0:00:01.0)
[04/04 17:41:44 1226s] *** CDM Built up (cpu=0:00:00.9 real=0:00:01.0
mem= 490.6M) ***
[04/04 17:41:44 1226s] Done building cte hold timing graph (fixHold)
cpu=0:00:19.0 real=0:00:19.0 totSessionCpu=0:00:36.0 mem=490.6M ***
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102

[04/04 17:41:44 1226s] Found active setup analysis view

Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13

[04/04 17:41:44 1226s] Found active setup analysis view

Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:41:44 1226s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15

[04/04 17:41:44 1226s] Found active hold analysis view

Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:41:44 1226s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:41:44 1226s] Done building hold timer [1794 node(s), 1922 edge(s), 1
view(s)] (fixHold) cpu=0:00:19.3 real=0:00:19.0 totSessionCpu=0:00:36.3
mem=455.5M ***
[04/04 17:41:44 1226s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13

Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:41:44 1226s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:41:44 1226s] Timing Data dump into file
.holdtw.Arise_analysis_view_func_min_cmin_T0V132.12308.twf, for view:
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:41:44 1226s] Dumping view 23
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:41:44 1245s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:41:44 1245s] SI iteration 1 ...
[04/04 17:41:44 1245s] Begin IPO call back ...
[04/04 17:41:44 1245s] End IPO call back ...
[04/04 17:41:44 1245s]
################################################
#################################
[04/04 17:41:44 1245s] # Design Stage: PostRoute

[04/04 17:41:44 1245s] # Design Mode: 90nm

[04/04 17:41:44 1245s] # Analysis Mode: MMMC OCV
[04/04 17:41:44 1245s] # Extraction Mode: detail/spef
[04/04 17:41:44 1245s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:41:44 1245s] # Switching Delay Calculation Engine to AAE-SI
[04/04 17:41:44 1245s]
################################################
#################################
[04/04 17:41:45 1246s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:41:45 1246s] Setting infinite Tws ...
[04/04 17:41:45 1246s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1689.6M)
[04/04 17:41:45 1246s]

First Iteration Infinite Tw...

[04/04 17:41:45 1246s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1689.6M)
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...

[04/04 17:41:45 1246s] Calculate early delays in OCV mode...

[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...

[04/04 17:41:45 1246s] Calculate early delays in OCV mode...

[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Calculate early delays in OCV mode...
[04/04 17:41:45 1246s] Calculate late delays in OCV mode...
[04/04 17:41:45 1246s] Topological Sorting (CPU = 0:00:00.0, MEM = 1689.6M,
InitMEM = 1689.6M)
[04/04 17:41:47 1248s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:48 1249s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:49 1250s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:50 1251s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:51 1252s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:52 1253s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:53 1254s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:54 1255s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:55 1256s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:56 1256s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:57 1258s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:58 1258s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:41:58 1259s] AAE_THRD: End delay calculation. (MEM=2088.5
CPU=0:00:12.1 REAL=0:00:12.0)
[04/04 17:41:58 1259s] *** CDM Built up (cpu=0:00:13.6 real=0:00:14.0
mem= 2088.5M) ***
[04/04 17:42:01 1261s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 2088.5M)
[04/04 17:42:01 1261s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:42:01 1262s] Loading CTE timing window is completed (CPU =
0:00:00.1, REAL = 0:00:00.0, MEM = 2053.1M)
[04/04 17:42:01 1262s]
[04/04 17:42:01 1262s] Executing IPO callback for view pruning ..
[04/04 17:42:01 1262s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_nom_cmax_T25V12

[04/04 17:42:01 1262s] Active hold views:

Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:42:01 1262s] SI iteration 2 ...
[04/04 17:42:02 1263s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:42:02 1263s] Calculate early delays in OCV mode...
[04/04 17:42:02 1263s] Calculate late delays in OCV mode...
[04/04 17:42:02 1263s] Calculate early delays in OCV mode...
[04/04 17:42:02 1263s] Calculate late delays in OCV mode...
[04/04 17:42:03 1264s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:04 1265s] AAE_INFO-618: Total number of nets in the design is
2677, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:04 1265s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:04 1265s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:04 1265s] AAE_THRD: End delay calculation. (MEM=2274.29
CPU=0:00:01.9 REAL=0:00:02.0)
[04/04 17:42:04 1265s] *** CDM Built up (cpu=0:00:02.0 real=0:00:02.0
mem= 2274.3M) ***
[04/04 17:42:04 1265s] Done building cte setup timing graph (fixHold)
cpu=0:00:42.7 real=0:00:44.0 totSessionCpu=0:20:59 mem=2274.3M ***
[04/04 17:42:04 1265s] *info: category slack lower bound [L -116.0] default
[04/04 17:42:04 1265s] *info: category slack lower bound [H 0.0] reg2cgate

[04/04 17:42:04 1265s] *info: category slack lower bound [H 0.0] reg2reg
[04/04 17:42:04 1265s] --------------------------------------------------[04/04 17:42:04 1265s]

Setup Violation Summary with Target Slack (0.000 ns)

[04/04 17:42:04 1265s] --------------------------------------------------[04/04 17:42:04 1265s]

[04/04 17:42:04 1265s]

WNS
-0.116 ns

reg2regWNS
0.064 ns

[04/04 17:42:04 1265s] --------------------------------------------------[04/04 17:42:08 1269s] Timing Snapshot:

[04/04 17:42:08 1269s]

Weighted WNS: -0.006

[04/04 17:42:08 1269s]

All PG WNS: -0.116

[04/04 17:42:08 1269s]

High PG WNS: 0.000

[04/04 17:42:08 1269s]

All PG TNS: -19.243

[04/04 17:42:08 1269s]

High PG TNS: 0.000

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+

WNS (ns):| -0.005 | 0.079 | 0.257 | -0.005 |

TNS (ns):| -0.009 | 0.000 | 0.000 | -0.009 |

|
|

Violating Paths:|

All Paths:| 521 | 432 | 12

| 82

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.210%
------------------------------------------------------------

[04/04 17:42:09 1269s] *Info: minBufDelay = 0.060900 ns ; LibStdDelay =

0.011600 ns; minBufSize = 1710000 (5); worstDelayView:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:42:09 1269s] Footprint list for hold buffering
[04/04 17:42:09 1269s]
================================================
=================
[04/04 17:42:09 1269s] *Info: holdDelay delayRatio IGArea drvRes
cellname(iterm,oterm)
[04/04 17:42:09 1269s] ------------------------------------------------------------------

23.9

2.76 11.0 9.90 CLKBUFX8 (A,Y)

[04/04 17:42:09 1269s] *Info:

60.0

3.01 11.0 19.49 DLY1X4 (A,Y)

[04/04 17:42:09 1269s] *Info:

23.9

2.80 15.0 6.72 CLKBUFX12 (A,Y)

[04/04 17:42:09 1269s] *Info:

23.9

2.80 15.0 6.72 BUFX12 (A,Y)

[04/04 17:42:09 1269s] *Info:

104.1

[04/04 17:42:09 1269s] *Info:

23.3

2.80 20.0 5.11 CLKBUFX16 (A,Y)

[04/04 17:42:09 1269s] *Info:

23.3

2.80 20.0 5.11 BUFX16 (A,Y)

[04/04 17:42:09 1269s] *Info:

3.35 31.0 19.53 DLY4X4 (A,Y)

3.31 17.0 77.12 DLY2X1 (A,Y)

3.24 20.0 19.41 DLY2X4 (A,Y)

[04/04 17:42:09 1269s]

================================================
=================
[04/04 17:42:09 1269s] Info: 23 clock nets excluded from IPO operation.
[04/04 17:42:09 1270s] ---------------------------------------------------

[04/04 17:42:09 1270s]

Hold Timing Summary - Initial

[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s] Target slack: 0.000 ns

[04/04 17:42:09 1270s] View: Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:42:09 1270s] WNS: -0.005
[04/04 17:42:09 1270s] TNS: -0.009
[04/04 17:42:09 1270s] VP: 2
[04/04 17:42:09 1270s] Worst hold path end point: port_address[0]
[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s]

Setup Timing Summary - Initial

[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s] Target slack: 0.000 ns

[04/04 17:42:09 1270s] View: Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:42:09 1270s] WNS: 0.064
[04/04 17:42:09 1270s] TNS: 0.000
[04/04 17:42:09 1270s] VP: 0
[04/04 17:42:09 1270s] Worst setup path end
point:EXECUTE_INST/ar1_reg[15]/state_remap/DFF/D
[04/04 17:42:09 1270s] View: Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:42:09 1270s] WNS: -0.116
[04/04 17:42:09 1270s] TNS: -19.243
[04/04 17:42:09 1270s] VP: 320
[04/04 17:42:09 1270s] Worst setup path end
point:PROG_BUS_MACH_INST/RC_CG_HIER_INST28/RC_CGIC_INST/LATCH/SE
[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:42:09 1270s]
[04/04 17:42:09 1270s] *** Starting Core Fixing (fixHold) cpu=0:00:48.0
real=0:00:49.0 totSessionCpu=0:21:04 mem=2247.7M density=52.210% ***

[04/04 17:42:09 1270s] Optimizer Target Slack 0.000 StdDelay is 0.012

[04/04 17:42:09 1270s] Phase I ......
[04/04 17:42:09 1270s] Executing transform: ECO Safe Resize
[04/04 17:42:09 1270s]
+-----------------------------------------------------------------------------------------------+
[04/04 17:42:09 1270s] |Iter| WNS | TNS
Density | Real Time | Mem |

| #VP | #Buffer | #Resize(F/F) |

[04/04 17:42:09 1270s]

+-----------------------------------------------------------------------------------------------+
[04/04 17:42:09 1270s] Worst hold path end point: FE_OFC64_port_address_0_/A
net FE_OFN62_port_address_0_ nrTerm=9
[04/04 17:42:09 1270s] | 0| -0.005|
52.21%| 0:00:49.0| 2250.7M|

-0.01|

0)|

[04/04 17:42:09 1270s] Worst hold path end point: FE_OFC64_port_address_0_/A

net FE_OFN62_port_address_0_ nrTerm=9
[04/04 17:42:09 1270s] | 1| -0.005|
52.21%| 0:00:49.0| 2251.7M|

-0.01|

0)|

[04/04 17:42:09 1270s]

+-----------------------------------------------------------------------------------------------+
[04/04 17:42:09 1270s] Executing transform: AddBuffer + LegalResize
[04/04 17:42:09 1270s]
+-----------------------------------------------------------------------------------------------+
[04/04 17:42:09 1270s] |Iter| WNS | TNS
Density | Real Time | Mem |

| #VP | #Buffer | #Resize(F/F) |

[04/04 17:42:09 1270s]

-0.01|

0)|

[04/04 17:42:09 1270s] | 1| 0.000|

52.23%| 0:00:49.0| 2271.2M|

0.00|

0)|

[04/04 17:42:09 1270s]

+-----------------------------------------------------------------------------------------------+

[04/04 17:42:09 1270s]

[04/04 17:42:09 1270s] *info:

Total 1 cells added for Phase I

[04/04 17:42:09 1270s] *info:

Total 1 instances resized for Phase I

[04/04 17:42:09 1270s] *info:

in which 0 FF resizing

[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s]

Hold Timing Summary - Phase I

[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s] Target slack: 0.000 ns

[04/04 17:42:09 1270s] View: Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:42:09 1270s] WNS: 0.003
[04/04 17:42:09 1270s] TNS: 0.000
[04/04 17:42:09 1270s] VP: 0
[04/04 17:42:09 1270s] Worst hold path end point: p_address[7]
[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s]

Setup Timing Summary - Phase I

[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s] Target slack: 0.000 ns

[04/04 17:42:09 1270s] --------------------------------------------------[04/04 17:42:09 1270s]

[04/04 17:42:09 1270s] *** Finished Core Fixing (fixHold) cpu=0:00:48.2
real=0:00:49.0 totSessionCpu=0:21:04 mem=2271.2M density=52.232% ***
[04/04 17:42:09 1270s] *info:
[04/04 17:42:09 1270s] *info: Added a total of 1 cells to fix/reduce hold violation
[04/04 17:42:09 1270s] *info:

in which 1 termBuffering

[04/04 17:42:09 1270s] *info:

[04/04 17:42:09 1270s] *info: Summary:
[04/04 17:42:09 1270s] *info:
used

1 cell of type 'CLKBUFX2' (5.0,

38.550)

[04/04 17:42:09 1270s] *info:

[04/04 17:42:09 1270s] *info:
[04/04 17:42:09 1270s] *info: Total 1 instances resized
[04/04 17:42:09 1270s] *info:

in which 0 FF resizing

[04/04 17:42:09 1270s] *info:

[04/04 17:42:09 1270s] *** Finish Post Route Hold Fixing (cpu=0:00:48.2
real=0:00:49.0 totSessionCpu=0:21:04 mem=2271.2M density=52.232%) ***
[04/04 17:42:10 1270s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:42:10 1270s] *** Starting refinePlace (0:21:05 mem=2194.9M) ***
[04/04 17:42:10 1270s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.438e+03)
[04/04 17:42:10 1270s] Starting refinePlace ...
[04/04 17:42:10 1270s] Spread Effort: high, post-route mode, useDDP on.
[04/04 17:42:10 1270s] [CPU] RefinePlace/preRPlace (cpu=0:00:00.0,
real=0:00:00.0, mem=2194.9MB) @(0:21:05 - 0:21:05).
[04/04 17:42:10 1270s] Move report: preRPlace moves 0 insts, mean move: 0.00
um, max move: 0.00 um
[04/04 17:42:10 1270s] wireLenOptFixPriorityInst 258 inst fixed

[04/04 17:42:10 1270s] Move report: legalization moves 0 insts, mean move:
0.00 um, max move: 0.00 um
[04/04 17:42:10 1270s] [CPU] RefinePlace/Legalization (cpu=0:00:00.0,
real=0:00:00.0, mem=2194.9MB) @(0:21:05 - 0:21:05).
[04/04 17:42:10 1270s] Move report: Detail placement moves 0 insts, mean
move: 0.00 um, max move: 0.00 um
[04/04 17:42:10 1270s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2194.9MB
[04/04 17:42:10 1270s] Statistics of distance of Instance movement in refine
placement:
[04/04 17:42:10 1270s] maximum (X+Y) =
[04/04 17:42:10 1270s] mean

(X+Y) =

0.00 um
0.00 um

[04/04 17:42:10 1270s] Summary Report:

[04/04 17:42:10 1270s] Instances move: 0 (out of 2242 movable)
[04/04 17:42:10 1270s] Mean displacement: 0.00 um
[04/04 17:42:10 1270s] Max displacement: 0.00 um
[04/04 17:42:10 1270s] Total instances moved : 0
[04/04 17:42:10 1270s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.438e+03)
[04/04 17:42:10 1270s] Runtime: CPU: 0:00:00.0 REAL: 0:00:00.0 MEM:
2194.9MB
[04/04 17:42:10 1270s] [CPU] RefinePlace/total (cpu=0:00:00.0, real=0:00:00.0,
mem=2194.9MB) @(0:21:05 - 0:21:05).
[04/04 17:42:10 1270s] *** Finished refinePlace (0:21:05 mem=2194.9M) ***
[04/04 17:42:10 1270s] Total net length = 6.057e+04 (3.152e+04 2.905e+04)
(ext = 7.438e+03)
[04/04 17:42:10 1270s] **Info: (ENCSP-307): Design contains fractional 153
cells.
[04/04 17:42:10 1271s] default core: bins with density > 0.75 = 59.2 % ( 100 /
169 )
[04/04 17:42:10 1271s] Density distribution unevenness ratio = 11.379%
[04/04 17:42:10 1271s] **optDesign ... cpu = 0:00:51, real = 0:00:53, mem =
2156.8M, totSessionCpu=0:21:05 **

[04/04 17:42:10 1271s] Found active setup analysis view

Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12

[04/04 17:42:10 1271s] Found active setup analysis view

Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:42:10 1271s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132

[04/04 17:42:10 1271s] Found active hold analysis view

Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:42:10 1271s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:10 1271s]
-----------------------------------------------------------Pre-ecoRoute Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.116 | 0.064 | 0.067 | -0.116 |

TNS (ns):| -19.243 | 0.000 | 0.000 | -19.243 |

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.232%
-----------------------------------------------------------*** Enable all active views. ***
[04/04 17:42:10 1271s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12

Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:10 1271s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:10 1271s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102

Line-2-Via Pitch =

[04/04 17:42:11 1271s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:42:11 1271s] # Metal8
0.385

V Track-Pitch = 0.200

Line-2-Via Pitch =

[04/04 17:42:11 1271s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.
[04/04 17:42:11 1271s] # Metal9
0.385

H Track-Pitch = 0.380

Line-2-Via Pitch =

[04/04 17:42:11 1271s] #WARNING (NRAG-44) Track pitch is too small compared
with line-2-via pitch.

[04/04 17:42:11 1271s] #60/2353 = 2% of signal nets have been set as priority
nets
[04/04 17:42:11 1271s] #Regenerating Ggrids automatically.
[04/04 17:42:11 1271s] #Auto generating G-grids with size=15 tracks, using
layer Metal2's pitch = 0.200.
[04/04 17:42:11 1271s] #Using automatically generated G-grids.
[04/04 17:42:11 1271s] #Done routing data preparation.
[04/04 17:42:11 1271s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1887.88 (MB), peak = 2271.97 (MB)
[04/04 17:42:11 1271s] #Merging special wires...
[04/04 17:42:11 1271s] #WARNING (NRDB-1005) Cannot establish connection to
PIN A at (163.810 110.370) on Metal1 for NET FE_OFN62_port_address_0_. The
NET is considered partially routed. Visually verify wiring at the specified location
as the wire/via origin may not touch the PIN. This NET will be rerouted with same
or different wiring.
[04/04 17:42:11 1271s] #WARNING (NRDB-1005) Cannot establish connection to
PIN A at (106.435 178.625) on Metal1 for NET FE_PHN89_port_as. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:42:11 1271s] #WARNING (NRDB-1005) Cannot establish connection to
PIN Y at (165.100 110.245) on Metal1 for NET port_address[0]. The NET is
considered partially routed. Visually verify wiring at the specified location as the
wire/via origin may not touch the PIN. This NET will be rerouted with same or
different wiring.
[04/04 17:42:11 1271s] #394 routed nets are extracted.
[04/04 17:42:11 1271s] #

3 (0.11%) extracted nets are partially routed.

[04/04 17:42:11 1271s] #1958 routed nets are imported.

[04/04 17:42:11 1271s] #1 (0.04%) nets are without wires.
[04/04 17:42:11 1271s] #325 nets are fixed|skipped|trivial (not extracted).
[04/04 17:42:11 1271s] #Total number of nets = 2678.
[04/04 17:42:11 1271s] #Found 0 nets for post-route si or timing fixing.
[04/04 17:42:11 1271s] #Number of eco nets is 3
[04/04 17:42:11 1271s] #

[04/04 17:42:11 1271s] #Start data preparation...

[04/04 17:42:11 1271s] #
[04/04 17:42:11 1271s] #Data preparation is done on Mon Apr 4 17:42:11 2016
[04/04 17:42:11 1271s] #
[04/04 17:42:11 1271s] #Analyzing routing resource...
[04/04 17:42:11 1272s] #Routing resource analysis is done on Mon Apr 4
17:42:11 2016
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] # Resource Analysis:
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] # Layer
Blocked

Routing #Avail
Direction Track

379

111

4900

18.98%

[04/04 17:42:11 1272s] # -------------------------------------------------------------[04/04 17:42:11 1272s] # Total

2770

57.07% 39200

54.52%

[04/04 17:42:11 1272s] #

[04/04 17:42:11 1272s] # 24 nets (0.90%) with 1 preferred extra spacing.
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #

[04/04 17:42:11 1272s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1888.11 (MB), peak = 2271.97 (MB)
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #start global routing iteration 1...
[04/04 17:42:11 1272s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1894.02 (MB), peak = 2271.97 (MB)
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #start global routing iteration 2...
[04/04 17:42:11 1272s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1894.02 (MB), peak = 2271.97 (MB)
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #Total number of trivial nets (e.g. < 2 pins) = 325
(skipped).
[04/04 17:42:11 1272s] #Total number of routable nets = 2353.
[04/04 17:42:11 1272s] #Total number of nets in the design = 2678.
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #4 routable nets have only global wires.
[04/04 17:42:11 1272s] #2349 routable nets have only detail routed wires.
[04/04 17:42:11 1272s] #1 global routed or unrouted (routable) net has been
constrained (e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:42:11 1272s] #82 detail routed (routable) nets have been constrained
(e.g. have preferred extra spacing, require shielding etc.)
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #Routed nets constraints summary:
[04/04 17:42:11 1272s] #Miscellaneous constraints include nets with expansionratio, avoid-detour, preferred-bottom-layer or preferred-top-layer etc. attributes
[04/04 17:42:11 1272s] #-----------------------------------------------[04/04 17:42:11 1272s] #

Rules Misc Constraints Unconstrained

[04/04 17:42:11 1272s] #-----------------------------------------------[04/04 17:42:11 1272s] #

Default

[04/04 17:42:11 1272s] #-----------------------------------------------[04/04 17:42:11 1272s] #

Total

[04/04 17:42:11 1272s] #-----------------------------------------------[04/04 17:42:11 1272s] #

[04/04 17:42:11 1272s] #Routing constraints summary of the whole design:
[04/04 17:42:11 1272s] #Miscellaneous constraints include nets with expansionratio, avoid-detour, preferred-bottom-layer or preferred-top-layer etc. attributes
[04/04 17:42:11 1272s] #------------------------------------------------------------------[04/04 17:42:11 1272s] #
Unconstrained

Rules Pref Extra Space Misc Constraints

[04/04 17:42:11 1272s] #------------------------------------------------------------------[04/04 17:42:11 1272s] #

Default

2270

[04/04 17:42:11 1272s] #------------------------------------------------------------------[04/04 17:42:11 1272s] #

Total

2270

[04/04 17:42:11 1272s] #------------------------------------------------------------------[04/04 17:42:11 1272s] #

[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] # Congestion Analysis: (blocked Gcells are excluded)
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #

Total

1(0.01%) (0.01%)

[04/04 17:42:11 1272s] #

[04/04 17:42:11 1272s] # The worst congested Gcell overcon (routing demand
over resource in number of tracks) = 1
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #Complete Global Routing.
[04/04 17:42:11 1272s] #Total number of nets with non-default rule or having
extra spacing = 24
[04/04 17:42:11 1272s] #Total wire length = 71375 um.
[04/04 17:42:11 1272s] #Total half perimeter of net bounding box = 61163 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal1 = 4923 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal2 = 17909 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal3 = 22688 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal4 = 15639 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal5 = 10216 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:42:11 1272s] #Total number of vias = 17739
[04/04 17:42:11 1272s] #Total number of multi-cut vias = 400 ( 2.3%)
[04/04 17:42:11 1272s] #Total number of single cut vias = 17339 ( 97.7%)
[04/04 17:42:11 1272s] #Up-Via Summary (total 17739):
[04/04 17:42:11 1272s] #

[04/04 17:42:11 1272s] #Max overcon = 1 tracks.
[04/04 17:42:11 1272s] #Total overcon = 0.01%.
[04/04 17:42:11 1272s] #Worst layer Gcell overcon rate = 0.00%.
[04/04 17:42:11 1272s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1894.02 (MB), peak = 2271.97 (MB)
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #Start data preparation for track assignment...
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #Data preparation is done on Mon Apr 4 17:42:11 2016
[04/04 17:42:11 1272s] #
[04/04 17:42:11 1272s] #cpu time = 00:00:00, elapsed time = 00:00:00,
memory = 1894.02 (MB), peak = 2271.97 (MB)
[04/04 17:42:11 1272s] #Start Track Assignment.
[04/04 17:42:11 1272s] #Done with 1 horizontal wires in 1 hboxes and 0 vertical
wires in 1 hboxes.
[04/04 17:42:11 1272s] #Done with 0 horizontal wires in 1 hboxes and 0 vertical
wires in 1 hboxes.
[04/04 17:42:11 1272s] #Complete Track Assignment.
[04/04 17:42:11 1272s] #Total number of nets with non-default rule or having
extra spacing = 24
[04/04 17:42:11 1272s] #Total wire length = 71375 um.
[04/04 17:42:11 1272s] #Total half perimeter of net bounding box = 61163 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal1 = 4923 um.

[04/04 17:42:11 1272s] #Total wire length on LAYER Metal2 = 17909 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal3 = 22688 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal4 = 15639 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal5 = 10216 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal6 = 0 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal7 = 0 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal8 = 0 um.
[04/04 17:42:11 1272s] #Total wire length on LAYER Metal9 = 0 um.
[04/04 17:42:11 1272s] #Total number of vias = 17737
[04/04 17:42:11 1272s] #Total number of multi-cut vias = 400 ( 2.3%)
[04/04 17:42:11 1272s] #Total number of single cut vias = 17337 ( 97.7%)
[04/04 17:42:11 1272s] #Up-Via Summary (total 17737):
[04/04 17:42:11 1272s] #

[04/04 17:42:14 1275s] #

By Layer and Type :

[04/04 17:42:14 1275s] #

Short Totals

[04/04 17:42:14 1275s] #

Metal1

[04/04 17:42:14 1275s] #

Metal2

[04/04 17:42:14 1275s] #

Totals

[04/04 17:42:14 1275s] #cpu time = 00:00:00, elapsed time = 00:00:00,

memory = 1945.53 (MB), peak = 2271.97 (MB)
[04/04 17:42:14 1275s] #start 12th optimization iteration ...
[04/04 17:42:14 1275s] #

number of violations = 2

[04/04 17:42:14 1275s] #

By Layer and Type :

[04/04 17:42:14 1275s] #Total number of DRC violations = 2
[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal1 = 0

[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal2 = 2

[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:42:14 1275s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:42:14 1275s] #Cpu time = 00:00:03
[04/04 17:42:14 1275s] #Elapsed time = 00:00:03
[04/04 17:42:14 1275s] #Increased memory = 56.64 (MB)
[04/04 17:42:14 1275s] #Total memory = 1945.53 (MB)
[04/04 17:42:14 1275s] #Peak memory = 2271.97 (MB)
[04/04 17:42:14 1275s] #
[04/04 17:42:14 1275s] #Start Post Routing Optimization.
[04/04 17:42:14 1275s] #start 1st post routing optimization iteration ...
[04/04 17:42:16 1276s] #

number of DRC violations = 2

[04/04 17:42:16 1276s] #

By Layer and Type :

single-cut

multi-cut

Total

[04/04 17:42:16 1276s] #----------------------------------------------------------[04/04 17:42:16 1276s] # Metal 1

9098 ( 95.8%)

400 ( 4.2%)

[04/04 17:42:16 1276s] # Metal 2

6199 (100.0%)

0 ( 0.0%)

6199

[04/04 17:42:16 1276s] # Metal 3

1445 (100.0%)

0 ( 0.0%)

1445

[04/04 17:42:16 1276s] # Metal 4

598 (100.0%)

0 ( 0.0%)

9498

598

[04/04 17:42:16 1276s] #----------------------------------------------------------[04/04 17:42:16 1276s] #

17340 ( 97.7%)

400 ( 2.3%)

[04/04 17:42:16 1276s] #

[04/04 17:42:16 1276s] #Total number of DRC violations = 2

17740

[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal1 = 0

[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:42:16 1276s] #Total number of violations on LAYER Metal9 = 0
[04/04 17:42:16 1276s] #
[04/04 17:42:16 1276s] #start routing for process antenna violation fix ...
[04/04 17:42:17 1277s] #
[04/04 17:42:17 1277s] #

By Layer and Type :

[04/04 17:42:17 1277s] #Total number of DRC violations = 2
[04/04 17:42:17 1277s] #Total number of net violated process antenna rule = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal1 = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal2 = 2
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal3 = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal4 = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal5 = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal6 = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal7 = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal8 = 0
[04/04 17:42:17 1277s] #Total number of violations on LAYER Metal9 = 0

[04/04 17:42:17 1277s] #

[04/04 17:42:17 1277s] #detailRoute Statistics:
[04/04 17:42:17 1277s] #Cpu time = 00:00:06
[04/04 17:42:17 1277s] #Elapsed time = 00:00:06
[04/04 17:42:17 1277s] #Increased memory = 2.48 (MB)
[04/04 17:42:17 1277s] #Total memory = 1891.37 (MB)
[04/04 17:42:17 1277s] #Peak memory = 2271.97 (MB)
[04/04 17:42:17 1277s] #Updating routing design signature
[04/04 17:42:17 1277s] #Created 492 library cell signatures
[04/04 17:42:17 1277s] #Created 2678 NETS and 0 SPECIALNETS signatures
[04/04 17:42:17 1277s] #Created 2269 instance signatures
[04/04 17:42:17 1278s] #
[04/04 17:42:17 1278s] #globalDetailRoute statistics:
[04/04 17:42:17 1278s] #Cpu time = 00:00:07
[04/04 17:42:17 1278s] #Elapsed time = 00:00:07
[04/04 17:42:17 1278s] #Increased memory = -557.95 (MB)
[04/04 17:42:17 1278s] #Total memory = 1337.55 (MB)
[04/04 17:42:17 1278s] #Peak memory = 2271.97 (MB)
[04/04 17:42:17 1278s] #Number of warnings = 18
[04/04 17:42:17 1278s] #Total number of warnings = 469
[04/04 17:42:17 1278s] #Number of fails = 0
[04/04 17:42:17 1278s] #Total number of fails = 1
[04/04 17:42:17 1278s] #Complete globalDetailRoute on Mon Apr 4 17:42:17
2016
[04/04 17:42:17 1278s] #
[04/04 17:42:17 1278s] **optDesign ... cpu = 0:00:58, real = 0:01:00, mem =
1577.4M, totSessionCpu=0:21:12 **
[04/04 17:42:17 1278s] -routeWithEco false

# bool, default=false

[04/04 17:42:17 1278s] -routeSelectedNetOnly false

default=false

# bool,

[04/04 17:42:17 1278s] -routeWithTimingDriven false

default=false, user setting

# bool,

[04/04 17:42:17 1278s] -routeWithSiDriven false

default=false, user setting

# bool,

[04/04 17:42:17 1278s] -drouteStartIteration 0

setting

# int, default=0, user

[04/04 17:42:17 1278s] Extraction called for design 'tdsp_core' of

instances=2268 and nets=2678 using extraction engine 'postRoute' at effort
level 'low' .
[04/04 17:42:17 1278s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:42:17 1278s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:42:17 1278s] PostRoute (effortLevel low) RC Extraction called for
design tdsp_core.
[04/04 17:42:17 1278s] RC Extraction called in multi-corner(2) mode.
[04/04 17:42:17 1278s] Process corner(s) are loaded.
[04/04 17:42:17 1278s] Corner: Arise_rc_corner_cmax
[04/04 17:42:17 1278s] Corner: Arise_rc_corner_cmin
[04/04 17:42:17 1278s] Metal density calculation for erosion effect completed
(CPU=0:00:00.1 MEM=1577.4M)
[04/04 17:42:17 1278s] extractDetailRC Option : -outfile
./tdsp_core_12308_nnzBe5.rcdb.d -maxResLength 200 -extended
[04/04 17:42:17 1278s] RC Mode: PostRoute effortLevel low [Extended CapTable,
RC Table Resistances]
[04/04 17:42:17 1278s]

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:32 1293s] AAE_THRD: End delay calculation. (MEM=1998.95
CPU=0:00:12.2 REAL=0:00:12.0)
[04/04 17:42:32 1293s] *** CDM Built up (cpu=0:00:13.8 real=0:00:14.0
mem= 1998.9M) ***
[04/04 17:42:35 1296s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1998.9M)
[04/04 17:42:35 1296s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:42:35 1296s] Loading CTE timing window is completed (CPU =
0:00:00.2, REAL = 0:00:00.0, MEM = 1960.8M)
[04/04 17:42:35 1296s] SI iteration 2 ...
[04/04 17:42:36 1296s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...

[04/04 17:42:36 1296s] Calculate early delays in OCV mode...

[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...

[04/04 17:42:36 1296s] Calculate early delays in OCV mode...

[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:36 1296s] Calculate early delays in OCV mode...
[04/04 17:42:36 1296s] Calculate late delays in OCV mode...
[04/04 17:42:37 1298s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:38 1299s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:39 1300s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:41 1301s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:42 1302s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:43 1303s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:44 1305s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:45 1306s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:47 1307s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:48 1308s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis

[04/04 17:42:49 1309s] AAE_INFO-618: Total number of nets in the design is

2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:50 1311s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:42:50 1311s] AAE_THRD: End delay calculation. (MEM=2182.99
CPU=0:00:14.2 REAL=0:00:14.0)
[04/04 17:42:50 1311s] *** CDM Built up (cpu=0:00:14.5 real=0:00:14.0
mem= 2183.0M) ***
[04/04 17:42:52 1312s] Running setup recovery post routing.
[04/04 17:42:53 1313s] Timing Snapshot:
[04/04 17:42:53 1313s]

Weighted WNS: -0.006

[04/04 17:42:53 1313s]

All PG WNS: -0.116

[04/04 17:42:53 1313s]

High PG WNS: 0.000

[04/04 17:42:53 1313s]

All PG TNS: -19.253

[04/04 17:42:53 1313s]

High PG TNS: 0.000

Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:57 1317s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:57 1317s] *** Finish setup-recovery (cpu=0:00:00, real=0:00:00,
mem=2146.97M, totSessionCpu=0:21:51 .
[04/04 17:42:57 1317s] **optDesign ... cpu = 0:01:37, real = 0:01:40, mem =
2147.0M, totSessionCpu=0:21:51 **

[04/04 17:42:57 1317s]

[04/04 17:42:57 1317s] Active setup views:
Arise_analysis_view_test_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T150V08
Arise_analysis_view_func_max_cmax_T140V102
Arise_analysis_view_func_max_cmax_T125V108
Arise_analysis_view_test_max_cmax_T125V108
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_max_cmin_T150V08
Arise_analysis_view_test_max_cmin_T150V08
Arise_analysis_view_func_max_cmin_T140V102
Arise_analysis_view_test_max_cmin_T140V102
Arise_analysis_view_func_max_cmin_T125V108
Arise_analysis_view_test_max_cmin_T125V108
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12
Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:57 1317s] Active hold views:
Arise_analysis_view_func_min_cmin_T0V132
Arise_analysis_view_test_min_cmin_T0V132
Arise_analysis_view_func_min_cmin_Tm20V15
Arise_analysis_view_test_min_cmin_Tm20V15
Arise_analysis_view_func_min_cmin_Tm40V18
Arise_analysis_view_test_min_cmin_Tm40V18
Arise_analysis_view_func_nom_cmax_T25V12
Arise_analysis_view_test_nom_cmax_T25V12
Arise_analysis_view_func_nom_cmax_T50V13
Arise_analysis_view_test_nom_cmax_T50V13
Arise_analysis_view_func_nom_cmax_T15V11
Arise_analysis_view_test_nom_cmax_T15V11
Arise_analysis_view_func_min_cmax_T0V132
Arise_analysis_view_test_min_cmax_T0V132
Arise_analysis_view_func_min_cmax_Tm20V15
Arise_analysis_view_func_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm40V15
Arise_analysis_view_test_min_cmax_Tm20V15
Arise_analysis_view_func_nom_cmin_T25V12
Arise_analysis_view_test_nom_cmin_T25V12

Arise_analysis_view_func_nom_cmin_T20V13
Arise_analysis_view_test_nom_cmin_T20V13
Arise_analysis_view_func_nom_cmin_T15V11
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:57 1317s] Reported timing to dir ./timingReports
[04/04 17:42:57 1317s] **optDesign ... cpu = 0:01:37, real = 0:01:40, mem =
2147.0M, totSessionCpu=0:21:51 **
[04/04 17:42:57 1317s] Begin: glitch net info
[04/04 17:42:57 1317s] glitch slack range: number of glitch nets
[04/04 17:42:57 1317s] glitch slack < -0.32 : 0
[04/04 17:42:57 1317s] -0.32 < glitch slack < -0.28 : 0
[04/04 17:42:57 1317s] -0.28 < glitch slack < -0.24 : 0
[04/04 17:42:57 1317s] -0.24 < glitch slack < -0.2 : 0
[04/04 17:42:57 1317s] -0.2 < glitch slack < -0.16 : 0
[04/04 17:42:57 1317s] -0.16 < glitch slack < -0.12 : 0
[04/04 17:42:57 1317s] -0.12 < glitch slack < -0.08 : 0
[04/04 17:42:57 1317s] -0.08 < glitch slack < -0.04 : 0
[04/04 17:42:57 1317s] -0.04 < glitch slack : 0
[04/04 17:42:57 1317s] End: glitch net info
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13

[04/04 17:42:57 1317s] Found active setup analysis view

Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:42:57 1317s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132

[04/04 17:42:57 1317s] Found active hold analysis view

Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12

[04/04 17:42:57 1317s] Found active hold analysis view

Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:42:57 1317s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:42:57 1318s] *info: Starting Blocking QThread with 1 CPU
[04/04 17:43:00 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:01 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:02 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:03 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:04 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:05 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:06 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:07 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:08 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:09 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:10 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:11 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:11 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:43:11 1318s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:11 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:11 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:11 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:11 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:12 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:01.0)
[04/04 17:43:12 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:12 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:12 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:12 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:12 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:12 1318s] AAE_THRD: End delay calculation. (MEM=0
CPU=0:00:12.4 REAL=0:00:13.0)
[04/04 17:43:16 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:17 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:18 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:19 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:20 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:21 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis

[04/04 17:43:22 1318s] AAE_INFO-618: Total number of nets in the design is

2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:23 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:25 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:26 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:27 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:28 1318s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:43:28 1318s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:43:28 1318s] AAE_THRD: End delay calculation. (MEM=0

CPU=0:00:12.3 REAL=0:00:13.0)
[04/04 17:43:31 1351s]
-----------------------------------------------------------optDesign Final SI Timing Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| -0.116 | 0.064 | 0.066 | -0.116 |

TNS (ns):| -19.253 | 0.000 | 0.000 | -19.253 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| 0.003 | 0.078 | 0.256 | 0.003 |

TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 |

|
|

Violating Paths:|

All Paths:| 521 | 432 | 12

| 82

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

was not saved. To save
[04/04 17:44:50 1369s] the RC information, use saveDesign's -rc option. Note:
Saving RC information can be quite large,
[04/04 17:44:50 1369s] so it should only be saved when it is really desired.
[04/04 17:44:50 1369s] Redoing specifyClockTree ...
[04/04 17:44:50 1369s] **WARN: (ENCCK-2070):
is obsolete.

The PadBufAfterGate option

[04/04 17:44:50 1369s] Checking spec file integrity...

[04/04 17:44:50 1369s] Writing Netlist "gopi/timing_tdsp.enc.dat/tdsp_core.v.gz"
...
[04/04 17:44:50 1369s] Saving AAE Data ...
[04/04 17:44:50 1369s] Saving clock tree spec file
'gopi/timing_tdsp.enc.dat/tdsp_core.ctstch' ...
[04/04 17:44:50 1369s] Saving configuration ...
[04/04 17:44:50 1369s] Saving preference file
gopi/timing_tdsp.enc.dat/enc.pref.tcl ...
[04/04 17:44:50 1369s] Saving floorplan ...
[04/04 17:44:50 1369s] Saving Drc markers ...
[04/04 17:44:50 1369s] ... 4 markers are saved ...
[04/04 17:44:50 1369s] ... 2 geometry drc markers are saved ...
[04/04 17:44:50 1369s] ... 0 antenna drc markers are saved ...
[04/04 17:44:50 1369s] Saving placement ...
[04/04 17:44:50 1369s] *** Completed savePlace (cpu=0:00:00.0
real=0:00:00.0 mem=2113.6M) ***
[04/04 17:44:50 1369s] Saving route ...
[04/04 17:44:50 1370s] *** Completed saveRoute (cpu=0:00:00.1
real=0:00:00.0 mem=2113.6M) ***
[04/04 17:44:50 1370s] Writing DEF file
'gopi/timing_tdsp.enc.dat/tdsp_core.def.gz', current time is Mon Apr 4 17:44:50
2016 ...
[04/04 17:44:50 1370s] unitPerMicron=1000, dbgMicronPerDBU=0.001000,
unitPerDBU=1.000000

[04/04 17:44:50 1370s] DEF file 'gopi/timing_tdsp.enc.dat/tdsp_core.def.gz' is

written, current time is Mon Apr 4 17:44:50 2016 ...
[04/04 17:44:50 1370s] Copying Timing Library...
[04/04 17:44:50 1370s] Copying LEF file...
[04/04 17:44:50 1370s] Copying Constraints file(s) ...
[04/04 17:44:51 1370s] Modifying Mode File...
[04/04 17:44:51 1370s] Modifying View File...
[04/04 17:44:51 1370s] Copying ../../LIB/typical_T25_12V.lib...
[04/04 17:44:51 1370s] Copying ../../LIB/fast_Tm20_15V.lib...
[04/04 17:44:51 1370s] Copying ../../LIB/slow_T140_102V.lib...
[04/04 17:44:51 1370s] Copying ../../LIB/fast_T0_132V.lib...
[04/04 17:44:51 1370s] Copying ../../LIB/typical_T50_13V.lib...
[04/04 17:44:51 1370s] Copying ../../LIB/slow_T125_108V.lib...
[04/04 17:44:51 1370s] Copying ../../LIB/typical_T15_11V.lib...
[04/04 17:44:51 1370s] Copying ../../LIB/fast_Tm40_18V.lib...
[04/04 17:44:51 1370s] Copying ../../DATA/captable_cmax...
[04/04 17:44:51 1370s] Copying ../../DATA/qrcTechFile...
[04/04 17:44:51 1370s] Copying ../../DATA/captable_cmin...
[04/04 17:44:51 1370s] Copying test...
[04/04 17:44:51 1371s] Modifying Globals File...
[04/04 17:44:52 1371s] Modifying Power Constraints File...
[04/04 17:44:52 1371s] Generated self-contained design:
/Projects/Training/user5/work/suraj/encounter/rundir/gopi
[04/04 17:44:52 1371s]
[04/04 17:44:52 1371s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:44:52 1371s] Severity ID

Count Summary

[04/04 17:44:52 1371s] WARNING ENCCK-2070

option is obsolete.

1 The PadBufAfterGate

[04/04 17:44:52 1371s] *** Message Summary: 1 warning(s), 0 error(s)

[04/04 17:44:52 1371s]

[04/04 17:45:33 1372s] <CMD> timeDesign -postRoute -hold -outDir
gopi/postroute_optimization
[04/04 17:45:33 1372s] Reset EOS DB
[04/04 17:45:33 1372s] Resetting the settings
[04/04 17:45:33 1372s] Ignoring AAE DB Resetting ...
[04/04 17:45:33 1372s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:45:33 1372s] Extraction called for design 'tdsp_core' of
instances=2268 and nets=2678 using extraction engine 'postRoute' at effort
level 'low' .
[04/04 17:45:33 1372s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:45:33 1372s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:45:33 1372s] PostRoute (effortLevel low) RC Extraction called for
design tdsp_core.
[04/04 17:45:33 1372s] RC Extraction called in multi-corner(2) mode.
[04/04 17:45:33 1372s] Process corner(s) are loaded.
[04/04 17:45:33 1372s] Corner: Arise_rc_corner_cmax
[04/04 17:45:33 1372s] Corner: Arise_rc_corner_cmin
[04/04 17:45:33 1372s] Metal density calculation for erosion effect completed
(CPU=0:00:00.1 MEM=2113.65M)
[04/04 17:45:33 1372s] extractDetailRC Option : -outfile
./tdsp_core_12308_nnzBe5.rcdb.d -maxResLength 200 -extended
[04/04 17:45:33 1372s] RC Mode: PostRoute effortLevel low [Extended CapTable,
RC Table Resistances]
[04/04 17:45:33 1372s]

RC Corner Indexes

[04/04 17:45:33 1372s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:45:33 1372s] Coupling Cap. Scaling Factor : 1.00000 1.00000
[04/04 17:45:33 1372s] Resistance Scaling Factor

: 1.00000 1.00000

[04/04 17:45:33 1372s] Clock Cap. Scaling Factor

: 1.00000 1.00000

[04/04 17:45:33 1372s] Clock Res. Scaling Factor

[04/04 17:45:33 1372s] Shrink Factor

: 1.00000 1.00000

: 1.00000

[04/04 17:45:33 1372s] Initializing multi-corner capacitance tables ...

[04/04 17:45:33 1372s] Initializing multi-corner resistance tables ...
[04/04 17:45:33 1372s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
2113.6M)
[04/04 17:45:33 1373s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for storing RC.
[04/04 17:45:33 1373s] Extracted 10.0055% (CPU Time= 0:00:00.2 MEM=
2144.3M)
[04/04 17:45:33 1373s] Extracted 20.0052% (CPU Time= 0:00:00.3 MEM=
2172.3M)
[04/04 17:45:33 1373s] Extracted 30.0049% (CPU Time= 0:00:00.3 MEM=
2172.3M)
[04/04 17:45:33 1373s] Extracted 40.0046% (CPU Time= 0:00:00.3 MEM=
2172.3M)
[04/04 17:45:33 1373s] Extracted 50.0043% (CPU Time= 0:00:00.4 MEM=
2172.3M)
[04/04 17:45:34 1373s] Extracted 60.004% (CPU Time= 0:00:00.4 MEM=
2172.3M)
[04/04 17:45:34 1373s] Extracted 70.0037% (CPU Time= 0:00:00.5 MEM=
2172.3M)
[04/04 17:45:34 1373s] Extracted 80.0035% (CPU Time= 0:00:00.5 MEM=
2172.3M)
[04/04 17:45:34 1373s] Extracted 90.0032% (CPU Time= 0:00:00.6 MEM=
2172.3M)
[04/04 17:45:34 1373s] Extracted 100% (CPU Time= 0:00:00.8 MEM= 2172.3M)
[04/04 17:45:34 1373s] Number of Extracted Resistors

: 52501

[04/04 17:45:34 1373s] Number of Extracted Ground Cap. : 54854

[04/04 17:45:34 1373s] Number of Extracted Coupling Cap. : 98824
[04/04 17:45:34 1373s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:34 1373s] Filtering XCap in 'relativeOnly' mode using values
relative_c_threshold=0.03 and total_c_threshold=5fF.

[04/04 17:45:34 1373s] Corner: Arise_rc_corner_cmax

[04/04 17:45:34 1373s] Corner: Arise_rc_corner_cmin
[04/04 17:45:34 1373s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
2130.3M)
[04/04 17:45:34 1373s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb_Filter.rcdb.d' for storing RC.
[04/04 17:45:34 1373s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:45:34 1374s] Lumped Parasitic Loading Started (total cpu=0:00:00.0,
real=0:00:00.0, current mem=2130.309M)
[04/04 17:45:34 1374s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:34 1374s] Lumped Parasitic Loading Completed (total
cpu=0:00:00.0, real=0:00:00.0, current mem=2126.293M)
[04/04 17:45:34 1374s] PostRoute (effortLevel low) RC Extraction DONE (CPU
Time: 0:00:01.0 Real Time: 0:00:01.0 MEM: 2126.293M)
[04/04 17:45:34 1374s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:45:34 1374s] SI iteration 1 ...
[04/04 17:45:34 1374s] Begin IPO call back ...
[04/04 17:45:34 1374s] End IPO call back ...
[04/04 17:45:34 1374s]
################################################
#################################
[04/04 17:45:34 1374s] # Design Stage: PostRoute
[04/04 17:45:34 1374s] # Design Mode: 90nm
[04/04 17:45:34 1374s] # Analysis Mode: MMMC OCV
[04/04 17:45:34 1374s] # Extraction Mode: detail/spef
[04/04 17:45:34 1374s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:45:34 1374s] # Switching Delay Calculation Engine to AAE-SI

[04/04 17:45:34 1374s]

################################################
#################################
[04/04 17:45:35 1374s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:45:35 1374s] Setting infinite Tws ...
[04/04 17:45:35 1374s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1572.2M)
[04/04 17:45:35 1374s]

First Iteration Infinite Tw...

[04/04 17:45:35 1374s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1572.2M)
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...

[04/04 17:45:35 1374s] Calculate early delays in OCV mode...

[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Calculate early delays in OCV mode...
[04/04 17:45:35 1374s] Calculate late delays in OCV mode...
[04/04 17:45:35 1374s] Topological Sorting (CPU = 0:00:00.0, MEM = 1572.2M,
InitMEM = 1572.2M)
[04/04 17:45:35 1374s] Initializing multi-corner capacitance tables ...

[04/04 17:45:35 1375s] Initializing multi-corner resistance tables ...

[04/04 17:45:36 1375s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:36 1375s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1942.2M)
[04/04 17:45:36 1375s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:45:36 1375s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:36 1375s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:45:36 1375s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1892.1M)
[04/04 17:45:36 1375s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:45:36 1375s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:36 1375s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:45:36 1375s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1912.2M)
[04/04 17:45:36 1375s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:45:37 1376s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:38 1377s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:39 1378s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:40 1379s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:41 1380s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:42 1381s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis

[04/04 17:45:42 1381s] Opening parasitic data file

'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:42 1381s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:45:42 1381s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1950.4M)
[04/04 17:45:42 1381s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:45:43 1382s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:44 1383s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:45 1384s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:46 1385s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:47 1386s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:48 1387s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:45:48 1387s] AAE_THRD: End delay calculation. (MEM=1950.39
CPU=0:00:12.0 REAL=0:00:12.0)
[04/04 17:45:48 1387s] *** CDM Built up (cpu=0:00:13.7 real=0:00:14.0
mem= 1950.4M) ***
[04/04 17:45:50 1389s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1950.4M)
[04/04 17:45:50 1389s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:45:50 1389s] Loading CTE timing window is completed (CPU =
0:00:00.1, REAL = 0:00:00.0, MEM = 1910.2M)
[04/04 17:45:50 1389s] SI iteration 2 ...
[04/04 17:45:50 1389s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...

[04/04 17:45:50 1389s] Calculate early delays in OCV mode...

[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1389s] Calculate late delays in OCV mode...
[04/04 17:45:50 1389s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...

[04/04 17:45:50 1390s] Calculate early delays in OCV mode...

[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Calculate early delays in OCV mode...
[04/04 17:45:50 1390s] Calculate late delays in OCV mode...
[04/04 17:45:50 1390s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:50 1390s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:45:50 1390s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 2114.4M)
[04/04 17:45:50 1390s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:45:52 1391s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:53 1392s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:54 1393s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:55 1394s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:56 1395s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:57 1397s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:45:57 1397s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:45:57 1397s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:45:57 1397s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 2134.4M)
[04/04 17:45:57 1397s] AAE_INFO: 1 threads acquired from CTE.

[04/04 17:45:58 1398s] AAE_INFO-618: Total number of nets in the design is

2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:00 1399s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:01 1400s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:02 1401s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:03 1403s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:04 1404s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:04 1404s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:46:04 1404s] AAE_THRD: End delay calculation. (MEM=2134.44

CPU=0:00:14.1 REAL=0:00:14.0)
[04/04 17:46:04 1404s] *** CDM Built up (cpu=0:00:14.4 real=0:00:14.0
mem= 2134.4M) ***
[04/04 17:46:05 1404s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but
to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".
[04/04 17:46:05 1404s] Effort level <high> specified for reg2reg path_group
[04/04 17:46:05 1405s] Effort level <high> specified for reg2cgate path_group
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08

[04/04 17:46:05 1405s] Found active setup analysis view

Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:46:05 1405s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12

[04/04 17:46:05 1405s] Found active hold analysis view

Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:46:05 1405s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:46:07 1406s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.

[04/04 17:46:07 1406s] Closing parasitic data file

'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:07 1406s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1908.1M)
[04/04 17:46:07 1406s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:07 1406s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:07 1406s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:07 1406s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1906.1M)
[04/04 17:46:07 1406s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:07 1406s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:07 1406s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:07 1406s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1929.1M)
[04/04 17:46:07 1406s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:08 1407s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:09 1408s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:10 1409s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:11 1410s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:12 1412s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:13 1412s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:13 1412s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.

[04/04 17:46:13 1412s] Closing parasitic data file

'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:13 1412s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1967.3M)
[04/04 17:46:13 1412s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:14 1413s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:15 1414s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:16 1415s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:17 1416s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:18 1417s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:19 1418s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:19 1418s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1418s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1418s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1418s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:19 1419s] AAE_THRD: End delay calculation. (MEM=1967.27
CPU=0:00:12.3 REAL=0:00:12.0)
[04/04 17:46:22 1421s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:22 1421s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:22 1421s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 2134.2M)
[04/04 17:46:22 1421s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:23 1422s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:24 1423s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:25 1424s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:26 1425s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:27 1427s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:28 1427s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:28 1427s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:28 1427s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:28 1427s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 2153.3M)
[04/04 17:46:28 1427s] AAE_INFO: 1 threads acquired from CTE.

[04/04 17:46:29 1428s] AAE_INFO-618: Total number of nets in the design is

2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:30 1430s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:31 1431s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:32 1432s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:33 1433s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:34 1434s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:46:34 1434s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:46:34 1434s] AAE_THRD: End delay calculation. (MEM=2153.31

CPU=0:00:12.4 REAL=0:00:12.0)
[04/04 17:46:35 1435s]
-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Hold mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+
|

WNS (ns):| 0.003 | 0.078 | 0.256 | 0.003 |

TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 |

|
|

Violating Paths:|

All Paths:| 521 | 432 | 12

| 82

+--------------------+---------+---------+---------+---------+

Density: 52.232%
-----------------------------------------------------------Reported timing to dir gopi/postroute_optimization
[04/04 17:46:35 1435s] Total CPU time: 62.21 sec
[04/04 17:46:35 1435s] Total Real time: 62.0 sec
[04/04 17:46:35 1435s] Total Memory Usage: 1516.019531 Mbytes
[04/04 17:46:35 1435s] Reset AAE Options
[04/04 17:46:49 1435s] <CMD> timeDesign -postRoute -outDir
gopi/postroute_optimization
[04/04 17:46:49 1435s] Reset EOS DB
[04/04 17:46:49 1435s] Resetting the settings
[04/04 17:46:49 1435s] Ignoring AAE DB Resetting ...

[04/04 17:46:49 1435s] Closing parasitic data file

'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:49 1435s] Extraction called for design 'tdsp_core' of
instances=2268 and nets=2678 using extraction engine 'postRoute' at effort
level 'low' .
[04/04 17:46:49 1435s] **WARN: (ENCEXT-3530): The process node is not set.
Use the command setDesignMode -process <process node> prior to extraction
for maximum accuracy and optimal automatic threshold setting.
[04/04 17:46:49 1435s] Type 'man ENCEXT-3530' for more detail.
[04/04 17:46:49 1435s] PostRoute (effortLevel low) RC Extraction called for
design tdsp_core.
[04/04 17:46:49 1435s] RC Extraction called in multi-corner(2) mode.
[04/04 17:46:49 1435s] Process corner(s) are loaded.
[04/04 17:46:49 1435s] Corner: Arise_rc_corner_cmax
[04/04 17:46:49 1435s] Corner: Arise_rc_corner_cmin
[04/04 17:46:49 1435s] Metal density calculation for erosion effect completed
(CPU=0:00:00.1 MEM=1516.02M)
[04/04 17:46:49 1435s] extractDetailRC Option : -outfile
./tdsp_core_12308_nnzBe5.rcdb.d -maxResLength 200 -extended
[04/04 17:46:49 1435s] RC Mode: PostRoute effortLevel low [Extended CapTable,
RC Table Resistances]
[04/04 17:46:49 1435s]

RC Corner Indexes

[04/04 17:46:49 1435s] Capacitance Scaling Factor : 1.00000 1.00000

[04/04 17:46:49 1435s] Coupling Cap. Scaling Factor : 1.00000 1.00000
[04/04 17:46:49 1435s] Resistance Scaling Factor

[04/04 17:46:50 1436s] Number of Extracted Ground Cap. : 54854

[04/04 17:46:50 1436s] Number of Extracted Coupling Cap. : 98824
[04/04 17:46:50 1436s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:50 1436s] Filtering XCap in 'relativeOnly' mode using values
relative_c_threshold=0.03 and total_c_threshold=5fF.
[04/04 17:46:50 1436s] Corner: Arise_rc_corner_cmax
[04/04 17:46:50 1436s] Corner: Arise_rc_corner_cmin
[04/04 17:46:50 1436s] Checking LVS Completed (CPU Time= 0:00:00.0 MEM=
1552.7M)
[04/04 17:46:50 1436s] Creating parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb_Filter.rcdb.d' for storing RC.

[04/04 17:46:50 1436s] Closing parasitic data file

'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:50 1436s] Lumped Parasitic Loading Started (total cpu=0:00:00.0,
real=0:00:00.0, current mem=1550.465M)
[04/04 17:46:50 1436s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:50 1436s] Lumped Parasitic Loading Completed (total
cpu=0:00:00.0, real=0:00:00.0, current mem=1546.465M)
[04/04 17:46:50 1436s] PostRoute (effortLevel low) RC Extraction DONE (CPU
Time: 0:00:01.0 Real Time: 0:00:01.0 MEM: 1546.465M)
[04/04 17:46:50 1436s] Generate Setup TimingWindows
[04/04 17:46:50 1436s] SI flow with analysisType aae and Opt Signoff SI using
infinite TWs ...
[04/04 17:46:50 1436s] SI iteration 1 ...
[04/04 17:46:50 1436s]
################################################
#################################
[04/04 17:46:50 1436s] # Design Stage: PostRoute
[04/04 17:46:50 1436s] # Design Mode: 90nm
[04/04 17:46:50 1436s] # Analysis Mode: MMMC OCV
[04/04 17:46:50 1436s] # Extraction Mode: detail/spef
[04/04 17:46:50 1436s] # Delay Calculation Options: engine=aae
SIAware=true(opt_signoff)
[04/04 17:46:50 1436s] # Switching Delay Calculation Engine to AAE-SI
[04/04 17:46:50 1436s]
################################################
#################################
[04/04 17:46:51 1437s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:51 1437s] Setting infinite Tws ...
[04/04 17:46:51 1437s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1550.5M)
[04/04 17:46:51 1437s]

First Iteration Infinite Tw...

[04/04 17:46:51 1437s] Loading CTE timing window is completed (CPU =

0:00:00.0, REAL = 0:00:00.0, MEM = 1550.5M)
[04/04 17:46:51 1437s] Calculate early delays in OCV mode...
[04/04 17:46:51 1437s] Calculate late delays in OCV mode...
[04/04 17:46:51 1437s] Calculate early delays in OCV mode
[04/04 17:46:51 1437s] Topological Sorting (CPU = 0:00:00.0, MEM = 1550.5M,
InitMEM = 1550.5M)
[04/04 17:46:51 1437s] *** Calculating scaling factor for
Arise_max_library_T150V08_set libraries using the default operating condition of
each library.
[04/04 17:46:51 1437s] Initializing multi-corner capacitance tables ...
[04/04 17:46:51 1437s] Initializing multi-corner resistance tables ...
[04/04 17:46:51 1437s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:51 1437s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1920.5M)
[04/04 17:46:51 1437s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:52 1437s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:52 1437s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:52 1437s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1890.5M)
[04/04 17:46:52 1437s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:52 1438s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:52 1438s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:52 1438s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1912.7M)
[04/04 17:46:52 1438s] AAE_INFO: 1 threads acquired from CTE.

[04/04 17:46:53 1439s] AAE_INFO-618: Total number of nets in the design is

2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:54 1440s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:55 1441s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:56 1442s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:57 1443s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:58 1444s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:46:58 1444s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:46:58 1444s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:46:58 1444s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 1950.8M)
[04/04 17:46:58 1444s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:46:59 1445s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:00 1446s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:01 1447s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:02 1448s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:03 1449s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:04 1450s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:04 1450s] AAE_THRD: End delay calculation. (MEM=1950.83
CPU=0:00:12.2 REAL=0:00:12.0)
[04/04 17:47:04 1450s] *** CDM Built up (cpu=0:00:13.9 real=0:00:14.0
mem= 1950.8M) ***
[04/04 17:47:06 1451s] Loading CTE timing window...(CPU = 0:00:00.0, REAL =
0:00:00.0, MEM = 1950.8M)
[04/04 17:47:06 1451s] Add other clocks and setupCteToAAEClockMapping
during iter 1
[04/04 17:47:06 1452s] Loading CTE timing window is completed (CPU =
0:00:00.1, REAL = 0:00:00.0, MEM = 1910.7M)
[04/04 17:47:06 1452s] SI iteration 2 ...
[04/04 17:47:06 1452s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...

[04/04 17:47:06 1452s] Calculate early delays in OCV mode...

[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...

[04/04 17:47:06 1452s] Calculate early delays in OCV mode...

[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Calculate early delays in OCV mode...
[04/04 17:47:06 1452s] Calculate late delays in OCV mode...
[04/04 17:47:06 1452s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:47:06 1452s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:47:06 1452s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 2114.9M)
[04/04 17:47:06 1452s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:47:08 1453s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:09 1454s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:10 1456s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis

[04/04 17:47:11 1457s] AAE_INFO-618: Total number of nets in the design is

2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:12 1458s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:14 1459s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:14 1459s] Opening parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d' for reading.
[04/04 17:47:14 1459s] Closing parasitic data file
'./tdsp_core_12308_nnzBe5.rcdb.d'. 2353 times net's RC data read were
performed.
[04/04 17:47:14 1459s] RC Database In Completed (CPU Time= 0:00:00.0 Real
Time=0:00:00.0 MEM= 2134.9M)
[04/04 17:47:14 1459s] AAE_INFO: 1 threads acquired from CTE.
[04/04 17:47:15 1461s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:16 1462s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:18 1463s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:19 1464s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:20 1465s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:21 1467s] AAE_INFO-618: Total number of nets in the design is
2678, 99.2 percent of the nets selected for SI analysis
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)

[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU

Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_MTTC: End Timing Check Calculation. (CPU
Time=0:00:00.0, Real Time=0:00:00.0)
[04/04 17:47:21 1467s] AAE_THRD: End delay calculation. (MEM=2134.88
CPU=0:00:14.4 REAL=0:00:15.0)
[04/04 17:47:21 1467s] *** CDM Built up (cpu=0:00:14.7 real=0:00:15.0
mem= 2134.9M) ***
[04/04 17:47:22 1467s] **WARN: (ENCTCM-70):
Option "-fixDRC" for
command getSIMode is obsolete and has been replaced by "report_si_slew_max_transition". The obsolete option still works in this release but
to avoid this warning and to ensure compatibility with future releases, update
your script to use "-report_si_slew_max_transition".
[04/04 17:47:22 1467s] Effort level <high> specified for reg2reg path_group
[04/04 17:47:22 1467s] Effort level <high> specified for reg2cgate path_group
[04/04 17:47:22 1467s] Begin: glitch net info
[04/04 17:47:22 1467s] glitch slack range: number of glitch nets
[04/04 17:47:22 1467s] glitch slack < -0.32 : 0
[04/04 17:47:22 1467s] -0.32 < glitch slack < -0.28 : 0
[04/04 17:47:22 1467s] -0.28 < glitch slack < -0.24 : 0
[04/04 17:47:22 1467s] -0.24 < glitch slack < -0.2 : 0
[04/04 17:47:22 1467s] -0.2 < glitch slack < -0.16 : 0
[04/04 17:47:22 1468s] -0.16 < glitch slack < -0.12 : 0
[04/04 17:47:22 1468s] -0.12 < glitch slack < -0.08 : 0

[04/04 17:47:22 1468s] -0.08 < glitch slack < -0.04 : 0

[04/04 17:47:22 1468s] -0.04 < glitch slack : 0
[04/04 17:47:22 1468s] End: glitch net info
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T150V08
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T150V08
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T140V102
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_max_cmax_T125V108
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_max_cmax_T125V108
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_nom_cmax_T15V11
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T150V08
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T150V08
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T140V102
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_max_cmin_T140V102
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_max_cmin_T125V108

[04/04 17:47:22 1468s] Found active setup analysis view

Arise_analysis_view_test_max_cmin_T125V108
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:47:22 1468s] Found active setup analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_T0V132
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_T0V132
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm20V15
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm20V15
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_min_cmin_Tm40V18
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_min_cmin_Tm40V18
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T25V12
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T25V12
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T50V13
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_nom_cmax_T50V13
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_nom_cmax_T15V11

[04/04 17:47:22 1468s] Found active hold analysis view

Arise_analysis_view_test_nom_cmax_T15V11
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_T0V132
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_T0V132
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm20V15
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_min_cmax_Tm40V15
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm40V15
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_min_cmax_Tm20V15
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T25V12
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T25V12
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T20V13
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T20V13
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_func_nom_cmin_T15V11
[04/04 17:47:22 1468s] Found active hold analysis view
Arise_analysis_view_test_nom_cmin_T15V11
[04/04 17:47:25 1470s]
-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------

+--------------------+---------+---------+---------+---------+
|

Setup mode

| all | reg2reg |reg2cgate| default |

+--------------------+---------+---------+---------+---------+

WNS (ns):| -0.116 | 0.064 | 0.066 | -0.116 |

TNS (ns):| -19.253 | 0.000 | 0.000 | -19.253 |

|
|

Violating Paths:| 319 |

| 319 |

All Paths:| 1055 | 432 | 12

| 616 |

+--------------------+---------+---------+---------+---------+

+----------------+-------------------------------+------------------+
|
|
|

|
DRVs

Real

Total

+------------------+------------+------------------|
| Nr nets(terms) | Worst Vio | Nr nets(terms) |

+----------------+------------------+------------+------------------+
| max_cap

0 (0)

| 0.000

0 (0)

| max_tran

0 (0)

| 0.000

0 (0)

| max_fanout |

0 (0)

| max_length |

0 (0)

+----------------+------------------+------------+------------------+

Density: 52.232%
Total number of glitch violations: 0
-----------------------------------------------------------Reported timing to dir gopi/postroute_optimization
[04/04 17:47:25 1470s] Total CPU time: 35.22 sec
[04/04 17:47:25 1470s] Total Real time: 36.0 sec
[04/04 17:47:25 1470s] Total Memory Usage: 2094.722656 Mbytes
[04/04 17:47:25 1470s] Reset AAE Options
[04/04 17:48:39 1471s] <CMD> zoomBox 80.012 132.357 108.011 98.337
[04/04 17:48:40 1471s] <CMD> zoomBox 87.891 121.062 94.191 113.142
[04/04 17:48:43 1471s] <CMD> fit

[04/04 17:49:00 1472s] <CMD> getLogFileName

[04/04 17:49:06 1472s]
[04/04 17:49:06 1472s] *** Memory Usage v#1 (Current mem = 2094.723M,
initial mem = 98.977M) ***
[04/04 17:49:06 1472s]
[04/04 17:49:06 1472s] *** Summary of all messages that are not suppressed in
this session:
[04/04 17:49:06 1472s] Severity ID

Count Summary

[04/04 17:49:06 1472s] WARNING ENCLF-200

has no ANTENNAGAT...

396 Pin '%s' in macro '%s'

[04/04 17:49:06 1472s] WARNING ENCLF-201

has no ANTENNADIF...

384 Pin '%s' in macro '%s'

[04/04 17:49:06 1472s] WARNING ENCFP-3300

greater than 1...

2 FPlan core utilization is

[04/04 17:49:06 1472s] WARNING ENCFP-325

is resized. All ...

3 Floorplan of the design

[04/04 17:49:06 1472s] ERROR

name for the select...

ENCPTN-963

1 Either specified pin

[04/04 17:49:06 1472s] ERROR

track for spreading ...

ENCPTN-970

1 Available [%d] free

[04/04 17:49:06 1472s] WARNING ENCTS-403

forced to extrapol...

1 Delay calculation was

[04/04 17:49:06 1472s] WARNING ENCEXT-6202

technology file, capa...

3 In addition to the

[04/04 17:49:06 1472s] WARNING ENCEXT-2710

layer M%d is ignored...

6 Basic Cap table for

[04/04 17:49:06 1472s] WARNING ENCEXT-2760

in the cap table is ...

12 Layer M%d specified

[04/04 17:49:06 1472s] WARNING ENCEXT-2776

between layers %s and...

48 The via resistance

[04/04 17:49:06 1472s] WARNING ENCEXT-3493

status has been re...
[04/04 17:49:06 1472s] WARNING ENCEXT-3530
not set. Use the com...

5 The design extraction

22 The process node is

[04/04 17:49:06 1472s] ERROR

ENCSYT-16250

[04/04 17:49:06 1472s] WARNING ENCSYC-6163

obsolete and will be mad...
[04/04 17:49:06 1472s] ERROR
command '%s'.

ENCSYC-194

[04/04 17:49:06 1472s] WARNING ENCCK-526

in the Buffer sta...
[04/04 17:49:06 1472s] WARNING ENCCK-2070
option is obsolete.

1 Choose the pin list first.

2 Command '%s' is
7 Incorrect usage for
39 The cell %s (specified
34 The PadBufAfterGate

[04/04 17:49:06 1472s] ERROR

%s specified wi...

ENCCK-543

1 CTS cannot find terminal

[04/04 17:49:06 1472s] ERROR

appear after the R...

ENCCK-3105

[04/04 17:49:06 1472s] ERROR

missing in the cloc...

ENCCK-627

1 The End statement is

[04/04 17:49:06 1472s] ERROR

clock %s in the...

ENCCK-657

2 No cell is specified for

2 The %s statement must

[04/04 17:49:06 1472s] WARNING ENCCK-6323

was moved by %g micr...

1 The placement of %s

[04/04 17:49:06 1472s] WARNING ENCCK-6328

preferred routing lay...

1 The utilization of

[04/04 17:49:06 1472s] WARNING ENCCK-6350

percent resistance d...

35 Clock net %s has %g

[04/04 17:49:06 1472s] WARNING ENCCK-719

synthesized.

2 No clock tree has been

[04/04 17:49:06 1472s] WARNING ENCCK-209

synthesized. Type 'man...

2 Clock %s has been

[04/04 17:49:06 1472s] WARNING ENCCK-767

the clock tree.

4 Find clock buffer %s in

[04/04 17:49:06 1472s] ERROR

ENCCK-9000

11 %s

[04/04 17:49:06 1472s] ERROR

ENCCK-427

7 %s %d: %s

[04/04 17:49:06 1472s] ERROR

rule was specifi...

ENCDB-1221

[04/04 17:49:06 1472s] WARNING ENCDC-1629

was set to %d. T...

3 A global net connection

9 The default delay limit

[04/04 17:49:06 1472s] WARNING ENCPP-531

rule violation, no vi...

12 ViaGen Warning: %s

[04/04 17:49:06 1472s] WARNING ENCPP-532

layer and bottom lay...

36 ViaGen Warning: top

[04/04 17:49:06 1472s] WARNING ENCPP-170

failed to create a wir...

14 The power planner

[04/04 17:49:06 1472s] WARNING ENCPP-4034

start_x/start_y is %s than val...

1 Value for

[04/04 17:49:06 1472s] WARNING ENCPP-610

matching VIARULE, so no...

1 Could not find a

[04/04 17:49:06 1472s] WARNING ENCPP-612

insufficient to...

4 The intersection area is

[04/04 17:49:06 1472s] WARNING ENCSR-4058

should be used in conj...

3 Sroute option: %s

[04/04 17:49:06 1472s] WARNING ENCSR-486

%.3f) (%.3f, %.3f)...

2 Ring/Stripe at (%.3f,

[04/04 17:49:06 1472s] WARNING ENCSP-9025

specified/traced.

9 No scan chain

[04/04 17:49:06 1472s] WARNING ENCSP-9042

defined, -ignoreSca...

9 Scan chains were not

[04/04 17:49:06 1472s] ERROR

needs to be set to 'OC...

ENCOPT-7027

[04/04 17:49:06 1472s] WARNING ENCTCM-70

command %s is obsolete a...

1 The analysis mode

9 Option "%s" for

[04/04 17:49:06 1472s] *** Message Summary: 1111 warning(s), 38 error(s)

[04/04 17:49:06 1472s]
[04/04 17:49:06 1472s] --- Ending "Encounter" (totcpu=0:24:24, real=1:50:54,
mem=2094.7M) ---

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