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Activity Memory Addressing

This document describes a microprocessor system with four main components: the microprocessor, memory, I/O device, and decoder logic. The memory consists of one 2KB ROM chip and three RAM chips totaling 6KB. The decoder logic decodes the microprocessor signals to either read, write, or select the memory and I/O. The document includes figures and tables explaining the memory map, signals, and decoding schema. It also provides three subquestions about determining memory addresses, identifying the correct logic gate for decoding, and deriving the logic functions for the chip select signals.

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Florlyn Mae Sudio Remegio
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92 views

Activity Memory Addressing

This document describes a microprocessor system with four main components: the microprocessor, memory, I/O device, and decoder logic. The memory consists of one 2KB ROM chip and three RAM chips totaling 6KB. The decoder logic decodes the microprocessor signals to either read, write, or select the memory and I/O. The document includes figures and tables explaining the memory map, signals, and decoding schema. It also provides three subquestions about determining memory addresses, identifying the correct logic gate for decoding, and deriving the logic functions for the chip select signals.

Uploaded by

Florlyn Mae Sudio Remegio
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 2

JMJ Marist Brothers

Notre Dame of Marbel University


Alunan Avenue
City of Koronadal

Graduate School
MIT 221
Activity
Memory Addressing

A. Read the following description concerning a simple microprocessor, and then answer Subquestions
1 through 3.

Figure 1. Block schema


The microprocessor system shown in Figure 1 includes four principal blocks:
1. The microprocessor itself.
2. Memory block that consists of 4 integrated circuits (hereinafter, chips) - one ROM chip and 3 RAM
chips (Refer to Figure 2 for more information). The signal CS1 is used for selecting ROM chip, and
signals CS2 to CS4 are used for selecting RAM chips (See Table 2 for more information), and CS1 to
CS4 will be decoded from higher address lines A11 to A15.
3. IO device.
4. Decoder logic block used for decoding memory read MRD, memory write MWR, IO read IORD, and
IO write IOWR from the three microprocessor's signals IO/M , RD, and WR (Refer to Table 1 for more
information).
Signal Name
Address bus
Data bus

Symbol
A0 to A15
D0 to D7

IO/memory
Select

IO/M

Read

RD

Write

WR

Table 1. Microprocessor Signals


Description
16 bit one-directional (output) address lines
8 bit bi-directional data lines
Control output line. This signal has two functions.
1) Select IO: when microprocessor selects IO device, the signal on this
IO/M line is 1.
2) Select memory: when microprocessor selects memory, the signal on
this IO/M line is 0.
Control output line.
When microprocessor reads IO device or memory (ROM or RAM), the signal on
this RD line is 0 in IO/memory reading cycle.
Control output line.
When microprocessor writes IO device or memory (RAM), the signal on this
WR line is 0 in IO/memory writing cycle.

Signal Name
Address bus
Data bus

Chip Select

Read
Write

MIT 221
Activity Memory Addressing

Table 2. Pin Description


Symbol
Description
A0 to A10 11 bit address lines.
D0 to D7
8 bit bi-directional data lines
The signal on the selected memory chip is 0 in
memory reading or writing cycle.
CS
There are CS1 to CS4: CS1 selects ROM chip,
CS2 selects first RAM chip, CS3 selects second
RAM chip, and CS4 selects third RAM chip.
The signal on this line is 0 in memory (ROM or
RD
RAM) reading cycle.
The signal on this line is 0 in memory (RAM)
WR
writing cycle.

Page 1 of 2

JMJ Marist Brothers


Notre Dame of Marbel University
Alunan Avenue
City of Koronadal

Graduate School
MIT 221
Activity
Memory Addressing

Figure 2. Memory Map


2KB ROM
ROM Chip

0000

2KB Empty, reserved


A

4KB RAM
First and Second RAM
Chip

54KB reserved

2KB RAM
Third RAM Chip

FFFF

Subquestion 1: Solve for the memory addresses represented by A, B, and C.


Subquestion 2: Figure 3 below shows how decoder logic works. In Figure 3, four identical logic gates are
used for decoding four signals: memory read, memory write, IO read, and IO write. What
would be the correct type of logic gate to be used?
Figure 3. Decoding Schema

Subquestion 3: The signals CS1 to CS4 are decoded from address lines A11 to A15. What would be the
logic function or signals for CS1, CS2, CS3, and CS4?

MIT 221
Activity Memory Addressing

Page 2 of 2

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