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    Ee 465 Lab 5

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    Richard Jiles and Michael Miller completed an EE lab on synthesis and optimization using an RTL synthesis tool. They optimized a circuit for lower power usage, which reduced power consumption but increased circuit area. They also analyzed timing delays by modifying clock parameters like period, rise/fall times, and latency. Increasing clock period eliminated timing violations. The lab informed them on accounting for non-ideal factors and tradeoffs of power and area optimization. However, the power optimization results were inconsistent, possibly due to restarting the synthesis tool between runs.

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    Ee 465 Lab 5

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    api-302211966
    208 views8 pages
    Richard Jiles and Michael Miller completed an EE lab on synthesis and optimization using an RTL synthesis tool. They optimized a circuit for lower power usage, which reduced power consumption but increased circuit area. They also analyzed timing delays by modifying clock parameters like period, rise/fall times, and latency. Increasing clock period eliminated timing violations. The lab informed them on accounting for non-ideal factors and tradeoffs of power and area optimization. However, the power optimization results were inconsistent, possibly due to restarting the synthesis tool between runs.

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    Richard Jiles and Michael Miller completed an EE lab on synthesis and optimization using an RTL synthesis tool. They optimized a circuit for lower power usage, which reduced power consumption but increased circuit area. They also analyzed timing delays by modifying clock parameters like period, rise/fall times, and latency. Increasing clock period eliminated timing violations. The lab informed them on accounting for non-ideal factors and tradeoffs of power and area optimization. However, the power optimization results were inconsistent, possibly due to restarting the synthesis tool between runs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    208 views8 pages

    Ee 465 Lab 5

    Uploaded by

    api-302211966
    Richard Jiles and Michael Miller completed an EE lab on synthesis and optimization using an RTL synthesis tool. They optimized a circuit for lower power usage, which reduced power consumption but increased circuit area. They also analyzed timing delays by modifying clock parameters like period, rise/fall times, and latency. Increasing clock period eliminated timing violations. The lab informed them on accounting for non-ideal factors and tradeoffs of power and area optimization. However, the power optimization results were inconsistent, possibly due to restarting the synthesis tool between runs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 8

    Richard Jiles

    Michael Miller

    EE 465

    4th October 2016

    EE 465 Synthesis & Optimization Lab


    Introduction
    In this lab we worked with the RTL synthesis tool using the rc interface and our circuit from the
    first lab. We utilized as few source files that would dictate under which optimization the circuit would be
    geared for. Specifically, if we optimized the circuit to use less power, the optimization would create logic
    gates of such sizes to reduce this, coming with a tradeoff that the circuit would take more area.
    Additionally, we may play with the slew characteristics and other properties to analyze the worst path.
    We used a source file that contained all of the given commands and values given in the rubric
    for the lab. These commands would edit values for the rc gui and store them in a timings file of sorts.
    After sourcing the file we usually had to wait 5 10 minutes given the amount of processing that is
    needed and computational power with complex algorithms. In future it would be better to divide and
    conquer given the amount of computing needed, it could be divided between two computers.

    Synthesis and Results


    So we had a series of commands that we inputted to the compiler and we need to explain these
    lines of code.
    define_clock -period -name clk [dc::get_ports {iCLK}] -rise -fall
    What this line of code does is actually change our clock period as well as the amount of time the
    signal takes to either rise or fall. You input these values in picoseconds. The easiest way to get an equal
    clock period high and low would be to choose rise and fall values of 0. This way you neglect them
    completely and do not have to deal with any other values. We find that if we increase the period of the
    clock signal that our slack actually goes to 0. Thus the slack of the worst path is actually decreased.

    Richard Jiles
    Michael Miller

    EE 465

    Arrival time (ps)


    Slack (ps)

    4th October 2016

    Clock Period = 2000


    Default
    ps
    1736
    1995
    -722
    0

    So we used the command to change the clock cycle and produced the data above. Showing that
    changes required to get rid of the timing violation.
    Next we have the command for changing the clock network latency. This command may be viewed as
    follows:
    set_attribute clock_network_late_latency clk
    What this command does is add a delay to the highest value of the clock. It will override the
    clock prorogation delay with this value and add to the max. By doing so we can account for some
    variations and worst cases with the clock signal. We can see this in our results as it adds the latency
    value to the clock signal therby increasing the period itself. We synthesized from the new file and
    created the following table.

    Arrival time (ps)


    Clock after adding Latency (ps)
    Slack (ps)

    Default
    Clock_network_late_latency = 10ps
    1736
    1711
    1000
    1010
    -722
    -706

    After noting the affects from above clock changes we analyzed another commands and its effect
    on the synthesis. This command was for the early latency of the clock:
    set_attribute clock_source_early_latency clk
    What this command does is change the delay between the clock source and the clock pin. Which
    could also be told as the number of clock pulses required by the circuit to give the first output. However

    Richard Jiles
    Michael Miller

    4th October 2016

    EE 465

    because we used such a smalled value for our delay we did not observe much changes. Compared to our
    default values, the new values we collected could be attributed to variations in the optimization and so
    if we closed the program each time before running the values would be different.
    Default
    Clock_source_early_latency = 8ps
    1736
    1000
    -722

    Arrival time (ps)


    Clock after adding Latency (ps)
    Slack (ps)

    1746
    1000
    -731

    The next variation we produced was the clock setup uncertainty. If we increase the clock
    uncertainty, then we would expect the arrival time to increase by an amount of time that is proportional
    to the increase in uncertainty. This uncertainty can be attributed to the jitter which is generated by the
    source or oscillator.
    set_attribute clock_setup_uncertainty clk
    Default
    Arrival time
    (ps)
    Slack (ps)

    Clock setup uncertainty = 50ps

    1736
    -722

    1760
    -816

    After changing the uncertainty we looked at how the slew would affect the circuit and synthesis.
    By increasing the slew we would expect that the arrival time is slightly increased and decreasing the
    slack. Our changes were only slight though as we doubled the slack. We collected the data from the new
    results and gathered the following data:
    set_attribute slew { } [find / -clock clk]
    Default
    Arrival time
    (ps)
    Slack (ps)

    Slew = {200 200 200 200}

    1736
    -722

    1743
    -742
    3

    Richard Jiles
    Michael Miller

    EE 465

    4th October 2016

    We move on now to increasing the external delay, which was given as the following command:
    external_delay -clock clk -input -name in_dly /designs/ALT_MULTADD/ports_in/*
    We see that external delay works by specified if the compiler will include delays specified by the
    latency values using this command. Specifically, if we apply it to the clock we will see a starting delay if
    specifying the input. We see that the starting point of the circuit is delayed roughly by the input delay.
    This created a worst path that was from the sel to the register and thus is from a primary port to a
    register.

    Figure 1 Worst path for input delay changes primary to reg

    Slack (ps)
    Start Point
    End Point

    Default
    external_delay -input 2000 (ps)
    -722
    -1157
    0
    2013
    1717
    2151

    After delaying the input, we then delayed the output whereby we used the same command as
    above but changed it to be output.
    external_delay -clock clk -output -name out_dly /designs/ALT_MULTADD/ports_out/*

    Richard Jiles
    Michael Miller

    EE 465

    4th October 2016

    By utilizing the above command, we now create a situation whereby the start and end point are
    significantly delayed compared to previously. This is because the starting and end point are now at
    different timings. This operation makes the worst path a reg to reg i.e. most critical.

    Figure 2 Output delay worst path picture

    Slack (ps)
    Start Point
    End Point

    Default
    external_delay -output 2000 (ps)
    -722
    -1143
    0
    154
    1717
    2154

    set_attribute external_driver [find [find / -libcell ] -libpin ] /designs/ ALT_MULTADD /ports_in/*


    This is used to discover the output pins and the port of the driving cell and then assign this
    information to the input ports. This means mostly the input is affected and should decrease.
    set_attribute external_pin_cap /designs/ ALT_MULTADD /ports_out/*
    This is used to tell the system what load it is driving in terms of capacitance. We usually put a
    capacitor load on the end of our schematics to simulate load and the same is being done here. And if
    you increase the capacitance then the timing of the output will increase.

    Richard Jiles
    Michael Miller

    EE 465

    4th October 2016

    Finally, for the end of the lab we optimized the power that the circuit used. We chose the
    degree to which the circuit would optimize this factor and analyzed how the area and slack would
    change depending of the level of optimization.
    set_attribute lp_power_unit
    dc::set_max_leakage_power
    set_attribute power_optimization_effort

    These commands work by specifying the unit of power, the max leakage current and the
    optimization level.

    Figure 3 Final parameters for optimization and the source file

    Richard Jiles
    Michael Miller

    EE 465

    4th October 2016

    Figure 4 RC GUI documentation for leakage power optimization

    We find that as we increase the levels of effort for optimization the power should in theory go
    down with each subsequent level. So we ran the flow and discovered that the power optimization flow
    shows improvement compared to the default settings, however there are inconsistencies with the
    power levels shown for each effort level.

    Richard Jiles
    Michael Miller

    EE 465

    Slack (ps)
    Area (um^2)
    Power (uW)

    4th October 2016

    Effort =
    Effort =
    Effort =
    Default
    Low
    Medium
    High
    -735
    -759
    -804
    -777
    8994
    8584
    8450
    8870
    6146.392
    3606.435
    5229.33
    3660

    As we can see the effect of the effort levels is not proportion to what one would think. I
    am getting a little sick of the poor results from this software and the fact I have to restart it every time in
    order to obtain ideal results. We ran of a few of these tests twice just to verify we were getting the
    correct results, and we got the same numbers so you cannot doubt these number. You can however
    doubt the software.

    Conclusion
    This lab informed us of the various constraints you can put on a system when you are optimizing
    the circuitry. If you want to account for non-ideal clock signals or delays inputs or outputs to view the
    effect this would have and how you can account for it. Specifically, how changing the clock period and
    the rise and fall times and how this affects the slack of the system. For power optimization you can
    specify the level but it has a tradeoff where by your area of the circuit is increased.
    A few things to note about this lab is how long the synthesis takes for each change you may
    want to perform. This can be divided between two people and two computers assuming they have the
    same files and do everything correctly. The power optimization software is either not user friendly or is
    not working correctly. This could be due to the fact we had to close the rc window every time we ran a
    synthesis, however we did that for the last part of the lab as well and it didnt seem to help with our
    results.

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