IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 26, NO.

5, AUGUST 2016

1301205

Design and Demonstration of an 8-bit Bit-Serial

RSFQ Microprocessor: CORE e4
Yuki Ando, Ryo Sato, Masamitsu Tanaka, Member, IEEE, Kazuyoshi Takagi, Member, IEEE,
Naofumi Takagi, Senior Member, IEEE, and Akira Fujimaki, Member, IEEE

AbstractWe present a design of an 8-bit bit-serial rapid singleflux-quantum (RSFQ) microprocessor, which is called CORE e4,
and its high-speed functionality test results. The CORE e4 is
equipped with four general-purpose registers and can execute
20 different instructions. The first version of the CORE e4, which
is called CORE e4v1, has been implemented using the National
Institute of Advanced Industrial Science and Technology (AIST)
10-kA/cm2 advanced process (ADP2) and the CONNECT cell
library. The CORE e4v1 consists of approximately 7000 Josephson
junctions and occupies a circuit area of 3.00 mm 1.98 mm. The
estimated power consumption and performance are 2.03 mW and
333 million instructions per second, respectively. CORE e4 is one
of the highest performing RSFQ microprocessors.
Index TermsArithmetic logic unit (ALU), microprocessor,
rapid single flux quantum (RSFQ), superconducting integrated
circuits.

I. I NTRODUCTION

single-flux-quantum (SFQ) circuit is a next-generation

circuit that uses superconductor devices and can realize
ultrahigh-speed computation of tens of gigahertz, as well as low
power consumption. Many SFQ logic circuits with rapid SFQ
(RSFQ) [1] logic have been presented. SFQ logic families, to
achieve further energy efficiency, including reduced-static power RSFQ (LR biasing [2], [3] and LV-RSFQ [4]), zero-static
power RSFQ (ERSFQ [5] and eSFQ [6]), and other ac-biased
new logic families (RQL [7] and AQFP [8]), are also being
developed.
Several RSFQ microprocessors have been developed. In [9],
a design of a microprocessor prototype FLUX was presented.
TIPPY [10][12] was developed around the same time as
FLUX, and the functional simulation results and a demonstration of the component circuits were reported. The development
of bit-serial microprocessors based on the complexity-reduced
Manuscript received January 15, 2016; revised April 4, 2016; accepted
April 13, 2016. Date of publication May 10, 2016; date of current version
June 9, 2016. This work was supported in part by the Advanced Low Carbon
Research and Development Program of the Japan Science and Technology
Agency (JST-ALCA) and in part by the VLSI Design and Education Center
of the University of Tokyo, in collaboration with Cadence Design System, Inc.
This paper was recommended by Associate Editor C. J. Fourie.
Y. Ando, K. Takagi, and N. Takagi are with the Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan (e-mail: [email protected].
kyoto-u.ac.jp; [email protected]).
R. Sato, M. Tanaka, and A. Fujimaki are with the Department of Quantum
Engineering, Nagoya University, Nagoya 464-8601, Japan (e-mail: masami_t@
ieee.org).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TASC.2016.2565609

(CORE) architecture [13], [14] began in 2002. CORE1

[15] and CORE1 [16] have been designed and successfully
demonstrated.
RSFQ data path components have also been developed. An
architecture of large-scale reconfigurable data path [17] was
developed, and the component circuits, including floating-point
units [18] and data path processors [19], were demonstrated.
Although the circuit behavior is not as complex as that of a microprocessor, these data path components are the largest RSFQ
circuits ever designed and tested, in terms of the number of
Josephson junctions (JJs). Developing these large-scale circuits
has become possible with the advances in process technology
[20]. An 8-bit asynchronous wave-pipelined sparse-tree RSFQ
arithmetic logic unit (ALU) [21] and an 8 8-bit multiport
register file [22] have also been designed and demonstrated.
Functionality of the previous RSFQ microprocessors was
limited in several respects. They did not have memory to store
both instructions and data and had only primitive instructions.
Their demonstrated operation frequency was up to 20 GHz.
Therefore, the high switching speed of the RSFQ device was
not fully utilized.
We are currently developing CORE e4 in the CORE e series.
Our goal is to show that developing a stored-program computer
using RSFQ circuits is possible.
II. M ICROARCHITECTURAL D ESIGN
A. Overview
The microarchitecture of CORE e4 is similar to that of
CORE1. The CORE e4 can handle full-fledged programs
such as summation and sorting. It is based on the Harvard
architecture [23]. The target frequency for the system clock is
2 GHz, and the target frequency for the bit-serial processing
is 50 GHz. Four registers are provided, and register indirect
access is adopted to handle sequence data in the memory. The
instruction and data memory have 256 bits (8 bits 32 words)
each and are addressable by a 5-bit address. By devising within
the 8-bit instruction length, the CORE e4 can execute 20 different instructions.
B. Instruction Set
Table I shows the instruction set of CORE e4. The CORE e4
has 20 instructions including ALU instructions (ADD, MV,
SUB, CMP, AND, XOR, OR, NOR, INC, and DEC), data
transfer instructions (LD and ST), immediate instruction (SET),

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TABLE I
I NSTRUCTION S ET OF THE CORE e4

unconditional and conditional branches (JMP, SKGE, SKLT,

SKZ, and SKNZ), halt (HLT), and no operation (NOP). The
bits of instruction words are named op7, op6, . . ., and op0 from
left to right. A and B are register numbers (2 bits each), C is
an address (5 bits), and D is an immediate value (5 bits). The
operand sizes are chosen such that each instruction fits in an
8-bit word while preserving the minimum required range.
After an ALU instruction is executed, program status word
(PSW) is set. A 2-bit PSW indicates whether the calculation
result of the ALU is nonzero and whether it is negative. Data
transfer instructions perform load and store by indirect addressing using Reg0. Immediate instruction sets five least significant
bits to Reg0. (The other bits are set to 0.) Conditional branches
determine whether the condition is satisfied using PSW.

The instruction is decoded at the controller, and the behavior of each component is determined. At ALU instructions, the registers to be read are selected by RegA_num
and RegB_num. Instruction HLT is executed in this phase
(hlt_trg). At instruction JMP, the lower five bits in the IR
are loaded to the PC by pc_ld_trg.
4) Execution 0 (EX0)
At ALU instructions, the content of the registers is read
out. At instruction LD, the DM is accessed to obtain the
value by DM_trg. At instruction ST, the existing data in
the word to be written in the DM are cleared. If the branch
condition is satisfied, the PC is incremented to skip the next
instruction by pc_inc_trg.
5) Execution 1 (EX1)
At ALU instructions, calculation in the ALU is completed and the registers to be read are deselected by
RegA/B_reset. At instruction LD, this phase is the latency
period for data transfer. At instruction ST, data are transferred from the register to the DM through DS2.
6) Write Back (WB)
At ALU instructions, as well as instructions SET and
LD, the register to be written is selected by Write_num.
At ALU instructions, alu_sw is sent to DS1, and the
calculation result of the ALU is sent to the LDB. The value
of the LDB is then written to the register by buffer_trg.
At instruction LD, ld_sw is sent to DS1, and the value of
the DM is sent to the LDB. The value of the LDB is then
written to the register by buffer_trg. At instruction SET,
the lower five bits of the LDB are written to the register by
set_trg.
III. L OGICAL AND P HYSICAL D ESIGN
A. Controller

C. Component Circuits
Fig. 1 shows the microarchitecture of the CORE e4. The
main circuit components are a 5-bit program counter (PC), an
instruction memory (IM), an instruction register (IR), a register
file with four 8-bit registers, a load buffer (LDB), a data memory (DM), an ALU, and a controller. DS1 and DS2 are switches
to select the input data.
D. Instruction Execution
CORE e4 is a multicycle microprocessor. Pipelining is not
adopted for simplicity, and data hazards do not occur in this
architecture. Execution of instructions in CORE e4 consists of
the following six phases.
1) Instruction Fetch 0 (IF0)
An instruction is read out from the IM according to the
value of the PC. The PC is incremented.
2) Instruction Fetch 1 (IF1)
This phase is reserved as the latency period for instruction propagation delay.
3) Instruction Decode (ID)

The controller of CORE e4 consists of a phase counter and a

decoder. The phase counter sends trigger signals to the decoder,
as well as to the other component circuits that work in the
phase. The decoder is a binary decision diagram (BDD)-based
circuit, which works asynchronously without feeding the clock
signal. Instruction words shown in Table I are assigned, so that
the BDD is minimized. The decoder determines the function
of each instruction and then sends a trigger signal to the
corresponding component circuits. When op7 is 1, for example,
the decoder determines that the instruction is an arithmetic or
logic operation and a trigger signal is sent to the ALU.
B. Register File
Fig. 2 shows a block diagram of the register file of CORE
e4. The register file consists of four shift registers (Reg0, Reg1,
Reg2, and Reg3), each of which holds an 8-bit serial data word.
CORE e4 has a buffer that holds a copy of Reg0 and can be
read out in parallel, by which we shorten the access time to the
DM. The 2-bit register numbers are decoded into one-hot code,
and one nondestructive readout cell with complemented output
(NDROC) is selected. The RegA register and write register are
selected by the op0 and op1 signals, and the RegB register is

ANDO et al.: DESIGN AND DEMONSTRATION OF AN 8-bit BIT-SERIAL RSFQ MICROPROCESSOR: CORE e4

1301205

Fig. 1. Microarchitecture of the CORE e4.

Fig. 2. Register File of the CORE e4.

selected by the op2 and op3 signals. The output of the RegA
register is X and that of the RegB register is Y.
C. ALU
We designed an 8-bit ALU to perform ten different instructions. The first version of our ALU is called ALUv1.
Fig. 3 shows a schematic diagram of ALUv1. The operation
to be executed is determined by 4-bit control signals: 1100
(ADD), 1101 (MV), 1110 (SUB), 1111 (CMP), 1010 (AND),
1011 (OR), 1001 (XOR), 1000 (NOR), 0100 (INC), 0110
(DEC). The bits of the control signal are named alu1, alu2,
alu3, and alu4 from left to right. These signals are determined
according to the following equations.

Fig. 3. ALUv1 of the CORE e4.

realized by addition of the twos complement. The constant 1

is added when the incr signal is input. Logical operations are
performed using an AND cell, a NOR cell, and an XOR cell.
The OR operation is realized by merging the AND and XOR
results. The output of the operation result is determined by a
combinational circuit using AND cells. The not zero (NZ)
and negative (NEG) flags are set by examining the operation
result using a D flip-flop (D) and a D flip-flop with reset function (RD). If a 1 exists in the operation result, the NZ flag is
set. If the last bit of the operation result is 1, NEG flag is set.
IV. I MPLEMENTATION AND T ESTING

alu1 = op7;
alu2 = op6 INC DEC;
alu3 = op5;
alu4 = op4.

This ALU performs the decoding of 4-bit control signals

and ALU operations, simultaneously. Arithmetic operations
are performed using a bit-serial adder. This ALU operates on
signed integer values. Instructions SUB, CMP, and DEC are

We implemented the circuits using the National Institute of Advanced Industrial Science and Technology (AIST)
10-kA/cm2 advanced process (ADP2) [20]. First, we demonstrated the operation of ALUv1 using an on-chip high-speed
test [24]. As a result of the measurement, we successfully
obtained the correct operation of ten ALU instructions. The estimated maximum operating frequency based on measurement
results is 80 GHz.

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 26, NO. 5, AUGUST 2016

Fig. 4. Micrograph of the CORE e4v1.

Fig. 6. Input and output waveforms of the LD-LD-ADD-ST instructions.

Fig. 5. Bias margins at instruction MV.

We next fabricated the whole CORE e4. The first version

of CORE e4 is called CORE e4v1. On-chip memory is not
integrated to the CORE e4v1. We arranged a shift register in
place of the memory. Fig. 4 shows a micrograph of CORE e4v1.
CORE e4v1 contains 7194 JJs and occupies an area of
3.00 mm 1.98 mm. The total bias current is 814 mA, and
the total power consumption is estimated to be 2.03 mW. The
bias current is supplied by several bias lines because the circuit
scale is large. CORE e4v1 is partitioned into five parts, namely,
ALU, REG + LDB, PC + IR, controller, and clock generator
(CG), and the bias current of each part is controlled separately.
Fig. 5 shows the dc bias margin of each circuit component when
instruction MV is executed in the high-frequency test. The bias
margins of the component circuits overlap by more than 10%.
The measured dc bias margin did not depend considerably on
the instructions. Not much difference exists in the path of the
Controller, PC + IR, and REG + LDB of instruction MV and
that of the other instructions. The dc bias margins of ALU and
REG + LDB were measured carefully by executing instructions ADD and NOR, and the measured margins were almost
comparable.
Fig. 6 shows a measurement result of the LD-LD-ADD-ST
instructions under high-frequency testing. The input lines labeled inst_din and inst_clk represent data and clock inputs
to the memory, respectively. The input line labeled ld_clk
represents the clock for read out. Unlabeled signals are miscellaneous input signals. The input waveform shows the ADD
(11000001) and ST (00010101) instructions, followed by the
clock pulses fed to the memory (shift register). The output
lines labeled st_dout and st_clkout represent data and clock
outputs from the memory, respectively. The output lines labeled

addr_out and outz represent an address and a calculation result of the ALU, respectively. The output line labeled psw_nz
and psw_neg represent the NZ and NEG flags, respectively.
This result shows the correct operation of 00010101(21) +
00011010(26) = 00101111(47), including the NZ flag which
is correctly set.
Thirteen of the 20 instructions (ADD, MV, SUB, CMP, AND,
XOR, OR, NOR, SET, LD, ST, NOP, and HLT) were successfully demonstrated in our measurement. However, the output
lines labeled addr_out and the operation of INC/DEC instructions were not successfully demonstrated because of errors in
the clock wiring.
V. C ONCLUSION
We have designed, fabricated, and tested the first version
of an 8-bit bit-serial RSFQ microprocessor, which is called
CORE e4. The functionality of some instruction sequences was
demonstrated in the RSFQ microprocessor. A 256-bit (8 bits
32 words) memory component was demonstrated on another
chip [25]. Integrating the memory with CORE e4 will result in
a complete microprocessor system.
ACKNOWLEDGMENT
The circuits were fabricated in the clean room for analog
digital superconductivity (CRAVITY) of the National Institute
of Advanced Industrial Science and Technology (AIST) with
the Advanced Process (ADP2).
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Yuki Ando received the B.E. degree from Ritsumeikan University, Shiga,
Japan, in 2014 and the M.E. degree in informatics from Kyoto University,
Kyoto, Japan, in 2016.
She was with the Graduate School of Informatics, Kyoto University. She has
been involved in the research of architectural and logical design of superconducting circuits.

1301205

Ryo Sato received the B.E. degree in electronics from Nagoya University,
Nagoya, Japan, in 2015.
He is currently with the Department of Quantum Engineering, Nagoya
University, studying high-performance microprocessors based on rapid singleflux-quantum circuits.

Masamitsu Tanaka (M06) received the M.E. and Ph.D. degrees in electronics
and information electronics from Nagoya University, Nagoya, Japan, in 2003
and 2006, respectively.
From 2005 to 2007, he was a Research Fellow of the Japan Society for
the Promotion of Science. In 2007, he joined the Department of Information
Engineering, Nagoya University, and moved to the Department of Quantum
Engineering, where he has been a Designated Lecturer since 2010. In 2011, he
was a Research Scholar with the University of California at Berkeley, Berkeley,
CA, USA. Since 2013, he has also been a Research Associate with the VLSI
Design and Education Center, University of Tokyo, Tokyo, Japan. His research
interests include ultrafast/energy-efficient computing using rapid single-fluxquantum circuits and logic design methodologies.
He is a member of the Institute of Electronics, Information and Communication Engineers, the Japan Society of Applied Physics, the Cryogenics and
Superconductivity Society of Japan, and the Institute of Electrical Engineers of
Japan.

Kazuyoshi Takagi (M04) received the B.E., M.E., and Dr.Eng. degrees from
Kyoto University, Kyoto, Japan, in 1991, 1993, and 1999, respectively, all in
information science.
From 1995 to 1999, he was a Research Associate with the Nara Institute
of Science and Technology, Ikoma, Japan. In 1999, he was an Assistant
Professor with the Department of Information Engineering, Nagoya University,
Nagoya, Japan, where he was promoted to an Associate Professor in 2006. In
2011, he joined the Department of Communications and Computer Engineering, Kyoto University. His current interests include large-scale integration
design and design algorithms.

Naofumi Takagi (SM03) received the B.E., M.E., and Ph.D. degrees from
Kyoto University, Kyoto, Japan, in 1981, 1983, and 1988, respectively, all in
information science.
In 1984, he joined Kyoto University as an Instructor and was promoted to
an Associate Professor in 1991. In 1994, he joined Nagoya University, Nagoya,
Japan, where he was promoted to a Professor in 1998. He returned to Kyoto
University in 2010. His current research interests include computer arithmetic,
hardware algorithms, and logic design.
Dr. Takagi was a recipient of the Japan IBM Science Award and the Sakai
Memorial Award of the Information Processing Society of Japan in 1995 and
the Commendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology of Japan in 2005.

Akira Fujimaki (M10) received the B.E., M.E., and Dr.Eng. degrees from
Tohoku University, Sendai, Japan, in 1982, 1984, and 1987, respectively.
In 1987, he was a Visiting Assistant Research Engineer with the University
of California at Berkeley, Berkeley, CA, USA. Since 1988, he has been working
on superconductor devices and circuits with the School of Engineering, Nagoya
University, Nagoya, Japan, where he is currently a Professor. His current
research interests include single-flux-quantum circuits and their applications
based on low- and high-temperature superconductors.