Instruction Set

Outline

What is an Instruction Set?

Characteristics of a good instruction Set
o Implementability
o Programmability
o Backward/Forward Compatibility
Instruction Format
Classification of an Instruction Format
o Number of Bytes
o Number of Operand Address
Instruction Set Architecture

What is an Instruction Set?

Instruction is a command to a processor to perform certain operations. Each instruction consists
of 2 parts: opcode and operand. The Opcode is the first part of an instruction which specifies the
task to be performed by the processor while the operand is the second part of an instruction that
specifies the data and/or the address. The operand may be an 8-bit data, 8-bit address, 16-bit
data, 16-bit address etc. e.g. MOV 3A00H
To interact with anyone freely, you need to understand the language he speaks. In the case of a
processor its language is the machine language. The set of instructions which a processor
understand is called the instruction set. Once you understand the instruction set of one machine,
it will be very easy to understand that of others. Instruction set is a sequence of 0s and 1s and
the memory is organized in term of bytes. Since this is very cumbersome for human, a step to
make it easier is to represent it in hexadecimal. However, this is still very tedious for human to
understand. The best solution so far is to present the instructions in mnemonics. Mnemonics are
symbols use to represents operands and opcode of an instruction. It is necessary to use welldefined format.
For the purpose of this class, an instruction set is defined as a list of all the instructions, and all
their variations, that a processor (or in the case of a virtual machine, an interpreter) can execute.
An instruction set serves as the vocabulary of the machine. It specifies a processors
functionality:

What operations it supports

What storage mechanisms it has & how they are accessed
How the programmer/compiler communicates programs to processor

Characteristics of a good Instruction Set

There are 3 major metrics to measure the efficiency of an instruction set: implementability,
programmability and backward/forward compatibility.
1. Implementability: This implies that the instruction set has supports for a range of
implementations i.e. instruction set can be implemented across a spectrum of
performance/cost. It implies that it has support for high performance implementations.
Low performance implementation. This is very easy. It is trapped to software to emulate complex
instructions
High performance implementation: This is more difficult. Its components include: pipelining,
parallelism, dynamic scheduling. Its advantages are:
avoid artificial sequential dependencies
deterministic execution latencies simplify scheduling
avoid instructions with multiple long latency components
avoid not-easily-interruptable instructions
2. Programmability:
This indicates the simplicity of expressing programs for human and/or compiler. Before 1975,
most code was hand-assembled i.e. programmed by human (Human programmability). The
instruction sets programmability focus was to be easy for human to program. The ISA
semantically was very close to high-level language (HLL). This closes the semantic gap
between human and computer. It has semantically heavy (CISC-like) instructions which
automatic saves/restores on procedure calls. People thought computers would someday execute
HLL directly however, this never materialized. The major drawback of human programmability
is the semantic clash due to several HLLs. Each programmer designed ISA according to
individual/personal semantic applicability.
Between 1975 and 1985, code was compiled (Compiler Programmability), however people
thought that hand-assembled code was superior. As at 1985, most compiled code was at least as
good as hand-assembly. The focus of instruction sets programmability (easy for compilers) is to
compile to primitive instructions from which solutions are synthesized. It was hard for compiler
to tell if complex instruction fits situation. By the year 2000, a lot of code has been translated
(i.e., java, C#). Current ISAs are targeted to one HLL which is HLL C programming language.
(C) is very low-level (assembly++). Over time, there has come to be a big shift in what
programmability actually stands for. The questions programmers are contemplating now are
will ISAs be different if:
Java was dominant?
It is more object-oriented?
It has support for garbage collection (GC)?
It has support for bounds-checking?
It has more security support?

3. Backward/forward compatibility:
This represents the implementability and programmability across microprocessors generations
e.g., x86 generations: 8086, 286, 386, 486, Pentium, Pentium II, Pentium III, Pentium 4... This is
ensures that all the written software works. In actual fact, the software cost is far greater than the
hardware cost. Intel was the first company to realize this which gives it an edge over other
manufacturers. This accounts for the so many versions of Intel processors in the market.
Backward compatibility is the ability to run old software on new machine. The forward
compatibility allows for future enhancements (upgrade)
Assignment1:
1. Describe the Evolution of Instruction Sets
2. Enumerate and explain the types of instruction sets
3. List and explain the addressing modes you know (at least 7)

Classification of Instruction set

The classification of instruction set in a complete 8085 processor ISA is as follows:

Data Transfer Instruction such as move, input, output, load, and store
Arithmetic Instructions such as add and subtract
Logical Instructions such as and, or, and not
Branching Instructions such as Jump, call, and return
Control Instructions such as Halt, Interrupt

DATA TRANSFER INSTRUCTION

These instructions move data between registers, or between memory and registers. They copy
data from source to destination. While copying, the contents of source are not modified.
S/N
1.

Opcode
MOV

Operand
Rd, Rs
M, Rs
Rd, M

Description
Copy from source to destination

This instruction copies the contents of the source register into the destination register. The
contents of the source register are not altered. If one of the operands is a memory location, its
location is specified by the contents of the HL registers. E.g MOV B, C or MOV B, M
S/N
2.

Opcode
MVI

Operand
Description
Rd, Data
Move immediately 8 bit
M, Data
Rd, M
The 8-bit data is stored in the destination register or memory. If the operand is a memory
location, its location is specified by the contents of the H-L registers. e.g MVI B, 57H or MVI M,
57H
S/N Opcode
Operand
Description
3.
LDA
16-bit address Load Accumulator
The contents of a memory location, specified by a 16- bit address in the operand, are copied to
the accumulator. The contents of the source are not altered. E.g LDA 2034H
S/N Opcode
Operand
Description
4.
LDAX
B/D Register Pair Load Accumulator indirect
The contents of the designated register pair point to a memory location. This instruction copies
the contents of that memory location into the accumulator. The contents of either the register pair
or the memory location are not altered. E.g LDAX B
S/N Opcode
Operand
Description
5.
LXI
Register Pair, 16-bit data Load register pair immediately
This instruction loads 16-bit data in the register pair. E.g LXI, 2034 H
S/N Opcode
Operand
Description
6.
LHLD
16-bit address
Load H-L register direct
This instruction copies the contents of memory location pointed out by 16-bit address into
register L. It copies the contents of next memory location into register H. e.g. LHLD 2040 H
S/N Opcode
Operand
Description
7.
STA
16-bit address
Store Accumulator direct
The contents of accumulator are copied into the memory location specified by the operand. E.g.
STA 2500 H
S/N Opcode
Operand
Description
8.
STAX
Register pair
Store Accumulator indirect
The contents of accumulator are copied into the memory location specified by the contents of the
register pair. E.g. STAX B
S/N
9.

Opcode
SHLD

Operand
16-bit address

Description
Store H-L register direct

The contents of register L are stored into memory location specified by the 16-bit address. The
contents of register H are stored into the next memory location. E.g. SHLD 2550 H
S/N Opcode
Operand
Description
10.
XCHG
None
Exchange H-L with D-E
The contents of register H are exchanged with the contents of register D. The contents of register
L are exchanged with the contents of register E. e.g. XCHG
S/N Opcode
Operand
Description
11.
SPHL
None
Copy H-L pair to the Stack Pointer (SP)
This instruction loads the contents of H-L pair into SP. E.g. SPHL
S/N Opcode
Operand
Description
12.
XTHL
None
Exchange H-L with top of Stack
The contents of L register are exchanged with the location pointed out by the contents of the SP.
The contents of H register are exchanged with the next location (SP + 1). E.g. XTHL
S/N Opcode
Operand
Description
13.
PCHL
None
Load Program Counter with H-L contents
The contents of registers H and L are copied into the program counter (PC). The contents of H
are placed as the high-order byte and the contents of L as the low-order byte. E.g. PCHL
S/N Opcode
Operand
Description
14.
POP
Register pair
Pop stack to register pair
The contents of top of stack are copied into register pair. The contents of location pointed out by
Stack Pointer are copied to the low-order register (C, E, L, Flags). Stack Pointer is then
incremented and the contents of location are copied to the high-order register (B, D, H, A). e.g.
POP H
S/N Opcode
Operand
Description
15.
OUT
8-bit port address Copy data from accumulator to a port with 8-bit address
The contents of accumulator are copied into the I/O port. E.g. OUT 78 H
S/N Opcode
Operand
Description
16.
IN
8-bit port address Copy data to accumulator from a port with 8-bit address
The contents of I/O port are copied into accumulator. E.g. IN 8C H

ARITHMETIC INSTRUCTIONS
These instructions perform the operations like: Addition, Subtraction, Increment and Decrement
Addition: Any 8-bit number, or the contents of register, or the contents of memory location can
be added to the contents of accumulator. The result (sum) is stored in the accumulator. No two
other 8-bit registers can be added directly. For instance, the contents of register B cannot be
added directly to the contents of register C.
Subtraction: Any 8-bit number, or the contents of register, or the contents of memory location
can be subtracted from the contents of accumulator. The result is stored in the accumulator. The

subtraction is performed in 2s complement form if the result is negative; it is stored in 2s

complement form. No two other 8-bit registers can be subtracted directly.
Increment/Decrement: The 8-bit contents of a register or a memory location can be
incremented or decremented by 1. The 16-bit contents of a register pair can be incremented or
decremented by 1. Increment or decrement can be performed on any register or a memory
location.
S/N
1.

Opcode
ADD

Operand
Description
R
Add register or memory to accumulator
M
The contents of register or memory are added to the contents of accumulator. The result is stored
in accumulator. If the operand is memory location, its address is specified by H-L pair. All flags
are modified to reflect the result of the addition. E.g. ADD B or ADD M
S/N Opcode
Operand
Description
2.
ADC
R
Add register or memory to accumulator with carry
M
The contents of register or memory and Carry Flag (CY) are added to the contents of
accumulator. The result is stored in accumulator. If the operand is memory location, its address is
specified by H-L pair. All flags are modified to reflect the result of the addition. E.g. ADC B or
ADC M
S/N Opcode
Operand
Description
3.
ADI
8-bit data
Add immediately to accumulator
The 8-bit data is added to the contents of accumulator. The result is stored in accumulator. All
flags are modified to reflect the result of the addition. E.g. ADI 45 H
S/N Opcode
Operand
Description
4.
ACI
8-bit data
Add immediately to accumulator with carry
The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator. The result is
stored in accumulator. All flags are modified to reflect the result of the addition. E.g. ACI 45 H
S/N Opcode
Operand
Description
5.
DAD
Register pair
Add register pair to H-L pair
The 16-bit contents of the register pair are added to the contents of H-L pair. The result is stored
in H-L pair. If the result is larger than 16 bits, then CY is set. No other flags are changed. E.g.
DAD B
S/N
6.

Opcode
SUB

S/N
7.

Opcode
SBB

Operand
Description
R
Subtract register or memory from accumulator
M
The contents of the register or memory location are subtracted from the contents of the
accumulator. The result is stored in accumulator. If the operand is memory location, its address is
specified by H-L pair. All flags are modified to reflect the result of subtraction. E.g. SUB B or
SUB M
Operand
R
M

Description
Subtract register or memory from accumulator with
borrow

The contents of the register or memory location and Borrow Flag (i.e. CY) are subtracted from
the contents of the accumulator. The result is stored in accumulator. If the operand is memory
location, its address is specified by H-L pair. All flags are modified to reflect the result of
subtraction. E.g. SBB B or SBB M
S/N Opcode
Operand
Description
8.
SUI
8-bit data
Subtract immediately from accumulator
The 8-bit data is subtracted from the contents of the accumulator. The result is stored in
accumulator. All flags are modified to reflect the result of subtraction. E.g. SUI 45 H
S/N Opcode
Operand
Description
9.
SBI
8-bit data
Subtract immediately from accumulator with borrow
The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from the contents of the accumulator.
The result is stored in accumulator. All flags are modified to reflect the result of subtraction. E.g.
SBI 45 H
S/N Opcode
Operand
Description
10.
INR
R
Increment register or memory by 1
M
The contents of register or memory location are incremented by 1. The result is stored in the
same place. If the operand is a memory location, its address is specified by the contents of H-L
pair. E.g. INR B or INR M
S/N Opcode
Operand
Description
11.
INX
R
Increment register pair by 1
The contents of register pair are incremented by 1. The result is stored in the same place. E.g.
INX H
S/N Opcode
Operand
Description
12.
DCR
R
Decrement register or memory by 1
M
The contents of register or memory location are decremented by 1. The result is stored in the
same place. If the operand is a memory location, its address is specified by the contents of H-L
pair. E.g. DCR B or DCR M
S/N Opcode
Operand
Description
13.
DCX
R
Decrement register pair by 1
The contents of register pair are decremented by 1. The result is stored in the same place. E.g.
DCX H
LOGICAL INSTRUCTIONS
These instructions perform logical operations on data stored in registers, memory and status
flags. The logical operations are: AND, OR, XOR, Rotate, Compare and Complement
AND, OR, XOR: Any 8-bit data, or the contents of register, or memory location can logically
have AND, OR and XOR operations with the contents of accumulator. The result is stored in
accumulator.
Rotate: Each bit in the accumulator can be shifted either left or right to the next position.
Compare: Any 8-bit data or the contents of register or memory location can be compared for:

[Equality (=), Greater Than (>) or Less Than (<)] with the contents of the accumulator. The
result is reflected in status flags.
Complement: The contents of accumulator can be complemented. Each 0 is replaced by 1 and
each 1 is replaced by 0.
S/N Opcode
Operand
Description
1.
CMP
R
Compare register or memory with accumulator
M
The contents of the operand (register or memory) are compared with the contents of the
accumulator. Both contents are preserved. The result of the comparison is shown by setting the
flags of the Program Status Word (PSW) as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset.
E.g. CMP B or CMP M
S/N Opcode
Operand
Description
2.
CPI
8-bit data
Compare immediately with accumulator
The 8-bit data is compared with the contents of the accumulator. The values being compared
remain unchanged. The result of the comparison is shown by setting the flags of the PSW as
follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
E.g. CPI 89H
S/N Opcode
Operand
Description
3.
ANA
R
Logical AND register or memory with accumulator
M
The contents of the accumulator are logically ANDed with the contents of register or memory.
The result is placed in the accumulator. If the operand is a memory location, its address is
specified by the contents of H-L pair. The Sign, Zero, Parity flags are modified to reflect the
result of the operation. CY is reset and AC is set. E.g. ANA B or ANA M.
S/N Opcode
Operand
Description
4.
ANI
8-bit data
Logical AND immediate with accumulator
The contents of the accumulator are logically ANDed with the 8-bit data. The result is placed in
the accumulator. The Sign, Zero, Parity flags are modified to reflect the result. CY is reset, AC is
set. E.g. ANI 86H.
S/N Opcode
Operand
Description
5.
ORA
R
Logical OR register or memory with accumulator
M
The contents of the accumulator are logically ORed with the contents of the register or memory.
The result is placed in the accumulator. If the operand is a memory location, its address is
specified by the contents of H-L pair. The Sign, Zero, Parity flags are modified to reflect the
result. CY and AC are reset. E.g. ORA B or ORA M.

S/N
6.

Opcode
ORI

Operand
8-bit data

Description
Logical OR immediate with accumulator

The contents of the accumulator are logically ORed with the 8-bit data. The result is placed in
the accumulator. The Sign, Zero, Parity flags are modified to reflect the result. CY and AC are
reset. E.g. ORI 86H.
S/N
7.

Opcode
XRA

Operand
Description
R
Logical XOR register or memory with accumulator
M
The contents of the accumulator are XORed with the contents of the register or memory. The
result is placed in the accumulator. If the operand is a memory location, its address is specified
by the contents of H-L pair. The Sign, Zero, Parity flags are modified to reflect the result. CY
and AC are reset. E.g. XRA B or XRA M.
S/N Opcode
Operand
Description
8.
XRI
8-bit data
XOR immediate with accumulator
The contents of the accumulator are XORed with the 8-bit data. The result is placed in the
accumulator. The Sign, Zero, Parity flags are modified to reflect the result. CY and AC are reset.
E.g. XRI 86H.
S/N Opcode
Operand
Description
9.
RLC
None
Rotate accumulator left
Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position
of D0 as well as in the Carry flag. CY is modified according to bit D7. The Sign, Zero, Parity and
Auxiliary Carry flags are not affected. E.g. RLC.
S/N Opcode
Operand
Description
10.
RRC
None
Rotate accumulator right
Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the
position of D7 as well as in the Carry flag. CY is modified according to bit D0. The Sign, Zero,
Parity and Auxiliary Carry flags are not affected. E.g. RRC.
S/N Opcode
Operand
Description
11.
RAL
None
Rotate accumulator left through carry
Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7
is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. The
carry flag (CY) is modified according to bit D7. The Sign, Zero, Parity and Auxiliary Carry flags
are not affected. E.g. RAL.
S/N Opcode
Operand
Description
12.
RAR
None
Rotate accumulator right through carry

Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0
is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is
modified according to bit D0. The Sign, Zero, Parity and Auxiliary Carry flags are not affected.
E.g. RAR.
S/N
13.

Opcode
CMA

Operand
None

Description
Complement accumulator

The contents of the accumulator are complemented. No flags are affected. E.g. CMA.
S/N Opcode
Operand
Description
14.
CMC
None
Complement carry
The Carry flag is complemented. No other flags are affected. E.g. CMC.
S/N
15.

Opcode
STC

Operand
None

Description
Set carry

The Carry flag is set to 1. No other flags are affected. E.g. STC.
BRANCHING INSTRUCTION
The branching instructions alter the normal sequential flow. These instructions alter either
unconditionally or conditionally.
S/N Opcode
Operand
Description
1.
JMP
16-bit address
Jump unconditionally
The program sequence is transferred to the memory location specified by the 16-bit address
given in the operand. E.g. JMP 2034 H.
S/N Opcode
Operand
Description
2.
Jx
16-bit address
Jump conditionally
The program sequence is transferred to the memory location specified by the 16-bit address
given in the operand based on the specified flag of the PSW. E.g. JZ 2034 H.
Conditional Jump
Opcode
Description
Status Flags
JC
Jump if Carry
CY = 1
JNC
Jump if No Carry
CY = 0
JP
Jump if Positive
S=0
JM
Jump if Minus
S=1
JZ
Jump if Zero
Z=1
JNZ
Jump if No Zero
Z=0
JPE
Jump if Parity Even
P=1
JPO
Jump if Parity Odd
P=0
Jump conditions
S/N

Opcode

Operand

Description

3.

CALL

16-bit address

Call unconditionally

The program sequence is transferred to the memory location specified by the 16-bit address
given in the operand. Before the transfer, the address of the next instruction after CALL (the
contents of the program counter) is pushed onto the stack. E.g. CALL 2034 H.
S/N
4.

Opcode
Cx

Operand
16-bit address

Description
Call conditionally

The program sequence is transferred to the memory location specified by the 16-bit address
given in the operand based on the specified flag of the PSW. Before the transfer, the address of
the next instruction after the call (the contents of the program counter) is pushed onto the stack.
E.g. CZ 2034 H.
Opcode
CC
CNC
CP
CM
CZ
CNZ
CPE
CPO
Call conditions
S/N
5.

Opcode
RET

Description
Call if Carry
Call if No Carry
Call if Positive
Call if Minus
Call if Zero
Call if No Zero
Call if Parity Even
Call if Parity Odd
Operand
None

Conditional Call
Status Flags
CY = 1
CY = 0
S=0
S=1
Z=1
Z=0
P=1
P=0
Description
Return unconditionally

The program sequence is transferred from the subroutine to the calling program. The two bytes
from the top of the stack are copied into the program counter, and program execution begins at
the new address. E.g. RET.
S/N Opcode
Operand
Description
6.
Rx
16-bit address
Return conditionally
The program sequence is transferred from the subroutine to the calling program based on the
specified flag of the PSW. The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address. E.g RZ
Opcode
RC
RNC
RP
RM

Description
Return if Carry
Return if No Carry
Return if Positive
Return if Minus

Conditional Return
Status Flags
CY = 1
CY = 0
S=0
S=1

RZ
Return if Zero
RNZ
Return if No Zero
RPE
Return if Parity Even
RPO
Return if Parity Odd
Return conditions
S/N
7.

Opcode
RST

Operand
0-7

Z=1
Z=0
P=1
P=0

Description
Restart (Software Interrupts)

The RST instruction jumps the control to one of eight memory locations depending upon the
number. These are used as software instructions in a program to transfer program execution to
one of the eight locations. E.g. RST 3.
Restart Address Table
Instructions
Restart Address
RST 0
0000 H
RST 1
0008 H
RST 2
0010 H
RST 3
0018 H
RST 4
0020 H
RST 5
0028 H
RST 6
0030 H
RST 7
0038 H
CONTROL INSTRUCTIONS
The control instructions control the operation of microprocessor.
S/N Opcode
Operand
Description
1.
NOP
None
No operation
No operation is performed. The instruction is fetched and decoded but no operation is executed.
E.g. NOP
S/N Opcode
Operand
Description
2.
HLT
None
Halt
The CPU finishes executing the current instruction and halts any further execution. An interrupt
or reset is necessary to exit from the halt state. E.g. HLT
S/N
3.

Opcode
DI

Operand
None

Description
Disable Interrupt

The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No
flags are affected. E.g. DI

S/N
4.

Opcode
EI

Operand
None

Description
Enable Interrupt

The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. This
instruction is necessary to re-enable the interrupts (except TRAP). E.g. EI
S/N
5.

Opcode
RIM

Operand
None

Description
Read Interrupt Mask

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial
data input bit. The instruction loads eight bits in the accumulator with the following
interpretations. E.g. RIM
RIM Instruction

S/N
6.

Opcode
SIM

Operand
None

Description
Set Interrupt Mask

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and
serial data output. The instruction interprets the accumulator contents as follows. E.g. SIM
SIM Instruction

Assignment 2: Select two microprocessors of your choice and present a complete

Instruction Set Architecture for each

Modes of Addressing and Assembly Language Format

Outline:
Instruction and Data Format
Addressing modes
o Immediate addressing mode
o Direct addressing mode
o Register addressing mode
o Register indirect addressing mode
o Implicit addressing mode
Assembly Language Format
Concepts of Pseudo-Opcode
INSTRUCTION AND DATA FORMATS
The format of a typical instruction is composed of two parts: an operation code or op-code and
an operand. Every instruction needs an opcode to specify what the operation of the instruction is
and then an operand that gives the appropriate data needed for that particular operation code.
Depending upon the size of machine codes, the 8085 instructions are classified into three types.
(a) One byte or single instructions
(b) Two byte instructions
(c) Three byte instructions
One-byte instructions: A 1
only which is one byte.
Ex: 1. MOV C, A
2. ADD B
3. CMA

byte instruction includes the opcode and the operand in the 8 bits
Hex code = 4FH (one byte)
Hex code = 80H (one byte)
Hex code = 2FH (one byte)

Two-byte instructions: The two byte instruction is one which contains an 8-bit op-code and 8-bit
operand (Data).
Ex: 1. MVI A, 09
Hex code = 3E, 09 (two bytes)
2. ADD B, 07
Hex code = 80, 07 (two bytes)
3. SUB A, 05
Hex code = 97, 05 (two bytes)
Three-byte instructions: In a three byte instruction the first byte is opcode and second and
third bytes are operands i.e. 16-bit data or 16-bit address.
1. LDA 8509H
Hex code = 3A, 09, 85 (Three bytes)
2. LXI 2500H
Hex code = 21, 00, 25 (Three bytes)
3. STA 2600H
Hex code = 32, 00, 26 (Three bytes)

ADDRESSING MODES
To perform any operation, we have to give the corresponding instructions to the microprocessor.
In each instruction, the programmer has to specify 3 basic things:
Operation to be performed.
Address of source of data.
Address of destination of result.
The method by which the address of source of data or the address of destination of result is given
in the instruction is called the Addressing Modes. This refers to the way in which the operand of
the instruction is specified. The various ways of specifying data (or operands) for instructions are
called addressing modes. The 8085 addressing modes are classified into following types:
1. Immediate addressing mode
2. Direct addressing mode
3. Register addressing mode
4. Register indirect addressing mode
5. Implicit addressing mode
Immediate Addressing mode: In this mode, operand is a part of the instruction itself. If the
immediate data is 8-bit, the instruction will be of two bytes. If the immediate data is 16 bit, the
instruction is of 3 bytes.
Examples:
1. MVI 08H;
Move the data 08 H immediately to the accumulator
2. ADI DATA; Add immediate the data to the contents of the accumulator.
3. LXI 8500H; Load immediate the H-L pair with the operand 8500H
4. SUI 05H;
Subtract immediately the data 05H from the accumulator
MVI is the operation; 08 H is the immediate data (source) and A is the destination.
Direct Addressing mode: In this mode, the address of the operand is available in the
instruction itself. It is a 3-byte instruction. The 16-bit address of the operand is directly available
in the instruction itself.
Examples:
1. LDA 9525H; Load the contents of memory location into Accumulator.
2. STA 8000H; Store the contents of the Accumulator in the location 8000H
3. IN 01H;
Read the data from port whose address is 01H.
LDA is the operation; 9525 H is the source address and the accumulator is the destination.
Register addressing modes: In this mode the operands are microprocessor registers only. i.e. the
operation is performed within various registers of the microprocessor. The operand is in the
general purpose register.
Examples:
1. MOV A, B; Move the contents of B register to A register.
2. SUB D;
Subtract the contents of D register from Accumulator.
3. ADD B, C; Add the contents of C register to the contents of B register.
MOV is the operation; B is the source of the data and A is the destination.
Register indirect addressing modes: In this mode, the address of operand is specified by a
register pair. The address of the operand is given in an indirect way with the help of a register

pair. The 16-bit address location of the operand stored in a register pair (H-L) is given in the
instruction. So it is called Register indirect addressing mode.
Examples:
1. MOV A, M; Move the contents of the memory location pointed by the H-L pair to
accumulator
2. LXI 9570H; Load immediate the H-L pair with the address of the location 9570H
3. LDA H
MOV is the operation; M is the memory location specified by the H-L register pair and A is
the destination.
Implicit Addressing mode: The mode of instruction which do not specify the operand in the
instruction but it is implicated, is known as implicit addressing mode. i.e., the operand is
supposed to be present generally in accumulator. If address of source of data as well as address
of destination of result is fixed, then there is no need to give any operand along with the
instruction.
Examples:
1. CMA; Complement the contents of Accumulator
2. CMC; Complement carry
3. RLC; Rotate Accumulator left by one bit
4. RRC; Rotate Accumulator right by one bit
5. STC; Set carry.
CMA is the operation; A is the source and also A is the destination.
ASSEMBLY LANGUAGE FORMAT
The general format of an assembly language instruction is as follows:
[Label:]
[Mnemonics]
[Operand(s)]
[;Comments]
Each instruction of an assembly language program consists of up to four fields. One or more
spaces or special delimiter characters must separate the fields if no blanks are left, it may lead to
an ambiguity. Except in the comments field; no space should appear within a field.
1. Label field: The label field may not always be present. Except for some special operations,
the presence of a label in an instruction is optional. However, if present, it defines symbols
that can be used as a reference point. The label field usually starts from column one and
consists of a variable number of characters. The characters may be either alphabets or
numeric, except that the first character should be alphabet. At least one space or a colon (:)
must terminate the label field.
2. Mnemonic field: All instructions must contain a mnemonic or operation field. The
mnemonic field contains the numeric machine operation code, or an assembler pseudo-code
or a macro call. The mnemonic field follows the label field and is separated from it by at least
one space or by a colon. If there is no label, the opcode may begin in any column position
after column one.
3. Operand(s) field: The operand field specifies value, locations and registers required by the
operation specified in the operation field. As a result, the presence and the meaning of the
operand(s) field depend on the opcode used in the operation field. Some instructions have no

operands, some have one and others have two. If there are two operands, they are separated
by a comma (,). Normally, the destination operand is followed by the source operand. The
notation of each operand must be sufficient to represent the addressing mode to be used in
getting the operand address. The operand field, if present, follows the operation field and is
separated from it by at least one space.
4. Comments field: The comment field is optional and may contain any information that is
used to highlight the operation performed by the instruction. It makes the program selfdocumenting and increases the understandability of the program. The comments field is
preceded by a semicolon (;) delimiter or a space after the operand field. By starting with a
semicolon, the comment field can start from any column, except column one.
Typically an instruction must be contained on one line. Additional lines may be used for
comments if necessary by preceding them with a semicolon. The formatting of the source code is
entirely up to the programmer. Most assemblers are not case sensitive, that is, label and LABEL
would be treated as the same word, however this is entirely up to the creators of the assembler.
Apart from the use of mnemonics in place of machine opcodes and that of symbolic names for
variables, memory and I/O addressed, an assembler provides a number of additional features.
The use of pseudo-opcode is discussed here.
The use of pseudo-ops
Assembly language programs contain some special instructions for the assemblers to perform
specific operations, e.g. to pre-assign values, reserve storage space, define the origin of program,
and so on. Since no equivalent machine code is generated for pseudo-opcodes, although they
appear in the assembly language instruction like an opcode, they provide directives to the
assemblers. Commonly used pseudo-ops are:
1. ORG (origin): This directive is used to indicate the starting address of an object code to the
assembler. The assembler, in turn, translates the entire program, such that it can be executed
with the starting address provided along with the ORG pseudo-op. the number that comes
after ORG can be either in hex or decimal form.
2. EQU (equate): This is used to define a constant without occupying a memory location. The
EQU directive does not set aside storage for a data item but associates a constant value with a
data label so that when the label appears in the program; its constant value will be substituted
for the label.
3. DB (define byte): It is used to define 8-bit data. It is used to put data in a particular location,
or to simply allocate space without pre-assigning anything to that location. When DB is used
to define data, numbers can be in decimal, binary, hex or ASCII format. For decimal, the D
after the decimal is optional, but using B (binary) and H (hexadecimal) for the others is
required. To indicate ASCII, simply place it in quotation marks.
4. END: This indicates the end of the source file. The END directive is the last line of an
assembly language program, meaning that in the source code anything after END directive is
ignored by the assembler.

Examples of common define byte (DB) pseudo-ops

DATA1:
DB
38
;decimal data
DATA2:
DB
01001011B ;binary data
DATA3:
DB
49H
;hex data
DATA4:
DB
34F8
;ASCII data
DATA5:
DB
HELLO
;ASCII data