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Circuit III RSS Output: With A 1, B 1, C 1

The document describes two circuits (Circuit III and Circuit II) implemented using Verilog code. Circuit III is an RSS circuit with inputs a=1, b=1, c=1. It contains modules for the main circuit, a ratsone module, and a rats module. Circuit II is an RSS circuit with inputs A=0, b=0, c=1, d=1, e=1, f=0, g=1, h=1. It also contains the main circuit module and modified ratsone and rats modules to implement RSS logic. Both circuits are then modified to also implement GSS by adding a third input to the main module and rats module.

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35 views16 pages

Circuit III RSS Output: With A 1, B 1, C 1

The document describes two circuits (Circuit III and Circuit II) implemented using Verilog code. Circuit III is an RSS circuit with inputs a=1, b=1, c=1. It contains modules for the main circuit, a ratsone module, and a rats module. Circuit II is an RSS circuit with inputs A=0, b=0, c=1, d=1, e=1, f=0, g=1, h=1. It also contains the main circuit module and modified ratsone and rats modules to implement RSS logic. Both circuits are then modified to also implement GSS by adding a third input to the main module and rats module.

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Anonymous 9ksuyYy34P
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Circuit III

RSS output : with a=1,b=1,c=1

Coding:circuit III (rss)


module ratsmain(clk,a,g,o1,o2);
input clk,a,g;
wire e;

output o1,o2;
tribuffer t1(a,e,a1);
tribuffer t2(g,e,g1);
ratsone t3(clk,a1,g1,b1);
rats t4(clk,a1,b1,o1,o2);
endmodule
module ratsone(clk,a,g,b);
input clk,a,g;
output reg b;
always @(posedge clk)
begin
if((g==1)&&(a==1))
begin
b<=1;
end
else
begin
b<=0;
end
end
endmodule
module rats(clk,a,b,o1,o2);
input clk,a,b;
output o1,o2;
wire c,d,g,h,i,j,k,l,m,n,o,p;
dff f1(clk,a,c);
dff f2(clk,b,d);
and1 f3(c,d,g);
dff f4(clk,g,h);
or1 f5(c,h,i);
or1 f6(d,h,j);
dff f7(clk,i,k);
dff f8(clk,j,l);
and1 f9(k,l,m);
dff f10(clk,m,n);
or1 f11(n,c,o);
or1 f12(n,d,p);
dff f13(clk,o,o1);
dff f14(clk,p,o2);
endmodule
module dff(clk,d,q);
input clk,d;
output reg q;
always@(posedge clk)
begin
if(d==1)
begin q<=1;
end

else begin
q<=0;
end
end
endmodule
module and1(a,b,c);
input a,b;
output c;
assign c=a&b;
endmodule
module or1(a,b,c);
input a,b;
output c;
assign c=a|b;
endmodule
module tribuffer(a,e,y);
input a,e;
output reg y;
always @(e)
begin
if(e==0)
begin
y<=a;
end
else
begin
y<=0;
end
end
endmodule

coding:
circuit III (RSS+GSS)
a=1,b=1,c=1,f=1
module ratsmain(clk,a,g,m,o1,o2);
input clk,a,g,m;
wire e;
output o1,o2;
tribuffer t1(a,e,a1);
tribuffer t2(g,e,g1);
tribuffer t3(m,e,m1);
ratsone t4(clk,a1,g1,b1);

rats t5(clk,a1,b1,m1,o1,o2);
endmodule
module ratsone(clk,a,g,b);
input clk,a,g;
output reg b;
always @(posedge clk)
begin
if((g==1)&&(a==1))
begin
b<=1;
end
else
begin
b<=0;
end
end
endmodule
module rats(clk,a,b,m,o1,o2);
input clk,a,b,m;
output o1,o2;
wire c,d,g,h,i,j,k,l,n,o,p;
dff f1(clk,a,c);
dff f2(clk,b,d);
and1 f3(c,d,g);
dff f4(clk,g,h);
or1 f5(c,h,i);
or1 f6(d,h,j);
dff f7(clk,i,k);
dff f8(clk,j,l);
and1 f9(k,l,m);
dff f10(clk,m,n);
or1 f11(n,c,o);
or1 f12(n,d,p);
dff f13(clk,o,o1);
dff f14(clk,p,o2);
endmodule
module dff(clk,d,q);
input clk,d;
output reg q;
always@(posedge clk)
begin

if(d==1)
begin q<=1;
end
else begin
q<=0;
end
end
endmodule
module and1(a,b,c);
input a,b;
output c;
assign c=a&b;
endmodule
module or1(a,b,c);
input a,b;
output c;
assign c=a|b;
endmodule
module tribuffer(a,e,y);
input a,e;
output reg y;
always @(e)
begin
if(e==0)
begin
y<=a;
end
else
begin
y<=0;
end
end
endmodule

Circuit II :
RSS

A=0,b=0,c=1,d=1,e=1,f=0,g=1,h=1

Coding:CIRCUIT ii (rss)
module ratsmain(clk,a,g,o1,o2);
input clk,a,g;
wire e;
output o1,o2;

tribuffer t1(a,e,a1);
tribuffer t2(g,e,g1);
ratsone t3(clk,a1,g1,b1);
rats t4(clk,a1,b1,o1,o2);
endmodule
module ratsone(clk,a,g,b);
input clk,a,g;
output reg b;
always @(posedge clk)
begin
if((g==1)&&(a==0))
begin
b<=0;
end
else
begin
b<=1;
end
end
endmodule
module rats(clk,a,b,o1,o2);
input clk,a,b;
output o1,o2;
wire c,d,g,h,i,j,k,l,m,n,o,p;
dff f1(clk,a,c);
dff f2(clk,b,d);
nor1 f3(c,d,g);
dff f4(clk,g,h);
nand1 f5(c,h,i);
nand1 f6(d,h,j);
dff f7(clk,i,k);
dff f8(clk,j,l);
nor1 f9(k,l,m);
dff f10(clk,m,n);
nand1 f11(n,c,o);
nand1 f12(n,d,p);
dff f13(clk,o,o1);
dff f14(clk,p,o2);
endmodule

module dff(clk,d,q);
input clk,d;
output reg q;
always@(posedge clk)
begin
if(d==1)
begin q<=1;
end
else begin
q<=0;
end
end
endmodule
module nand1(a,b,c);
input a,b;
output c;
assign c=~(a&b);
endmodule
module nor1(a,b,c);
input a,b;
output c;
assign c=~(a|b);
endmodule
module tribuffer(a,e,y);
input a,e;
output reg y;
always @(e)
begin
if(e==0)
begin
y<=a;
end
else
begin
y<=0;
end
end
endmodule
circuit II
RSS+GSS

module ratsmain(clk,a,g,m,o1,o2);
input clk,a,g,m;
wire e;
output o1,o2;
tribuffer t1(a,e,a1);
tribuffer t2(g,e,g1);
tribuffer t3(m,e,m1);
ratsone t4(clk,a1,g1,b1);
rats t5(clk,a1,b1,o1,o2);
endmodule
module ratsone(clk,a,g,b);
input clk,a,g;
output reg b;
always @(posedge clk)
begin
if((g==1)&&(a==0))
begin
b<=0;
end
else
begin
b<=1;

end
end
endmodule
module rats(clk,a,b,m,o1,o2);
input clk,a,b,m;
output o1,o2;
wire c,d,g,h,i,j,k,l,n,o,p;
dff f1(clk,a,c);
dff f2(clk,b,d);
nor1 f3(c,d,g);
dff f4(clk,g,h);
nand1 f5(c,h,i);
nand1 f6(d,h,j);
dff f7(clk,i,k);
dff f8(clk,j,l);
nor1 f9(k,l,m);
dff f10(clk,m,n);
nand1 f11(n,c,o);
nand1 f12(n,d,p);
dff f13(clk,o,o1);
dff f14(clk,p,o2);
endmodule
module dff(clk,d,q);
input clk,d;
output reg q;
always@(posedge clk)
begin
if(d==1)
begin q<=1;
end
else begin
q<=0;
end
end
endmodule
module nand1(a,b,c);
input a,b;
output c;
assign c=~(a&b);
endmodule
module nor1(a,b,c);

input a,b;
output c;
assign c=~(a|b);
endmodule
module tribuffer(a,e,y);
input a,e;
output reg y;
always @(e)
begin
if(e==0)
begin
y<=a;
end
else
begin
y<=0;
end
end
endmodule

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