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Muhammad Basyir Bin Burhanuddin 1227025 Lab Assignment

1. The document discusses CMOS NAND and NOR logic gates. It explains how the gates are constructed using pFET and nFET transistors. 2. For a NAND gate, the output is 1 when any of the inputs are 0. This is because the pFET transistors are in parallel. For a NOR gate, the output is 1 only when both inputs are 0, since the pFETs are in series. 3. Circuit diagrams and timing waveforms are provided to illustrate the behavior of the CMOS NAND and NOR gates during simulation. The gates function as expected based on their transistor configurations and logic tables.

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89 views

Muhammad Basyir Bin Burhanuddin 1227025 Lab Assignment

1. The document discusses CMOS NAND and NOR logic gates. It explains how the gates are constructed using pFET and nFET transistors. 2. For a NAND gate, the output is 1 when any of the inputs are 0. This is because the pFET transistors are in parallel. For a NOR gate, the output is 1 only when both inputs are 0, since the pFETs are in series. 3. Circuit diagrams and timing waveforms are provided to illustrate the behavior of the CMOS NAND and NOR gates during simulation. The gates function as expected based on their transistor configurations and logic tables.

Uploaded by

Basyir Al-Mashoori
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MUHAMMAD BASYIR BIN BURHANUDDIN

1227025
LAB ASSIGNMENT
Before we proceed further to the CMOS NAND and NOR gate, we will discuss on basic AND and OR
logic.

NAND Inverter

Figure 1

Figure 1 shows an example of AND logic circuit. Assume the switch is an input. Thus, to make the light
bulb ON or 1, input A and input B must be ON or 1. It is because the circuit is a series
connection. However, when either one of the input is OFF or 0, the light bulb will OFF or 0. The
truth table for the AND gate are as follows:
A
0
0
1
1

B
0
1
0
1

OUTPUT
0
0
0
1

Thus, for NAND logic, we just can conclude the inversion from the AND output which are:
A
0
0
1
1

B
0
1
0
1

AND
0
0
0
1

NAND
1
1
1
0

As we learned from the previous lab example (INVERTER), pFET is responsible for the
conduction of current leading a logic 1 at the output, while nFET leading a logic 0 at output. Thus

from this understanding, as long there are no voltage supply at input, the output will be 1 as the current
flows through the pFET.
1. Components were dropped and dragged to the board as shown in figure 2. The width and length of the
transistors size were also adjusted.

Figure 2

2 pFETs were placed in a parallel, while two nFETs were placed in a series. Thus whenever there are no
voltage, 0 at input (A and B) the output will 1.
2. Start the simulation.

Figure 3

The Vdd is higher than the voltage at input, pFET responsible for current conduction a logic 1 at output.

Figure 4

Figure 4 shows that, input A is 1 while input B is 0. As the pFET is in parallel connection, as the
Vdd is higher than any voltage at input, the net output will be 1.

Figure 5

Figure 5 shows the same result with figure 4.

Figure 6

Now, when both input A and input B are ON or 1, it is higher than Vdd, thus no current flow at both
pFET. The result at output is 0.
3. Toggle the input value 1 and 0 to get a timing diagrams.

Figure 7

Thus, as we can see from the figure 7, when either one of the input is 0 the output will be 1. On the
other hand, when both input is 1, the output will be 0. This is CMOS NAND inverter.

NOR Inverter

Figure 8

Figure 8 shows an example of OR logic circuit. Assume the switch is an input. Thus, to make the light
bulb ON or 1, either one of input A and input B must be ON or 1. It is because the circuit is a
parallel connection. This means, when both of them is OFF, the output is 0. The truth table for the
OR gate are as follows:

A
0
0
1
1

B
0
1
0
1

OUTPUT
0
1
1
1

Thus, for NAND logic, we just can conclude the inversion from the AND output which are:
A
0
0
1
1

B
0
1
0
1

OR
0
1
1
1

NOR
1
0
0
0

1. Components were dropped and dragged to the board as shown in figure 9. The width and length of the
transistors size were also adjusted.

Figure 9

2 pFETs were placed in series while 2 nFETs in parallel, thus to make the output 1, both input A and
input B should be 0. The objective is to make the current can flow at both pFETs so that, current can
flows to make the output 1.
2. Start the simulation.

Figure 10

From the figure 10, we can see that the output is ON or 1, this is because, both input A and input B
is 0. The current flows at both switch.

Figure 11

Figure 11 shows that, although input B is 0 the resulting output still 0. As we discussed before, the
pFET connection is in series. Thus, both switch need to be connected in order to make the current flows
(Vdd must be greater).

Figure 12

Above figure concept is same as figure 11.

Figure 13

Both input A and input B is 1. Thus output is 0.


3. Toggle the input value to get the timing diagrams.

Figure 14

Thus, as we can see from the figure 14, both of input must be 0 in order to get 1 at output. On the
other hand, when both either one of the input is 1 the output will be 0. This is CMOS NOR inverter.

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