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*******************************************************************
* Copyright (c) Cadence Design Systems, Inc. 1996 - 2014.
*

All rights reserved.

* This program contains confidential and trade secret information *

* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use,

* distribution or disclosure of this program or any portion of it,*

* or any attempt to obtain a human-readable version of this

* program, without the express, prior written consent of

* Cadence Design Systems, Inc., is strictly prohibited.
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Cadence Design Systems, Inc.

2655 Seely Avenue

San Jose, CA 95134, USA

*******************************************************************

@(#)CDS: Encounter v14.28-s033_1 (64bit) 03/21/2016 13:34 (Linux 2.6.18194.el5)

@(#)CDS: NanoRoute v14.28-s005 NR160313-1959/14_28-UB (database version

2.30, 267.6.1) {superthreading v1.25}
@(#)CDS: CeltIC v14.28-s006_1 (64bit) 03/08/2016 00:08:23 (Linux 2.6.18194.el5)
@(#)CDS: AAE 14.28-s002 (64bit) 03/21/2016 (Linux 2.6.18-194.el5)
@(#)CDS: CTE 14.28-s007_1 (64bit) Mar 7 2016 23:11:05 (Linux 2.6.18-194.el5)
@(#)CDS: CPE v14.28-s006
@(#)CDS: IQRC/TQRC 14.2.2-s217 (64bit) Wed Apr 15 23:10:24 PDT 2015 (Linux
2.6.18-194.el5)
@(#)CDS: OA 22.50-p011 Tue Nov 11 03:24:55 2014
@(#)CDS: SGN 10.10-p124 (19-Aug-2014) (64 bit executable)
@(#)CDS: RCDB 11.5
--- Starting "Encounter v14.28-s033_1" on Fri Apr 1 16:07:17 2016
(mem=99.0M) ----- Running on SRV01 (x86_64 w/Linux 2.6.18-308.el5) --This version was compiled on Mon Mar 21 13:34:48 PDT 2016.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000

**INFO: MMMC transition support version v31-84

<CMD> set_global _enable_mmmc_by_default_flow

<CMD> suppressMessage ENCEXT-2799
<CMD> win
<CMD> set conf_ioOri R0
<CMD> set conf_qxconf_file NULL
<CMD> set conf_qxlib_file NULL
<CMD> set dcgHonorSignalNetNDR 1
<CMD> set defHierChar /

$CTE::mmmc_default

<CMD> set delaycal_input_transition_delay 0.1ps

Set Input Pin Transition Delay as 0.1 ps.
<CMD> set distributed_client_message_echo 1
<CMD> set fpAllowShifterIn3rdPD 1
<CMD> set fpIsMaxIoHeight 0
<CMD> set fp_core_height 147.060000
<CMD> set fp_core_width 148.685000
<CMD> set gpsPrivate::dpgNewAddBufsDBUpdate 1
<CMD> set gpsPrivate::lsgEnableNewDbApiInRestruct 1
<CMD> set init_design_settop 0
<CMD> set init_gnd_net {VSS }
<CMD> set init_lef_file ../../LEF/gsclib045.lef
<CMD> set init_oa_search_lib {}
<CMD> set init_pwr_net VDD
<CMD> set init_verilog ../../NETLIST/tdsp_core.v
<CMD> set lsgOCPGainMult 1.000000
<CMD> set pegDefaultResScaleFactor 1.000000
<CMD> set pegDetailResScaleFactor 1.000000
<CMD> set ptngPAMaxRouteLayer 9
<CMD> set spgDecolorGeom 1
<CMD> set timing_library_float_precision_tol 0.000010
<CMD> set timing_library_load_pin_cap_indices {}
<CMD> set timing_library_mark_cell_latch_construct_flag 0
<CMD> set tso_post_client_restore_command {update_timing ; write_eco_opt_db
;}
<CMD> create_rc_corner -name my_rc_corner_cmax -cap_table
{../../DATA/captable_cmax} -T {125} -preRoute_res {1.0} -preRoute_cap {1.0}
-preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0}
-postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0}
-postRoute_clkcap {0.0} -qx_tech_file {../../DATA/qrcTechFile}

<CMD> create_rc_corner -name my_rc_corner_cmin -cap_table

{../../DATA/captable_cmin} -T {25} -preRoute_res {1.0} -preRoute_cap {1.0}
-preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0}
-postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0}
-postRoute_clkcap {0.0} -qx_tech_file {../../DATA/qrcTechFile}
<CMD> create_library_set -name my_max_library_T150V08_set -timing
{../../LIB/slow_T150_08V.lib}
<CMD> create_library_set -name my_max_library_T140V102_set -timing
{../../LIB/slow_T140_102V.lib}
<CMD> create_library_set -name my_max_library_T125V108_set -timing
{../../LIB/slow_T125_108V.lib}
<CMD> create_library_set -name my_min_library_T0V132_set -timing
{../../LIB/fast_T0_132V.lib}
<CMD> create_library_set -name my_min_library_Tm20V15_set -timing
{../../LIB/fast_Tm20_15V.lib}
<CMD> create_library_set -name my_min_library_Tm40V18_set -timing
{../../LIB/fast_Tm40_18V.lib}
<CMD> create_library_set -name my_nom_library_T25V12_set -timing
{../../LIB/typical_T25_12V.lib}
<CMD> create_library_set -name my_nom_library_T50V13_set -timing
{../../LIB/typical_T50_13V.lib}
<CMD> create_library_set -name my_nom_library_T15V11_set -timing
{../../LIB/typical_T15_11V.lib}
<CMD> create_constraint_mode -name func -sdc_files {../../SDC/func.sdc}
<CMD> create_constraint_mode -name test -sdc_files {../../SDC/test.sdc}
<CMD> create_delay_corner -name my_delay_corner_max_cmax_T150V08
-library_set {my_max_library_T150V08_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_max_cmax_T140V102
-library_set {my_max_library_T140V102_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_max_cmax_T125V108
-library_set {my_max_library_T125V108_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_min_cmin_T0V132
-library_set {my_min_library_T0V132_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_delay_corner -name my_delay_corner_min_cmin_Tm20V15
-library_set {my_min_library_Tm20V15_set} -rc_corner {my_rc_corner_cmin}

<CMD> create_delay_corner -name my_delay_corner_min_cmin_Tm40V18

-library_set {my_min_library_Tm40V18_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_delay_corner -name my_delay_corner_nom_cmax_T25V12
-library_set {my_nom_library_T25V12_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_nom_cmax_T50V13
-library_set {my_nom_library_T50V13_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_nom_cmax_T15V11
-library_set {my_nom_library_T15V11_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_max_cmin_T150V08
-library_set {my_max_library_T150V08_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_delay_corner -name my_delay_corner_max_cmin_T140V102
-library_set {my_max_library_T140V102_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_delay_corner -name my_delay_corner_max_cmin_T125V108
-library_set {my_max_library_T125V108_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_delay_corner -name my_delay_corner_min_cmax_T0V132
-library_set {my_min_library_T0V132_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_min_cmax_Tm20V15
-library_set {my_min_library_Tm20V15_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_min_cmax_Tm40V15
-library_set {my_min_library_Tm40V18_set} -rc_corner {my_rc_corner_cmax}
<CMD> create_delay_corner -name my_delay_corner_nom_cmin_T25V12
-library_set {my_nom_library_T25V12_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_delay_corner -name my_delay_corner_nom_cmin_T20V13
-library_set {my_nom_library_T50V13_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_delay_corner -name my_delay_corner_nom_cmin_T15V11
-library_set {my_nom_library_T15V11_set} -rc_corner {my_rc_corner_cmin}
<CMD> create_analysis_view -name my_analysis_view_test_max_cmax_T150V08
-constraint_mode {test} -delay_corner {my_delay_corner_max_cmax_T150V08}
<CMD> create_analysis_view -name
my_analysis_view_func_max_cmax_T150V08 -constraint_mode {func}
-delay_corner {my_delay_corner_max_cmax_T150V08}
<CMD> create_analysis_view -name
my_analysis_view_func_max_cmax_T140V102 -constraint_mode {func}
-delay_corner {my_delay_corner_max_cmax_T140V102}

<CMD> create_analysis_view -name

myanalysis_view_test_max_cmax_T140V102 -constraint_mode {test}
-delay_corner {my_delay_corner_max_cmax_T140V102}
<CMD> create_analysis_view -name
my_analysis_view_func_max_cmax_T125V108 -constraint_mode {func}
-delay_corner {my_delay_corner_max_cmax_T125V108}
<CMD> create_analysis_view -name
my_analysis_view_test_max_cmax_T125V108 -constraint_mode {test}
-delay_corner {my_delay_corner_max_cmax_T125V108}
<CMD> create_analysis_view -name my_analysis_view_func_min_cmin_T0V132
-constraint_mode {func} -delay_corner {my_delay_corner_min_cmin_T0V132}
<CMD> create_analysis_view -name my_analysis_view_test_min_cmin_T0V132
-constraint_mode {test} -delay_corner {my_delay_corner_min_cmin_T0V132}
<CMD> create_analysis_view -name my_analysis_view_func_min_cmin_Tm20V15
-constraint_mode {func} -delay_corner {my_delay_corner_min_cmin_Tm20V15}
<CMD> create_analysis_view -name my_analysis_view_test_min_cmin_Tm20V15
-constraint_mode {test} -delay_corner {my_delay_corner_min_cmin_Tm20V15}
<CMD> create_analysis_view -name my_analysis_view_func_min_cmin_Tm40V18
-constraint_mode {func} -delay_corner {my_delay_corner_min_cmin_Tm40V18}
<CMD> create_analysis_view -name my_analysis_view_test_min_cmin_Tm40V18
-constraint_mode {test} -delay_corner {my_delay_corner_min_cmin_Tm40V18}
<CMD> create_analysis_view -name my_analysis_view_func_nom_cmax_T25V12
-constraint_mode {func} -delay_corner {my_delay_corner_nom_cmax_T25V12}
<CMD> create_analysis_view -name my_analysis_view_test_nom_cmax_T25V12
-constraint_mode {test} -delay_corner {my_delay_corner_nom_cmax_T25V12}
<CMD> create_analysis_view -name my_analysis_view_func_nom_cmax_T50V13
-constraint_mode {func} -delay_corner {my_delay_corner_nom_cmax_T50V13}
<CMD> create_analysis_view -name my_analysis_view_test_nom_cmax_T50V13
-constraint_mode {test} -delay_corner {my_delay_corner_nom_cmax_T50V13}
<CMD> create_analysis_view -name my_analysis_view_func_nom_cmax_T15V11
-constraint_mode {func} -delay_corner {my_delay_corner_nom_cmax_T15V11}
<CMD> create_analysis_view -name my_analysis_view_test_nom_cmax_T15V11
-constraint_mode {test} -delay_corner {my_delay_corner_nom_cmax_T15V11}
<CMD> create_analysis_view -name my_analysis_view_func_max_cmin_T150V08
-constraint_mode {func} -delay_corner {my_delay_corner_max_cmin_T150V08}

<CMD> create_analysis_view -name my_analysis_view_test_max_cmin_T150V08

-constraint_mode {test} -delay_corner {my_delay_corner_max_cmin_T150V08}
<CMD> create_analysis_view -name
my_analysis_view_func_max_cmin_T140V102 -constraint_mode {func}
-delay_corner {my_delay_corner_max_cmin_T140V102}
<CMD> create_analysis_view -name
my_analysis_view_test_max_cmin_T140V102 -constraint_mode {test}
-delay_corner {my_delay_corner_max_cmin_T140V102}
<CMD> create_analysis_view -name
my_analysis_view_func_max_cmin_T125V108 -constraint_mode {func}
-delay_corner {my_delay_corner_max_cmin_T125V108}
<CMD> create_analysis_view -name
my_analysis_view_test_max_cmin_T125V108 -constraint_mode {test}
-delay_corner {my_delay_corner_max_cmin_T125V108}
<CMD> create_analysis_view -name my_analysis_view_func_min_cmax_T0V132
-constraint_mode {func} -delay_corner {my_delay_corner_min_cmax_T0V132}
<CMD> create_analysis_view -name my_analysis_view_test_min_cmax_T0V132
-constraint_mode {test} -delay_corner {my_delay_corner_min_cmax_T0V132}
<CMD> create_analysis_view -name
my_analysis_view_func_min_cmax_Tm20V15 -constraint_mode {func}
-delay_corner {my_delay_corner_min_cmax_Tm20V15}
<CMD> create_analysis_view -name
my_analysis_view_func_min_cmax_Tm40V15 -constraint_mode {test}
-delay_corner {my_delay_corner_min_cmax_Tm20V15}
<CMD> create_analysis_view -name my_analysis_view_test_min_cmax_Tm40V15
-constraint_mode {test} -delay_corner {my_delay_corner_min_cmax_Tm40V15}
<CMD> create_analysis_view -name my_analysis_view_func_nom_cmin_T25V12
-constraint_mode {func} -delay_corner {my_delay_corner_nom_cmin_T25V12}
<CMD> create_analysis_view -name my_analysis_view_test_nom_cmin_T25V12
-constraint_mode {test} -delay_corner {my_delay_corner_nom_cmin_T25V12}
<CMD> create_analysis_view -name my_analysis_view_func_nom_cmin_T20V13
-constraint_mode {func} -delay_corner {my_delay_corner_nom_cmin_T20V13}
<CMD> create_analysis_view -name my_analysis_view_test_nom_cmin_T20V13
-constraint_mode {test} -delay_corner {my_delay_corner_nom_cmin_T20V13}
<CMD> create_analysis_view -name my_analysis_view_func_nom_cmin_T15V11
-constraint_mode {func} -delay_corner {my_delay_corner_nom_cmin_T15V11}

<CMD> create_analysis_view -name my_analysis_view_test_nom_cmin_T15V11

-constraint_mode {test} -delay_corner {my_delay_corner_nom_cmin_T15V11}
<CMD> create_analysis_view -name my_analysis_view_test_min_cmax_Tm20V15
-constraint_mode {test} -delay_corner {my_delay_corner_min_cmax_Tm20V15}
<CMD> set_analysis_view -setup {my_analysis_view_test_max_cmax_T150V08
my_analysis_view_func_max_cmax_T150V08
my_analysis_view_func_max_cmax_T140V102
myanalysis_view_test_max_cmax_T140V102
my_analysis_view_func_max_cmax_T125V108
my_analysis_view_test_max_cmax_T125V108
my_analysis_view_func_nom_cmax_T25V12
my_analysis_view_func_nom_cmax_T50V13
my_analysis_view_test_nom_cmax_T25V12
my_analysis_view_test_nom_cmax_T50V13
my_analysis_view_func_nom_cmax_T15V11
my_analysis_view_test_nom_cmax_T15V11
my_analysis_view_func_max_cmin_T150V08
my_analysis_view_test_max_cmin_T150V08
my_analysis_view_func_max_cmin_T140V102
my_analysis_view_test_max_cmin_T140V102
my_analysis_view_func_max_cmin_T125V108
my_analysis_view_test_max_cmin_T125V108
my_analysis_view_func_nom_cmin_T25V12
my_analysis_view_test_nom_cmin_T25V12
my_analysis_view_func_nom_cmin_T20V13
my_analysis_view_test_nom_cmin_T20V13
my_analysis_view_func_nom_cmin_T15V11
my_analysis_view_test_nom_cmin_T15V11} -hold
{my_analysis_view_func_min_cmin_T0V132
my_analysis_view_test_min_cmin_T0V132
my_analysis_view_func_min_cmin_Tm20V15
my_analysis_view_test_min_cmin_Tm20V15
my_analysis_view_func_min_cmin_Tm40V18
my_analysis_view_test_min_cmin_Tm40V18
my_analysis_view_func_nom_cmax_T25V12
my_analysis_view_test_nom_cmax_T25V12
my_analysis_view_func_nom_cmax_T50V13
my_analysis_view_test_nom_cmax_T50V13
my_analysis_view_func_nom_cmax_T15V11
my_analysis_view_test_nom_cmax_T15V11
my_analysis_view_func_min_cmax_T0V132
my_analysis_view_test_min_cmax_T0V132
my_analysis_view_func_min_cmax_Tm20V15
my_analysis_view_func_min_cmax_Tm40V15
my_analysis_view_test_min_cmax_Tm40V15
my_analysis_view_test_min_cmax_Tm20V15}

<CMD> save_global Default.globals

<CMD> set init_mmmc_file gopi/mmmc.view
<CMD> init_design

Loading LEF file ../../LEF/gsclib045.lef ...

Set DBUPerIGU to M2 pitch 200.

viaInitial starts at Fri Apr 1 16:08:00 2016

viaInitial ends at Fri Apr 1 16:08:00 2016
*** Begin netlist parsing (mem=361.0M) ***
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist '../../NETLIST/tdsp_core.v'

*** Memory Usage v#1 (Current mem = 367.223M, initial mem = 98.977M) ***
*** End netlist parsing (cpu=0:00:00.1, real=0:00:00.0, mem=367.2M) ***
Top level cell is tdsp_core.
Loading view definition file from gopi/mmmc.view
Reading my_max_library_T150V08_set timing library
'/Projects/Training/user5/work/suraj/LIB/slow_T150_08V.lib' ...
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell
'ADDFHX2' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'S' of cell
'ADDFHX2' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell
'ADDFHX4' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'S' of cell
'ADDFHX4' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell
'ADDFHXL' is not defined in the library.

**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'S' of cell

'ADDFHXL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell
'ADDFXL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'S' of cell
'ADDFXL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell
'ADDHX2' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'S' of cell
'ADDHX2' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell
'ADDHXL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'S' of cell
'ADDHXL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND2X4' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND2X6' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND2XL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND3X1' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND3X8' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND3XL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND4X1' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND4X4' is not defined in the library.
Message <TECHLIB-436> has exceeded the message display limit of '20'.
setMessageLimit/set_message_limit sets the limit.
unsetMessageLimit/unset_message_limit can be used to reset this.
Read 477 cells in library 'gpdk045bc'
Reading my_min_library_T0V132_set timing library
'/Projects/Training/user5/work/suraj/LIB/fast_T0_132V.lib' ...

Read 477 cells in library 'gpdk045wc'

*** End library_loading (cpu=0.00min, mem=0.0M, fe_cpu=0.15min,
fe_real=0.82min, fe_mem=418.2M) ***
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell tdsp_core ...
*** Netlist is unique.
** info: there are 1523 modules.
** info: there are 3533 stdCell insts.

*** Memory Usage v#1 (Current mem = 426.684M, initial mem = 98.977M) ***
*info: set bottom ioPad orient R0
Horizontal Layer M1 offset = 95 (derived)
Vertical Layer M2 offset = 100 (derived)
Generated pitch 0.2 in Metal9 is different from 0.33 defined in technology file in
unpreferred direction.
Generated pitch 0.38 in Metal9 is different from 0.33 defined in technology file in
preferred direction.
Generated pitch 0.285 in Metal8 is different from 0.2 defined in technology file in
unpreferred direction.
Generated pitch 0.285 in Metal7 is different from 0.2 defined in technology file in
preferred direction.
Generated pitch 0.19 in Metal6 is different from 0.2 defined in technology file in
unpreferred direction.
Generated pitch 0.19 in Metal5 is different from 0.2 defined in technology file in
preferred direction.
Generated pitch 0.19 in Metal4 is different from 0.2 defined in technology file in
unpreferred direction.
Generated pitch 0.19 in Metal3 is different from 0.2 defined in technology file in
preferred direction.
Generated pitch 0.19 in Metal2 is different from 0.2 defined in technology file in
unpreferred direction.

Generated pitch 0.2 in Metal1 is different from 0.19 defined in technology file in
unpreferred direction.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 0.1 ps.
Initializing multi-corner RC extraction with 2 active RC Corners ...
**WARN: (ENCEXT-6202): In addition to the technology file, capacitance table file
is specified for all RC corners. If the technology file for all RC corners is already
specified, the capacitance table file is not required for preRoute and postRoute
extraction. In a new session, the capacitance table files can be removed from the
create_rc_corner command. In this case, the technology file will be used for
preRoute extraction and effort level medium/high/signoff of postRoute extraction.
Type 'man ENCEXT-6202' for more detail.
Reading Capacitance Table File ../../DATA/captable_cmax ...
Cap table was created using Encounter 09.10-p004_1.
Process name: GPDK45.
**WARN: (ENCEXT-2760): Layer M10 specified in the cap table is ignored because
it is greater than the maximum number of layers, 9, specified in the technology
LEF file. Check the cap table for the invalid layer specification.
**WARN: (ENCEXT-2760): Layer M11 specified in the cap table is ignored because
it is greater than the maximum number of layers, 9, specified in the technology
LEF file. Check the cap table for the invalid layer specification.
**WARN: (ENCEXT-2776): The via resistance between layers M1 and M2 is not
defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M2 and M3 is not
defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M3 and M4 is not
defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.

**WARN: (ENCEXT-2776): The via resistance between layers M4 and M5 is not

defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M5 and M6 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M6 and M7 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M7 and M8 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M8 and M9 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2710): Basic Cap table for layer M10 is ignored because the
layer is not specified in the technology LEF file.
Reading Capacitance Table File ../../DATA/captable_cmin ...
Cap table was created using Encounter 09.10-p004_1.
Process name: GPDK45.
**WARN: (ENCEXT-2760): Layer M10 specified in the cap table is ignored because
it is greater than the maximum number of layers, 9, specified in the technology
LEF file. Check the cap table for the invalid layer specification.
**WARN: (ENCEXT-2760): Layer M11 specified in the cap table is ignored because
it is greater than the maximum number of layers, 9, specified in the technology
LEF file. Check the cap table for the invalid layer specification.
**WARN: (ENCEXT-2776): The via resistance between layers M1 and M2 is not
defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.

**WARN: (ENCEXT-2776): The via resistance between layers M2 and M3 is not

defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M3 and M4 is not
defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M4 and M5 is not
defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M5 and M6 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M6 and M7 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M7 and M8 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2776): The via resistance between layers M8 and M9 is not
defined in the capacitance table file. The via resistance of 1.675 Ohms defined in
the LEF technology file will be used as via resistance between these layers.
Type 'man ENCEXT-2776' for more detail.
**WARN: (ENCEXT-2710): Basic Cap table for layer M10 is ignored because the
layer is not specified in the technology LEF file.
Importing multi-corner RC tables ...
Summary of Active RC-Corners :

Analysis View: my_analysis_view_test_max_cmax_T150V08

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_max_cmax_T150V08

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_max_cmax_T140V102

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: myanalysis_view_test_max_cmax_T140V102

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_max_cmax_T125V108

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_max_cmax_T125V108

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_nom_cmax_T25V12

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_nom_cmax_T50V13

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_nom_cmax_T25V12

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_nom_cmax_T50V13

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_nom_cmax_T15V11

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_nom_cmax_T15V11

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_max_cmin_T150V08

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_max_cmin_T150V08

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_max_cmin_T140V102

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_max_cmin_T140V102

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_max_cmin_T125V108

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_max_cmin_T125V108

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_nom_cmin_T25V12

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_nom_cmin_T25V12

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_nom_cmin_T20V13

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_nom_cmin_T20V13

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_nom_cmin_T15V11

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_nom_cmin_T15V11

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_min_cmin_T0V132

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_min_cmin_T0V132

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_min_cmin_Tm20V15

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_min_cmin_Tm20V15

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_min_cmin_Tm40V18

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_min_cmin_Tm40V18

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmin
:1

RC-Corner Temperature : 25 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmin'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_min_cmax_T0V132

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_min_cmax_T0V132

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_min_cmax_Tm20V15

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_min_cmax_Tm40V15

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_min_cmax_Tm40V15

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_min_cmax_Tm20V15

RC-Corner Name
RC-Corner Index

: my_rc_corner_cmax
:0

RC-Corner Temperature : 125 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor

:1

RC-Corner PreRoute Cap Factor

:1

RC-Corner PostRoute Res Factor

:1

RC-Corner PostRoute Cap Factor

:1

RC-Corner PostRoute XCap Factor

:1

RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Technology file '../../DATA/qrcTechFile' associated with first view
'my_analysis_view_test_max_cmax_T150V08' specified to command
'set_analysis_view' will be used as the primary corner for the multi-corner
extraction. TQRC/IQRC extraction leverages a single primary corner extraction,

then derives the other corners based on their technology files and operating
conditions from the primary corner.
*Info: initialize multi-corner CTS.
Reading my_max_library_T140V102_set timing library
'/Projects/Training/user5/work/suraj/LIB/slow_T140_102V.lib' ...
Read 477 cells in library 'gpdk045bc'
Reading my_max_library_T125V108_set timing library
'/Projects/Training/user5/work/suraj/LIB/slow_T125_108V.lib' ...
Read 477 cells in library 'gpdk045bc'
Reading my_nom_library_T25V12_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T25_12V.lib' ...
Read 477 cells in library 'typical'
Reading my_nom_library_T50V13_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T50_13V.lib' ...
Read 477 cells in library 'typical'
Reading my_nom_library_T15V11_set timing library
'/Projects/Training/user5/work/suraj/LIB/typical_T15_11V.lib' ...
Read 477 cells in library 'typical'
Reading my_min_library_Tm20V15_set timing library
'/Projects/Training/user5/work/suraj/LIB/fast_Tm20_15V.lib' ...
Read 477 cells in library 'gpdk045wc'
Reading my_min_library_Tm40V18_set timing library
'/Projects/Training/user5/work/suraj/LIB/fast_Tm40_18V.lib' ...
Read 477 cells in library 'gpdk045wc'
CTE reading timing constraint file '../../SDC/test.sdc' ...
Current (total cpu=0:00:14.7, real=0:00:55.0, peak res=604.1M, current
mem=735.1M)
**WARN: (TCLNL-330):
set_input_delay on clock root 'clk' is not supported. You
should use the -source option to set_clock_latency to provide this offset. You can
also use the global timing_allow_input_delay_on_clock_source to allow
set_input_delay assertion to have an effect on clock source paths beginning at
this clock root. (File ../../SDC/test.sdc, Line 188).

Number of path exceptions in the constraint file = 47

Number of paths exceptions after getting compressed = 5

INFO (CTE): read_dc_script finished with 1 WARNING.
Ending "Constraint file reading stats" (total cpu=0:00:00.1, real=0:00:00.0, peak
res=622.2M, current mem=751.6M)
Current (total cpu=0:00:14.9, real=0:00:55.0, peak res=622.2M, current
mem=751.6M)
CTE reading timing constraint file '../../SDC/func.sdc' ...
Current (total cpu=0:00:14.9, real=0:00:55.0, peak res=622.3M, current
mem=751.6M)
**WARN: (TCLNL-330):
set_input_delay on clock root 'clk' is not supported. You
should use the -source option to set_clock_latency to provide this offset. You can
also use the global timing_allow_input_delay_on_clock_source to allow
set_input_delay assertion to have an effect on clock source paths beginning at
this clock root. (File ../../SDC/func.sdc, Line 188).

Number of path exceptions in the constraint file = 47

Number of paths exceptions after getting compressed = 5
INFO (CTE): read_dc_script finished with 1 WARNING.
Ending "Constraint file reading stats" (total cpu=0:00:00.1, real=0:00:00.0, peak
res=623.2M, current mem=751.6M)
Current (total cpu=0:00:14.9, real=0:00:55.0, peak res=623.2M, current
mem=751.6M)
Total number of combinational cells: 317
Total number of sequential cells: 150
Total number of tristate cells: 10
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0

List of usable buffers: BUFX2 BUFX12 BUFX16 BUFX20 CLKBUFX2 BUFX3 BUFX4
CLKBUFX12 CLKBUFX16 CLKBUFX20 CLKBUFX4 CLKBUFX6 CLKBUFX8 BUFX8
CLKBUFX3 BUFX6
Total number of usable buffers: 16
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: CLKINVX1 CLKINVX2 CLKINVX12 CLKINVX16 CLKINVX20
INVX1 CLKINVX3 CLKINVX4 CLKINVX6 INVX12 INVX2 INVX3 CLKINVX8 INVX20
INVX4 INVX6 INVX16 INVXL INVX8
Total number of usable inverters: 19
List of unusable inverters:
Total number of unusable inverters: 0
List of identified usable delay cells: DLY1X4 DLY2X4 DLY3X4 DLY1X1 DLY4X1
DLY2X1 DLY3X1 DLY4X4
Total number of identified usable delay cells: 8
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0

*** Summary of all messages that are not suppressed in this session:
Severity ID

Count Summary

WARNING ENCEXT-6202

1 In addition to the technology file, capa...

WARNING ENCEXT-2710

2 Basic Cap table for layer M%d is ignored...

WARNING ENCEXT-2760

4 Layer M%d specified in the cap table is ...

WARNING ENCEXT-2776

16 The via resistance between layers %s and...

*** Message Summary: 23 warning(s), 0 error(s)

<CMD> fit
<CMD> setDrawView fplan
<CMD> loadIoFile io/tdsp_core.save.io
Reading IO assignment file "io/tdsp_core.save.io" ...

<CMD> fit
<CMD> clearGlobalNets
<CMD> globalNetConnect VDD -type pgpin -pin VDD -inst *
<CMD> globalNetConnect VSS -type pgpin -pin VSS -inst *
<CMD> set sprCreateIeStripeNets {}
<CMD> set sprCreateIeStripeLayers {}
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeSpacing 2.0
<CMD> set sprCreateIeStripeThreshold 1.0
CMD> addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit
Metal3 -max_same_layer_jog_length 0.14 -padcore_ring_bottom_layer_limit
Metal1 -set_to_set_distance 25 -skip_via_on_pin Standardcell
-stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal3 -spacing 0.45
-xleft_offset 5 -xright_offset 5 -merge_stripes_value 0.165 -layer Metal2
-block_ring_bottom_layer_limit Metal1 -width 2.1 -nets {VDD VSS}
-stacked_via_bottom_layer Metal1

Starting stripe generation ...

Non-Default setAddStripeOption Settings :
NONE
The core ring for VDD is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
The core ring for VSS is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
Stripe generation is complete; vias are now being generated.
The power planner created 12 wires.
*** Ending Stripe Generation (totcpu: 0:00:00.0,real: 0:00:00.0, mem: 764.0M)
***
<CMD> undo
<CMD> addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit
Metal7 -max_same_layer_jog_length 0.14 -padcore_ring_bottom_layer_limit
Metal5 -set_to_set_distance 25 -skip_via_on_pin Standardcell

-stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal7 -spacing 0.45

-xleft_offset 5 -xright_offset 5 -merge_stripes_value 0.165 -layer Metal6
-block_ring_bottom_layer_limit Metal5 -width 2.1 -nets {VDD VSS}
-stacked_via_bottom_layer Metal1

Starting stripe generation ...

Non-Default setAddStripeOption Settings :
NONE
The core ring for VDD is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
The core ring for VSS is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
Stripe generation is complete; vias are now being generated.
The power planner created 12 wires.
*** Ending Stripe Generation (totcpu: 0:00:00.0,real: 0:00:00.0, mem: 764.0M)
***
<CMD> addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit
Metal6 -max_same_layer_jog_length 0.14 -padcore_ring_bottom_layer_limit
Metal4 -set_to_set_distance 25 -ybottom_offset 5 -skip_via_on_pin Standardcell
-stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal6 -spacing 0.45
-merge_stripes_value 0.165 -direction horizontal -layer Metal5
-block_ring_bottom_layer_limit Metal4 -ytop_offset 5 -width 2.1 -nets {VDD VSS}
-stacked_via_bottom_layer Metal1

Starting stripe generation ...

Non-Default setAddStripeOption Settings :
NONE
The core ring for VDD is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
The core ring for VSS is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
Stripe generation is complete; vias are now being generated.

The power planner created 12 wires.

*** Ending Stripe Generation (totcpu: 0:00:00.0,real: 0:00:00.0, mem: 764.0M)
***
<CMD> addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit
Metal5 -max_same_layer_jog_length 0.14 -padcore_ring_bottom_layer_limit
Metal3 -set_to_set_distance 25 -skip_via_on_pin Standardcell
-stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal5 -spacing 0.45
-xleft_offset 15 -xright_offset 15 -merge_stripes_value 0.165 -layer Metal4
-block_ring_bottom_layer_limit Metal3 -width 2.1 -nets {VDD VSS}
-stacked_via_bottom_layer Metal1

Starting stripe generation ...

Non-Default setAddStripeOption Settings :
NONE
The core ring for VDD is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
The core ring for VSS is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
Stripe generation is complete; vias are now being generated.
The power planner created 10 wires.
*** Ending Stripe Generation (totcpu: 0:00:00.0,real: 0:00:00.0, mem: 764.0M)
***
<CMD> sroute -connect { corePin } -layerChangeRange { Metal1 Metal9 }
-blockPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd }
-allowJogging 0 -crossoverViaLayerRange { Metal1 Metal4 } -nets { VDD VSS }
-allowLayerChange 0 -targetViaLayerRange { Metal1 Metal4 }
**WARN: (ENCSR-4058): Sroute option: blockPinTarget should be used in
conjunction with option: -connect blockPin.
*** Begin SPECIAL ROUTE on Fri Apr 1 16:10:21 2016 ***
SPECIAL ROUTE ran on directory:
/Projects/Training/user5/work/suraj/encounter/rundir
SPECIAL ROUTE ran on machine: SRV01 (Linux 2.6.18-308.el5 x86_64 2.66Ghz)

Begin option processing ...

srouteConnectPowerBump set to false
routeSelectNet set to "VDD VSS"
routeSpecial set to true
srouteBottomLayerLimit set to 1
srouteBottomTargetLayerLimit set to 1
srouteConnectBlockPin set to false
srouteConnectConverterPin set to false
srouteConnectPadPin set to false
srouteConnectStripe set to false
srouteCrossoverViaBottomLayer set to 1
srouteCrossoverViaTopLayer set to 4
srouteFollowCorePinEnd set to 3
srouteFollowPadPin set to false
srouteNoLayerChangeRoute set to true
sroutePadPinAllPorts set to true
sroutePreserveExistingRoutes set to true
srouteRoutePowerBarPortOnBothDir set to true
srouteStopBlockPin set to "nearestTarget"
srouteStraightConnections set to "straightWithDrcClean"
srouteTopLayerLimit set to 9
srouteTopTargetLayerLimit set to 4
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 1325.00 megs.

Reading DB technology information...

Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.

Read in 19 layers, 9 routing layers, 1 overlap layer

Read in 2 nondefault rules, 0 used
Read in 487 macros, 68 used
Read in 68 components
68 core components: 68 unplaced, 0 placed, 0 fixed
Read in 212 physical pins
212 physical pins: 0 unplaced, 0 placed, 212 fixed
Read in 144 nets
Read in 2 special nets, 2 routed
Read in 348 terminals
2 nets selected.

Begin power routing ...

CPU time for FollowPin 0 seconds
CPU time for FollowPin 0 seconds
**WARN: (ENCSR-486):
Ring/Stripe at (0.000, 5.000) (148.685, 7.100) on layer
Metal5 is out of layer range and is ignored. The ports will route to other nearby
rings/stripes. (Same type of warning will be suppressed)
Number of Core ports routed: 0 open: 87
Number of Followpin connections: 87
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 1357.00 megs.

Begin updating DB with routing results ...

Updating DB with 152 via definition ...
Updating DB with 212 io pins ...Extracting standard cell pins and blockage ......
Pin and blockage extraction finished

sroute post-processing starts at Fri Apr 1 16:10:21 2016

The viaGen is rebuilding shadow vias for net VSS.
sroute post-processing ends at Fri Apr 1 16:10:21 2016

sroute post-processing starts at Fri Apr 1 16:10:21 2016

The viaGen is rebuilding shadow vias for net VDD.
sroute post-processing ends at Fri Apr 1 16:10:21 2016
sroute: Total CPU time used = 0:0:0
sroute: Total Real time used = 0:0:0
sroute: Total Memory used = 26.36 megs
sroute: Total Peak Memory used = 791.38 megs
<CMD> setLayerPreference violation -isVisible 1
<CMD> violationBrowser -all -no_display_false
<CMD> clearDrc
<CMD> zoomBox 76.910 131.304 112.858 99.849
<CMD> fit
<CMD> setPlaceMode -fp false
<CMD> placeDesign
*** Starting placeDesign default flow ***
**INFO: Enable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 101.
**WARN: (ENCDC-1629): The default delay limit was set to 101. This is less than
the default of 1000 and may result in inaccurate delay calculation for nets with a
fanout higher than the setting. If needed, the default delay limit may be
adjusted by running the command 'set delaycal_use_default_delay_limit'.
Set Default Net Delay as 0 ps.
Set Default Net Load as 0 pF.
**INFO: Analyzing IO path groups for slack adjustment

Effort level <high> specified for reg2reg_tmp.15393 path_group

################################################
#################################
# Design Stage: PreRoute
# Design Mode: 90nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=aae SIAware=false(opt_signoff)
# Switching Delay Calculation Engine to AAE
################################################
#################################
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...

Calculate delays in BcWc mode...

Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Calculate delays in BcWc mode...
Topological Sorting (CPU = 0:00:00.0, MEM = 814.7M, InitMEM = 814.7M)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:01.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_THRD: End delay calculation. (MEM=1123.88 CPU=0:00:08.0
REAL=0:00:08.0)
*** CDM Built up (cpu=0:00:09.9 real=0:00:10.0 mem= 1123.9M) ***

*** Start deleteBufferTree ***

Info: Detect buffers to remove automatically.
Analyzing netlist ...
All-RC-Corners-Per-Net-In-Memory is turned ON...
Updating netlist

*summary: 49 instances (buffers/inverters) removed

*** Finish deleteBufferTree (0:00:00.2) ***
**INFO: Disable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
*** Starting "NanoPlace(TM) placement v#1 (mem=931.8M)" ...
**WARN: (ENCTS-403):
Delay calculation was forced to extrapolate table data
outside of the characterized range. In some cases, extrapolation can reduce the
accuracy of the delay calculation. You can enable more detailed reporting of
these cases by enabling the command 'setDelayCalMode -reportOutBound true'.
Type 'man ENCTS-403' for more detail.
*** Build Buffered Sizing Timing Model
(cpu=0:00:14.5 mem=972.1M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:14.8 mem=979.1M) ***
Options: timingDriven clkGateAware ignoreScan pinGuide congEffort=auto
gpeffort=medium
**WARN: (ENCSP-9042):
be ignored.

Scan chains were not defined, -ignoreScan option will

Define the scan chains before using this option.

Type 'man ENCSP-9042' for more detail.
#std cell=3505 (0 fixed + 3505 movable) #block=0 (0 floating + 0 preplaced)
#ioInst=0 #net=3562 #term=13004 #term/net=3.65, #fixedIo=144,
#floatIo=0, #fixedPin=117, #floatPin=0

stdCell: 3505 single + 0 double + 0 multi

Total standard cell length = 8.9324 (mm), area = 0.0153 (mm^2)
**Info: (ENCSP-307): Design contains fractional 153 cells.
Average module density = 0.699.
Density for the design = 0.699.
= stdcell_area 44662 sites (15274 um^2) / alloc_area 63898 sites (21853
um^2).
Pin Density = 0.291.
= total # of pins 13004 / total Instance area 44662.
=== lastAutoLevel = 8
Clock gating cells determined by native netlist tracing.
Iteration 1: Total net bbox = 1.748e+04 (8.19e+03 9.29e+03)
Est. stn bbox = 1.984e+04 (9.25e+03 1.06e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 1203.1M
Iteration 2: Total net bbox = 1.748e+04 (8.19e+03 9.29e+03)
Est. stn bbox = 1.984e+04 (9.25e+03 1.06e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 1203.1M
Iteration 3: Total net bbox = 1.926e+04 (8.74e+03 1.05e+04)
Est. stn bbox = 2.340e+04 (1.06e+04 1.28e+04)
cpu = 0:00:01.1 real = 0:00:01.0 mem = 1203.1M
Iteration 4: Total net bbox = 4.528e+04 (2.21e+04 2.32e+04)
Est. stn bbox = 5.562e+04 (2.65e+04 2.91e+04)
cpu = 0:00:02.8 real = 0:00:03.0 mem = 1204.1M
Iteration 5: Total net bbox = 4.845e+04 (2.47e+04 2.38e+04)
Est. stn bbox = 6.078e+04 (3.07e+04 3.00e+04)
cpu = 0:00:01.9 real = 0:00:02.0 mem = 1204.1M
Iteration 6: Total net bbox = 5.033e+04 (2.50e+04 2.54e+04)
Est. stn bbox = 6.242e+04 (3.09e+04 3.15e+04)
cpu = 0:00:01.4 real = 0:00:01.0 mem = 1204.1M

Iteration 7: Total net bbox = 5.198e+04 (2.64e+04 2.56e+04)

Est. stn bbox = 6.425e+04 (3.24e+04 3.18e+04)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 1204.1M
Iteration 8: Total net bbox = 5.250e+04 (2.66e+04 2.59e+04)
Est. stn bbox = 6.476e+04 (3.26e+04 3.21e+04)
cpu = 0:00:02.2 real = 0:00:03.0 mem = 1204.1M
Iteration 9: Total net bbox = 5.335e+04 (2.65e+04 2.68e+04)
Est. stn bbox = 6.498e+04 (3.21e+04 3.29e+04)
cpu = 0:00:01.3 real = 0:00:02.0 mem = 1204.1M
Iteration 10: Total net bbox = 5.359e+04 (2.66e+04 2.70e+04)
Est. stn bbox = 6.520e+04 (3.22e+04 3.30e+04)
cpu = 0:00:00.6 real = 0:00:00.0 mem = 1204.1M
Iteration 11: Total net bbox = 5.491e+04 (2.78e+04 2.71e+04)
Est. stn bbox = 6.670e+04 (3.34e+04 3.33e+04)
cpu = 0:00:05.5 real = 0:00:05.0 mem = 1204.1M
Iteration 12: Total net bbox = 5.491e+04 (2.78e+04 2.71e+04)
Est. stn bbox = 6.670e+04 (3.34e+04 3.33e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 1204.1M
Iteration 13: Total net bbox = 5.491e+04 (2.78e+04 2.71e+04)
Est. stn bbox = 6.670e+04 (3.34e+04 3.33e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 1204.1M
*** cost = 5.491e+04 (2.78e+04 2.71e+04) (cpu for global=0:00:16.6)
real=0:00:18.0***
Info: 12 clock gating cells identified, 12 (on average) moved
Core Placement runtime cpu: 0:00:13.0 real: 0:00:13.0
**WARN: (ENCSP-9025):

No scan chain specified/traced.

Type 'man ENCSP-9025' for more detail.

**Info: (ENCSP-307): Design contains fractional 153 cells.
*** Starting refinePlace (0:01:14 mem=969.8M) ***

Total net length = 5.491e+04 (2.777e+04 2.715e+04) (ext = 7.567e+03)

Move report: Detail placement moves 3505 insts, mean move: 1.08 um, max
move: 20.90 um
Max move on inst
(EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH): (65.81, 47.57) -->
(86.40, 47.88)
Runtime: CPU: 0:00:01.0 REAL: 0:00:01.0 MEM: 972.2MB
Summary Report:
Instances move: 3505 (out of 3505 movable)
Mean displacement: 1.08 um
Max displacement: 20.90 um (Instance:
EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH) (65.806, 47.572) ->
(86.4, 47.88)
Length: 38 sites, height: 1 rows, site name: CoreSite, cell type:
TLATNTSCAX16
Total net length = 5.473e+04 (2.756e+04 2.717e+04) (ext = 7.565e+03)
Runtime: CPU: 0:00:01.1 REAL: 0:00:01.0 MEM: 972.2MB
*** Finished refinePlace (0:01:15 mem=972.2M) ***
Total net length = 5.475e+04 (2.756e+04 2.719e+04) (ext = 7.565e+03)
*** End of Placement (cpu=0:00:41.6, real=0:00:43.0, mem=972.2M) ***
**Info: (ENCSP-307): Design contains fractional 153 cells.
default core: bins with density > 0.75 = 34.6 % ( 28 / 81 )
Density distribution unevenness ratio = 5.731%
*** Free Virtual Timing Model ...(mem=972.2M)
Starting IO pin assignment...
Starting congestion repair ...
*** Starting trialRoute (mem=972.2M) ***

There are 0 guide points passed to trialRoute for fixed pins.

There are 0 guide points passed to trialRoute for pinGroup/netGroup/pinGuide
pins.

Options: -noPinGuide

Phase 1a-1d Overflow: 0.00% H + 0.00% V (0:00:00.1 972.2M)

Overflow: 0.00% H + 0.00% V (0:00:00.0 972.2M)

Phase 1l Overflow: 0.00% H + 0.02% V (0:00:00.2 972.2M)

Congestion distribution:

Remain

cntH

cntV

--------------------------------------1:

0.00%

0.02%

-------------------------------------0:

0.00%

0.02%

1:

0.00%

0.05%

2:

0.00%

27

0.21%

3:

0.00%

41

0.32%

4:

0.00%

85

0.67%

5:

12728100.00%

1256498.71%

Total length: 6.350e+04um, number of vias: 28300

M1(H) length: 2.641e+01um, number of vias: 12887
M2(V) length: 2.219e+04um, number of vias: 12079
M3(H) length: 2.825e+04um, number of vias: 1778

M4(V) length: 7.270e+03um, number of vias: 796

M5(H) length: 2.212e+03um, number of vias: 695
M6(V) length: 3.218e+03um, number of vias: 57
M7(H) length: 1.850e+02um, number of vias: 8
M8(V) length: 1.459e+02um, number of vias: 0
M9(H) length: 0.000e+00um

Peak Memory Usage was 972.2M

*** Finished trialRoute (cpu=0:00:00.7 mem=972.2M) ***

Local HotSpot Analysis: normalized max congestion hotspot area = 0.00,

normalized total congestion hotspot area = 0.00 (area is in unit of 4 std-cell row
bins)
describeCongestion: hCong = 0.00 vCong = 0.00
Trial Route Overflow 0.000000(H) 0.015713(V).
Start repairing congestion with level 1.
Skipped repairing congestion.
End of congRepair (cpu=0:00:00.7, real=0:00:01.0)
*** Finishing placeDesign default flow ***
**placeDesign ... cpu = 0: 0:56, real = 0: 0:57, mem = 942.6M **
Active setup views: my_analysis_view_test_max_cmax_T150V08
my_analysis_view_func_max_cmax_T150V08
my_analysis_view_func_max_cmax_T140V102
myanalysis_view_test_max_cmax_T140V102
my_analysis_view_func_max_cmax_T125V108
my_analysis_view_test_max_cmax_T125V108
my_analysis_view_func_nom_cmax_T25V12
my_analysis_view_func_nom_cmax_T50V13
my_analysis_view_test_nom_cmax_T25V12
my_analysis_view_test_nom_cmax_T50V13
my_analysis_view_func_nom_cmax_T15V11
my_analysis_view_test_nom_cmax_T15V11
my_analysis_view_func_max_cmin_T150V08
my_analysis_view_test_max_cmin_T150V08
my_analysis_view_func_max_cmin_T140V102

my_analysis_view_test_max_cmin_T140V102
my_analysis_view_func_max_cmin_T125V108
my_analysis_view_test_max_cmin_T125V108
my_analysis_view_func_nom_cmin_T25V12
my_analysis_view_test_nom_cmin_T25V12
my_analysis_view_func_nom_cmin_T20V13
my_analysis_view_test_nom_cmin_T20V13
my_analysis_view_func_nom_cmin_T15V11
my_analysis_view_test_nom_cmin_T15V11
Active hold views: my_analysis_view_func_min_cmin_T0V132
my_analysis_view_test_min_cmin_T0V132
my_analysis_view_func_min_cmin_Tm20V15
my_analysis_view_test_min_cmin_Tm20V15
my_analysis_view_func_min_cmin_Tm40V18
my_analysis_view_test_min_cmin_Tm40V18
my_analysis_view_func_nom_cmax_T25V12
my_analysis_view_test_nom_cmax_T25V12
my_analysis_view_func_nom_cmax_T50V13
my_analysis_view_test_nom_cmax_T50V13
my_analysis_view_func_nom_cmax_T15V11
my_analysis_view_test_nom_cmax_T15V11
my_analysis_view_func_min_cmax_T0V132
my_analysis_view_test_min_cmax_T0V132
my_analysis_view_func_min_cmax_Tm20V15
my_analysis_view_func_min_cmax_Tm40V15
my_analysis_view_test_min_cmax_Tm40V15
my_analysis_view_test_min_cmax_Tm20V15

*** Summary of all messages that are not suppressed in this session:
Severity ID

Count Summary

WARNING ENCTS-403

1 Delay calculation was forced to extrapol...

WARNING ENCDC-1629

1 The default delay limit was set to %d. T...

WARNING ENCSP-9025

1 No scan chain specified/traced.

WARNING ENCSP-9042

1 Scan chains were not defined, -ignoreSca...

*** Message Summary: 4 warning(s), 0 error(s)

<CMD> setNanoRouteMode -quiet -timingEngine {}

<CMD> setNanoRouteMode -quiet -routeWithSiPostRouteFix 0

<CMD> setNanoRouteMode -quiet -drouteStartIteration default

<CMD> setNanoRouteMode -quiet -routeTopRoutingLayer 3
<CMD> setNanoRouteMode -quiet -routeBottomRoutingLayer 1
<CMD> setNanoRouteMode -quiet -drouteEndIteration default
<CMD> setNanoRouteMode -quiet -routeWithTimingDriven false
<CMD> setNanoRouteMode -quiet -routeWithSiDriven false
Running Native NanoRoute ...
<CMD> routeDesign -globalDetail
#routeDesign: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 822.05
(MB), peak = 1252.13 (MB)
#WARNING (NRIG-96) Selected single pass global detail route "-globalDetail".
Clock eco and post optimizations will not be run. See "man NRIG-96" for more
details.
**Info: (ENCSP-307): Design contains fractional 153 cells.
Begin checking placement ... (start mem=962.6M, init mem=962.6M)
*info: Placed = 3505
*info: Unplaced = 0
Placement Density:69.90%(15274/21853)
Finished checkPlace (cpu: total=0:00:00.1, vio checks=0:00:00.0; mem=962.6M)
#**INFO: honoring user setting for routeWithTimingDriven set to false
#**INFO: honoring user setting for routeWithSiDriven set to false

changeUseClockNetStatus Option : -noFixedNetWires

*** Changed status on (0) nets in Clock.
*** End changeUseClockNetStatus (cpu=0:00:00.0, real=0:00:00.0,
mem=962.6M) ***

globalDetailRoute

#setNanoRouteMode -routeBottomRoutingLayer 1

#setNanoRouteMode -routeTopRoutingLayer 3
#setNanoRouteMode -routeWithSiDriven false
#setNanoRouteMode -routeWithTimingDriven false
#Start globalDetailRoute on Fri Apr 1 16:13:34 2016
#
#WARNING (NRDB-976) The TRACK STEP 0.1900 for preferred direction tracks is
smaller than the PITCH 0.2000 for LAYER Metal3. This will cause routability
problems for NanoRoute.
#WARNING (NRDB-976) The TRACK STEP 0.1900 for preferred direction tracks is
smaller than the PITCH 0.2000 for LAYER Metal5. This will cause routability
problems for NanoRoute.
#NanoRoute Version v14.28-s005 NR160313-1959/14_28-UB
#Bottom routing layer is M1, bottom routing layer for shielding is M1, bottom
shield layer is M1
#Start routing data preparation.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal1 is not
specified for width 0.060.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal1 is not
specified for width 0.060.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal3 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal3 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal3 is not
specified for width 0.070.

#WARNING (NRDB-2078) The above via enclosure for LAYER Metal4 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal3 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal4 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal4 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal5 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal4 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal5 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal5 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal6 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal5 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal6 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal6 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal7 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal6 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal7 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal7 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal8 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal7 is not
specified for width 0.070.

#WARNING (NRDB-2078) The above via enclosure for LAYER Metal8 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal8 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal9 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal8 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal9 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal1 is not
specified for width 0.060.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal1 is not
specified for width 0.060.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal3 is not
specified for width 0.070.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal2 is not
specified for width 0.070.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal3 is not
specified for width 0.070.
#WARNING (EMS-27) Message (NRDB-2077) has exceeded the current message
display limit of 20.
#To increase the message display limit, refer to the product command reference
manual.
#WARNING (EMS-27) Message (NRDB-2078) has exceeded the current message
display limit of 20.
#To increase the message display limit, refer to the product command reference
manual.
#WARNING (NRDB-812) Cuts within VIA VIA12_4C violate adjacent cut spacing
rule.

#WARNING (NRDB-812) Cuts within VIA VIA23_4C violate adjacent cut spacing
rule.
#WARNING (NRDB-812) Cuts within VIA VIA34_4C violate adjacent cut spacing
rule.
#WARNING (NRDB-812) Cuts within VIA VIA45_4C violate adjacent cut spacing
rule.
#Minimum voltage of a net in the design = 0.000.
#Maximum voltage of a net in the design = 1.800.
#Voltage range [0.000 - 0.000] has 1 net.
#Voltage range [1.100 - 1.800] has 1 net.
#Voltage range [0.000 - 1.800] has 3884 nets.
# Metal1

H Track-Pitch = 0.190

Line-2-Via Pitch = 0.125

# Metal2

V Track-Pitch = 0.200

Line-2-Via Pitch = 0.140

# Metal3

H Track-Pitch = 0.190

Line-2-Via Pitch = 0.140

# Metal4

V Track-Pitch = 0.200

Line-2-Via Pitch = 0.140

# Metal5

H Track-Pitch = 0.190

Line-2-Via Pitch = 0.140

# Metal6

V Track-Pitch = 0.200

Line-2-Via Pitch = 0.170

# Metal7

H Track-Pitch = 0.285

Line-2-Via Pitch = 0.445

#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch.
# Metal8

V Track-Pitch = 0.200

Line-2-Via Pitch = 0.385

#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch.
# Metal9

H Track-Pitch = 0.380

Line-2-Via Pitch = 0.385

#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch.
#Regenerating Ggrids automatically.
#Auto generating G-grids with size=20 tracks, using layer Metal2's pitch =
0.200.
#Using automatically generated G-grids.
#Done routing data preparation.
#cpu time = 00:00:03, elapsed time = 00:00:04, memory = 897.88 (MB), peak =
1252.13 (MB)

#Merging special wires...

#Number of eco nets is 0
#
#Start data preparation...
#
#Data preparation is done on Fri Apr 1 16:13:38 2016
#
#Analyzing routing resource...
#Routing resource analysis is done on Fri Apr 1 16:13:38 2016
#
# Resource Analysis:
#
#
# Layer

Routing #Avail
Direction Track

#Track

#Total

Blocked

%Gcell

Gcell

Blocked

# -------------------------------------------------------------# Metal 1

774

1369

1.83%

# Metal 2

743

1369

0.00%

# Metal 3

774

1369

0.00%

# Metal 4

598

145

1369

8.11%

# Metal 5

596

178

1369

5.41%

# Metal 6

569

174

1369

5.41%

# -------------------------------------------------------------# Total

4054

10.99% 8214

3.46%

#
#
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 898.41 (MB), peak =
1252.13 (MB)
#

#start global routing iteration 1...

#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 900.92 (MB), peak =
1252.13 (MB)
#
#start global routing iteration 2...
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 909.61 (MB), peak =
1252.13 (MB)
#
#start global routing iteration 3...
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 910.50 (MB), peak =
1252.13 (MB)
#
#start global routing iteration 4...
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 910.50 (MB), peak =
1252.13 (MB)
#
#start global routing iteration 5...
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 910.54 (MB), peak =
1252.13 (MB)
#
#
#Total number of trivial nets (e.g. < 2 pins) = 324 (skipped).
#Total number of routable nets = 3562.
#Total number of nets in the design = 3886.
#
#3562 routable nets have only global wires.
#
#Routed nets constraints summary:
#----------------------------#

Rules Unconstrained

#----------------------------#

Default

3562

#----------------------------#

Total

3562

#----------------------------#
#Routing constraints summary of the whole design:
#----------------------------#

Rules Unconstrained

#----------------------------#

Default

3562

#----------------------------#

Total

3562

#----------------------------#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
#

OverCon

#Gcell

Layer

(1-2)

OverCon
#Gcell

OverCon
#Gcell

(3-5)

(6-8)

OverCon
#Gcell

%Gcell

(9-11) OverCon

# -------------------------------------------------------------------------# Metal 1

0(0.00%)

0(0.00%)

# Metal 2

89(6.50%)

# Metal 3

0(0.00%)

0(0.00%)

0(0.00%)

0(0.00%) (0.00%)

# Metal 4

0(0.00%)

0(0.00%)

0(0.00%)

0(0.00%) (0.00%)

# Metal 5

0(0.00%)

0(0.00%)

0(0.00%)

0(0.00%) (0.00%)

# Metal 6

0(0.00%)

0(0.00%)

0(0.00%)

0(0.00%) (0.00%)

76(5.55%)

0(0.00%)
45(3.29%)

0(0.00%) (0.00%)
23(1.68%) (17.0%)

# -------------------------------------------------------------------------#

Total

89(1.12%)

76(0.96%)

45(0.57%)

23(0.29%) (2.93%)

#
# The worst congested Gcell overcon (routing demand over resource in number
of tracks) = 11
#
#Complete Global Routing.
#Total wire length = 62720 um.
#Total half perimeter of net bounding box = 59121 um.
#Total wire length on LAYER Metal1 = 96 um.
#Total wire length on LAYER Metal2 = 30516 um.
#Total wire length on LAYER Metal3 = 32108 um.
#Total wire length on LAYER Metal4 = 0 um.
#Total wire length on LAYER Metal5 = 0 um.
#Total wire length on LAYER Metal6 = 0 um.
#Total wire length on LAYER Metal7 = 0 um.
#Total wire length on LAYER Metal8 = 0 um.
#Total wire length on LAYER Metal9 = 0 um.
#Total number of vias = 20169
#Up-Via Summary (total 20169):
#
#----------------------# Metal 1

12396

# Metal 2

7773

#----------------------#

20169

#
#Max overcon = 11 tracks.
#Total overcon = 2.93%.

#Worst layer Gcell overcon rate = 0.00%.

#cpu time = 00:00:02, elapsed time = 00:00:02, memory = 910.61 (MB), peak =
1252.13 (MB)
#
#
#Start data preparation for track assignment...
#
#Data preparation is done on Fri Apr 1 16:13:40 2016
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 910.62 (MB), peak =
1252.13 (MB)
#Start Track Assignment.
#Done with 5369 horizontal wires in 1 hboxes and 5136 vertical wires in 1
hboxes.
#Done with 1403 horizontal wires in 1 hboxes and 1470 vertical wires in 1
hboxes.
#Complete Track Assignment.
#Total wire length = 60943 um.
#Total half perimeter of net bounding box = 59121 um.
#Total wire length on LAYER Metal1 = 101 um.
#Total wire length on LAYER Metal2 = 29400 um.
#Total wire length on LAYER Metal3 = 31442 um.
#Total wire length on LAYER Metal4 = 0 um.
#Total wire length on LAYER Metal5 = 0 um.
#Total wire length on LAYER Metal6 = 0 um.
#Total wire length on LAYER Metal7 = 0 um.
#Total wire length on LAYER Metal8 = 0 um.
#Total wire length on LAYER Metal9 = 0 um.
#Total number of vias = 20169
#Up-Via Summary (total 20169):

#
#----------------------# Metal 1

12396

# Metal 2

7773

#----------------------#

20169

#
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 874.83 (MB), peak =
1252.13 (MB)
#
#Cpu time = 00:00:07
#Elapsed time = 00:00:07
#Increased memory = 21.43 (MB)
#Total memory = 874.83 (MB)
#Peak memory = 1252.13 (MB)
#
#Start Detail Routing..
#start initial detail routing ...
#

number of violations = 14

#
#
#

By Layer and Type :

MetSpc

Metal1

Metal2

11

Totals

12

Loop Totals
0
2
2

1
13
14

#cpu time = 00:00:43, elapsed time = 00:00:43, memory = 1101.48 (MB), peak
= 1252.13 (MB)
#start 1st optimization iteration ...
#

number of violations = 0

#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1101.59 (MB), peak
= 1252.13 (MB)
#Complete Detail Routing.
#Total wire length = 62610 um.
#Total half perimeter of net bounding box = 59121 um.
#Total wire length on LAYER Metal1 = 5741 um.
#Total wire length on LAYER Metal2 = 30758 um.
#Total wire length on LAYER Metal3 = 26111 um.
#Total wire length on LAYER Metal4 = 0 um.
#Total wire length on LAYER Metal5 = 0 um.
#Total wire length on LAYER Metal6 = 0 um.
#Total wire length on LAYER Metal7 = 0 um.
#Total wire length on LAYER Metal8 = 0 um.
#Total wire length on LAYER Metal9 = 0 um.
#Total number of vias = 24203
#Total number of multi-cut vias = 410 ( 1.7%)
#Total number of single cut vias = 23793 ( 98.3%)
#Up-Via Summary (total 24203):
#

single-cut

multi-cut

Total

#----------------------------------------------------------# Metal 1

14528 ( 97.3%)

410 ( 2.7%)

# Metal 2

9265 (100.0%)

0 ( 0.0%)

14938
9265

#----------------------------------------------------------#

23793 ( 98.3%)

410 ( 1.7%)

#
#Total number of DRC violations = 0
#Cpu time = 00:00:44
#Elapsed time = 00:00:45
#Increased memory = 226.75 (MB)

24203

#Total memory = 1101.61 (MB)

#Peak memory = 1252.13 (MB)
#
#start routing for process antenna violation fix ...
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 884.02 (MB), peak =
1252.13 (MB)
#
#Total wire length = 62610 um.
#Total half perimeter of net bounding box = 59121 um.
#Total wire length on LAYER Metal1 = 5741 um.
#Total wire length on LAYER Metal2 = 30758 um.
#Total wire length on LAYER Metal3 = 26111 um.
#Total wire length on LAYER Metal4 = 0 um.
#Total wire length on LAYER Metal5 = 0 um.
#Total wire length on LAYER Metal6 = 0 um.
#Total wire length on LAYER Metal7 = 0 um.
#Total wire length on LAYER Metal8 = 0 um.
#Total wire length on LAYER Metal9 = 0 um.
#Total number of vias = 24203
#Total number of multi-cut vias = 410 ( 1.7%)
#Total number of single cut vias = 23793 ( 98.3%)
#Up-Via Summary (total 24203):
#

single-cut

multi-cut

Total

#----------------------------------------------------------# Metal 1

14528 ( 97.3%)

410 ( 2.7%)

# Metal 2

9265 (100.0%)

0 ( 0.0%)

14938
9265

#----------------------------------------------------------#
#

23793 ( 98.3%)

410 ( 1.7%)

24203

#Total number of DRC violations = 0

#Total number of net violated process antenna rule = 0
#
#
#Start Post Route wire spreading..
#
#Start data preparation for wire spreading...
#
#Data preparation is done on Fri Apr 1 16:14:28 2016
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 884.04 (MB), peak =
1252.13 (MB)
#
#Spread distance (# of tracks): min = 0.500000; max = 2.000000
#
#Start Post Route Wire Spread.
#Done with 2129 horizontal wires in 1 hboxes and 1823 vertical wires in 1
hboxes.
#Complete Post Route Wire Spread.
#
#Total wire length = 64282 um.
#Total half perimeter of net bounding box = 59121 um.
#Total wire length on LAYER Metal1 = 5758 um.
#Total wire length on LAYER Metal2 = 31486 um.
#Total wire length on LAYER Metal3 = 27038 um.
#Total wire length on LAYER Metal4 = 0 um.
#Total wire length on LAYER Metal5 = 0 um.
#Total wire length on LAYER Metal6 = 0 um.
#Total wire length on LAYER Metal7 = 0 um.

#Total wire length on LAYER Metal8 = 0 um.

#Total wire length on LAYER Metal9 = 0 um.
#Total number of vias = 24203
#Total number of multi-cut vias = 410 ( 1.7%)
#Total number of single cut vias = 23793 ( 98.3%)
#Up-Via Summary (total 24203):
#

single-cut

multi-cut

Total

#----------------------------------------------------------# Metal 1

14528 ( 97.3%)

410 ( 2.7%)

# Metal 2

9265 (100.0%)

0 ( 0.0%)

14938
9265

#----------------------------------------------------------#

23793 ( 98.3%)

410 ( 1.7%)

24203

#
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 890.78 (MB), peak =
1252.13 (MB)
#
#Post Route wire spread is done.
#Total wire length = 64282 um.
#Total half perimeter of net bounding box = 59121 um.
#Total wire length on LAYER Metal1 = 5758 um.
#Total wire length on LAYER Metal2 = 31486 um.
#Total wire length on LAYER Metal3 = 27038 um.
#Total wire length on LAYER Metal4 = 0 um.
#Total wire length on LAYER Metal5 = 0 um.
#Total wire length on LAYER Metal6 = 0 um.
#Total wire length on LAYER Metal7 = 0 um.
#Total wire length on LAYER Metal8 = 0 um.
#Total wire length on LAYER Metal9 = 0 um.
#Total number of vias = 24203

#Total number of multi-cut vias = 410 ( 1.7%)

#Total number of single cut vias = 23793 ( 98.3%)
#Up-Via Summary (total 24203):
#

single-cut

multi-cut

Total

#----------------------------------------------------------# Metal 1

14528 ( 97.3%)

410 ( 2.7%)

# Metal 2

9265 (100.0%)

0 ( 0.0%)

14938
9265

#----------------------------------------------------------#

23793 ( 98.3%)

410 ( 1.7%)

24203

#
#
#Start DRC checking..
#

number of violations = 0

#cpu time = 00:00:04, elapsed time = 00:00:04, memory = 1085.27 (MB), peak
= 1252.13 (MB)
#

number of violations = 0

#cpu time = 00:00:04, elapsed time = 00:00:04, memory = 1085.27 (MB), peak
= 1252.13 (MB)
#CELL_VIEW tdsp_core,init has no DRC violation.
#Total number of DRC violations = 0
#Total number of net violated process antenna rule = 0
#detailRoute Statistics:
#Cpu time = 00:00:51
#Elapsed time = 00:00:52
#Increased memory = 210.36 (MB)
#Total memory = 1085.19 (MB)
#Peak memory = 1252.13 (MB)
#
#globalDetailRoute statistics:

#Cpu time = 00:00:59

#Elapsed time = 00:00:59
#Increased memory = 263.15 (MB)
#Total memory = 1085.28 (MB)
#Peak memory = 1252.13 (MB)
#Number of warnings = 51
#Total number of warnings = 52
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Fri Apr 1 16:14:33 2016
#
#routeDesign: cpu time = 00:00:59, elapsed time = 00:00:59, memory =
1085.28 (MB), peak = 1252.13 (MB)
*** Message Summary: 0 warning(s), 0 error(s)

<CMD> getLogFileName