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MC68HC11PA8 MC68HC711PA8 MC68HC11PB8 MC68HC711PB8: Technical Data

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54 views238 pages

MC68HC11PA8 MC68HC711PA8 MC68HC11PB8 MC68HC711PB8: Technical Data

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Carlos Vicente Lemes

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MC68HC11PA8/D

MC68HC11PA8

HC11

TECHNICAL DATA

MC68HC11PA8
MC68HC711PA8
MC68HC11PB8
MC68HC711PB8
TECHNICAL
DATA

INTRODUCTION

PIN DESCRIPTIONS

CPU CORE AND INSTRUCTION SET

OPERATING MODES AND ON-CHIP MEMORY

RESETS AND INTERRUPTS

PARALLEL INPUT/OUTPUT

SERIAL COMMUNICATIONS INTERFACE

I2C BUS

SERIAL PERIPHERAL INTERFACE

TIMING SYSTEM

ANALOG-TO-DIGITAL CONVERTER

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA AND ORDERING INFORMATION

DEVELOPMENT SUPPORT

TPG

INTRODUCTION

PIN DESCRIPTIONS

CPU CORE AND INSTRUCTION SET

OPERATING MODES AND ON-CHIP MEMORY

RESETS AND INTERRUPTS

PARALLEL INPUT/OUTPUT

SERIAL COMMUNICATIONS INTERFACE

I2C BUS

SERIAL PERIPHERAL INTERFACE

TIMING SYSTEM

ANALOG-TO-DIGITAL CONVERTER

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA AND ORDERING INFORMATION

DEVELOPMENT SUPPORT
TPG

MC68HC11PA8/
MC68HC11PB8
MC68HC711PA8/
MC68HC711PB8
High-density complementary
metal oxide semiconductor
(HCMOS) microcontroller unit

All Trade Marks recognized. This document contains information on new products. Specifications and information herein are
subject to change without notice.

All products are sold on Motorolas Terms & Conditions of Supply. In ordering a product covered by this document the
Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part
of a contract (with the exception of the contents of this Notice). A copy of Motorolas Terms & Conditions of Supply is available
on request.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All
operating parameters, including Typicals, must be validated for each customer application by customers technical experts.
Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and !are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office.
This document supersedes any earlier documentation relating to the products referred to herein. The information contained
in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.

MOTOROLA LTD., 1997

TPG

Conventions
Where abbreviations are used in the text, an explanation can be found in the
glossary, at the back of this manual. Register and bit mnemonics are defined in the
paragraphs describing them.
An overbar is used to designate an active-low signal, eg: RESET.
Because the bits in any one register are not necessarily linked by a common
function, the description of a register may appear in several sections referring to
different aspects of device operation. A full description of a bit is given only in a
section in which it has relevance. Elsewhere, it appears shaded in the register
diagram and is only briefly described.
When the state of a bit on reset is described as x, this means that its state depends
on factors such as the operating mode selected. A u indicates that the bits state on
reset is undefined.

TPG

CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC11PA8/D)

Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you
have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer).
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SECTION 1

INTRODUCTION

SECTION 2

PIN DESCRIPTIONS

SECTION 3

CPU CORE AND INSTRUCTION SET

SECTION 4

OPERATING MODES AND ON-CHIP MEMORY

SECTION 5

RESETS AND INTERRUPTS

SECTION 6

PARALLEL INPUT/OUTPUT

SECTION 7

SERIAL COMMUNICATIONS INTERFACE

SECTION 8

I2C BUS

SECTION 9

SERIAL PERIPHERAL INTERFACE

SECTION 10

TIMING SYSTEM

SECTION 11

ANALOG-TO-DIGITAL CONVERTER

SECTION A

ELECTRICAL SPECIFICATIONS

SECTION B

MECHANICAL DATA AND ORDERING INFORMATION

SECTION C

DEVELOPMENT SUPPORT

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TPG

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!MOTOROLA

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IBRS NUMBER PHQ-B/207/G

CCRI NUMERO PHQ-B/207/G

F.A.O. Technical Publications Group

(re: MC68HC11PA8/D)

Semiconductor Products Sector

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TPG

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TABLE OF CONTENTS
Paragraph
Number

TITLE

Page
Number

1
INTRODUCTION
1.1
1.2

Features ................................................................................................................ 1-1

Mask options ......................................................................................................... 1-2

2
PIN DESCRIPTIONS
2.1
VDD and VSS ........................................................................................................ 2-2
2.2
RESET................................................................................................................... 2-3
2.3
Crystal driver and external clock input (XTAL, EXTAL).......................................... 2-3
2.4
E clock output (E) .................................................................................................. 2-5
2.5
Phase-locked loop (XFC, VDDSYN)...................................................................... 2-6
2.5.1
PLL operation .................................................................................................. 2-7
2.5.2
Synchronization of PLL with subsystems ........................................................ 2-8
2.5.3
Changing the PLL frequency ........................................................................... 2-8
2.5.4
PLL registers.................................................................................................... 2-8
2.5.4.1
PLLCR PLL control register................................................................... 2-9
2.5.4.2
SYNR Synthesizer program register ..................................................... 2-11
2.6
Interrupt request (IRQ) .......................................................................................... 2-12
2.7
Nonmaskable interrupt (XIRQ/VPPE).................................................................... 2-12
2.8
MODA and MODB (MODA/LIR and MODB/VSTBY)............................................. 2-13
2.9
VRH and VRL ........................................................................................................ 2-13
2.10 PG7/R/W ............................................................................................................... 2-13
2.11 Port signals............................................................................................................ 2-14
2.11.1
Port A ............................................................................................................... 2-14
2.11.2
Port B ............................................................................................................... 2-14
2.11.3
Port C............................................................................................................... 2-15
2.11.4
Port D............................................................................................................... 2-16
2.11.5
Port E ............................................................................................................... 2-16
2.11.6
Port F ............................................................................................................... 2-17
2.11.7
Port G .............................................................................................................. 2-17

TPG

MC68HC11PA8

TABLE OF CONTENTS

MOTOROLA
i

Paragraph
Number

TITLE

Page
Number

3
CPU CORE AND INSTRUCTION SET
3.1
Registers ............................................................................................................... 3-1
3.1.1
Accumulators A, B and D................................................................................. 3-2
3.1.2
Index register X (IX)......................................................................................... 3-2
3.1.3
Index register Y (IY) ......................................................................................... 3-2
3.1.4
Stack pointer (SP)............................................................................................ 3-2
3.1.5
Program counter (PC)...................................................................................... 3-4
3.1.6
Condition code register (CCR) ........................................................................ 3-4
3.1.6.1
Carry/borrow (C) ........................................................................................ 3-5
3.1.6.2
Overflow (V) ............................................................................................... 3-5
3.1.6.3
Zero (Z) ...................................................................................................... 3-5
3.1.6.4
Negative (N) ............................................................................................... 3-5
3.1.6.5
Interrupt mask (I)........................................................................................ 3-5
3.1.6.6
Half carry (H) ............................................................................................. 3-6
3.1.6.7
X interrupt mask (X) ................................................................................... 3-6
3.1.6.8
Stop disable (S) ......................................................................................... 3-6
3.2
Data types ............................................................................................................. 3-6
3.3
Opcodes and operands ......................................................................................... 3-7
3.4
Addressing modes................................................................................................. 3-7
3.5
Immediate (IMM) ................................................................................................... 3-7
3.5.1
Direct (DIR)...................................................................................................... 3-7
3.5.2
Extended (EXT) ............................................................................................... 3-8
3.5.3
Indexed (IND, X; IND, Y)................................................................................... 3-8
3.5.4
Inherent (INH) .................................................................................................. 3-8
3.5.5
Relative (REL) ................................................................................................. 3-8
3.6
Instruction set ........................................................................................................ 3-8

4
OPERATING MODES AND ON-CHIP MEMORY
4.1
Operating modes................................................................................................... 4-1
4.1.1
Single chip operating mode ............................................................................. 4-1
4.1.2
Expanded operating mode .............................................................................. 4-1
4.1.3
Special test mode ............................................................................................ 4-2
4.1.4
Special bootstrap mode ................................................................................... 4-2
4.2
On-chip memory.................................................................................................... 4-4
4.2.1
Mapping allocations ......................................................................................... 4-4
4.2.1.1
RAM ........................................................................................................... 4-5
4.2.1.2
ROM and EPROM...................................................................................... 4-6
4.2.1.3
Bootloader ROM ........................................................................................ 4-6
4.2.2
Registers ......................................................................................................... 4-6
4.3
System initialization............................................................................................... 4-10
4.3.1
Mode selection ................................................................................................ 4-10

TPG

MOTOROLA
ii

TABLE OF CONTENTS

MC68HC11PA8

Paragraph
Number

TITLE

Page
Number

4.3.1.1
HPRIO Highest priority I-bit interrupt & misc. register ........................... 4-11
4.3.2
Initialization ...................................................................................................... 4-12
4.3.2.1
CONFIG System configuration register ................................................. 4-12
4.3.2.2
INIT RAM and I/O mapping register ...................................................... 4-14
4.3.2.3
INIT2 EEPROM mapping register ......................................................... 4-15
4.3.2.4
OPTION System configuration options register 1.................................. 4-16
4.3.2.5
OPT2 System configuration options register 2 ...................................... 4-18
4.3.2.6
BPROT Block protect register................................................................ 4-20
4.3.2.7
TMSK2 Timer interrupt mask register 2................................................. 4-21
4.4
EPROM, EEPROM and CONFIG register ............................................................. 4-22
4.4.1
EPROM............................................................................................................ 4-22
4.4.1.1
EPROG EPROM programming control register..................................... 4-22
4.4.1.2
EPROM programming ................................................................................ 4-23
4.4.2
EEPROM ......................................................................................................... 4-24
4.4.2.1
PPROG EEPROM programming control register .................................. 4-24
4.4.2.2
EEPROM bulk erase .................................................................................. 4-26
4.4.2.3
EEPROM row erase ................................................................................... 4-27
4.4.2.4
EEPROM byte erase .................................................................................. 4-27
4.4.3
CONFIG register programming........................................................................ 4-27
4.4.4
RAM and EEPROM security ............................................................................ 4-28

5
RESETS AND INTERRUPTS
5.1
Resets ................................................................................................................... 5-1
5.1.1
Power-on reset................................................................................................. 5-1
5.1.2
External reset (RESET) ................................................................................... 5-2
5.1.3
COP reset ........................................................................................................ 5-2
5.1.3.1
COPRST Arm/reset COP timer circuitry register................................... 5-3
5.1.4
Clock monitor reset .......................................................................................... 5-3
5.1.5
OPTION System configuration options register 1 ....................................... 5-4
5.1.6
CONFIG Configuration control register ....................................................... 5-5
5.2
Effects of reset....................................................................................................... 5-7
5.2.1
Central processing unit .................................................................................... 5-7
5.2.2
Memory map.................................................................................................... 5-7
5.2.3
Parallel I/O ....................................................................................................... 5-8
5.2.4
Timer................................................................................................................ 5-8
5.2.5
Real-time interrupt (RTI) .................................................................................. 5-8
5.2.6
Pulse accumulator ........................................................................................... 5-8
5.2.7
Computer operating properly (COP)................................................................ 5-9
5.2.8
Serial communications interface (SCI)............................................................. 5-9
5.2.9
Serial peripheral interface (SPI)....................................................................... 5-9
5.2.10
I2C bus ............................................................................................................. 5-9
5.2.11
Analog-to-digital converter............................................................................... 5-9
5.2.12
System............................................................................................................. 5-9

TPG

MC68HC11PA8

TABLE OF CONTENTS

MOTOROLA
iii

Paragraph
Number

TITLE

Page
Number

5.3
Reset and interrupt priority.................................................................................... 5-10
5.3.1
HPRIO Highest priority I-bit interrupt and misc. register ............................. 5-11
5.4
Interrupts ............................................................................................................... 5-14
5.4.1
Interrupt recognition and register stacking ...................................................... 5-14
5.4.2
Nonmaskable interrupt request (XIRQ) ........................................................... 5-15
5.4.3
Illegal opcode trap ........................................................................................... 5-15
5.4.4
Software interrupt ............................................................................................ 5-15
5.4.5
Maskable interrupts ......................................................................................... 5-16
5.4.6
Reset and interrupt processing........................................................................ 5-16
5.5
Low power operation ............................................................................................. 5-16
5.5.1
WAIT................................................................................................................ 5-16
5.5.2
STOP ............................................................................................................... 5-17

6
PARALLEL INPUT/OUTPUT
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.5
6.5.1
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6.9
6.9.1
6.10
6.10.1
6.10.2

Port A .................................................................................................................... 6-2

PORTA Port A data register ........................................................................ 6-2
DDRA Data direction register for port A...................................................... 6-2
Port B .................................................................................................................... 6-3
PORTB Port B data register........................................................................ 6-3
DDRB Data direction register for port B...................................................... 6-3
Port C .................................................................................................................... 6-4
PORTC Port C data register ....................................................................... 6-4
DDRC Data direction register for port C ..................................................... 6-4
Port D .................................................................................................................... 6-5
PORTD Port D data register ....................................................................... 6-5
DDRD Data direction register for port D ..................................................... 6-5
Port E .................................................................................................................... 6-6
PORTE Port E data register........................................................................ 6-6
Port F..................................................................................................................... 6-7
PORTF Port F data register ........................................................................ 6-7
DDRF Data direction register for port F ...................................................... 6-7
Port G .................................................................................................................... 6-8
PORTG Port G data register ....................................................................... 6-8
DDRG Data direction register for port G ..................................................... 6-8
XIRQ and IRQ pins................................................................................................ 6-9
SPSR SPI status register ............................................................................ 6-9
Internal pull-up resistors ........................................................................................ 6-10
PPAR Port pull-up assignment register ....................................................... 6-10
System configuration............................................................................................. 6-10
OPT2 System configuration options register 2............................................ 6-11
CONFIG System configuration register....................................................... 6-12

TPG

MOTOROLA
iv

TABLE OF CONTENTS

MC68HC11PA8

Paragraph
Number

TITLE

Page
Number

7
SERIAL COMMUNICATIONS INTERFACE
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.5
7.6
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
7.7.1

Data format............................................................................................................ 7-2

Transmit operation ................................................................................................. 7-2
Receive operation.................................................................................................. 7-2
Wake-up feature .................................................................................................... 7-4
Idle-line wake-up.............................................................................................. 7-4
Address-mark wake-up .................................................................................... 7-4
SCI error detection ................................................................................................ 7-5
SCI registers.......................................................................................................... 7-5
SCBDH, SCBDL SCI baud rate control registers ........................................ 7-6
SCCR1 SCI control register 1 ..................................................................... 7-7
SCCR2 SCI control register 2 ..................................................................... 7-9
SCSR1 SCI status register 1....................................................................... 7-10
SCSR2 SCI status register 2....................................................................... 7-12
SCDRH, SCDRL SCI data high/low registers ............................................. 7-12
Status flags and interrupts..................................................................................... 7-13
Receiver flags .................................................................................................. 7-13

8
I2C BUS
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
8.5.1
8.5.2
8.5.3

I2C bus features..................................................................................................... 8-2

I2C bus system configuration................................................................................. 8-2
I2C bus protocol..................................................................................................... 8-2
START signal ................................................................................................... 8-4
Transmission of the slave address ................................................................... 8-4
Data transfer .................................................................................................... 8-4
STOP signal..................................................................................................... 8-4
Repeated START signal................................................................................... 8-5
Arbitration procedure ....................................................................................... 8-5
Clock synchronization ...................................................................................... 8-5
Handshaking.................................................................................................... 8-6
Registers ............................................................................................................... 8-6
CONFIG System configuration register....................................................... 8-6
MADR I2C bus address register .................................................................. 8-7
MFDR I2C bus frequency divider register.................................................... 8-7
MCR I2C bus control register ...................................................................... 8-8
MSR I2C bus status register........................................................................ 8-9
MDR I2C bus data register .......................................................................... 8-10
Programming considerations................................................................................. 8-11
Initialization ...................................................................................................... 8-11
START signal and the first byte of data............................................................ 8-11
Software response ........................................................................................... 8-12

TPG

MC68HC11PA8

TABLE OF CONTENTS

MOTOROLA
v

Paragraph
Number
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8

TITLE

Page
Number

Generation of a STOP signal........................................................................... 8-12

Generation of a repeated START signal .......................................................... 8-13
Slave mode...................................................................................................... 8-13
Arbitration lost.................................................................................................. 8-14
Operation during STOP and WAIT modes....................................................... 8-14

9
SERIAL PERIPHERAL INTERFACE
9.1
9.2
9.2.1
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4

Functional description ........................................................................................... 9-1

SPI transfer formats............................................................................................... 9-2
Clock phase and polarity controls.................................................................... 9-3
SPI signals ............................................................................................................ 9-3
Master in slave out........................................................................................... 9-4
Master out slave in........................................................................................... 9-4
Serial clock ...................................................................................................... 9-4
Slave select ..................................................................................................... 9-4
SPI system errors.................................................................................................. 9-5
SPI registers.......................................................................................................... 9-5
SPCR SPI control register .......................................................................... 9-6
SPSR SPI status register ............................................................................ 9-8
SPDR SPI data register .............................................................................. 9-9
OPT2 System configuration options register 2............................................ 9-9

10
TIMING SYSTEM
10.1 Timer operation ................................................................................................... 10-1
10.1.1
Timer structure .............................................................................................. 10-4
10.1.2
Input capture.................................................................................................. 10-6
10.1.2.1
TCTL2 Timer control register 2............................................................ 10-7
10.1.2.2
TIC1TIC3 Timer input capture registers ............................................ 10-8
10.1.2.3
TI4/O5 Timer input capture 4/output compare 5 register..................... 10-8
10.1.3
Output compare ............................................................................................. 10-9
10.1.3.1
TOC1TOC4 Timer output compare registers..................................... 10-10
10.1.3.2
CFORC Timer compare force register................................................. 10-10
10.1.3.3
OC1M Output compare 1 mask register.............................................. 10-11
10.1.3.4
OC1D Output compare 1 data register................................................ 10-11
10.1.3.5
TCNT Timer counter register............................................................... 10-12
10.1.3.6
TCTL1 Timer control register 1............................................................ 10-12
10.1.3.7
TMSK1 Timer interrupt mask register 1............................................... 10-13
10.1.3.8
TFLG1 Timer interrupt flag register 1 .................................................. 10-14
10.1.3.9
TMSK2 Timer interrupt mask register 2............................................... 10-15
10.1.3.10
TFLG2 Timer interrupt flag register 2 .................................................. 10-16

TPG

MOTOROLA
vi

TABLE OF CONTENTS

MC68HC11PA8

Paragraph
Number
10.1.4
10.1.4.1
10.1.4.2
10.1.4.3
10.1.5
10.1.6
10.1.6.1
10.1.6.2
10.1.6.3
10.1.6.4
10.1.6.5

TITLE

Page
Number

Real-time interrupt ......................................................................................... 10-17

TMSK2 Timer interrupt mask register 2............................................... 10-17
TFLG2 Timer interrupt flag register 2 .................................................. 10-18
PACTL Pulse accumulator control register .......................................... 10-19
Computer operating properly watchdog function ........................................... 10-20
Pulse accumulator ......................................................................................... 10-20
PACTL Pulse accumulator control register .......................................... 10-22
PACNT Pulse accumulator count register............................................ 10-23
Pulse accumulator status and interrupt bits ............................................. 10-23
TMSK2 Timer interrupt mask 2 register............................................... 10-23
TFLG2 Timer interrupt flag 2 register .................................................. 10-23

11
ANALOG-TO-DIGITAL CONVERTER
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
11.1.7
11.2
11.2.1
11.3
11.3.1
11.3.2
11.4
11.4.1
11.4.2
11.5

Overview.............................................................................................................. 11-2
Multiplexer...................................................................................................... 11-3
Analog converter............................................................................................ 11-3
Digital control ................................................................................................. 11-4
Result registers.............................................................................................. 11-4
A/D converter clocks ...................................................................................... 11-4
Conversion sequence .................................................................................... 11-4
Conversion process ....................................................................................... 11-4
A/D converter power-up and clock select ............................................................ 11-5
OPTION System configuration options register 1 ..................................... 11-5
Channel assignments .......................................................................................... 11-7
Single-channel operation ............................................................................... 11-7
Multiple-channel operation............................................................................. 11-8
Control, status and results registers .................................................................... 11-8
ADCTL A/D control and status register ..................................................... 11-8
ADR1ADR4 A/D converter results registers............................................ 11-10
Operation in STOP and WAIT modes.................................................................. 11-10

A
ELECTRICAL SPECIFICATIONS
A.1
A.2
A.3
A.4
A.4.1
A.5
A.5.1
A.5.2

Maximum ratings ...................................................................................................A-1

Thermal characteristics and power considerations ...............................................A-1
Test methods .........................................................................................................A-3
DC electrical characteristics ..................................................................................A-4
DC electrical characteristics modes of operation ........................................A-5
Control timing ........................................................................................................A-5
Peripheral port timing.......................................................................................A-9
PLL control timing ............................................................................................A-10

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MC68HC11PA8

TABLE OF CONTENTS

MOTOROLA
vii

Paragraph
Number

TITLE

Page
Number

A.5.3
Analog-to-digital converter characteristics....................................................... A-11
A.5.4
Serial peripheral interface timing ..................................................................... A-12
A.5.5
Non-multiplexed expansion bus timing ............................................................ A-15
A.6
EEPROM characteristics....................................................................................... A-16
A.7
EPROM characteristics ......................................................................................... A-17

B
MECHANICAL DATA AND ORDERING INFORMATION
B.1

Ordering information.............................................................................................. B-4

C
DEVELOPMENT SUPPORT
C.1
C.2
C.3

EVS Evaluation system ....................................................................................C-1

MMDS11 Motorola modular development system ............................................C-2
SPGMR11 Serial programmer system .............................................................C-2

TPG

MOTOROLA
viii

TABLE OF CONTENTS

MC68HC11PA8

LIST OF FIGURES
Figure
Number
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
4-1
4-2
5-1
5-2
5-3
5-4
5-5
5-6
7-1
7-2
7-3
8-1
8-2
8-3
8-4
9-1
9-2
10-1
10-2
10-3
11-1
11-2

TITLE

Page
Number

MC68HC11PA8/MC68HC11PB8 and
MC68HC711PA8/MC68HC711PB8 block diagram................................................... 1-3
64-pin QFP pinout (MC68HC11PA8) ........................................................................ 2-1
64-pin QFP pinout (MC68HC11PB8) ....................................................................... 2-2
External reset circuitry .............................................................................................. 2-3
Oscillator connections (VDDSYN = 0, PLL disabled) ............................................... 2-4
Oscillator connections (VDDSYN = 1, PLL enabled)................................................ 2-5
PLL circuit ................................................................................................................. 2-6
RAM stand-by connections....................................................................................... 2-13
Programming model ................................................................................................. 3-1
Stacking operations .................................................................................................. 3-3
MC68HC11PA8/MC68HC11PB8/MC68HC711PA8/MC68HC711PB8 memory map 4-4
RAM and register overlap ......................................................................................... 4-15
Processing flow out of reset (1 of 2) ......................................................................... 5-18
Processing flow out of reset (2 of 2) ......................................................................... 5-19
Interrupt priority resolution (1 of 3) ........................................................................... 5-20
Interrupt priority resolution (2 of 3) ........................................................................... 5-21
Interrupt priority resolution (3 of 3) ........................................................................... 5-22
Interrupt source resolution within the SCI subsystem .............................................. 5-23
SCI baud rate generator circuit diagram................................................................... 7-1
SCI block diagram .................................................................................................... 7-3
Interrupt source resolution within SCI....................................................................... 7-14
I2C bus transmission signal diagrams ...................................................................... 8-3
Clock synchronization............................................................................................... 8-5
Example of a typical I2C bus interrupt routine (sheet 1 of 2) .................................... 8-15
Example of a typical I2C bus interrupt routine (sheet 2 of 2) .................................... 8-16
SPI block diagram..................................................................................................... 9-2
SPI transfer format.................................................................................................... 9-3
Timer clock divider chains ...................................................................................... 10-3
Capture/compare block diagram............................................................................. 10-5
Pulse accumulator block diagram ........................................................................... 10-21
A/D converter block diagram................................................................................... 11-2
Electrical model of an A/D input pin (in sample mode)........................................... 11-3

TPG

MC68HC11PA8

LIST OF FIGURES

MOTOROLA
ix

Figure
Number
11-3
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
B-1
11-4
B-2

TITLE

Page
Number

A/D conversion sequence........................................................................................11-5

Test methods ............................................................................................................ A-3
Timer inputs.............................................................................................................. A-6
Reset timing ............................................................................................................. A-7
Interrupt timing ......................................................................................................... A-7
STOP recovery timing .............................................................................................. A-8
WAIT recovery timing ............................................................................................... A-8
Port read timing diagram .......................................................................................... A-9
Port write timing diagram.......................................................................................... A-9
SPI master timing (CPHA = 0).................................................................................. A-13
SPI master timing (CPHA = 1).................................................................................. A-13
SPI slave timing (CPHA = 0) .................................................................................... A-14
SPI slave timing (CPHA = 1) .................................................................................... A-14
Expansion bus timing ............................................................................................... A-16
64-pin QFP pinout (MC68HC11PA8)........................................................................ B-1
64-pin QFP pinout (MC68HC11PB8) ....................................................................... B-2
64-pin QFP mechanical dimensions......................................................................... B-3

TPG

MOTOROLA
x

LIST OF FIGURES

MC68HC11PA8

LIST OF TABLES
Table
Number
2-1
2-2
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
5-3
5-4
5-5
6-1
7-1
8-1
9-1
10-1
10-2
10-3
11-1
K-2
K-3
C-1

TITLE

Page
Number

PLL mask options ..................................................................................................... 2-7

Port signal functions ................................................................................................. 2-15
Reset vector comparison .......................................................................................... 3-4
Instruction set ........................................................................................................... 3-9
Example bootloader baud rates................................................................................ 4-3
Register and control bit assignments ....................................................................... 4-7
Registers with limited write access........................................................................... 4-10
Hardware mode select summary.............................................................................. 4-11
RAM and register remapping.................................................................................... 4-14
EEPROM remapping ................................................................................................ 4-16
EEPROM block protect ............................................................................................. 4-20
Erase mode selection ............................................................................................... 4-25
COP timer rate select ............................................................................................... 5-2
Reset cause, reset vector and operating mode ........................................................ 5-7
Highest priority interrupt selection ............................................................................ 5-12
Interrupt and reset vector assignments .................................................................... 5-13
Stacking order on entry to interrupts ........................................................................ 5-14
Port configuration...................................................................................................... 6-1
Example SCI baud rate control values ..................................................................... 7-7
I2C bus prescaler ...................................................................................................... 8-7
SPI clock rates.......................................................................................................... 9-7
Timer resolution and capacity................................................................................. 10-2
RTI periodic rates ................................................................................................... 10-17
Pulse accumulator timing........................................................................................ 10-20
A/D converter channel assignments ....................................................................... 11-7
Standard device ordering information....................................................................... B-4
Custom ROM device ordering information................................................................ B-4
M68HC11 development tools ................................................................................... C-1

TPG

MC68HC11PA8

LIST OF TABLES

MOTOROLA
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MOTOROLA
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LIST OF TABLES

MC68HC11PA8

1
INTRODUCTION
The MC68HC11PA8 and the MC68HC11PB8 are members of the M68HC11 family of HCMOS
microcontrollers. In addition to 48K bytes of ROM, the MC68HC11PA8/MC68HC11PB8 contains
2K bytes of RAM and 512 bytes of EEPROM. The combination of large memory and
state-of-the-art, power-saving timer features makes the MC68HC11PA8/MC68HC11PB8 ideal for
complex, power-sensitive applications. In addition, the integrated A/D and timer systems, together
with the use of the 64-pin QFP package, means that the MC68HC11PA8/MC68HC11PB8 is an
excellent choice for space-critical applications. Another notable feature of the device is its wide
range of serial communications; in addition to an SCI subsystem, the device contains an SPI
subsystem and an I 2 C serial interface.
The MC68HC711PA8/MC68HC711PB8 is an EPROM version of the MC68HC11PA8/
MC68HC11PB8, with the user ROM replaced by a similar amount of EPROM. All references to
the MC68HC11PA8/MC68HC11PB8 apply equally to the MC68HC711PA8/MC68HC711PB8,
unless otherwise noted. References specific to the MC68HC711PA8/MC68HC711PB8 are
italicised in the text.

1.1

Features

Low-power, high performance M68HC11 CPU core

4.4MHz bus frequency

48K bytes of ROM (MC68HC11PA8/MC68HC11PB8); 48K bytes of user EPROM

(MC68HC711PA8/MC68HC711PB8)

2K bytes of RAM

512 bytes of byte-erasable EEPROM, with on-chip charge pump

Non-multiplexed address and data buses

Power-saving PLL clock generation circuit

I 2 C bus is a proprietary Philips interface bus.

TPG

MC68HC11PA8

INTRODUCTION

MOTOROLA
1-1

SCI subsystem with modulus baud rate selection

I 2 C bus subsystem

SPI subsystem with software-selectable MSB/LSB first option

8-bit analog to digital (A/D) converter

Up to 39 general-purpose I/O lines plus up to 6 input-only lines

Schmitt trigger input buffers on every I/O line (except ports C and E) for reduced noise
sensitivity

16-bit timer with 3/4 input captures and 4/5 output compares; pulse accumulator and COP
watchdog timer

Power saving STOP and WAIT modes

Available in 64-pin QFP and 68-pin CLCC packaging. CLCC packaged devices are available
as samples only. Contact your Motorola sales office for more information.

1.2

Mask options

There are five mask options available on the MC68HC11PA8/MC68HC11PB8. These options are
programmed during manufacture and should be specified on the order form.

POR/exit from STOP start-up time (4064/128 bus cycles); see Section 4.3.2.4.

PLL oscillator frequency (32kHz/614kHz/2MHz and above); see Section 2.5.

State of the PLL synthesizer program register (SYNR) on reset (customer defined); see
Section 2.5.4.2.

Security option (available/unavailable); see Section 4.4.4.

Oscillator buffer type (inverter/Schmitt trigger); see Section 2.3.

Note:

These options are not available on the MC68HC711PA8/MC68HC711PB8; on this

device the POR/exit from STOP start-up time is 4064 bus cycles, the SYNR register
contains $01 on reset, the security feature is available, the oscillator buffer is an
inverter, and the PLL oscillator is optimized for operation at frequencies of 2 MHz and
above.

TPG

MOTOROLA
1-2

INTRODUCTION

MC68HC11PA8

COP watchdog

OC1/PAI
OC1/OC2
OC1/OC3
OC1/OC4
IC4/OC1/OC5
IC1
IC2
IC3

SCI+

TXD
RXD

Pulse accumulator

ROM or EPROM
48K bytes

Timer
Periodic interrupt

512 bytes EEPROM

Port A

PD1
PD0

XTAL
EXTAL
E
XOUT2
XFC
VDDSYN

Interrupts
&
mode
select

Oscillator

I2C bus

SCL
SDA

8-channel
A/D
converter

PLL

AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

Port E

XIRQ
IRQ
RESET
MODA/LIR
MODB/VSTBY

SS
SCK
MOSI
MISO

Port D

2K bytes RAM
SPI

3
4

R/W

M68HC11
CPU

Port G

VDD
VSS

PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0

PD5
PD4
PD3
PD2

PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VRH
VRL
PG7

A15
A14
A13
A12
A11
A10
A9
A8

A7
A6
A5
A4
A3
A2
A1
A0

D7
D6
D5
D4
D3
D2
D1
D0

Port B

Port F

Port C

PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0

PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0

PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

Non-multiplexed address and data buses

Notes:
1. Either pins PD[4, 3] or pins PE[7, 6] may be used for the I2C bus.
2. The XOUT pin is not available on 64-pin QFP packaged devices, but it is present on the 68-pin CLCC package.
Pins PE4 and PE5 are available on the 64-pin QFP MC68HC11PB8/MC68HC711PB8 devices and on all 68-pin CLCC devices.

Figure 1-1 MC68HC11PA8/MC68HC11PB8 and

MC68HC711PA8/MC68HC711PB8 block diagram

TPG

MC68HC11PA8

INTRODUCTION

MOTOROLA
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TPG

MOTOROLA
1-4

INTRODUCTION

MC68HC11PA8

2
PIN DESCRIPTIONS

PD0/RXD

MODA/LIR

MODB/VSTBY

RESET

XTAL

EXTAL

PC7/D7

PC6/D6

PC5/D5

PC4/D4

PC3/D3

PC2/D2

PC1/D1

PC0/D0

PF0/A0

The MC68HC11PA8/MC68HC11PB8 and MC68HC711PA8/MC68HC711PB8 are available

packaged in a 64-pin quad flat pack (QFP). Windowed samples however, are only available in a
68-pin CLCC. Most pins on this MCU serve two or more functions, as described in the following
paragraphs. Refer to Figure 2-1 and Figure 2-2, which show the pin assignments in the 64-pin
package for the MC68HC11PA8 and MC68HC11PB8 respectively.

PD1/TXD

PF1/A1

PD2/MISO

PF2/A2

PD3/MOSI/SDA

PF3/A3

PD4/SCK/SCL

PF4/A4

PD5/SS

PF5/A5

VSS

PF6/A6

VDDEX

PF7/A7

VDD

VSS

PE6/AD6/SDA

XIRQ/VPPE

PG7/R/W

IRQ

VDDAD

VSSEX

33
PE7/AD7/SCL

16
26

PE3/AD3

PA0/IC3

XFC

34
25

VDDSYN

PE2/AD2

PA1/IC2

PB0/A8

PE1/AD1

PA2/IC1

PB1/A9

PB2/A10

PE0/AD0

PA3/OC5/IC4/OC1

PB3/A11

VRL

PA4/OC4/OC1

PB4/A12

PB5/A13

VRH

PA5/OC3/OC1

VSSAD

PB6/A14

PB7/A15

PA7/PAI/OC1
PA6/OC2/OC1

Figure 2-1 64-pin QFP pinout (MC68HC11PA8)

TPG

MC68HC11PA8

PIN DESCRIPTIONS

MOTOROLA
2-1

PD0/RXD

MODA/LIR

MODB/VSTBY

RESET

XTAL

EXTAL

PC7/D7

PC6/D6

PC5/D5

PC4/D4

PC3/D3

PC2/D2

PC1/D1

PC0/D0

PF0/A0

2
PD1/TXD

PF1/A1

PD2/MISO

PF2/A2

PD3/MOSI/SDA

PF3/A3

PD4/SCK/SCL

PF4/A4

PD5/SS

PF5/A5

VSS

PF6/A6

VDDEX

PF7/A7

VDD

VSS/VSSAD

PE6/AD6/SDA

XIRQ/VPPE

PG7/R/W

IRQ

VDDAD

PE5

33
PE7/AD7/SCL

16
26

PE4

PA0/IC3

XFC

34
25

VDDSYN

PE3

PA1/IC2

PB0/A8

PE2

PA2/IC1

PB1/A9

PB2/A10

PE1

PA3/OC5/IC4/OC1

PB3/A11

PE0

PA4/OC4/OC1

PB4/A12

PB5/A13

VRL

PA5/OC3/OC1

VRH

PB6/A14

PB7/A15

PA7/PAI/OC1
PA6/OC2/OC1

Figure 2-2 64-pin QFP pinout (MC68HC11PB8)

2.1

VDD and VSS

Power is supplied to the microcontroller via these pins. VDD is the positive supply and VSS is
ground. The MCU operates from a single 5V (nominal) power supply.
It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These short
rise and fall times place very high short-duration current demands on the power supply. To prevent
noise problems, special care must be taken to provide good power supply bypassing at the MCU.
Bypass capacitors should have good high-frequency characteristics and be as close to the MCU as
possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.
The 64-pin packaged device has three VDD pins and four VSS pins (two VSS pins on the
MC68HC11PB8). These pins supply power to the ADC and to the internal logic and port logic on
each half of the chip.

TPG

MOTOROLA
2-2

PIN DESCRIPTIONS

MC68HC11PA8

2.2

RESET

An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been
detected in either the clock monitor or the COP watchdog circuit. The CPU distinguishes between
internal and external reset conditions by sensing whether the reset pin rises to a logic one in less
than four E clock cycles after an internal reset has been released. It is therefore not advisable to
connect an external resistor-capacitor (RC) power-up delay circuit to the reset pin of M68HC11
devices because the circuit charge time constant can cause the device to misinterpret the type of
reset that occurred. Refer to Section 5 for further information.
VDD

VDD
2

4.7 k

IN
RESET

Manual
reset

MC34064
GND
3

VDD

To M68HC11
RESET

4.7 k

2
IN
RESET

MC34164
GND
3

Figure 2-3 External reset circuitry

Figure 2-3 illustrates a typical reset circuit that includes an external switch together with a low
voltage inhibit circuit, to prevent power transitions or RAM or EEPROM corruption.

2.3

Crystal driver and external clock input (XTAL, EXTAL)

These two pins provide the interface for either a crystal or a CMOS compatible clock to control the
internal clock generator circuitry. If the PLL circuit is not being used to provide the E clock, the
frequency applied to these pins must be four times higher than the desired E clock rate. Figure 2-4

TPG

MC68HC11PA8

PIN DESCRIPTIONS

MOTOROLA
2-3

shows oscillator connections that should be used when the PLL is disabled, and Figure 2-5 shows the
connections that should be used when the PLL is enabled.
The XTAL pin is normally left unconnected when an external CMOS compatible clock input is
connected to the EXTAL pin. The XTAL output is normally intended to drive only a crystal. The
XTAL output can be buffered with a high-impedance buffer, or it can be used to drive the EXTAL
input of another M68HC11 family device (unless the PLL circuit is in use).
On the MC68HC11PA8/MC68HC11PB8, the type of internal crystal oscillator buffer is determined
by a mask option; it can be either an inverter or a Schmitt trigger. Use of the Schmitt trigger type
reduces problems caused by noise, in particular with slow clocks. At crystal power-up, the Schmitt
trigger will only generate internal clocks when the crystal amplitude is sufficient. However, this type
of buffer requires a larger XTAL amplitude and is not recommended for use with high frequency
crystals, especially if a second MCU is to be driven. This option is not available on the
MC68HC711PA8/MC68HC711PB8, on which the crystal oscillator buffer is an inverter.
In all cases, use caution when designing circuitry associated with the oscillator pins.

C1
EXTAL
(a) Common crystal
connections

4E
crystal

10 M

M68HC11
XTAL

EXTAL
(b) External oscillator
connections

External oscillator

M68HC11
XTAL

220

EXTAL

EXTAL
10 M

M68HC11

4E
crystal

M68HC11
NC

XTAL

(c) One crystal driving two MCUs

Note: capacitor values include all stray capacitance.

Figure 2-4 Oscillator connections (VDDSYN = 0, PLL disabled)

TPG

MOTOROLA
2-4

PIN DESCRIPTIONS

MC68HC11PA8

EXTAL
(a) Common crystal connections
(32 to 38.4 kHz crystal)

M68HC11

22 M

crystal

XTAL
C2

390 k

C1
EXTAL
(b) Common crystal connections
(500 to 16000 kHz crystal)

M68HC11

10 M

crystal

XTAL
C2

External oscillator

EXTAL
(c) External oscillator
connections

M68HC11
XTAL

Note: capacitor values include all stray capacitance.

Note: all values of capacitance and resistance shown are approximate; exact values must be calculated knowing the crystal parameters
and the expected voltage and temperature ranges; as a guide C1 = C2 0.5 x crystal capacitance.

Figure 2-5 Oscillator connections (VDDSYN = 1, PLL enabled)

2.4

E clock output (E)

E is the output connection for the internally generated E clock. The signal from E is used as a
timing reference. The frequency of the E clock output is one quarter that of the input frequency at
the XTAL and EXTAL pins (except when the PLL is used as the clock source). When E clock output
is low, an internal process is taking place; when it is high, data is being accessed. All clocks,
including the E clock, are halted when the MCU is in STOP mode. The E clock output can be
turned off in single-chip modes to reduce the effects of RFI (see Section 4.3.2.5).

TPG

MC68HC11PA8

PIN DESCRIPTIONS

MOTOROLA
2-5

2.5

Phase-locked loop (XFC, VDDSYN)

The XFC and VDDSYN pins are the inputs for the on-chip PLL (phase-locked loop) circuitry. On
reset, all system clocks are derived from the internal EXTAL signal (EXTALi). If enabled (VDDSYN
high), the PLL uses the EXTALi frequency as a reference to generate a clock frequency that can
be varied under software control. The user may choose to use the PLL output instead of EXTALi
as the source clock for the system.
The PLL consists of a variable bandwidth loop filter, a voltage controlled oscillator (VCO), a
feedback frequency divider and a digital phase detector. PLL functions are controlled by the
PLLCR and SYNR registers. A block diagram of the PLL circuit is shown in Figure 2-6; refer also
to Figure 10-1.
0.1 F

VDDSYN

XTAL EXTAL STOP

CXFC
XFC
fREF

Phase
detect

PCOMP

Loop filter

0.01 F
BCS

VDDSYN
VCOOUT

VCO

Bus clock
select

EXTALi
fFB
Module clock
select

Frequency divider

4XCLK
To clock
generation
circuitry
ST4XCK
For SCI
and timer

EXTALi

MCS

SYNR
XOUT clock
select

Key:
Note:

XOUT

EXT4X

External connection
The XOUT pin is NOT present on 64-pin packaged devices.
It is present on 68-pin CLCC packaged versions of the MC68HC711PA8 and MC68HC711PB8,
which are available as samples only.
Contact your local Sales Office for further information.

Figure 2-6 PLL circuit

TPG

MOTOROLA
2-6

PIN DESCRIPTIONS

MC68HC11PA8

2.5.1

PLL operation

The voltage controlled oscillator (VCO) generates the PLL output frequency VCOOUT. This signal
is fed back through a frequency divider, which divides the signal frequency by a factor determined
by the contents of the SYNR register, to produce the feedback signal fFB. This signal is input to the
phase detector along with the reference signal, fREF. The phase detector generates a control
signal (PCOMP) which is a function of the phase difference between fFB and fREF. PCOMP is then
integrated, and the resultant dc voltage (visible on XFC) is applied to the VCO, modifying the
output signal VCOOUT to lock it in phase with fREF.

Note:

Because the operation of the PLL depends on repeated adjustments to the voltage
input to the VCO, a time tPLLS is required for the stabilization of the output frequency.

The state of two bits in the PLLCR register, MCS and BCS, determine whether VCOOUT or
EXTALi is used for the system clocks.
A mask option on the MC68HC11PA8/MC68HC11PB8 allows the PLL circuit to be optimized for
operation in one of three frequency ranges, as shown in Table 2-1. (this option is not available on
the MC68HC711PA8/MC68HC711PB8; on this device the PLL is optimized for operation at
frequencies of 2 MHz and above). Input frequencies other than those included in Table 2-1 can be
used. However, for options one or two, at operation above the maximum frequency specified,
VDDSYN should be grounded to disable the PLL and enable the high frequency oscillator circuit.
In this state, the oscillator is designed to operate at frequencies up to 16 MHz and XFC may be
left unconnected. Refer also to Figure 2-5.

Table 2-1 PLL mask options

Characteristic
Typical input frequency
Maximum input frequency

Mask option 1 Mask option 2 Mask option 3

32 kHz
614 kHz
4 MHz
50 kHz
2 MHz
16 MHz

VDDSYN is the power supply pin for the PLL and should be suitably bypassed. Connecting it high
enables the internal low frequency oscillator circuitry designed for the PLL. The external capacitor
on XFC (CXFC) should be located as close to the chip as possible to minimize noise. In general,
a larger capacitor will improve the PLLs frequency stability, at the expense of increasing the time
required for it to settle (tPLLS) at the desired frequency. A capacitor value of 47nF is usually
adequate for 32kHz or 614kHz applications, while a 4.7nF capacitor is suitable for 4 MHz
applications.
The PLL filter has two bandwidths that can be manually selected under control of the BWC bit in
PLLCR. Whenever the PLL is first enabled, the wide bandwidth mode should be used, to enable

TPG

MC68HC11PA8

PIN DESCRIPTIONS

MOTOROLA
2-7

the PLL frequency to ramp up quickly. After a time tPLLS has elapsed, the filter can be switched to
the narrow bandwidth mode, to make the final frequency more stable.
Caution: Bit 5 of the PLLCR (AUTO) must be cleared before an attempt is made to use BWC;
manual bandwidth control should always be used.

2.5.2

Synchronization of PLL with subsystems

If the MCS bit in PLLCR is set, then the SCI and timer clocks run off the PLL output (4XCLK) as
does the CPU. If MCS is cleared, then the timer and SCI subsystems operate off the EXTALi
frequency, but are accessed by the CPU relative to the internal PH2 signal. In this case, although
EXTALi is used as the reference for the PLL, the PH2 clock and the module clocks for the timer
and the SCI are not synchronized. In order to ensure synchronized data, special circuitry has been
incorporated into both subsystems.

2.5.3

Changing the PLL frequency

The PLL output frequency can be changed by altering the contents of the SYNR register (see
Section 2.5.4.2). To prevent possible bursts of high frequency operation during the reconfiguration
of the PLL, the following sequence should be performed:
1) Switch to the low frequency bus rate (BCS = 0).
2) Disable the PLL (PLLON = 0).
3) Change the value in SYNR.
4) Enable the PLL (PLLON = 1).
5) Wait a time tPLLS for the PLL frequency to stabilize.
6) Switch to the high frequency bus rate (BCS = 1).

2.5.4

PLL registers

Two registers are used to control the operation of the MC68HC11PA8/MC68HC11PB8 phase
locked loop circuitry. These are the PLL control register and the synthesizer program register, each
of which is described in the following paragraphs.

TPG

MOTOROLA
2-8

PIN DESCRIPTIONS

MC68HC11PA8

2.5.4.1

PLLCR PLL control register

Address

PLL control (PLLCR)

bit 7

$002E PLLON

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

BCS

AUTO

BWC

VCOT

MCS

WEN

Automatic bandwidth control selected.

Manual bandwidth control selected.

Reset sets this bit.

Caution: This bit must be cleared before an attempt is made to use BWC; manual bandwidth
control should always be used.
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PIN DESCRIPTIONS

MOTOROLA
2-9

BWC Bandwidth control

1 (set)

0 (clear)

Wide (high and low) bandwidth control selected.

Narrow (low) bandwidth control selected.

Bandwidth selection can only be controlled by BWC when AUTO is cleared. After the PLL is first
enabled, or after a change in frequency, a delay of tPLLS is required before clearing BWC. The low
bandwidth driver is always enabled, so this bit determines whether the high bandwidth driver is on
or off. Reset sets this bit.
VCOT VCO test (Test mode only)
1 (set)

0 (clear)

Loop filter operates as specified by AUTO and BWC.

Low bandwidth mode of the PLL filter is disabled.

This bit is used to isolate the loop filter from the VCO for testing purposes. VCOT is always set in
user modes. This bit is writable only in bootstrap and test modes. Reset sets this bit.
MCS Module clock select
1 (set)

4XCLK is the source for the SCI and timer divider chain.

0 (clear)

EXTALi is the source for the SCI and timer divider chain.

Reset clears this bit.

Bit 1 not implemented; always reads zero
WEN WAIT enable
1 (set)

0 (clear)

Low-power WAIT mode selected (PLL set to idle in WAIT mode).

Do not alter 4XCLK during WAIT mode.

This bit determines whether the 4XCLK is disconnected from VCOOUT during WAIT and
connected to EXTALi. Reset clears this bit.
When WEN is set, the CPU will respond to a WAIT instruction by first stacking the relevant
registers, then by clearing BCS and setting the PLL to idle, with modulus = 1. BWC is set so that
the wide bandwidth control is selected.
Any interrupt, any reset, or the assertion of RAF (receiver active flag) in the SCI will allow the PLL
to resume operating at the frequency specified in the SYNR. The user must set BCS after the PLL
has had time to adjust (tPLLS). If the SCI RE bit (receiver enable bit) is clear, then RAF cannot
become set, hence the PLL will not resume normal operation. For a description of RAF and RE,
see Section 7.

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PIN DESCRIPTIONS

MC68HC11PA8

2.5.4.2

SYNR Synthesizer program register

Address

Synthesizer program (SYNR)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PIN DESCRIPTIONS

MC68HC11PA8

2.8

MODA and MODB (MODA/LIR and MODB/VSTBY)

During reset, MODA and MODB select one of the four operating modes. Refer to Section 4.
After the operating mode has been selected, the LIR pin provides an open-drain output (driven
low) to indicate that execution of an instruction has begun. In order to detect consecutive
instructions in a high-speed application, this signal drives high for a short time to prevent false
triggering. A series of E clock cycles occurs during execution of each instruction. The LIR signal
goes low during the first E clock cycle of each instruction (opcode fetch). This output is provided
for assistance in program debugging and its operation is controlled by the LIRDV bit in the OPT2
register.
The VSTBY pin is used to input RAM stand-by power. The MCU is powered from the VDD pin
unless the difference between the level of VSTBY and VDD is greater than one MOS threshold
(about 0.7 volts). When these voltages differ by more than 0.7 volts, the internal RAM and part of
the reset logic are powered from VSTBY rather than VDD. This allows RAM contents to be retained
without VDD power applied to the MCU. Reset must be driven low before VDD is removed and must
remain low until VDD has been restored to a valid level.
VDD

4.7k
VDD

4.8 V NiCd

VOUT

To MODB/VSTBY
pin of M68HC11

MAX 690
(+)
VBATT

Figure 2-7 RAM stand-by connections

2.9

VRH and VRL

These pins provide the reference voltages for the analog-to-digital converter.

2.10

PG7/R/W

This pin provides two separate functions, depending on the operating mode. In single chip and
bootstrap modes, PG7/R/W acts as input/output port G bit 7. Refer to Section 6 for further information.
In expanded and test modes, PG7/R/W performs the read/write function. PG7/R/W signals the
direction of transfers on the external data bus. A high on this pin indicates that a read cycle is in
progress.

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PIN DESCRIPTIONS

MOTOROLA
2-13

2.11

Port signals

The MC68HC11PA8/MC68HC11PB8 includes 45 pins that are arranged into five 8-bit ports (A, B,
C, E and F), one 6-bit port (D) and one 1-bit port (G).
Ports A, B, C, D, F and G are fully bidirectional; port E pins are input only, except for port E[7, 6]
which may be used as I/O lines for the I2C bus system. Each of the bidirectional ports serves a
purpose other than I/O, depending on the operating mode or peripheral function selected. Note
that ports B, C, F, and G are available for I/O functions only in single chip and bootstrap modes.
Refer to Table 2-2 for details of the port signals functions in different operating modes.

Note:

When using the information about port functions, do not confuse pin function with the
electrical state of the pin at reset. All general purpose I/O pins configured as inputs at
reset are in a high-impedance state. Port data registers reflect the functional state of
the port at reset. The pin function is mode dependent.

2.11.1

Port A

Port A is an 8-bit general purpose I/O port with a data register (PORTA) and a data direction
register (DDRA). Port A pins share functions with the 16-bit timer system (see Section 10 for
further information). PORTA can be read at any time and always returns the pin level. If written,
PORTA stores the data in internal latches. The pins are driven only if they are configured as
outputs. Writes to PORTA do not change the pin state when the pins are configured for timer
output compares.
Out of reset, port A pins [7:0] are general purpose high-impedance inputs. When the functions
associated with these pins are disabled, the bits in DDRA govern the I/O state of the associated
pin. For further information, refer to Section 6.

2.11.2

Port B

Port B is an 8-bit general purpose I/O port with a data register (PORTB) and a data direction
register (DDRB). In single chip mode, port B pins are general purpose I/O pins (PB[7:0]). In
expanded mode, port B pins act as the high-order address lines (A[15:8]) of the address bus.
PORTB can be read at any time and always returns the pin level. If PORTB is written, the data is
stored in internal latches. The pins are driven only if they are configured as outputs in single chip
or bootstrap mode. For further information, refer to Section 6.

Pins PE5 and PE4 are not present on 64-pin QFP MC68HC11PA8 packed devices. They are
present on 64-pin QFP MC68HC11PB8 devices and also on 68-pin CLCC packaged versions
of the MC68HC711PA8/MC68HC711PB8, which are available as samples only. Contact your
local Motorola Sales Office for more information.

TPG

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PIN DESCRIPTIONS

MC68HC11PA8

Table 2-2 Port signal functions

Port/bit
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB[7:0]
PC[7:0]
PD5
PD4
PD3
PD2
PD1
PD0
PE7
PE6
PE[5:0]
PF[7:0]
PG7

Single chip and

Expanded multiplexed
bootstrap mode
and special test mode
PA7/PAI and/or OC1
PA6/OC2 and/or OC1
PA5/OC3 and/or OC1
PA4/OC4 and/or OC1
PA3/OC5/IC4 and/or OC1
PA2/IC1
PA1/IC2
PA0/IC3
PB[7:0]
A[15:8]
PC[7:0]
D[7:0]
PD5/SS
PD4/SCK/SCL
PD3/MOSI/SDA
PD2/MISO
PD1/TXD
PD0/RXD
Input only/analog inputs/SCL
Input only/analog inputs/SDA
Input only/analog inputs
PF[7:0]
A[7:0]
PG7
R/W

Port B pins include on-chip pull-up devices which can be enabled or disabled via the port pull-up
assignment register (PPAR).

2.11.3

Port C

Port C is an 8-bit general purpose I/O port with a data register (PORTC) and a data direction
register (DDRC). In single chip mode, port C pins are general purpose I/O pins (PC[7:0]). In the
expanded mode, port C pins are configured as data bus pins (D[7:0]).
PORTC can be read at any time; inputs return the pin level and outputs return the pin driver input
level. If PORTC is written, the data is stored in internal latches. The pins are driven only if they are
configured as outputs in single chip or bootstrap mode. Port C pins are general purpose inputs out
of reset in single chip and bootstrap modes. In expanded and test modes, these pins are data bus
lines out of reset.
The CWOM control bit in the OPT2 register disables port Cs p-channel output drivers. Because
the n-channel driver is not affected by CWOM, setting CWOM causes port C to become an
open-drain-type output port suitable for wired-OR operation. In wired-OR mode (PORTC bits at
logic level zero), the pins are actively driven low by the n-channel driver. When a port C bit is at

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PIN DESCRIPTIONS

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2-15

logic level one, the associated pin is in a high impedance state as neither the n-channel nor the
p-channel devices are active. It is customary to have an external pull-up resistor on lines that are
driven by open-drain devices. Port C can only be configured for wired-OR operation when the
MCU is in single chip mode. For further information, refer to Section 6.

2.11.4

Port D

Port D, a 6-bit general purpose I/O port, has a data register (PORTD) and a data direction register
(DDRD). The six port D lines (D[5:0]) can be used for general purpose I/O, for the serial
communications interface (SCI, pins [1,0]) and for either the serial peripheral interface (SPI, pins
[5:2]) or the I2C bus system (pins [4, 3]).
PORTD can be read at any time; inputs return the pin level and outputs return the pin driver input
level. If PORTD is written, the data is stored in internal latches. The pins are driven only if port D
is configured for general purpose output.
The DWOM bit in SPCR disables the p-channel output drivers of pins D[5:2], and the WOMS bit
in SCCR1 disables those of pins D[1,0]. Because the n-channel driver is not affected by DWOM
or WOMS, setting either bit causes the corresponding port D pins to become open-drain-type
outputs suitable for wired-OR operation. In wired-OR mode (PORTD bits at logic level zero), the
pins are actively driven low by the n-channel driver. When a port D bit is at logic level one, the
associated pin is in a high impedance state as neither the n-channel nor the p-channel devices
are active. It is customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port D can be configured for wired-OR operation when the MCU is in single chip or
expanded mode.
For further information, refer to Section 6, Section 7 (SCI), Section 8 (I2C) and Section 9 (SPI).

2.11.5

Port E

Port E pins can be used as the analog inputs for the analog-to-digital converter, or as
general-purpose inputs. Pins PE[7, 6] may alternatively be used as the I/O pins for the I2C bus,
depending on the state of the MBSP bit in the CONFIG register.
For further information, refer to Section 6, Section 8 (I2C bus) and Section 11 (A/D).

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PIN DESCRIPTIONS

MC68HC11PA8

2.11.6

Port F

Port F is an 8-bit general purpose I/O port with a data register (PORTF) and a data direction
register (DDRF). In single chip mode, port F pins are general purpose I/O pins (PF[7:0]). In
expanded mode, port F pins act as the low-order address lines (A[7:0]) of the address bus.

PORTF can be read at any time and always returns the pin level. If PORTF is written, the data is
stored in internal latches. The pins are driven only if they are configured as outputs in single chip
or bootstrap mode.
Port F pins include on-chip pull-up devices that can be enabled or disabled via the port pull-up
assignment register (PPAR). For further information, refer to Section 6.

2.11.7

Port G

In single-chip and bootstrap modes, Port G is a 1-bit general purpose I/O port with a data register
(PORTG) and a data direction register (DDRG). In expanded mode, PG7 is the R/W signal.
PORTG can be read at any time in single-chip and bootstrap modes; when an input, it returns the
pin level, and when an output, it returns the pin driver input level. If PORTG is written, the data is
stored into an internal latch. The pin is driven only if it is configured as an output.
PG7 includes an on-chip pull-up device that can be enabled or disabled via the port pull-up
assignment register (PPAR). For further information, refer to Section 6.

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PIN DESCRIPTIONS

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THIS PAGE LEFT BLANK INTENTIONALLY

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PIN DESCRIPTIONS

MC68HC11PA8

3
CPU CORE AND INSTRUCTION SET
This section discusses the M68HC11 central processing unit (CPU) architecture, its addressing
modes and the instruction set. For more detailed information on the instruction set, refer to the
M68HC11 Reference Manual (M68HC11RM/AD).
The CPU is designed to treat all peripheral, I/O and memory locations identically, as addresses in
the 64Kbyte memory map. This is referred to as memory-mapped I/O. There are no special
instructions for I/O that are separate from those used for memory. This architecture also allows
accessing an operand from an external memory location with no execution-time penalty.

3.1

Registers

M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were
memory locations. The seven registers are shown in Figure 3-1 and are discussed in the following
paragraphs.

7
15

Accumulator A
0 7
Accumulator B
Double accumulator D

0
0

A:B
D

Index register X

Index register Y

Stack pointer

Program counter

Condition code register

S X H

N Z V C

CCR
Carry
Overflow
Zero
Negative
I Interrupt mask
Half carry (from bit 3)
X Interrupt mask
Stop disable

Figure 3-1 Programming model

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MOTOROLA
3-1

3.1.1

Accumulators A, B and D

Accumulators A and B are general purpose 8-bit registers that hold operands and results of
arithmetic calculations or data manipulations. For some instructions, these two accumulators are
treated as a single double-byte (16-bit) accumulator called accumulator D. Although most
operations can use accumulators A or B interchangeably, the following exceptions apply:

The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents of 16-bit
register X or Y, but there are no equivalent instructions that use A instead of B.

The TAP and TPA instructions transfer data from accumulator A to the condition code register,
or from the condition code register to accumulator A, however, there are no equivalent
instructions that use B rather than A.

The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD)
arithmetic operations, but there is no equivalent BCD instruction to adjust accumulator B.

The add, subtract, and compare instructions associated with both A and B (ABA, SBA, and
CBA) only operate in one direction, making it important to plan ahead to ensure the correct
operand is in the correct accumulator.

3.1.2

Index register X (IX)

The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in
an instruction to create an effective address. The IX register can also be used as a counter or as
a temporary storage register.

3.1.3

Index register Y (IY)

The 16-bit IY register performs an indexed mode function similar to that of the IX register.
However, most instructions using the IY register require an extra byte of machine code and an
extra cycle of execution time because of the way the opcode map is implemented. Refer to
Section 3.3 for further information.

3.1.4

Stack pointer (SP)

The M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the
address space and can be any size up to the amount of memory available in the system. Normally
the SP is initialized by one of the first instructions in an application program. The stack is
configured as a data structure that grows downward from high memory to low memory. Each time
a new byte is pushed onto the stack, the SP is decremented. Each time a byte is pulled from the
stack, the SP is incremented. At any given time, the SP holds the 16-bit address of the next free
location in the stack. Figure 3-2 is a summary of SP operations.

TPG

MOTOROLA
3-2

CPU CORE AND INSTRUCTION SET

MC68HC11PA8

JSR, Jump to subroutine

Main program
PC
DIRECT
RTN

BSR, Branch to subroutine

Stack

Main program
PC

$9D = JSR
dd
Next instruction

$8D = BSR
rr
Next instruction

RTN

SP2
SP1
SP

RTNH
RTNL

Main program
PC
IND, X
RTN

$AD = JSR
ff
Next instruction

Main program
PC
IND, Y
RTN

$18 = PRE
$AD = JSR
ff
Next instruction

SWI, Software interrupt

Main program

Stack
SP2
SP1
SP

RTNH
RTNL

PC
RTN

$3F = SWI

WAI, Wait for interrupt

Main program

Main program
PC
EXTEND
RTN

PC
RTN

$BD = JSR
hh
ll
Next instruction

$3E = WAI

Stack
SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP

Condition Code
Accumulator B
Accumulator A
Index register (IXH)
Index register (IXL)
Index register (IYH)
Index register (IYL)
RTNH
RTNL

RTI, Return from interrupt

Interrupt program
PC

$3B = RTI

RTS, Return from subroutine

Main program
PC

$39 = RTS

Stack
SP
SP+1
SP+2

RTNH
RTNL

Stack
SP
SP+1
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9

Condition Code
Accumulator B
Accumulator A
Index register (IXH)
Index register (IXL)
Index register (IYH)
Index register (IYL)
RTNH
RTNL

LEGEND
RTN Address of the next instruction in the main program, to be executed on return from subroutine
RTNH More significant byte of return address
RTNL Less significant byte of return address
Shaded cells show stack pointer position after the operation is complete
dd 8-bit direct address ($0000$00FF); the high byte is assumed to be $00
ff 8-bit positive offset ($00 to $FF (0 to 256)) is added to the index register contents
hh High order byte of 16-bit extended address
ll Low order byte of 16-bit extended address
rr Signed relative offset ($80 to $7F (128 to +127)); offset is relative to the address following the offset byte

Figure 3-2 Stacking operations

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CPU CORE AND INSTRUCTION SET

MOTOROLA
3-3

When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine (BSR)

instruction, the address of the instruction after the JSR or BSR is automatically pushed onto the
stack, less significant byte first. When the subroutine is finished, a return from subroutine (RTS)
instruction is executed. The RTS pulls the previously stacked return address from the stack, and
loads it into the program counter. Execution then continues at this recovered return address.
When an interrupt is recognized, the current instruction finishes normally, the return address (the
current value in the program counter) is pushed onto the stack, all of the CPU registers are pushed
onto the stack, and execution continues at the address specified by the vector for the interrupt. At
the end of the interrupt service routine, an RTI instruction is executed. The RTI instruction causes
the saved registers to be pulled off the stack in reverse order. Program execution resumes at the
return address.
There are instructions that push and pull the A and B accumulators and the X and Y index
registers. These instructions are often used to preserve program context. For example, pushing
accumulator A onto the stack when entering a subroutine that uses accumulator A, and then
pulling accumulator A off the stack just before leaving the subroutine, ensures that the contents of
a register will be the same after returning from the subroutine as it was before starting the
subroutine.

3.1.5

Program counter (PC)

The program counter, a 16-bit register, contains the address of the next instruction to be executed.
After reset, the program counter is initialized from one of six possible vectors, depending on
operating mode and the cause of reset.

Table 3-1 Reset vector comparison

Normal
Test or Boot

3.1.6

POR or RESET pin

$FFFE, $FFFF
$BFFE, $BFFF

Clock monitor
$FFFC, $FFFD
$BFFE, $BFFF

COP watchdog
$FFFA, $FFFB
$BFFE, $BFFF

Condition code register (CCR)

This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two interrupt masking
bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU, condition codes are
automatically updated by most instructions. For example, load accumulator A (LDAA) and store
accumulator A (STAA) instructions automatically set or clear the N, Z, and V condition code flags.
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange instructions do not affect
the condition codes. Refer to Table 3-2, which shows the condition codes that are affected by a
particular instruction.

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CPU CORE AND INSTRUCTION SET

MC68HC11PA8

3.1.6.1

Carry/borrow (C)

The C-bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic
operation. The C-bit also acts as an error flag for multiply and divide operations. Shift and rotate
instructions operate with and through the carry bit to facilitate multiple-word shift operations.

3.1.6.2

Overflow (V)

The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V-bit is cleared.

3.1.6.3

Zero (Z)

The Z-bit is set if the result of an arithmetic, logic, or data manipulation operation is zero.
Otherwise, the Z-bit is cleared. Compare instructions do an internal implied subtraction and the
condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX,
INY, and DEY) affect the Z-bit and no other condition flags. For these operations, only = and
conditions can be determined.

3.1.6.4

Negative (N)

The N-bit is set if the result of an arithmetic, logic, or data manipulation operation is negative;
otherwise, the N-bit is cleared. A result is said to be negative if its most significant bit (MSB) is set
(MSB = 1). A quick way to test whether the contents of a memory location has the MSB set is to
load it into an accumulator and then check the status of the N-bit.

3.1.6.5

Interrupt mask (I)

The interrupt request (IRQ) mask (I-bit) is a global mask that disables all maskable interrupt
sources. While the I-bit is set, interrupts can become pending, but the operation of the CPU
continues uninterrupted until the I-bit is cleared. After any reset, the I-bit is set by default and can
only be cleared by a software instruction. When an interrupt is recognized, the I-bit is set after the
registers are stacked, but before the interrupt vector is fetched. After the interrupt has been
serviced, a return from interrupt instruction is normally executed, restoring the registers to the
values that were present before the interrupt occurred. Normally, the I-bit is zero after a return from
interrupt is executed. Although the I-bit can be cleared within an interrupt service routine, nesting
interrupts in this way should only be done when there is a clear understanding of latency and of
the arbitration mechanism. Refer to Section 5.

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CPU CORE AND INSTRUCTION SET

MOTOROLA
3-5

3.1.6.6

Half carry (H)

The H-bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an
ADD, ABA, or ADC instruction. Otherwise, the H-bit is cleared. Half carry is used during BCD
operations.

3.1.6.7

X interrupt mask (X)

The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set by default
and must be cleared by a software instruction. When an XIRQ interrupt is recognized, the X- and
I-bits are set after the registers are stacked, but before the interrupt vector is fetched. After the
interrupt has been serviced, an RTI instruction is normally executed, causing the registers to be
restored to the values that were present before the interrupt occurred. The X interrupt mask bit is
set only by hardware RESET or XIRQ acknowledge). X is cleared only by program instruction
(TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value loaded into the CCR from
the stack has been cleared). There is no hardware action for clearing X.

3.1.6.8

Stop disable (S)

Setting the STOP disable (S) bit prevents the STOP instruction from putting the M68HC11 into a
low-power stop condition. If the STOP instruction is encountered by the CPU while the S-bit is set,
it is treated as a no-operation (NOP) instruction, and processing continues to the next instruction.
S is set by reset STOP disabled by default.

3.2

Data types

The M68HC11 CPU supports the following data types:

Bit data

8-bit and 16-bit signed and unsigned integers

16-bit unsigned fractions

16-bit addresses

A byte is eight bits wide and can be accessed at any byte location. A word is composed of two
consecutive bytes with the most significant byte at the lower value address. Because the
M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or
operands.

TPG

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CPU CORE AND INSTRUCTION SET

MC68HC11PA8

3.3

Opcodes and operands

The M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular
instruction and associated addressing mode to the CPU. Several opcodes are required to provide
each instruction with a range of addressing capabilities. Only 256 opcodes would be available if
the range of values were restricted to the number able to be expressed in 8-bit binary numbers.

A four-page opcode map has been implemented to expand the number of instructions. An
additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of
the other three pages. As its name implies, the additional byte precedes the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three
operands. The operands contain information the CPU needs for executing the instruction.
Complete instructions can be from one to five bytes long.

3.4

Addressing modes

Six addressing modes; immediate, direct, extended, indexed, inherent, and relative, detailed in the
following paragraphs, can be used to access memory. All modes except inherent mode use an
effective address. The effective address is the memory address from which the argument is
fetched or stored, or the address from which execution is to proceed. The effective address can
be specified within an instruction, or it can be calculated.

3.5

Immediate (IMM)

In the immediate addressing mode an argument is contained in the byte(s) immediately following
the opcode. The number of bytes following the opcode matches the size of the register or memory
location being operated on. There are two, three, and four (if prebyte is required) byte immediate
instructions. The effective address is the address of the byte following the instruction.

3.5.1

Direct (DIR)

In the direct addressing mode, the low-order byte of the operand address is contained in a single
byte following the opcode, and the high-order byte of the address is assumed to be $00.
Addresses $00$FF are thus accessed directly, using two-byte instructions. Execution time is
reduced by eliminating the additional memory access required for the high-order address byte. In
most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11
MCUs, the memory map can be configured for combinations of internal registers, RAM, or
external memory to occupy these addresses.

TPG

MC68HC11PA8

CPU CORE AND INSTRUCTION SET

MOTOROLA
3-7

3.5.2

Extended (EXT)

In the extended addressing mode, the effective address of the argument is contained in two bytes
following the opcode byte. These are three-byte instructions (or four-byte instructions if a prebyte
is required). One or two bytes are needed for the opcode and two for the effective address.

3.5.3

Indexed (IND, X; IND, Y)

In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to
the value contained in an index register (IX or IY) the sum is the effective address. This
addressing mode allows referencing any memory location in the 64Kbyte address space. These
are two- to five-byte instructions, depending on whether or not a prebyte is required.

3.5.4

Inherent (INH)

In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations that use only the index registers or accumulators, as well as
control instructions with no arguments, are included in this addressing mode. These are one or
two-byte instructions.

3.5.5

Relative (REL)

The relative addressing mode is used only for branch instructions. If the branch condition is true,
an 8-bit signed offset included in the instruction is added to the contents of the program counter
to form the effective branch address. Otherwise, control proceeds to the next instruction. These
are usually two-byte instructions.

3.6

Instruction set

Refer to Table 3-2, which shows all the M68HC11 instructions in all possible addressing modes.
For each instruction, the table shows the operand construction, the number of machine code
bytes, and execution time in CPU E clock cycles.

TPG

MOTOROLA
3-8

CPU CORE AND INSTRUCTION SET

MC68HC11PA8

Table 3-2 Instruction set (Page 1 of 6)

Addressing
mode

Mnemonic

Operation

Description

ABA

Add accumulators

A+BA

INH

ABX

Add B to X

IX + (00:B) IX

ABY

Add B to Y

IY + (00:B) IY

ADCA (opr)

Add with carry to A

A+M+CA

ADCB (opr)

Add with carry to B

ADDA (opr)

Instruction
Opcode

Operand

Condition codes
Cycles

S X H

N Z V C

INH

18 3A

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

89
99
B9
A9
18 A9

ii
dd
hh ll
ff
ff

2
3
4
4
5

B+M+CB

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

C9
D9
F9
E9
18 E9

ii
dd
hh ll
ff
ff

2
3
4
4
5

Add memory to A

A+MA

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

8B
9B
BB
AB
18 AB

ii
dd
hh ll
ff
ff

2
3
4
4
5

ADDB (opr)

Add memory to B

B+MB

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

CB
DB
FB
EB
18 EB

ii
dd
hh ll
ff
ff

2
3
4
4
5

ADDD (opr)

Add 16-bit to D

D + (M:M+1) D

IMM
DIR
EXT
IND, X
IND, Y

C3
D3
F3
E3
18 E3

jj kk
dd
hh ll
ff
ff

4
5
6
6
7

ANDA (opr)

AND A with memory

AMA

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

84
94
B4
A4
18 A4

ii
dd
hh ll
ff
ff

2
3
4
4
5

ANDB (opr)

AND B with memory

BMB

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

C4
D4
F4
E4
18 E4

ii
dd
hh ll
ff
ff

2
3
4
4
5

ASL (opr)

Arithmetic shift left

EXT
IND, X
IND, Y

78
68
18 68

hh ll
ff
ff

6
6
7

ASLA

Arithmetic shift left A

ASLB

Arithmetic shift left B

ASLD

Arithmetic shift left D

INH

hh ll
ff
ff

6
6
7

C
b15

ASR

Arithmetic shift right

ASRA

Arithmetic shift right A

ASRB

Arithmetic shift right B

BCC (rel)

Branch if carry clear

C=0?

BCLR (opr)
(msk)

Clear bit(s)

M (mm) M

EXT
IND, X
IND, Y

C
b7

77
67
18 67

INH

REL

dd mm
ff mm
ff mm

6
7
8

DIR
IND, X
IND, Y

15
1D
18 1D

BCS (rel)

Branch if carry set

C=1?

REL

BEQ (rel)

Branch if equal to zero

Z=1?

REL

BGE (rel)

Branch if zero

NV=0?

REL

BGT (rel)

Branch if > zero

Z + (N V) = 0 ?

REL

BHI (rel)

Branch if higher

C+Z=0?

REL

TPG

MC68HC11PA8

CPU CORE AND INSTRUCTION SET

MOTOROLA
3-9

Table 3-2 Instruction set (Page 2 of 6)

Addressing
mode

Mnemonic

Operation

Description

BHS (rel)

Branch if higher or same

C=0?

BITA (opr)

Bit(s) test A with memory

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

BITB (opr)

Bit(s) test B with memory

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

REL

Instruction
Opcode
24

Operand

Condition codes
Cycles

S X H

N Z V C

85
95
B5
A5
18 A5

ii
dd
hh ll
ff
ff

2
3
4
4
5

C5
D5
F5
E5
18 E5

ii
dd
hh ll
ff
ff

2
3
4
4
5

BLE (rel)

Branch if zero

Z + (N V) = 1 ?

REL

BLO (rel)

Branch if lower

C=1?

REL

BLS (rel)

Branch if lower or same

C+Z=1?

REL

BLT (rel)

Branch if < zero

NV=1?

REL

BMI (rel)

Branch if minus

N=1?

REL

BNE (rel)

Branch if zero

Z=0?

REL

BPL(rel)

Branch if plus

N=0?

REL

BRA (rel)

Branch always

1=1?

BRCLR(opr)
(msk)
(rel)

Branch if bit(s) clear

M mm = 0 ?

DIR
IND, X
IND, Y
REL

20
13
1F
18 1F
21

rr
dd mm rr
ff mm rr
ff mm rr

BRN (rel)

Branch never

1=0?

BRSET(opr)
(msk)
(rel)

Branch if bit(s) set

M mm = 0 ?

DIR
IND, X
IND, Y

12
1E
18 1E

dd mm rr
ff mm rr
ff mm rr

6
7
8

BSET (opr)
(msk)

Set bit(s)

M + mm M

DIR
IND, X
IND, Y

14
1C
18 1C

dd mm
ff mm
ff mm

INH

CLR (opr)

Clear memory byte

DIR
IND, X
IND, Y

hh ll
ff
ff

6
6
7

0 1 0 0

7F
6F
18 6F

3
6
7
8

CLRA

Clear accumulator A

INH

0 1 0 0

CLRB

Clear accumulator B

INH

0 1 0 0

CLV

Clear overflow flag

CMPA (opr)

Compare A with memory

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

81
91
B1
A1
18 A1

ii
dd
hh ll
ff
ff

2
3
4
4
5

CMPB (opr)

Compare B with memory

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

C1
D1
F1
E1
18 E1

ii
dd
hh ll
ff
ff

2
3
4
4
5

COM (opr)

Ones complement memory byte

$FF M M

EXT
IND, X
IND, Y

73
63
18 63

hh ll
ff
ff

6
6
7

0 1

INH

COMA

Ones complement A

$FF A A

INH

0 1

COMB

Ones complement B

$FF B B

INH

0 1

TPG

MOTOROLA
3-10

CPU CORE AND INSTRUCTION SET

MC68HC11PA8

Table 3-2 Instruction set (Page 3 of 6)

Mnemonic

Operation

Description

CPD (opr)

Compare D with memory (16-bit)

D (M:M+1)

Addressing
mode

Instruction

Condition codes

Opcode

Operand

Cycles

S X H

IMM
DIR
EXT
IND, X
IND, Y

1A
1A
1A
1A
CD

83
93
B3
A3
A3

jj kk
dd
hh ll
ff
ff

5
6
7
7
7

N Z V C

CPX (opr)

Compare IX with memory (16-bit)

IX (M:M+1)

IMM
DIR
EXT
IND, X
IND, Y

8C
9C
BC
AC
CD AC

jj kk
dd
hh ll
ff
ff

4
5
6
6
7

CPY (opr)

Compare IY with memory (16-bit)

IY (M:M+1)

IMM
DIR
EXT
IND, X
IND, Y

18
18
18
1A
18

jj kk
dd
hh ll
ff
ff

5
6
7
7
7

DAA

Decimal adjust A

adjust sum to BCD

DEC (opr)

Decrement memory byte

M1M

INH
EXT
IND, X
IND, Y

8C
9C
BC
AC
AC
19

7A
6A
18 6A

hh ll
ff
ff

6
6
7

DECA

Decrement accumulator A

A1A

INH

DECB

Decrement accumulator B

B1B

INH

DES

Decrement stack pointer

SP 1 SP

INH

DEX

Decrement index register X

IX 1 IX

INH

DEY

Decrement index register Y

IY 1 IY

INH

18 09

EORA (opr)

Exclusive OR A with memory

AMA

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

88
98
B8
A8
18 A8

ii
dd
hh ll
ff
ff

2
3
4
4
5

EORB (opr)

Exclusive OR B with memory

BMA

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

C8
D8
F8
E8
18 E8

ii
dd
hh ll
ff
ff

2
3
4
4
5

FDIV

Fractional divide, 16 by 16

D / IX IX; r D

INH

IDIV

Integer divide, 16 by 16

D / IX IX; r D

INH

INC (opr)

Increment memory byte

M+1M

hh ll
ff
ff

6
6
7

INCA

Increment accumulator A

A+1A

INH

INCB

Increment accumulator B

B+1B

INH

INS

Increment stack pointer

SP + 1 SP

INH

EXT
IND, X
IND, Y

7C
6C
18 6C

INX

Increment index register X

IX + 1 IX

INH

INY

Increment index register Y

IY + 1 IY

INH

18 08

JMP (opr)

Jump

see Figure 3-2

EXT
IND, X
IND, Y

7E
6E
18 6E

hh ll
ff
ff

3
3
4

JSR (opr)

Jump to subroutine

see Figure 3-2

DIR
EXT
IND, X
IND, Y

9D
BD
AD
18 AD

dd
hh ll
ff
ff

5
6
6
7

LDAA (opr)

Load accumulator A

IMM
DIR
EXT
IND, X
IND, Y

86
96
B6
A6
18 A6

ii
dd
hh ll
ff
ff

2
3
4
4
5

A
A
A
A
A

TPG

MC68HC11PA8

CPU CORE AND INSTRUCTION SET

MOTOROLA
3-11

Table 3-2 Instruction set (Page 4 of 6)

Instruction

Condition codes

Addressing
mode

Opcode

Operand

IMM
DIR
EXT
IND, X
IND, Y

C6
D6
F6
E6
18 E6

ii
dd
hh ll
ff
ff

2
3
4
4
5

M A; M+1 B

IMM
DIR
EXT
IND, X
IND, Y

CC
DC
FC
EC
18 EC

jj kk
dd
hh ll
ff
ff

3
4
5
5
6

Load stack pointer

M:M+1 SP

IMM
DIR
EXT
IND, X
IND, Y

8E
9E
BE
AE
18 AE

jj kk
dd
hh ll
ff
ff

3
4
5
5
6

LDX (opr)

Load index register X

M:M+1 IX

IMM
DIR
EXT
IND, X
IND, Y

CE
DE
FE
EE
CD EE

jj kk
dd
hh ll
ff
ff

3
4
5
5
6

LDY (opr)

Load index register Y

M:M+1 IY

IMM
DIR
EXT
IND, X
IND, Y

18
18
18
1A
18

jj kk
dd
hh ll
ff
ff

4
5
6
6
6

LSL (opr)

Logical shift left

EXT
IND, X
IND, Y

78
68
18 68

hh ll
ff
ff

6
6
7

LSLA

Logical shift left A

LSLB

Logical shift Left B

LSLD

Logical shift left D

LSR (opr)

Logical shift right

Mnemonic

Operation

Description

LDAB (opr)

Load accumulator B

LDD (opr)

Load double accumulator D

LDS (opr)

B
B
B
B
B

C
b7

C
b15

CE
DE
FE
EE
EE

Cycles

S X H

N Z V C

INH

EXT
IND, X
IND, Y

hh ll
ff
ff

6
6
7

0
b7

LSRA

Logical shift right A

LSRB

Logical shift right B

LSRD

Logical shift right D

MUL

Multiply, 8 x 8

A*BD

INH

NEG (opr)

Twos complement memory byte

0MM

EXT
IND, X
IND, Y

INH

hh ll
ff
ff

6
6
7

C
b15

74
64
18 64

3D
70
60
18 60

NEGA

Twos complement A

0AA

INH

NEGB

Twos complement B

0BB

INH

NOP

No operation

no operation

ORAA

OR accumulator A (inclusive)

A+MA

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

INH

8A
9A
BA
AA
18 AA

ii
dd
hh ll
ff
ff

2
3
4
4
5

ORAB

OR accumulator B (inclusive)

B+MB

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

CA
DA
FA
EA
18 EA

ii
dd
hh ll
ff
ff

2
3
4
4
5

PSHA

Push A onto stack

A Stack; SP = SP1

INH

PSHB

Push B onto stack

B Stack; SP = SP1

INH

PSHX

Push IX onto stack (low first)

IX Stack; SP = SP2

INH

PSHY

Push IY onto stack (low first)

IY Stack; SP = SP2

INH

18 3C

TPG

MOTOROLA
3-12

CPU CORE AND INSTRUCTION SET

MC68HC11PA8

Table 3-2 Instruction set (Page 5 of 6)

Addressing
mode

Instruction

Condition codes

Mnemonic

Operation

Description

PULA

Pull A from stack

SP = SP+1; Stack A

INH

Opcode

Operand

Cycles

S X H

N Z V C

PULB

Pull B from stack

SP = SP+1; Stack B

INH

PULX

Pull IX from stack (high first)

SP = SP+2; Stack IX

INH

PULY

Pull IY from stack (high first)

SP = SP+2; Stack IY

INH

18 38

ROL (opr)

Rotate left

EXT
IND, X
IND, Y

79
69
18 69

hh ll
ff
ff

6
6
7

ROLA

Rotate left A

ROLB

Rotate left B

ROR (opr)

Rotate right

RORA

Rotate right A

RORB

Rotate right B

RTI

Return from interrupt

RTS

Return from subroutine

INH

IMM
DIR
EXT
IND, X
IND, Y

C2
D2
F2
E2
18 E2

ii
dd
hh ll
ff
ff

2
3
4
4
5

SEC

Set carry

INH

SEI

Set interrupt mask

INH

SEV

Set overflow flag

INH

STAA (opr)

Store accumulator A

A
A
A
A

DIR
EXT
IND, X
IND, Y

97
B7
A7
18 A7

dd
hh ll
ff
ff

3
4
4
5

STAB (opr)

Store accumulator B

B
B
B
B

DIR
EXT
IND, X
IND, Y

D7
F7
E7
18 E7

dd
hh ll
ff
ff

3
4
4
5

STD (opr)

Store accumulator D

A M; B M+1

DIR
EXT
IND, X
IND, Y

DD
FD
ED
18 ED

dd
hh ll
ff
ff

4
5
5
6

INH

STOP

Stop internal clocks

STS (opr)

Store stack pointer

SP M:M+1

DIR
EXT
IND, X
IND, Y

INH

9F
BF
AF
18 AF

dd
hh ll
ff
ff

4
5
5
6

STX (opr)

Store index register X

IX M:M+1

DIR
EXT
IND, X
IND, Y

DF
FF
EF
CD EF

dd
hh ll
ff
ff

4
5
5
6

STY (opr)

Store index register Y

IY M:M+1

DIR
EXT
IND, X
IND, Y

18
18
1A
18

dd
hh ll
ff
ff

5
6
6
6

DF
FF
EF
EF

TPG

MC68HC11PA8

CPU CORE AND INSTRUCTION SET

MOTOROLA
3-13

Table 3-2 Instruction set (Page 6 of 6)

Instruction

Condition codes

Addressing
mode

Opcode

Operand

A
A
A
A
A

IMM
DIR
EXT
IND, X
IND, Y

80
90
B0
A0
18 A0

ii
dd
hh ll
ff
ff

2
3
4
4
5

B
B
B
B
B

IMM
DIR
EXT
IND, X
IND, Y

C0
D0
F0
E0
18 E0

ii
dd
hh ll
ff
ff

2
3
4
4
5

IMM
DIR
EXT
IND, X
IND, Y

83
93
B3
A3
18 A3

jj kk
dd
hh ll
ff
ff

4
5
6
6
7

INH

Mnemonic

Operation

Description

SUBA (opr)

Subtract memory from A

AMA

SUBB (opr)

Subtract memory from B

BMB

SUBD (opr)

Subtract memory from D

D M:M+1 D

SWI

Software interrupt

see Figure 3-2

INH

TAB

Transfer A to B

INH

TAP

Transfer A to CC register

A CCR

TBA

Transfer B to A

TEST

Test (only in test modes)

address bus increments

INH

TPA

Transfer CC register to A

CCR A

INH

TST (opr)

Test for zero or minus

hh ll
ff
ff

6
6
7

0 0

EXT
IND, X
IND, Y

7D
6D
18 6D

Cycles

S X H

N Z V C

TSTA

SP + 1 IY

INH

18 30

TXS

INH

XGDY

Exchange D with Y

IY D; D IY

INH

18 8F

Operators
Is transferred to
Boolean AND
+ Arithmetic addition, except where used as an
inclusive-OR symbol in Boolean formulae
Exclusive-OR
* Multiply
: Concatenation
Arithmetic subtraction, or negation symbol
(Twos complement)

Operands
dd 8-bit direct address ($0000$00FF); the high byte is assumed
to be zero
ff 8-bit positive offset ($00 to $FF (0 to 256)) is added to the
contents of the index register
hh High order byte of 16-bit extended address
ii One byte of immediate data
jj High order byte of 16-bit immediate data
kk Low order byte of 16-bit immediate data
ll Low order byte of 16-bit extended address
mm 8-bit mask (set bits to be affected)
rr Signed relative offset ($80 to $7F (128 to +127));
offset is relative to the address following the offset byte

Cycles

Condition Codes
Bit not changed
0 Bit always cleared
1 Bit always set
Bit set or cleared, depending on the operation
Bit can be cleared, but cannot become set
? Not defined

Infinite, or until reset occurs

12 cycles are used, beginning with the opcode
fetch. A wait state is entered, which remains
in effect for an integer number of MPU E clock
cycles (n) until an interrupt is recognised.
Finally, two additional cycles are used to fetch
the appropriate interrupt vector. (14 + n, total).

TPG

MOTOROLA
3-14

CPU CORE AND INSTRUCTION SET

MC68HC11PA8

4
OPERATING MODES AND ON-CHIP MEMORY

This section contains information about the modes that define MC68HC11PA8/MC68HC11PB8
operating conditions, and about the on-chip memory that allows the MCU to be configured for various
applications.

4.1

Operating modes

The values of the mode select inputs MODB and MODA during reset determine the operating
mode (See Table 4-4). Single chip and expanded modes are the normal modes. In single chip
mode only on-board memory is available. Expanded mode, however, allows access to external
memory. Each of these two normal modes is paired with a special mode. Bootstrap, a variation of
the single chip mode, is a special mode that executes a bootloader program in an internal
bootstrap ROM. Test is a special mode that allows privileged access to internal resources.

4.1.1

Single chip operating mode

In single chip operating mode, the MC68HC11PA8/MC68HC11PB8 microcontroller has no

external address or data bus. Ports B, C, F, and the R/W pin are available for general purpose
parallel I/O.

4.1.2

Expanded operating mode

In expanded operating mode, the MCU can access a 64K byte physical address space. The
address space includes the same on-chip memory addresses used for single chip mode, in
addition to external memory and peripheral devices.
The expansion bus is made up of ports B, C, and F, and the R/W signal. In expanded mode, high
order address bits are output on the port B pins, low order address bits on the port F pins, and the
data bus on port C. The R/W/PG7 pin signals the direction of data transfer on the port C bus.

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-1

To allow access to slow peripherals, off chip accesses can be extended by one E clock cycle, under
control of the STRCH bit in the OPT2 register. The E clock stretches externally, but the internal clocks
are not affected so that timers and serial systems are not corrupted. See Section 4.3.2.5.
A security feature can protect EEPROM data when in expanded mode; see Section 4.4.4.

4.1.3

Special test mode

Special test, a variation of the expanded mode, is used during Motorolas internal production
testing, and is not intended or recommended for any other purpose. Its specification is subject to
change without notice.

4.1.4

Special bootstrap mode

When the MCU is reset in special bootstrap mode, a small on-chip ROM is enabled at address
$BE40$BFFF. The ROM contains a reset vector and a bootloader program. The MCU fetches the
reset vector, then executes the bootloader.
For normal use of the bootloader program, send a synchronization byte $FF to the SCI receiver
at either E clock 256, or E clock 1664 (7812 or 1200 baud respectively, for an E clock of 2MHz).
Then download up to 2048 bytes of program data (which is put into RAM starting at $0080). These
characters are echoed through the transmitter. The bootloader program ends the download after
a timeout of four character times or 2048 bytes. When loading is complete, the program jumps to
location $0080 and begins executing the code. Use of an external pull-up resistor is required when
using the SCI transmitter pin (TXD) because port D pins are configured for wired-OR operation by
the bootloader. In bootstrap mode, the interrupt vectors point to RAM. This allows the use of
interrupts through a jump table.
Further baud rate options are available on the MC68HC11PA8/MC68HC11PB8 by using a
different value for the synchronization byte, as shown in Table 4-1.
A special mode exists that allows a low frequency crystal to be used if the PLL is active. In this case,
the value on port F is loaded into the SYNR register just after reset, to be used as the multiplication
factor for the crystal frequency. If the PLL is not active, then the bootloader runs at the crystal
frequency. Refer to Section 2.5 for more information on the operation of the PLL circuitry.
Refer also to Motorola application note AN1060, M68HC11 Bootstrap Mode (the bootloader
mode is similar to that used on the MC68HC11K4).

TPG

MOTOROLA
4-2

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

Table 4-1 Example bootloader baud rates

Baud rates for an E clock of:
Sync. Timeout
byte
delay 2.00MHz 2.10MHz 3.00MHz 3.15MHz 4.00MHz
$FF
4 char.
7812
8192
11718
12288
15624
$FF
4
1200
1260
1800
1890
2400
$F0
4.9
9600
10080
14400
15120
19200
$FD
17.3
5208
5461
7812
8192
10416
$FD
13
3906
4096
5859
6144
7812

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-3

4.2

On-chip memory

The MC68HC11PA8/MC68HC11PB8 MCU includes 2K bytes of on-chip RAM, 48K bytes of

ROM/EPROM and 512 bytes of EEPROM. The bootloader ROM occupies a 512 byte block of the
memory map. The CONFIG register is implemented as a separate EEPROM byte.

Start
address
$0000
$0080
$0880

$0E00
$1000

$x87F

This block may be remapped

to any 4K page, using INIT2.

BootROM $BE40

Special bootstrap mode only.

$4000

$BFFF

Special modes only.

$4000

48K bytes ROM

(MC68HC11PA8/
MC68HC11PB8) or
48K bytes EPROM
(MC68HC711PA8/
MC68HC711PB8).

NVM
48K bytes

$C000

$FFBF

$FFC0
$FFFF

Vectors
Single
chip

Expanded

Special
bootstrap

using the INIT register.

EEPROM $xE00
512 bytes $xFFF

Vectors

$BE40

$x000 Each of these blocks

$x07F can be mapped to any

$x080 4K page boundary,

$FFFF

Can be mapped to either

$0000$BFFF or
$4000$FFFF,
using the CONFIG register.
Normal mode vectors.

Special
test

Figure 4-1 MC68HC11PA8/MC68HC11PB8/MC68HC711PA8/MC68HC711PB8

memory map

4.2.1

Mapping allocations

Memory locations for on-chip resources are the same for both expanded and single chip modes.
The 128-byte register block originates at $0000 on reset and can be placed at any other 4K
boundary ($x000) after reset by writing an appropriate value to the INIT register. Refer to
Figure 4-1, which shows the memory map.
The on-board 2K byte RAM is initially located at $0080 after reset. The RAM is divided into two
sections, of 128 bytes and 1920 bytes. If RAM and registers are both mapped to the same 4K
boundary, RAM starts at $x080 and 128 bytes are remapped at $x800$x87F. Otherwise, RAM
starts at $x000. See Figure 4-2.
Remapping is accomplished by writing appropriate values into the two nibbles of the INIT register.
See Section 4.3.2.2.

TPG

MOTOROLA
4-4

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

The 512-byte EEPROM is initially located at $0E00 after reset, when EEPROM is enabled in the
memory map by the CONFIG register. EEPROM can be placed in any other 4K page ($xE00) by
writing to the INIT2 register.
The ROMAD and ROMON bits in the CONFIG register control the position and presence of ROM,
or EPROM, in the memory map. In special test mode, the ROMON bit is cleared so the
ROM/EPROM is removed from the memory map. In single chip mode, the ROMAD bit is set to
one after reset, which enables the ROM/EPROM at $4000$FFFF. In expanded mode, the
ROM/EPROM may be enabled from $0000$BFFF (ROMAD = 0) to allow an external memory to
contain the interrupt vectors and initialization code.

In special bootstrap mode, a bootloader ROM is enabled at locations $BE40$BFFF. The vectors
for special bootstrap mode are contained in the bootloader program. The boot ROM occupies a
512 byte block of the memory map, though not all locations are used.

4.2.1.1

RAM

The MC68HC11PA8/MC68HC711PB8 has 2K bytes of fully static RAM that are used for storing
instructions, variables and temporary data during program execution. RAM can be placed at any
4K boundary in the 64K byte address space by writing an appropriate value to the INIT register.
By default, RAM is initially located at $0080 in the memory map. Direct addressing mode can
access the first 128 locations of RAM using a one-byte address operand. Direct mode accesses
save program memory space and execution time. Registers can be moved to other boundaries to
allow 256 bytes of RAM to be located in direct addressing space. See Figure 4-2.
The on-chip RAM is a fully static memory. RAM contents can be preserved during periods of
processor inactivity by either of two methods, both of which reduce power consumption:
1) During the software-based STOP mode, MCU clocks are stopped, but the
MCU continues to draw power from VDD. Power supply current is directly
related to operating frequency in CMOS integrated circuits and there is very
little leakage when the clocks are stopped. These two factors reduce power
consumption while the MCU is in STOP mode.
2) To reduce power consumption to a minimum, VDD can be turned off, and the
MODB/VSTBY pin can be used to supply RAM power from either a battery
back-up or a second power supply. Although this method requires external
hardware, it is very effective. Refer to Section 2 for information about how to
connect the stand-by RAM power supply and to Section 5 for a description
of low power operation.

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-5

4.2.1.2

ROM and EPROM

The MCU has 48K bytes of ROM/EPROM. The ROM/EPROM array is enabled when the ROMON
bit in the CONFIG register is set to one (erased). The ROMAD bit in CONFIG places the
ROM/EPROM at either $4000$FFFF (ROMAD = 1) or at $0000$BFFF (ROMAD = 0) when
coming out of reset in expanded mode.

4.2.1.3

Bootloader ROM

The bootloader ROM is enabled at address $BE40$BFFF during special bootstrap mode. The
reset vector is fetched from this ROM and the MCU executes the bootloader firmware. In normal
modes, the bootloader ROM is disabled.

4.2.2

Registers

In Table 4-2, a summary of registers and control bits, the registers are shown in ascending order
within the 128-byte register block. The addresses shown are for default block mapping
($0000$007F), however, the INIT register remaps the block to any 4K page ($x000$x07F). See
Section 4.3.2.2.

TPG

MOTOROLA
4-6

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

Table 4-2 Register and control bit assignments (Page 1 of 3)

Address bit 7
PA7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

PA6

PA5

PA4

PA3

PA2

PA1

PA0

undefined

Port A data (PORTA)

$0000

Data direction A (DDRA)

$0001

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

DDA0 0000 0000

Data direction B (DDRB)

$0002

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0 0000 0000

Data direction F (DDRF)

$0003

DDF7

DDF6

DDF5

DDF4

DDF3

DDF2

DDF1

DDF0 0000 0000

Port B data (PORTB)

$0004

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

undefined

Port F data (PORTF)

$0005

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

undefined

Port C data (PORTC)

$0006

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

undefined

Data direction C (DDRC)

$0007

Port D data (PORTD)

$0008

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000
0

PD5

PD4

PD3

PD2

PD1

PD0

undefined

Data direction D (DDRD)

$0009

Port E data (PORTE)

$000A

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

undefined

$000B

FOC1

FOC2

FOC3

FOC4

FOC5

0000 0000

Timer compare force (CFORC)

DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 0000 0000

Output compare 1 mask (OC1M)

$000C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3

Output compare 1 data (OC1D)

$000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3

(14)

(13)

(12)

(11)

(10)

(9)

Timer count (TCNT) high

$000E (bit 15)

Timer count (TCNT) low

$000F

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 0000 0000

Timer input capture 1 (TIC1) high

$0010

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8)

(bit 8) 0000 0000

undefined

Timer input capture 1 (TIC1) low

$0011

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

Timer input capture 2 (TIC2) high

$0012

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8)

undefined

Timer input capture 2 (TIC2) low

$0013

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

Timer input capture 3 (TIC3) high

$0014

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8)

undefined
undefined

Timer input capture 3 (TIC3) low

$0015

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

Timer output compare 1 (TOC1) high

$0016

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 1 (TOC1) low

$0017

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Timer output compare 2 (TOC2) high

$0018

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 2 (TOC2) low

$0019

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Timer output compare 3 (TOC3) high

$001A (bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 3 (TOC3) low

$001B

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Timer output compare 4 (TOC4) high

$001C (bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 4 (TOC4) low

$001D

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Capture 4/compare 5 (TI4/O5) high

$001E (bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Capture 4/compare 5 (TI4/O5) low

$001F

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Timer control 1 (TCTL1)

$0020

OM2

OL2

OM3

OL3

OM4

OL4

OM5

Timer control 2 (TCTL2)

$0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000

Timer interrupt mask 1 (TMSK1)

$0022

OC1I

OC2I

OC3I

OC4I

I4/O5I

IC1I

IC2I

OL5

IC3I

0000 0000

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-7

Table 4-2 Register and control bit assignments (Page 2 of 3)

Address bit 7

Timer interrupt flag 1 (TFLG1)

$0023

OC1F

bit 6

bit 5

bit 4

bit 3

OC2F

OC3F

OC4F I4/O5F

bit 2

bit 1

bit 0

State
on reset

IC1F

IC2F

IC3F

0000 0000

Timer interrupt mask 2 (TMSK2)

$0024

TOI

RTII

PAOVI

PAII

PR1

PR0

0000 0000

Timer interrupt flag 2 (TFLG2)

$0025

TOF

RTIF PAOVF

PAIF

0000 0000

Pulse accumulator control (PACTL)

$0026

I4/O5

RTR1

Pulse accumulator count (PACNT)

$0027

(bit 7)

(3)

(2)

(1)

SPI control (SPCR)

$0028

SPIE

SPE

SPI status (SPSR)

$0029

SPIF

WCOL

SPI data (SPDR)

$002A

(bit 7)

(6)

EPROM programming (EPROG)

$002B

MBE

Port pull-up assignment (PPAR)

$002C

Reserved

$002D
BCS

AUTO

BWC

VCOT

PLL control (PLLCR)

$002E PLLON

Synthesizer program (SYNR)

PAEN PAMOD PEDGE

(6)

(5)

(4)

DWOM MSTR CPOL CPHA SPR1

MODF

XPIN

(5)

(4)

(3)

(2)
0

ELAT EXCOL EXROW

RTR0 0000 0000

(bit 0)

undefined

SPR0 0000 01uu

IPIN

0000 00uu

(1)

(bit 0)

undefined

EPGM 0000 0000

GPPUE FPPUE BPPUE 0000 1111

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

$0035 BULKP

EE2

EE1

Block protect (BPROT)

SCAN MULT

PTCON BPRT3 BPRT2 BPRT1 BPRT0 1001 1111

Reserved

$0036

EEPROM mapping (INIT2)

$0037

System config. options 2 (OPT2)

$0038

LIRDV CWOM STRCH IRVNE LSBF

SPR2 EXT4X XIRQE 000x 0000

System config. options 1 (OPTION)

$0039

ADPU CSEL

CME

FCME

CR1

CR0

0001 0000

(3)

(2)

(1)

(bit 0)

undefined

EE3

IRQE

EE0

DLY

COP timer arm/reset (COPRST)

$003A

(bit 7)

(6)

(5)

(4)

EEPROM programming (PPROG)

$003B

ODD

EVEN

BYTE

Highest priority interrupt (HPRIO)

$003C RBOOT SMOD

MDA

0000 0000

ROW ERASE EELAT EEPGM 0000 0000

PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110

RAM & I/O mapping (INIT)

$003D

RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000

Factory test (TEST1)

$003E

TILOP PLTST OCCR CBYP

Configuration control (CONFIG)

I2C bus address (MADR)

FCM

FCOP

$0040 MADR7 MADR6 MADR5 MADR4 MADR3 MADR2 MADR1

I2C bus frequency divider (MFDR)

$0041

I2C bus control (MCR)

$0042

I2C bus status register (MSR)

$0043

I2C bus data register (MDR)

Reserved

DISR

0000 0000

$003F ROMAD MBSP CLK4X PAREN NOSEC NOCOP ROMON EEON xxxx xxxx

MEN

MIEN

MSTA

MTX

TXAK

MCF

MAAS

MBB

MAL

SRW

MIF

0000 0000

MBC4 MBC3 MBC2 MBC1 MBC0 0000 0000

0000 0000

RXAK 1000 0001

$0044 TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 undefined
$0045

TPG

MOTOROLA
4-8

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

Table 4-2 Register and control bit assignments (Page 3 of 3)

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

Reserved

$0046

Reserved

$006F

SCI baud rate high (SCBDH)

$0070

BTST

BSPL

BRST SBR12 SBR11 SBR10 SBR9

SBR8 0000 0000

SCI baud rate low (SCBDL)

$0071

SBR7

SBR6

SBR5

SBR0 0000 0100

SBR4

SBR3

SBR2

SBR1

SCI control 1 (SCCR1)

$0072 LOOPS WOMS

WAKE

ILT

0000 0000

SCI control 2 (SCCR2)

$0073

TIE

TCIE

RIE

ILIE

RWU

SBK

0000 0000

SCI status 1 (SCSR1)

$0074

TDRE

RDRF

IDLE

1100 0000

SCI status 2 (SCSR2)

$0075

RAF

0000 0000

SCI data high (SCDRH)

$0076

undefined

SCI data low (SCDRL)

$0077

R7T7

R6T6

R5T5

R4T4

R3T3

R2T2

R1T1

R0T0

undefined

Reserved

$0078

Reserved

$0079

Reserved

$007A

Reserved

$007B

Reserved

$007C

Reserved

$007D

Port G data (PORTG)

$007E

PG7

undefined

Data direction G (DDRG)

$007F

DDG7

0000 0000

KEY
Applies only to EPROM devices
x State on reset depends on mode selected
u State of bit on reset is undefined

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-9

4.3

System initialization

Registers and bits that control initialization and the basic operation of the MCU are protected
against writes except under special circumstances. The following table lists registers that can be
written only once after reset, or that must be written within the first 64 cycles after reset.
Table 4-3 Registers with limited write access

(2)
Block protect register (BPROT)

EEPROM mapping register (INIT2)

No
Yes
(3)
System configuration options register 2 (OPT2)
No
(4)
System configuration options register (OPTION)

(5)
RAM and I/O map register (INIT)

(1) When SMOD = 0, bits 1 and 0 can be written only once, during the first 64 cycles, after
which they become read-only. When SMOD = 1, however, these bits can be written at any
time. All other bits can be written at any time.
(2) Bits can be written to zero once and only in the first 64 cycles or in special modes. Bits can
be set to one at any time.
(3) Bit 0 (XIRQE) and bit 1 (EXT4X) can be written only once; bit 4 (IRVNE) can be written only
once in single chip and user expanded modes.
(4) When SMOD = 0, bits 5, 4, 2, 1, and 0 can be written once and only in the first 64 cycles.
When SMOD = 1, however, bits 5, 4, 2, 1, and 0 can be written at any time. All other bits can
be written at any time.
(5) When SMOD = 0, bits can be written only once, during the first 64 cycles, after which the
register becomes read-only. When SMOD = 1, bits can be written at any time.

4.3.1

Mode selection

The four mode variations are selected by the logic states of the mode A (MODA) and mode B
(MODB) pins during reset. The MODA and MODB logic levels determine the logic state of the
special mode (SMOD) and mode A (MDA) control bits in the highest priority I-bit interrupt and
miscellaneous (HPRIO) register.
After reset is released, the mode select pins no longer influence the MCU operating mode. In
single chip operating mode, MODA pin is connected to a logic zero. In expanded mode, MODA is
normally connected to VDD through a pull-up resistor of 4.7 k. The MODA pin also functions as
the load instruction register (LIR) pin when the MCU is not in reset. The open-drain active low LIR
output pin drives low during the first E cycle of each instruction. The MODB pin also functions as
the stand-by power input (VSTBY), which allows the RAM contents to be maintained in the
absence of VDD.
TPG

MOTOROLA
4-10

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

Refer to Table 4-4, which is a summary of mode pin operation, the mode control bits and the four
operating modes.
A normal mode is selected when MODB is logic one during reset. One of three reset vectors is
fetched from address $FFFA$FFFF, and program execution begins from the address indicated
by this vector. If MODB is logic zero during reset, the special mode reset vector is fetched from
addresses $BFFA$BFFF and software has access to special test features. Refer to Section 5.

4.3.1.1

HPRIO Highest priority I-bit interrupt & misc. register

Address

Highest priority interrupt (HPRIO)

Note:

bit 7

bit 6

$003C RBOOT SMOD

bit 5
MDA

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110

RBOOT, SMOD and MDA bits depend on the power-up initialization mode and can only
be written in special modes when SMOD = 1. Refer to Table 4-4.

RBOOT Read bootstrap ROM

1 (set)

0 (clear)

Bootloader ROM enabled, at $BE40$BFFF.

Bootloader ROM disabled and not in map.

SMOD Special mode select

1 (set)

Special mode variation in effect.

0 (clear)

Normal mode variation in effect.

Once cleared, cannot be set again.

MDA Mode select A
1 (set)

0 (clear)

Normal expanded or special test mode. (Expanded buses active.)

Normal single chip or special bootstrap mode. (Ports active.)
Table 4-4 Hardware mode select summary
Inputs
MODB MODA
1
0
1
1
0
0
0
1

Control bits in HPRIO (latched at reset)

RBOOT
SMOD
MDA
Single chip
0
0
0
Expanded
0
0
1
Special bootstrap
1
1
0
Special test
0
1
1
Mode

PSEL[4:0] Priority select bits (refer to Section 5)

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-11

4.3.2

Initialization

Because bits in the following registers control the basic configuration of the MCU, an accidental
change of their values could cause serious system problems. The protection mechanism,
overridden in special operating modes, requires a write to the protected bits only within the first 64
bus cycles after any reset, or only once after each reset. See Table 4-3.

4.3.2.1

CONFIG System configuration register

Address

Configuration control (CONFIG)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

ROM/EPROM excluded from the memory map.

In single chip mode, reset sets this bit. In special test mode, reset clears ROMON.
EEON EEPROM enable
1 (set)

0 (clear)

EEPROM included in the memory map.

EEPROM is excluded from the memory map.

The XOUT pin is not present on 64-pin QFP packaged devices. It is present on 68-pin CLCC
packaged versions of the MC68HC711PA8/MC68HC711PB8, which are available as samples
only. Contact your local Motorola Sales Office for more information.

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-13

4.3.2.2

INIT RAM and I/O mapping register

Address

RAM & I/O mapping (INIT)

$003D

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000

The internal registers used to control the operation of the MCU can be relocated on 4K boundaries
within the memory space with the use of INIT. This 8-bit special-purpose register can change the
default locations of the RAM and control registers within the MCU memory map. It can be written
to only once within the first 64 E clock cycles after a reset. It then becomes a read-only register.
RAM[3:0] RAM map position
These four bits, which specify the upper hexadecimal digit of the RAM address, control the
position of the RAM in the memory map. The RAM can be positioned at the beginning of any 4K
page in the memory map. Refer to Table 4-5.
REG[3:0] 128-byte register block position
These four bits specify the upper hexadecimal digit of the address for the 128-byte block of internal
registers. The register block is positioned at the beginning of any 4K page in the memory map.
Refer to Table 4-5.

Table 4-5 RAM and register remapping

RAM[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Location
$0000$07FF
$1000$17FF
$2000$27FF
$3000$37FF
$4000$47FF
$5000$57FF
$6000$67FF
$7000$77FF
$8000$87FF
$9000$97FF
$A000$A7FF
$B000$B7FF
$C000$C7FF
$D000$D7FF
$E000$E7FF
$F000$F7FF

REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Location
$0000$007F
$1000$107F
$2000$207F
$3000$307F
$4000$407F
$5000$507F
$6000$607F
$7000$707F
$8000$807F
$9000$907F
$A000$A07F
$B000$B07F
$C000$C07F
$D000$D07F
$E000$E07F
$F000$F07F

TPG

MOTOROLA
4-14

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

When the memory map has the 128-byte register block mapped at the same location as RAM, the
registers have priority and the RAM is relocated to the memory space immediately following the
register block. This mapping feature keeps all the RAM available for use. Refer to Figure 4-2, which
illustrates the overlap.

$x000
$x07F
$x080

RAM A

RAM B

$x7FF

$x7FF
$x800
$x87F

Register and RAM mapped

to different 4K boundaries.

RAM A

Register and RAM mapped

to the same 4K boundary.

Figure 4-2 RAM and register overlap

4.3.2.3

INIT2 EEPROM mapping register

EEPROM mapping (INIT2)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0037

EE3

EE2

EE1

EE0

0000 0000

This register determines the location of EEPROM in the memory map. INIT2 may be read at any
time but bits 74 may be written only once after reset in normal modes.
EE[3:0] EEPROM map position
EEPROM is located at $xE00$xFFF, where x is the hexadecimal digit represented by EE[3:0].
Refer to Table 4-6.
Bits [3:0] Not implemented; always read zero.

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-15

Table 4-6 EEPROM remapping

EE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111

4
4.3.2.4

Location
$0E00$0FFF
$1E00$1FFF
$2E00$2FFF
$3E00$3FFF
$4E00$4FFF
$5E00$5FFF
$6E00$6FFF
$7E00$7FFF

EE[3:0]
1000
1001
1010
1011
1100
1101
1110
1111

Location
$8E00$8FFF
$9E00$9FFF
$AE00$AFFF
$BE00$BFFF
$CE00$CFFF
$DE00$DFFF
$EE00$EFFF
$FE00$FFFF

OPTION System configuration options register 1

Address

System config. options 1 (OPTION)

$0039

bit 7

bit 6

ADPU CSEL

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

IRQE

DLY

CME

FCME

CR1

CR0

0001 0000

The 8-bit special-purpose OPTION register sets internal system configuration options during
initialization. The time protected control bits IRQE, DLY, FCME and CR[1:0] can be written only
once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the
possibility of any accidental changes to the system configuration. They may be written at any time
in special modes.
ADPU A/D power-up (refer to Section 11)
1 (set)

0 (clear)

A/D system power enabled.

A/D system disabled, to reduce supply current.

After enabling the A/D power, at least 100s should be allowed for system stabilization.
CSEL Clock select (refer to Section 11)
1 (set)

0 (clear)

A/D, EPROM and EEPROM use internal RC clock source (about

1.5MHz).
A/D, EPROM and EEPROM use system E clock
(must be at least 1MHz).

This bit selects the clock source for the on-chip EPROM, EEPROM and A/D charge pumps. The
on-chip RC clock should be used when the E clock frequency falls below 1MHz.
IRQE Configure IRQ for falling-edge-sensitive operation
1 (set)

0 (clear)

Falling-edge-sensitive operation.
Low-level-sensitive operation.
TPG

MOTOROLA
4-16

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

DLY Enable oscillator start-up delay

1 (set)

0 (clear)

A stabilization delay is imposed as the MCU is started up from STOP

mode (or power-on reset).
The oscillator start-up delay is bypassed and the MCU resumes
processing within about four bus cycles. A stable external oscillator
is required if this option is selected.

DLY is set on reset, so a delay is always imposed as the MCU is started up from power-on reset.
A mask option on the MC68HC11PA8/MC68HC11PB8 allows the selection of either a short or
long delay time for power-on reset and exit from STOP mode; either 128 or 4064 bus cycles.This
option is not available on the MC68HC711PA8/MC68HC11PA8 on which the delay time is 4064
bus cycles.

CME Clock monitor enable (refer to Section 5)

1 (set)

Clock monitor enabled.

0 (clear)

Clock monitor disabled.

In order to use both STOP and clock monitor, the CME bit should be cleared before executing
STOP, then set after recovering from STOP.
FCME Force clock monitor enable (refer to Section 5)
1 (set)

0 (clear)

Clock monitor enabled; cannot be disabled until next reset.

Clock monitor follows the state of the CME bit.

When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize
STOP mode, FCME should always be cleared.
CR[1:0] COP timer rate select bits (refer to Section 5)
These control bits determine a scaling factor for the watchdog timer.

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-17

4.3.2.5

OPT2 System configuration options register 2

Address

System config. options 2 (OPT2)

$0038

bit 7

bit 6

bit 5

bit 4

bit 3

LIRDV CWOM STRCH IRVNE LSBF

bit 2

bit 1

bit 0

State
on reset

SPR2 EXT4X XIRQE 000x 0000

LIRDV LIR driven

1 (set)

0 (clear)

Enable LIR drive high pulse.

LIR not driven high on MODA/LIR pin.

In single-chip and bootstrap modes, this bit has no meaning or effect. The LIR pin is driven low to
indicate that execution of an instruction has begun. The LIR pin is normally configured for
wired-OR operation (only pulls low). In order to detect consecutive instructions in a high-speed
application, this signal can be made to drive high for a quarter of a cycle to prevent false triggering
(LIRDV set).
CWOM Port C wired-OR mode (refer to Section 6)
1 (set)

0 (clear)

Port C outputs are open-drain.

Port C operates normally.

STRCH Stretch external accesses

1 (set)

0 (clear)

Off-chip accesses are extended by one E clock cycle.

Normal operation.

When this bit is set, off-chip accesses of addresses $0000 to $3FFF (with ROMAD = 1) or $C000
to $FFFF (with ROMAD = 0) are extended by one E clock cycle to allow access to slow
peripherals. The E clock stretches externally, but the internal clocks are not affected, so that timers
and serial systems are not corrupted.

Note:

STRCH is cleared on reset; therefore a program cannot execute out of reset in a slow
external ROM.

To use this feature, ROMON must be set on reset so that the device starts with internal ROM
included in the memory map. STRCH should then be set.
STRCH has no effect in single chip and boot modes.

TPG

MOTOROLA
4-18

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

IRVNE Internal read visibility/not E

IRVNE can be written once in any user mode. In expanded modes, IRVNE determines whether
internal read visibility (IRV) is on or off, but has no meaning in user expanded secure mode, as
IRV must be disabled. In special test modes, IRVNE is reset to one. In normal and bootstrap
modes, IRVNE is reset to zero.
1 (set)

0 (clear)

Data from internal reads is driven out of the external data bus.
No visibility of internal reads on external bus.

In single chip modes this bit determines whether the E clock drives out from the chip.
1 (set)

0 (clear)

E pin is driven low.

E clock is driven out from the chip.

Refer to the following table for a summary of the operation immediately following reset.

IRVNE
E clock
IRV
IRVNE
IRVNE
after reset after reset after reset affects only can be written
Single chip
0
On
Off
E
Once
Expanded
0
On
Off
IRV
Once
Boot
0
On
Off
E
Unlimited
Special test
1
On
On
IRV
Unlimited
Mode

LSBF LSB-first enable (refer to Section 9)

1 (set)

Data is transferred LSB first.

0 (clear)

Data is transferred MSB first.

SPR2 SPI clock rate select (refer to Section 9)

This bit adds a divide-by-four to the SPI clock chain.
EXT4X XOUT clock output select
This bit can be written once and can be read at any time.
1 (set)

EXTALi clock is output on the XOUT pin.

0 (clear)

4XCLK clock is output on the XOUT pin.

This bit selects which clock is to be output on the XOUT pin, when enabled by the CLK4X bit in
CONFIG (see Section 4.3.2.1). 4XCLK can either be the output of the PLL circuit, or the same as
EXTALi (see Section 2.5). There is a phase delay between EXTALi and XOUT.

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-19

XIRQE Configure XIRQ for falling edge sensitive operation

This bit can be written once and can be read at any time.
1 (set)

0 (clear)

4.3.2.6

Falling-edge-sensitive operation.
Low-level-sensitive operation.

BPROT Block protect register

Address
Block protect (BPROT)

bit 7

bit 6

bit 5

$0035 BULKP

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

PTCON BPRT3 BPRT2 BPRT1 BPRT0 1001 1111

BPROT prevents accidental writes to EEPROM and the CONFIG register. The bits in this register
can be written to zero only once during the first 64 E clock cycles after reset in the normal modes;
they can be set at any time. Once the bits are cleared, the EEPROM array and the CONFIG
register can be programmed or erased. Setting the bits in the BPROT register to logic one protects
the EEPROM and CONFIG register until the next reset. Refer to Table 4-7.
BULKP Bulk erase of EEPROM protect
1 (set)

0 (clear)

EEPROM cannot be bulk or row erased.

EEPROM can be bulk erased normally.

Bits [6, 5] Not implemented; always read zero.

PTCON Protect for CONFIG register
1 (set)

0 (clear)

CONFIG register cannot be programmed or erased.

CONFIG register can be programmed or erased normally.

Note that, in special modes, CONFIG may be written regardless of the state of PTCON.
BPRT[3:0] Block protect bits for EEPROM
1 (set)

0 (clear)

Protection is enabled for associated block; it cannot be programmed

or erased.
Protection disabled for associated block.

Each of these four bits protects a block of EEPROM against writing or erasure, as follows:
Table 4-7 EEPROM block protect
Bit name Block protected
BPRT0 $xE00$xE1F
BPRT1 $xE20$xE5F
BPRT2 $xE60$xEDF
BPRT3 $xEE0$xFFF

Block size
32 bytes
64 bytes
128 bytes
288 bytes

TPG

MOTOROLA
4-20

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

4.3.2.7

TMSK2 Timer interrupt mask register 2

Timer interrupt mask 2 (TMSK2)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0024

TOI

RTII

PAOVI

PAII

PR1

PR0

0000 0000

PR[1:0] are time-protected control bits and can be changed only once and then only within the first
64 bus cycles after reset in normal modes.

Note:

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-21

4.4

EPROM, EEPROM and CONFIG register

4.4.1

EPROM

Using the on-chip EPROM programming feature requires an external power supply (VPPE).
Normal programming is accomplished using the EPROG register. Program EPROM at room
temperature only and place an opaque label over the quartz window during and after
programming.
The CSEL bit in the OPTION register selects an on-chip oscillator clock for programming the
EPROM while operating at frequencies below 1MHz.
The erased state of each EPROM byte is $FF.

4.4.1.1

EPROG EPROM programming control register

EPROM programming (EPROG)

Address

bit 7

bit 6

$002B

MBE

bit 5

bit 4

bit 3

ELAT EXCOL EXROW

bit 2

bit 1

bit 0

State
on reset

EPGM 0000 0000

MBE Multiple byte program enable

1 (set)

0 (clear)

Program 12 bytes with the same data.

Normal programming.

EPROM is made up of three blocks of 16K bytes. When programming, address bits 4 and 7 are
ignored, so that 4 addresses per block are programmed simultaneously. Address bits 14 and 15
are also ignored so that a total of twelve addresses are written at once, four in each 16K byte block.
For example, with the EPROM mapped to $4000$FFFF, a write to $4026 will actually program
$4026, $4036, $40A6, $40B6, $8026, $8036, $80A6, $80B6, $C026, $C036. $C0A6 and $C0B6
(i.e. %xx00 0000 x01x 0110).
This bit may be read or written only in special modes; it will always read zero in normal modes.
Bits [6, 2, 1] Not implemented; always read zero.
ELAT EPROM latch control
1 (set)

0 (clear)

EPROM address and data buses configured for programming.

EPROM cannot be read.
EPROM address and data buses configured for normal operation.

When set, this bit causes the address and data for writes to the EPROM to be latched. ELAT may
be read and written at any time.

TPG

MOTOROLA
4-22

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

Programming voltage (VPPE) disconnected from the EPROM array.

This bit can be read at any time, but may only be written if ELAT is set.
Note:

If ELAT = 0 (normal operation) then EPGM = 0 (programming voltage disconnected).

4.4.1.2

EPROM programming

The EPROM may be programmed and verified in software, via the MCU, using the following
procedure. The ROMON bit in the CONFIG register should be set. To use this method in special
bootstrap mode, the external EPROM programming voltage must be applied on pin VPPE. On
entry, A contains the data to be programmed and X contains the EPROM address.
EPROG

LDAB
STAB
STAA
LDAB
STAB
JSR
CLR

#$20
$002B
$0, X
#$21
$002B
DLYEP
$002B

Set ELAT bit (PGM=0) to enable EPROM latches.

Store data to EPROM address
Set EPGM bit, with ELAT=1, to enable prog. voltage
Delay tEPROG
Turn off programming voltage and set to READ mode

User-developed software can be uploaded through the SCI, or an EPROM programming utility
resident in the bootstrap ROM can be used. To use the resident utility, bootload a three-byte
program into RAM consisting of a single jump instruction to $BF00 (the starting address of a
resident EPROM programming utility), along with instructions to set the X and Y index registers to
default values. The utility program receives programming data from an external host and puts it in

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-23

EPROM. The value in IX determines programming delay time; for example, at 4 MHz operation, a
delay constant of 8000 in IX will give a 2ms delay time. The value in IY is a pointer to the first
address in EPROM to be programmed (normally = $4000). When the utility program is ready to
receive programming data, it sends the host an $FF character; then it waits. When the host sees
the $FF character, the EPROM programming data is sent, starting with location $4000. After the
last byte to be programmed is sent and the corresponding verification data is returned, the
programming operation is terminated by resetting the MCU.

4.4.2

EEPROM

The 512-byte on-board EEPROM is initially located from $0E00 to $0FFF after reset in all modes.
It can be mapped to any other 4K page by writing to the INIT2 register. The EEPROM is enabled
by the EEON bit in the CONFIG register. Programming and erasing are controlled by the PPROG
register.
Unlike information stored in ROM, data in the 512 bytes of EEPROM can be erased and
reprogrammed under software control. Because programming and erasing operations use an
on-chip charge pump driven by VDD, a separate external power supply is not required.
An internal charge pump supplies the programming voltage. Use of the block protect register
(BPROT) prevents inadvertent writes to (or erases of) blocks of EEPROM (see Section 4.3.2.6).
The CSEL bit in the OPTION register selects an on-chip oscillator clock for programming and
erasing the EEPROM while operating at frequencies below 1MHz.
In special modes there is one extra row of EEPROM, which is used for factory testing. Endurance
and data retention specifications do not apply to these cells.
The erased state of each EEPROM byte is $FF.

4.4.2.1

PPROG EEPROM programming control register

EEPROM programming (PPROG)

Note:

bit 2

bit 1

bit 0

State
on reset

Address

bit 7

bit 6

bit 5

bit 4

bit 3

$003B

ODD

EVEN

BYTE

ROW ERASE EELAT EEPGM 0000 0000

Writes to EEPROM addresses are inhibited while EEPGM is one. A write to a different
EEPROM location is prevented while a program or erase operation is in progress.

ODD Program odd rows in half of EEPROM (Test)

EVEN Program even rows in half of EEPROM (Test)
If both ODD and EVEN are set to one then all odd and even rows in half of the EEPROM will be
programmed with the same data, within one programming cycle.
Bit 5 Not implemented; always reads zero.
TPG

MOTOROLA
4-24

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

BYTE EEPROM byte erase mode

1 (set)

0 (clear)

Erase only one byte of EEPROM.

Row or bulk erase mode used.

This bit may be read or written at any time.

ROW EEPROM row/bulk erase mode (only valid when BYTE = 0)
1 (set)

0 (clear)

Erase only one 16 byte row of EEPROM.

Erase all 512 bytes of EEPROM.

This byte can be read or written at any time.

Table 4-8 Erase mode selection
Byte
0
0
1
1

Row
0
1
0
1

Action
Bulk erase (all 512 bytes)
Row erase (16 bytes)
Byte erase
Byte erase

ERASE Erase/normal control for EEPROM

1 (set)

0 (clear)

Erase mode.
Normal read or program mode.

This byte can be read or written at any time.

EELAT EEPROM latch control
1 (set)

0 (clear)

EEPROM address and data bus set up for programming or erasing.

EEPROM address and data bus set up for normal reads.

When the EELAT bit is cleared, the EEPROM can be read as if it were a ROM. The block protect
register has no effect during reads. This bit can be read and written at any time.
EEPGM EEPROM program command
1 (set)

Program or erase voltage switched on to EEPROM array.

0 (clear)

Program or erase voltage switched off to EEPROM array.

This bit can be read at any time but can only be written if EELAT = 1.

Note:

If EELAT = 0 (normal operation) then EEPGM = 0 (programming voltage disconnected).

TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-25

During EEPROM programming, the ROW and BYTE bits of PPROG are not used. If the frequency
of the E clock is 1MHz or less, set the CSEL bit in the OPTION register. Remember that the
EEPROM must be erased by a separate erase operation before programming. The following
example of how to program an EEPROM byte assumes that the appropriate bits in BPROT have
been cleared.
PROG

LDAB
STAB
STAA
LDAB
STAB
JSR
CLR

4.4.2.2

#$02
$003B
$0E00
#$03
$003B
DLY10
$003B

EELAT=1
Set EELAT bit
Store data to EEPROM address
EELAT=EEPGM=1
Turn on programming voltage
Delay tEEPROG
Turn off high voltage and set to READ mode

EEPROM bulk erase

To erase the EEPROM, ensure that the appropriate bits in the BPROT register are cleared, then
complete the following steps using the PPROG register:
1) Write to PPROG with the ERASE, EELAT and appropriate BYTE and ROW
bits set.
2) Write to the appropriate EEPROM address with any data. Row erase only
requires a write to any location in the row. Bulk erase is accomplished by
writing to any location in the array.
3) Write to PPROG with ERASE, EELAT, EEPGM and the appropriate BYTE
and ROW bits set.
4) Delay for time tEEPROG.
5) Clear the EEPGM bit in PPROG to turn off the high voltage.
6) Clear the PPROG register to reconfigure the EEPROM address and data
buses for normal operation.
The following is an example of how to bulk erase the 512-byte EEPROM. The CONFIG register is
not affected in this example.
BULKE

LDAB
STAB
STAA
LDAB
STAB
JSR
CLR

#$06
$003B
$0E00
#$07
$003B
DLY10
$003B

EELAT=ERASE=1
Set EELAT bit
Store data to any EEPROM address
EELAT=ERASE=EEPGM=1
Turn on programming voltage
Delay tEEPROG
Turn off high voltage and set to READ mode

TPG

MOTOROLA
4-26

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

4.4.2.3

EEPROM row erase

The following example shows how to perform a fast erase of 16 bytes of EEPROM:
ROWE

LDAB
STAB
STAB
LDAB
STAB
JSR
CLR

4.4.2.4

#$0E
$003B
0,X
#$0F
$003B
DLY10
$003B

ROW=ERASE=EELAT=1
Set to ROW erase mode
Write any data to any address in ROW
ROW=ERASE=EELAT=EEPGM=1
Turn on high voltage
Delay tEEPROG
Turn off high voltage and set to READ mode

EEPROM byte erase

The following is an example of how to erase a single byte of EEPROM:

BYTEE

4.4.3

LDAB
STAB
STAB
LDAB
STAB
JSR
CLR

#$16
$003B
0,X
#$17
$003B
DLY10
$003B

BYTE=ERASE=EELAT=1
Set to BYTE erase mode
Write any data to address to be erased
BYTE=ERASE=EELAT=EEPGM=1
Turn on high voltage
Delay tEEPROG
Turn off high voltage and set to READ mode

CONFIG register programming

Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to
erase and program this register. The procedure for programming is the same as for programming
a byte in the EEPROM array, except that the CONFIG register address is used. CONFIG can be
programmed or erased (including byte erase) while the MCU is operating in any mode, provided
that PTCON in BPROT is clear. To change the value in the CONFIG register, complete the
following procedure. Do not initiate a reset until the procedure is complete.
1) Erase the CONFIG register.
2) Program the new value to the CONFIG address.
3) Initiate reset.
CONFIG System configuration register
Address
Configuration control (CONFIG)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$003F ROMAD MBSP CLK4X PAREN NOSEC NOCOP ROMON EEON xxxx xxxx

For a description of the bits contained in the CONFIG register refer to Section 4.3.2.1.
TPG

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-27

CONFIG is made up of EEPROM cells and static working latches. The operation of the MCU is
controlled directly by these latches and not the EEPROM byte. When programming the CONFIG
register, the EEPROM byte is accessed. When the CONFIG register is read, the static latches are
accessed.
These bits can be read at any time. The value read is the one latched into the register from the
EEPROM cells during the last reset sequence. A new value programmed into this register is not
readable until after a subsequent reset sequence.

Bits in CONFIG can be written at any time if SMOD = 1 (bootstrap or special test mode). If
SMOD = 0 (single chip or expanded mode), these bits can only be written using the EEPROM
programming sequence, and none of the bits is readable or active until latched via the next reset.

4.4.4

RAM and EEPROM security

The optional security feature protects the contents of EEPROM and RAM from unauthorized
access. Data, codes, keys, a program, or a key portion of a program, can be protected against
access. To accomplish this, the protection mechanism restricts operation of protected devices to
single-chip modes, and thus prevents the memory locations from being monitored externally
(single-chip modes do not allow visibility of the internal address and data buses).Resident
programs, however, have unlimited access to the internal EEPROMand RAM and can read, write,
or transfer the contents of these memories.

Note:

A mask option on the MC68HC11PA8/MC68HC11PB8 determines whether or not the

security
feature
is
available
(it
is
always
available
on
the
MC68HC711PA8/MC68HC711PB8). If the feature is available, then the secure mode
can be invoked by programming the NOSEC bit to zero. Otherwise, the NOSEC bit is
permanently set to one, disabling security.

If the security feature is present and enabled and bootstrap mode is selected, then the following
sequence is performed by the bootstrap program:
1) Output $FF on the SCI.
2) Turn block protect off. Clear BPROT register.
3) If EEPROM is enabled, erase it all.
4) Verify that the EEPROM is erased; if not, begin sequence again.
5) Write $FF to every RAM byte.
6) Erase the CONFIG register.
If all the above operations are successful, the bootloading process continues as if the device has
not been secured.

TPG

MOTOROLA
4-28

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

CONFIG System configuration register

Address
Configuration control (CONFIG)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$003F ROMAD MBSP CLK4X PAREN NOSEC NOCOP ROMON EEON xxxx xxxx

For a description of the other bits contained in the CONFIG register refer to Section 4.3.2.1.

NOSEC EEPROM security disabled

1 (set)

Disable security.

0 (clear)

Enable security.

With security enabled, selection of special test mode is prevented; single chip and user expanded
modes may be accessed. If the MODA and MODB pins are configured for special test mode, the
part will start in bootstrap mode.

MC68HC11PA8

OPERATING MODES AND ON-CHIP MEMORY

MOTOROLA
4-29

MOTOROLA
4-30

OPERATING MODES AND ON-CHIP MEMORY

MC68HC11PA8

5
RESETS AND INTERRUPTS
Resets and interrupt operations load the program counter with a vector that points to a new
location from which instructions are to be fetched. A reset immediately stops execution of the
current instruction and forces the program counter to a known starting address. Internal registers
and control bits are initialized so that the MCU can resume executing instructions. An interrupt
temporarily suspends normal program execution whilst an interrupt service routine is being
executed. After an interrupt has been serviced, the main program resumes as if there had been
no interruption.

5.1

Resets

There are four possible sources of reset. Power-on reset (POR) and external reset share the
normal reset vector. The computer operating properly (COP) reset and the clock monitor reset
each has its own vector.

5.1.1

Power-on reset

A positive transition on VDD generates a power-on reset (POR), which is used only for power-up
conditions. POR cannot be used to detect drops in power supply voltages. A delay is imposed which
allows the clock generator to stabilize after the oscillator becomes active. If RESET is at logical zero at
the end of the delay time, the CPU remains in the reset condition until RESET goes to logical one. A
mask option selects one of two delay times; either 128 or 4064 tCYC (internal clock cycles).

Note:

This mask option is not available on the MC68HC711PA8/MC68HC711PB8, where the

delay time is 4064 tCYC.

It is important to protect the MCU during power transitions. Most M68HC11 systems need an
external circuit that holds the RESET pin low whenever VDD is below the minimum operating level.
This external voltage level detector, or other external reset circuits, are the usual source of reset
in a system. The POR circuit only initializes internal circuitry during cold starts. Refer to Figure 2-3.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-1

5.1.2

External reset (RESET)

The CPU distinguishes between internal and external reset conditions by sensing whether the
reset pin rises to a logic one in less than four E clock cycles after an internal device releases reset.
When a reset condition is sensed, the RESET pin is driven low by an internal device for eight E
clock cycles, then released. Four E clock cycles later it is sampled. If the pin is still held low, the
CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor. It is not advisable to connect an
external resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices
because the circuit charge time constant can cause the device to misinterpret the type of reset
that occurred. To guarantee recognition of an external reset, the RESET pin should be held low
for at least 16 clock cycles.

5.1.3

COP reset

The MCU includes a COP system to help protect against software failures. When the COP is enabled,
the software is responsible for keeping a free-running watchdog timer from timing out. When the
software is no longer being executed in the intended sequence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP system is
enabled or disabled. To change the enable status of the COP system, change the contents of the
CONFIG register and then perform a system reset. In the special test and bootstrap operating
modes, the COP system is initially inhibited by the disable resets (DISR) control bit in the TEST1
register. The DISR bit can subsequently be written to zero to enable COP resets.
The COP system is clocked by ST4XCK/217 (see Section 10). If the PLL circuit is active
(VDDSYN = 1) and MCS and BCS are both set, then ST4XCK is equal to the output of the PLL
circuit, VCOOUT. Otherwise, ST4XCK is the same as EXTALi. Refer to Figure 10-1.
The COP timer rate control bits, CR[1:0], in the OPTION register determine the COP timeout
period. ST4XCK/217 is scaled by the factor shown in Table 5-1. After reset, bits CR[1:0] are zero,
which selects the shortest timeout period. In normal operating modes, these bits can only be
written once, within 64 bus cycles after reset.
Table 5-1 COP timer rate select
CR[1:0]
00
01
10
11

Divide
ST4XCK/217 by
1
4
16
64

ST4XCK = 4 MHz:
timeout(1)
32.77 ms
131.07 ms
524.29 ms
2.097 ms

ST4XCK = 8MHz:
timeout(1)
16.384 ms
65.536 ms
262.14 ms
1.049 sec

ST4XCK = 16MHz:
timeout(1)
8.192 ms
32.768 ms
131.07 ms
524.29 ms

(1) The timeout period has a tolerance of 0/+one cycle of the ST4XCK/217 clock due to the
asynchronous implementation of the COP circuitry. For example, with ST4XCK = 8MHz, the
uncertainty is 0/+16.384ms. See also the M68HC11 Reference Manual, (M68HC11RM/AD).

TPG

MOTOROLA
5-2

RESETS AND INTERRUPTS

MC68HC11PA8

5.1.3.1

COPRST Arm/reset COP timer circuitry register

COP timer arm/reset (COPRST)

State
on reset

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

$003A

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) not affected

Complete the following reset sequence to service the COP timer. Write $55 to COPRST to arm
the COP timer clearing mechanism. Then write $AA to COPRST to clear the COP timer. Executing
instructions between these two steps is possible as long as both steps are completed in the
correct sequence before the timer times out.

5.1.4

Clock monitor reset

The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges are
detected within this RC time delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled or disabled by the CME control bit in the OPTION register. The
presence of a timeout is determined by the RC delay, which allows the clock monitor to operate
without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs a clock to
function, it is disabled when the clocks stop. Therefore, the clock monitor system can detect clock
failures not detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout values between individual
devices. An E clock frequency below 10 kHz is detected as a clock monitor error. An E clock
frequency of 200 kHz or more prevents clock monitor errors. Use of the clock monitor function
when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed and the clock monitor is
enabled. Because the STOP function causes the clocks to be halted, the clock monitor function
generates a reset sequence if it is enabled at the time the STOP mode was initiated. Before
executing a STOP instruction, clear the CME bit in the OPTION register to zero to disable the clock
monitor. After recovery from STOP, set the CME bit to logic one to enable the clock monitor.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-3

5.1.5

OPTION System configuration options register 1

Address

System config. options 1 (OPTION)

$0039

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

ADPU CSEL

IRQE

DLY

CME

FCME

CR1

CR0

0001 0000

bit 7

The special-purpose OPTION register sets internal system configuration options during
initialization. The time protected control bits (IRQE, DLY, FCME and CR[1:0]) can be written to only
once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the
possibility of any accidental changes to the system configuration. They may be written at any time
in special modes.

ADPU A/D power-up (Refer to Section 11)

1 (set)

0 (clear)

A/D system power enabled.

A/D system disabled, to reduce supply current.

CSEL Clock select (Refer to Section 11)

1 (set)

mode (or from power-on reset).
The oscillator start-up delay is bypassed and the MCU resumes
processing within about four bus cycles. A stable external oscillator
is required if this option is selected.

Because DLY is set on reset, a delay is always imposed as the MCU is started up from
power-on reset.

A mask option on the MC68HC11PA8/MC68HC11PB8 allows the selection of either a short or

long delay time for power-on reset and exit from STOP mode; either 128 or 4064 bus cycles.This
option is not available on the MC68HC711PA8/MC68HC711PB8 where the delay time is 4064 bus
cycles.

TPG

MOTOROLA
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RESETS AND INTERRUPTS

MC68HC11PA8

CME Clock monitor enable

1 (set)

Clock monitor enabled.

0 (clear)

Clock monitor disabled.

This control bit can be read or written at any time and controls whether or not the internal clock
monitor circuit triggers a reset sequence when the system clock is slow or absent. When it is clear,
the clock monitor circuit is disabled, and when it is set, the clock monitor circuit is enabled. Reset
clears the CME bit.
In order to use both STOP and clock monitor, the CME bit should be cleared before executing
STOP, then set after recovering from STOP.

FCME Force clock monitor enable

1 (set)

0 (clear)

Clock monitor enabled; cannot be disabled until next reset.

Clock monitor follows the state of the CME bit.

When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize
STOP mode, FCME should always be cleared.
CR[1:0] COP timer rate select bits
The COP function is clocked by ST4XCK/217. ST4XCK can be either EXTALi or VCOOUT (see
Section 5.1.3). These control bits determine a scaling factor for the watchdog timer period. See
Table 5-1.

5.1.6

CONFIG Configuration control register

Address

Configuration control (CONFIG)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$003F ROMAD MBSP CLK4X PAREN NOSEC NOCOP ROMON EEON xxxx xxxx

Among other things, CONFIG controls the presence and location of EEPROM in the memory map
and enables the COP watchdog system. A security feature that protects data in EEPROM and
RAM is available on mask programmed MCUs.
CONFIG is made up of EEPROM cells and static working latches. The operation of the MCU is
controlled directly by these latches and not the EEPROM byte. When programming the CONFIG
register, the EEPROM byte is accessed. When the CONFIG register is read, the static latches
are accessed.
These bits can be read at any time. The value read is the one latched into the register from the
EEPROM cells during the last reset sequence. A new value programmed into this register is not
readable until after a subsequent reset sequence.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-5

Bits in CONFIG can be written at any time if SMOD = 1 (bootstrap or special test mode). If
SMOD = 0 (single chip or expanded mode), they can only be written using the EEPROM
programming sequence, and are neither readable nor active until latched via the next reset.
ROMAD ROM/EPROM mapping control (refer to Section 4)
1 (set)

0 (clear)

ROM addressed from $4000 to $FFFF.

ROM addressed from $0000 to $BFFF (expanded mode only).

In single chip mode, reset sets this bit.

MBSP Synchronous serial interface select (refer to Section 4)

1 (set)

0 (clear)

If enabled, the I2C bus uses port D[4, 3] pins; SPI is disabled.
If enabled, the I2C bus uses port E[7, 6] pins.

CLK4X 4X clock enable (refer to Section 4)

1 (set)

0 (clear)

ROM/EPROM excluded from the memory map.

TPG

MOTOROLA
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RESETS AND INTERRUPTS

MC68HC11PA8

EEON EEPROM enable (refer to Section 4)

1 (set)

0 (clear)

5.2

EEPROM included in the memory map.

EEPROM excluded from the memory map.

Effects of reset

When a reset condition is recognized, the internal registers and control bits are forced to an initial
state. Depending on the cause of the reset and the operating mode, the reset vector can be
fetched from any of six possible locations, as shown in Table 5-2.

Table 5-2 Reset cause, reset vector and operating mode

Cause of reset
Normal mode vector Special test or bootstrap
POR or RESET pin
$FFFE, $FFFF
$BFFE, $BFFF
Clock monitor failure
$FFFC, $FFFD
$BFFC, $BFFD
COP watchdog timeout
$FFFA, $FFFB
$BFFA, $BFFB

These initial states then control on-chip peripheral systems to force them to known start-up states,
as described in the following paragraphs.

5.2.1

Central processing unit

After reset, the CPU fetches the restart vector from the appropriate address during the first three
cycles, and begins executing instructions. The stack pointer and other CPU registers are
indeterminate immediately after reset; however, the X and I interrupt mask bits in the condition
code register (CCR) are set to mask any interrupt requests. Also, the S-bit in the CCR is set to
inhibit the STOP mode.

5.2.2

Memory map

After reset, the INIT register is initialized to $00, putting the 2K bytes of RAM at locations
$0080$087F, and the control registers at locations $0000$007F. The INIT2 register puts
EEPROM at locations $0E00$0FFF.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-7

5.2.3

Parallel I/O

When a reset occurs in expanded operating modes, port B, C, and F pins and PG7 used for
parallel I/O are dedicated to the expansion bus. If a reset occurs during a single chip operating
mode, all ports are configured as general purpose high-impedance inputs.

Note:

Do not confuse pin function with the electrical state of the pin at reset. All
general-purpose I/O pins configured as inputs at reset are in a high-impedance state.
Port data registers reflect the ports functional state at reset. The pin function is mode
dependent.

5.2.4

Timer

During reset, the timer system is initialized to a count of $0000. The prescaler bits are cleared,
and all output compare registers are initialized to $FFFF. All input capture registers are
indeterminate after reset. The output compare 1 mask (OC1M) register is cleared so that
successful OC1 compares do not affect any I/O pins. The other four output compares are
configured so that they do not affect any I/O pins on successful compares. All input capture
edge-detector circuits are configured for capture disabled operation. The timer overflow interrupt
flag and all eight timer function interrupt flags are cleared. All nine timer interrupts are disabled
because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5; however,
the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin.

5.2.5

Real-time interrupt (RTI)

The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are masked. The
rate control bits are cleared after reset and can be initialized by software before the real-time
interrupt (RTI) system is used.

5.2.6

Pulse accumulator

The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin
defaults to being a general-purpose input pin.

TPG

MOTOROLA
5-8

RESETS AND INTERRUPTS

MC68HC11PA8

5.2.7

Computer operating properly (COP)

The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared,
and disabled if NOCOP is set. The COP rate is set for the shortest duration timeout.

5.2.8

Serial communications interface (SCI)

The reset condition of the SCI system is independent of the operating mode. At reset, the SCI
baud rate control register is initialized to $0004. All transmit and receive interrupts are masked and
both the transmitter and receiver are disabled so the port pins default to being general purpose
I/O lines. The SCI frame format is initialized to an 8-bit character size. The send break and receiver
wake-up functions are disabled. The TDRE and TC status bits in the SCI status register are both
set, indicating that there is no transmit data in either the transmit data register or the transmit serial
shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status bits are cleared.

5.2.9

Serial peripheral interface (SPI)

The SPI system is disabled by reset. Its associated port pins default to being general purpose I/O lines.

5.2.10

I2C bus

The I2C bus is disabled on reset.

5.2.11

Analog-to-digital converter

The A/D converter configuration is indeterminate after reset. The ADPU bit is cleared by reset,
which disables the A/D system. The conversion complete flag is cleared by reset.

5.2.12

System

The EEPROM programming controls are disabled, so the memory system is configured for normal
read operation. PSEL[4:0] are initialized with the binary value %00110, causing the external IRQ
pin to have the highest I-bit interrupt priority. The IRQ and XIRQ pins are configured for
level-sensitive operation (for wired-OR systems). The RBOOT, SMOD, and MDA bits in the HPRIO
register reflect the status of the MODB and MODA inputs at the rising edge of reset. The DLY
control bit is set to specify that an oscillator start-up delay is imposed upon recovery from STOP
mode or power-on reset. The clock monitor system is disabled because CME and FCME are
cleared.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-9

5.3

Reset and interrupt priority

Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced
first when simultaneous requests occur. Any maskable interrupt can be given priority over other
maskable interrupts.
The first six interrupt sources are not maskable by the I-bit in the CCR. The priority arrangement
for these sources is fixed and is as follows:
1) POR or RESET pin
2) Clock monitor reset
3) COP watchdog reset

4) XIRQ interrupt

Illegal opcode interrupt see Section 5.4.3 for details of handling

Software interrupt (SWI) see Section 5.4.4 for details of handling

The maskable interrupt sources have the following priority arrangement:

5) IRQ
6) Real-time interrupt
7) Timer input capture 1
8) Timer input capture 2
9) Timer input capture 3
10) Timer output compare 1
11) Timer output compare 2
12) Timer output compare 3
13) Timer output compare 4
14) Timer input capture 4/output compare 5
15) I2C bus
16) Timer overflow
17) Pulse accumulator overflow
18) Pulse accumulator input edge
19) SPI transfer complete
20) SCI system
Any one of these maskable interrupts can be assigned the highest maskable interrupt priority by
writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the priority
arrangement remains the same. An interrupt that is assigned highest priority is still subject to
global masking by the I-bit in the CCR, or by any associated local bits. Interrupt vectors are not
affected by priority assignment. To avoid race conditions, HPRIO can only be written while I-bit
interrupts are inhibited.

TPG

MOTOROLA
5-10

RESETS AND INTERRUPTS

MC68HC11PA8

5.3.1

HPRIO Highest priority I-bit interrupt and misc. register

Address

Highest priority interrupt (HPRIO)

bit 7

bit 6

$003C RBOOT SMOD

bit 5
MDA

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110

RBOOT, SMOD, and MDA bits depend on power-up initialization mode and can only be written in
special modes when SMOD = 1. Refer to Table 4-4.
RBOOT Read bootstrap ROM (refer to Section 4)
1 (set)

0 (clear)

Bootloader ROM enabled, at $BE40$BFFF.

Bootloader ROM disabled and not in map.

SMOD Special mode select (refer to Section 4)

1 (set)

Special mode variation in effect.

0 (clear)

Normal mode variation in effect.

MDA Mode select A (refer to Section 4)

1 (set)

0 (clear)

Normal expanded or special test mode in effect.

Normal single chip or special bootstrap mode in effect.

PSEL[4:0] Priority select bits

These bits select one interrupt source to be elevated above all other I-bit-related sources and can
be written to only while the I-bit in the CCR is set (interrupts disabled). See Table 5-3.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-11

Table 5-3 Highest priority interrupt selection

4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

3
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1

PSELx
2 1
0 X
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
X X

0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X

Interrupt source promoted

Reserved (default to IRQ)
Reserved (default to IRQ)
Reserved (default to IRQ)
IRQ (external pin)
Real-time interrupt
Timer input capture 1
Timer input capture 2
Timer input capture 3
Timer output compare 1
Timer output compare 2
Timer output compare 3
Timer output compare 4
Timer output compare 5/input capture 4
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
SCI serial system
I2C serial system
Reserved (default to IRQ)
Reserved (default to IRQ)

TPG

MOTOROLA
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RESETS AND INTERRUPTS

MC68HC11PA8

Table 5-4 Interrupt and reset vector assignments

Vector address

Interrupt source

FFC0, C1 FFD2, D3 Reserved

FFD4, D5
I2C bus
SCI receive data register full
SCI receiver overrun
FFD6, D7
SCI transmit data register empty
SCI transmit complete
SCI idle line detect
FFD8, D9
SPI serial transfer complete
FFDA, DB
Pulse accumulator input edge
FFDC, DD
Pulse accumulator overflow
FFDE, DF
Timer overflow
FFE0, E1
Timer input capture 4/output compare 5
FFE2, E3
Timer output compare 4
FFE4, E5
Timer output compare 3
FFE6, E7
Timer output compare 2
FFE8, E9
Timer output compare 1
FFEA, EB
Timer input capture 3
FFEC, ED
Timer input capture 2
FFEE, EF
Timer input capture 1
FFF0, F1
Real-time interrupt
FFF2, F3
IRQ pin
FFF4, F5
XIRQ pin
FFF6, F7
Software interrupt
FFF8, F9
Illegal opcode trap
FFFA, FB
COP failure
FFFC, FD
Clock monitor fail
FFFE, FF
RESET

CCR
mask bit

I
I
I
I
I
I
I
I
I
I
I
I
I
I
X
None
None
None
None
None

Local
mask

MIEN
RIE
RIE
TIE
TCIE
ILIE
SPIE
PAII
PAOVI
TOI
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
IC2I
IC1I
RTII
None
None
None
None
NOCOP
CME
None

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-13

5.4

Interrupts

Excluding reset type interrupts, the MC68HC11PA8/MC68HC11PB8 has 19 interrupt vectors that
support 23 interrupt sources. The 16 maskable interrupts are generated by on-chip peripheral
systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition
code register (CCR) is clear. The three nonmaskable interrupt sources are illegal opcode trap,
software interrupt, and XIRQ pin. Refer to Table 5-4, which shows the interrupt sources and vector
assignments for each source.

For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during
the normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI
system is cleared by the automatic clearing mechanism consisting of a read of the SCI status
register while RDRF is set, followed by a read of the SCI data register. The normal response to an
RDRF interrupt request would be to read the SCI status register to check for receive errors, then
to read the received data from the SCI data register. These two steps satisfy the automatic
clearing mechanism without requiring any special instructions.

5.4.1

Interrupt recognition and register stacking

An interrupt can be recognized at any time after it is enabled by its local mask, if any, and by the
global mask bit in the CCR. Once an interrupt source is recognized, the CPU responds at the
completion of the instruction being executed. Interrupt latency varies according to the number of
cycles required to complete the current instruction. When the CPU begins to service an interrupt,
the contents of the CPU registers are pushed onto the stack in the order shown in Table 5-5. After
the CCR value is stacked, the I-bit and the X-bit, if XIRQ is pending, are set to inhibit further
interrupts. The interrupt vector for the highest priority pending source is fetched, and execution
continues at the address specified by the vector. At the end of the interrupt service routine, the
return from interrupt instruction is executed and the saved registers are pulled from the stack in
reverse order so that normal program execution can resume. Refer to Section 3 for further
information.

Table 5-5 Stacking order on entry to interrupts

Memory location CPU registers
SP
PCL
SP 1
PCH
SP 2
IYL
SP 3
IYH
SP 4
IXL
SP 5
IXH
SP 6
ACCA
SP 7
ACCB
SP 8
CCR

TPG

MOTOROLA
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RESETS AND INTERRUPTS

MC68HC11PA8

5.4.2

Nonmaskable interrupt request (XIRQ)

Nonmaskable interrupts are useful because they can always interrupt CPU operations. The most
common use for such an interrupt is for serious system problems, such as program runaway or
power failure. The XIRQ input is an updated version of the NMI (nonmaskable interrupt) input of
earlier MCUs.
Upon reset, both the X-bit and I-bit of the CCR are set to inhibit all maskable interrupts and XIRQ.
After minimum system initialization, software can clear the X-bit by a TAP instruction, enabling
XIRQ interrupts. Thereafter, software cannot set the X-bit. Thus, an XIRQ interrupt is a
nonmaskable interrupt. Because the operation of the I-bit-related interrupt structure has no effect
on the X-bit, the internal XIRQ pin remains unmasked. In the interrupt priority logic, the XIRQ
interrupt has a higher priority than any source that is maskable by the I-bit. All I-bit-related
interrupts operate normally with their own priority relationship.

When an I-bit-related interrupt occurs, the I-bit is automatically set by hardware after stacking the
CCR byte. The X-bit is not affected. When an X-bit-related interrupt occurs, both the X and I bits
are automatically set by hardware after stacking the CCR. A return from interrupt instruction
restores the X and I bits to their pre-interrupt request state.

5.4.3

Illegal opcode trap

Because not all possible opcodes or opcode sequences are defined, the MCU includes an illegal
opcode detection circuit, which generates an interrupt request. When an illegal opcode is detected
and the interrupt is recognized, the current value of the program counter is stacked. After interrupt
service is complete, the user should reinitialize the stack pointer to ensure that repeated execution
of illegal opcodes does not cause stack underflow. Left uninitialized, the illegal opcode vector can
point to a memory location that contains an illegal opcode. This condition causes an infinite loop
that causes stack underflow. The stack grows until the system crashes.
The illegal opcode trap mechanism works for all unimplemented opcodes on all four opcode map
pages. The address stacked as the return address for the illegal opcode interrupt is the address
of the first byte of the illegal opcode. Otherwise, it would be almost impossible to determine
whether the illegal opcode had been one or two bytes. The stacked return address can be used
as a pointer to the illegal opcode, so that the illegal opcode service routine can evaluate the
offending opcode.

5.4.4

Software interrupt

SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhibited by the
global mask bits in the CCR. Because execution of SWI sets the I mask bit, once an SWI interrupt
begins, other interrupts are inhibited until SWI is complete, or until user software clears the I bit in
the CCR.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-15

5.4.5

Maskable interrupts

The maskable interrupt structure of the MCU can be extended to include additional external
interrupt sources through the IRQ pin. The default configuration of this pin is a low-level sensitive
wired-OR network. When an event triggers an interrupt, a software accessible interrupt flag is set.
When enabled, this flag causes a constant request for interrupt service. After the flag is cleared,
the service request is released.

5.4.6

Reset and interrupt processing

The following flow diagrams illustrate the reset and interrupt process. Figure 5-1 and Figure 5-2
illustrate how the CPU begins from a reset and how interrupt detection relates to normal opcode
fetches. Figure 5-3 to Figure 5-4 provide an expanded version of a block in Figure 5-1 and illustrate
interrupt priorities. Figure 5-6 shows the resolution of interrupt sources within the SCI subsystem.

5.5

Low power operation

Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The WAIT condition
suspends processing and reduces power consumption to an intermediate level. The STOP
condition turns off all on-chip clocks and reduces power consumption to an absolute minimum
while retaining the contents of all bytes of the RAM.

5.5.1

WAIT

The WAI opcode places the MCU in the WAIT condition, during which the CPU registers are stacked
and CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an
external IRQ, an XIRQ, or any of the internally generated interrupts, such as the timer or serial
interrupts. The on-chip crystal oscillator remains active throughout the WAIT stand-by period.
The reduction of power in the WAIT condition depends on how many internal clock signals driving
on-chip peripheral functions can be shut down. The CPU is always shut down during WAIT. While
in the wait state, the address/data bus repeatedly runs read cycles to the address where the CCR
contents were stacked. The MCU leaves the wait state when it senses any interrupt that has not
been masked.
The PH2 clock to the free-running timer system is stopped if the I-bit is set and the COP system
is disabled by NOCOP being set. Several other systems can also be in a reduced power
consumption state depending on the state of software-controlled configuration control bits. Power
consumption by the analog-to-digital (A/D) converter is not affected significantly by the WAIT
condition. However, the A/D converter current can be eliminated by writing the ADPU bit to zero
and halting the RC clock (CSEL cleared). The SPI system is enabled or disabled by the SPE

TPG

MOTOROLA
5-16

RESETS AND INTERRUPTS

MC68HC11PA8

control bit, and the I2C bus is disabled by the MEN bit. The SCI transmitter is enabled or disabled
by the TE bit, and the SCI receiver is enabled or disabled by the RE bit (lowest power consumption
is achieved when RE=TE=0). Setting the WEN bit in PLLCR will result in WAIT mode using a
slower clock and hence less power (see Section 2.5). Therefore the power consumption in WAIT
is dependent on the particular application.

5.5.2

STOP

Executing the STOP instruction while the S-bit in the CCR is clear places the MCU in the STOP
condition. If the S-bit is set, the STOP opcode is treated as a no-op (NOP). The STOP condition
offers minimum power consumption because all clocks, including the crystal oscillator, are
stopped while in this mode. To exit STOP and resume normal processing, a logic low level must
be applied to one of the external interrupts (IRQ or XIRQ) or to the RESET pin. A pending
edge-triggered IRQ can also bring the CPU out of STOP.

Because all clocks are stopped in this mode, all internal peripheral functions also stop. The data
in the internal RAM is retained as long as VDD power is maintained. The CPU state and I/O pin
levels are static and are unchanged by STOP. Therefore, when an interrupt comes to restart the
system, the MCU resumes processing as if there were no interruption. If reset is used to restart
the system a normal reset sequence results where all I/O pins and functions are also restored to
their initial states.
To use the IRQ pin or the XIRQ pin as a means of recovering from STOP, the I-bit or the X-bit in
CCR respectively must be clear. (IRQ or XIRQ not masked).
Because the oscillator is stopped in STOP mode, a restart delay may be imposed to allow
oscillator stabilization upon leaving STOP. If the internal oscillator is being used, this delay is
required; however, if a stable external oscillator is being used, the DLY control bit can be used to
bypass this start-up delay. The DLY control bit is set by reset and can be optionally cleared during
initialization. If the DLY equal to zero option is used to avoid start-up delay on recovery from STOP,
then reset should not be used as the means of recovering from STOP, as this causes DLY to be
set again by reset, imposing the restart delay. This same delay also applies to power-on-reset,
regardless of the state of the DLY control bit, but does not apply to a reset while the clocks are
running. See Section 4.3.2.4.

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-17

Power-on reset
(POR)

Highest

Priority

External
reset

Clock monitor fail

(CME = 1)

Delay
(128/4064 cycles)

Lowest
COP watchdog
timeout
(NOCOP = 0)

Load program counter

with contents of
$FFFE, $FFFF
(vector fetch)

Load program counter

with contents of
$FFFC, $FFFD
(vector fetch)

Load program counter

with contents of
$FFFA, $FFFB
(vector fetch)

Set S, X, and I bits

in CCR.
Reset MCU hardware

1A
Begin an instruction
sequence

Yes

X-bit in
CCR set?
No

XIRQ pin
low?

Yes

Stack CPU registers.

Set X and I bits.
Fetch vector at
$FFF4, $FFF5

See Section 5.1.1

Figure 5-1 Processing flow out of reset (1 of 2)

TPG

MOTOROLA
5-18

RESETS AND INTERRUPTS

MC68HC11PA8

100

Yes

I-bit in
CCR set?
No
I-bit interrupt
pending?

Stack
CPU registers

Yes

Fetch
opcode

Stack CPU registers.

Set I bit.
Fetch vector at
$FFF8, $FFF9

Legal
opcode?
Yes
Yes

WAI?

Stack
CPU registers

No
Stack CPU registers.
Set I bit.
Fetch vector at
$FFF6, $FFF7

Yes

Interrupt
yet?

SWI?

No
Restore
CPU registers
from Stack

Yes

RTI?

Set I-bit

No
Execute this
instruction

Resolve interrupt
priority and fetch vector
for highest pending
source (Figure 5-3)

Start next instruction

sequence

Figure 5-2 Processing flow out of reset (2 of 2)

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-19

101

Begin

X-bit in
CCR set?

Yes

XIRQ pin
low?

Yes

Set X-bit in CCR.

Fetch vector at
$FFF4, $FFF5

Highest priority
interrupt?

Yes

Fetch vector

IRQ?

Fetch vector at
$FFF2, $FFF3

Yes

No
RTII = 1?

Yes

RTIF = 1?

Yes

Fetch vector at
$FFF0, $FFF1

Yes

Fetch vector at
$FFEE, $FFEF

Yes

Fetch vector at
$FFEC, $FFED

Yes

Fetch vector at
$FFEA, $FFEB

Yes

Fetch vector at
$FFE8, $FFE9

IC1I = 1?

Yes

IC1F = 1?
No

IC2I = 1?

Yes

IC2F = 1?
No

IC3I = 1?

Yes

IC3F = 1?
No

OC1I = 1?

Yes

OC1F = 1?
No

No
2A

Figure 5-3 Interrupt priority resolution (1 of 3)

TPG

MOTOROLA
5-20

RESETS AND INTERRUPTS

MC68HC11PA8

102

OC2I = 1?

Yes

OC2F = 1?

Yes

Fetch vector at
$FFE6, $FFE7

Yes

Fetch vector at
$FFE4, $FFE5

Yes

Fetch vector at
$FFE2, $FFE3

Yes

Fetch vector at
$FFE0, $FFE1

Yes

Fetch vector at
$FFD4, $FFD5

Yes

Fetch vector at
$FFDE, $FFDF

OC3I = 1?

Yes

OC3F = 1?
No

Yes
OC4I = 1?

OC4F = 1?

I4/O5I = 1?

Yes

I4/O5F = 1?
No

MIEN = 1?

Yes

MIF = 1?
No

TOI = 1?
No

Yes

TOF = 1?
No

Figure 5-4 Interrupt priority resolution (2 of 3)

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-21

103

PAOVI = 1?

Yes

PAII = 1?

SPIE = 1?

Yes

Fetch vector at
$FFDC, $FFDD

Yes

Fetch vector at
$FFDA, $FFDB

Yes

Fetch vector at
$FFD8, $FFD9

Yes

PAOVF = 1?

PAIF = 1?
No

Yes

SPIF = 1?
No
MODF = 1?

Yes

SCI
interrupt?
No

Fetch vector at
$FFD6, $FFD7

Yes

Spurious interrupt take IRQ vector

Fetch vector at
$FFF2, $FFF3

Refer to Figure 5-6 for further details on SCI interrupts.

END

Figure 5-5 Interrupt priority resolution (3 of 3)

TPG

MOTOROLA
5-22

RESETS AND INTERRUPTS

MC68HC11PA8

104

Begin

RDRF = 1?

Yes

OR = 1?

Yes

TDRE = 1?

Yes

TIE = 1?

Yes

TCIE = 1?

RE = 1?

Yes

IDLE = 1?

Yes

TC = 1?

RIE = 1?

TE = 1?

Yes

ILIE = 1?
No

Yes

RE = 1?

Yes

No valid SCI
interrupt request

Valid SCI
interrupt request

Figure 5-6 Interrupt source resolution within the SCI subsystem

TPG

MC68HC11PA8

RESETS AND INTERRUPTS

MOTOROLA
5-23

105

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

MOTOROLA
5-24

RESETS AND INTERRUPTS

MC68HC11PA8

106

6
PARALLEL INPUT/OUTPUT
The MC68HC(7)11PA8/MC68HC(7)11PB8 has up to 39 input/output lines and 10 input-only lines
(including the XIRQ and IRQ pins), depending on the operating mode. To enhance the I/O
functions, the data bus of this microcontroller is non-multiplexed. The following table is a summary
of the configuration and features of each port.

Table 6-1 Port configuration

Port
A
B
C
D
E
F
G

Note:

Input
pins

Output
pins

Bidirectional
pins
8
8
8
6

8
1

Alternative functions
Timer
High order address
Data bus
SCI and SPI / I2C bus
A/D converter / I2C bus
Low order address
R/W

Do not confuse pin function with the electrical state of that pin at reset. All
general-purpose I/O pins that are configured as inputs at reset are in a high-impedance
state and the contents of the port data registers are undefined; in port descriptions, a
u indicates this condition. The pin function is mode dependent.

Pins PE5 and PE4 are not present on the 64-pin QFP packaged MC68HC11PA8, which has
only six port E pins. They are present on the 64-pin MC68HC11PB8 and on 68-pin CLCC
packages (available as samples only). Contact your local Motorola Sales Office for more
information.

TPG

MC68HC11PA8

PARALLEL INPUT/OUTPUT

MOTOROLA
6-1

107

6.1

Port A

Port A is an 8-bit bidirectional port, with both data and data direction registers. In addition to their
I/O capability, port A pins are shared with timer functions, as shown in the following table.

Pin
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

Alternative function
IC3
IC2
IC1
OC5 and/or OC1, or IC4
OC4 and/or OC1
OC3 and/or OC1
OC2 and/or OC1
PAI and/or OC1

See Section 10 for

more information.

On reset the pins are configured as general purpose high-impedance inputs.

6.1.1

PORTA Port A data register

Port A data (PORTA)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0000

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

undefined

This is a read/write register and is not affected by reset. The bits may be read and written at any
time, but, when a pin is allocated to its alternative function, a write to the corresponding register
bit has no effect on the pin state.

6.1.2

DDRA Data direction register for port A

Data direction A (DDRA)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

$0001

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

bit 0

State
on reset

DDA0 0000 0000

DDA[7:0] Data direction for port A

1 (set)

0 (clear)

The corresponding pin is configured as an output.

The corresponding pin is configured as an input.

TPG

MOTOROLA
6-2

PARALLEL INPUT/OUTPUT

MC68HC11PA8

108

6.2

Port B

Port B is an 8-bit bidirectional port, with both data and data direction registers. In addition to their
I/O capability, port B pins are used as the non-multiplexed high order address pins, as shown in
the following table.

Alternative
function
A8
A9
A10
A11
A12
A13
A14
A15

Pin
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

In expanded or test
mode, the pins
become the high
order address lines
and port B is not
included in the
memory map.

The state of the pins on reset is mode dependent. In single chip or bootstrap mode, port B pins
are high-impedance inputs with selectable internal pull-up resistors (see Section 6.9). In
expanded or test mode, port B pins are high order address outputs and PORTB/DDRB are not in
the memory map.

6.2.1

PORTB Port B data register

Port B data (PORTB)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0004

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

undefined

bit 0

State
on reset

The bits may be read and written at any time and are not affected by reset.

6.2.2

DDRB Data direction register for port B

Data direction B (DDRB)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

$0002

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0 0000 0000

DDB[7:0] Data direction for port B

1 (set)

0 (clear)

The corresponding pin is configured as an output.

The corresponding pin is configured as an input.

TPG

MC68HC11PA8

PARALLEL INPUT/OUTPUT

MOTOROLA
6-3

109

6.3

Port C

Port C is an 8-bit bidirectional port, with both data and data direction registers. In addition to their I/O
capability, port C pins are used as the non-multiplexed data bus pins, as shown in the following table.

Pin
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

Alternative
function
D0
D1
D2
D3
D4
D5
D6
D7

In expanded or test
mode, the pins
become the data
bus and port C is
not included in the
memory map.

The state of the pins on reset is mode dependent. In single chip or bootstrap mode, port C pins
are high-impedance inputs. In expanded or test modes, port C pins are the data bus I/O and
PORTC/DDRC are not in the memory map.

6.3.1

PORTC Port C data register

Port C data (PORTC)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0006

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

undefined

bit 1

bit 0

State
on reset

The bits may be read and written at any time and are not affected by reset.

6.3.2

DDRC Data direction register for port C

Address

Data direction C (DDRC)

$0007

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000

DDC[7:0] Data direction for port C

1 (set)

0 (clear)

The corresponding pin is configured as an output.

The corresponding pin is configured as an input.

TPG

MOTOROLA
6-4

PARALLEL INPUT/OUTPUT

MC68HC11PA8

110

6.4

Port D

Port D is a 6-bit bidirectional port, with both data and data direction registers. In addition to their
I/O capability, port D pins are shared with SCI and SPI or I2C bus functions, as shown in the
following table.

PD0
PD1

Alternative
function
RXD
TXD

See Section 10 for

more information.

PD2
PD3
PD4
PD5

MISO
MOSI / SDA
SCK / SCL
SS

See Section 9 and

Section 8 for more
information.

On reset the pins are configured as general purpose high-impedance inputs.

6.4.1

PORTD Port D data register

Port D data (PORTD)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0008

PD5

PD4

PD3

PD2

PD1

PD0

undefined

This is a read/write register and is not affected by reset. The bits may be read and written at any
time, but, when a pin is allocated to an alternative function, a write to the corresponding register
bit has no effect on the pin state.

6.4.2

DDRD Data direction register for port D

Data direction D (DDRD)

Address

bit 7

bit 6

$0009

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 0000 0000

Bits [7:6] Reserved; always read zero

DDD[5:0] Data direction for port D
1 (set)

0 (clear)

The corresponding pin is configured as an output.

The corresponding pin is configured as an input.

TPG

MC68HC11PA8

PARALLEL INPUT/OUTPUT

MOTOROLA
6-5

111

6.5

Port E

Port E is an input-only port. In addition to their input capability, port E pins are shared with A/D and
I2C bus functions, as shown in the following table.

Alternative
function
AD0
AD1
AD2
AD3
AD4(1)
AD5(1)
AD6 / SCL
AD7 / SDA

Pin
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7

See Section 11 and

Section 8 for more
information.

(1) The XOUT pin is not available on 64-pin QFP packaged devices,
but it is present on the 68-pin CLCC package. Pins PE4 and PE5
are available on the 64-pin QFP MC68HC11PB8 devices and on
all 68-pin CLCC devices.

On reset, the pins are configured as general purpose high-impedance inputs.

6.5.1

PORTE Port E data register

Port E data (PORTE)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$000A

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

undefined

This is a read-only register and is not affected by reset. The bits may be read at any time.

Note:

As port E shares pins with the A/D converter, a read of this register may affect any
conversion currently in progress, if it coincides with the sample portion of the
conversion cycle. Hence, normally port E should not be read during the sample portion
of any conversion.

TPG

MOTOROLA
6-6

PARALLEL INPUT/OUTPUT

MC68HC11PA8

112

6.6

Port F

Port F is an 8-bit bidirectional port, with both data and data direction registers. In addition to their
I/O capability, port F pins are used as the non-multiplexed low order address pins, as shown in the
following table.

Pin
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7

Alternative
function
A0
A1
A2
A3
A4
A5
A6
A7

In expanded or test
mode, the pins
become the low
order address and
port F is not
included in the
memory map.

The state of the pins on reset is mode dependent. In single chip or bootstrap mode, port F pins
are high-impedance inputs with selectable internal pull-up resistors (see Section 6.9). In
expanded or test modes, port F pins are low order address outputs and PORTF/DDRF are not in
the memory map.

6.6.1

PORTF Port F data register

Port F data (PORTF)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0005

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

undefined

bit 0

State
on reset

The bits may be read and written at any time and are not affected by reset.

6.6.2

DDRF Data direction register for port F

Data direction F (DDRF)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

$0003

DDF7

DDF6

DDF5

DDF4

DDF3

DDF2

DDF1

DDF0 0000 0000

DDF[7:0] Data direction for port F

1 (set)

0 (clear)

The corresponding pin is configured as an output.

The corresponding pin is configured as an input.

TPG

MC68HC11PA8

PARALLEL INPUT/OUTPUT

MOTOROLA
6-7

113

6.7

Port G

Port G is a 1-bit bidirectional port, with both data and data direction registers. In addition to its I/O
capability, the single port G pin is shared with the R/W function.

Alternative
function

PG7

R/W

See Section 2 for

more information.

Pin PG7 is a high-impedance input with a software selectable pull-up resistor in single chip and
bootstrap modes (see Section 6.9). In expanded or test modes, PG7 is the R/W output.

6.7.1

PORTG Port G data register

Port G data (PORTG)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$007E

PG7

undefined

This is a read/write register and is not affected by reset.

The bits may be read and written at any time, but, when a pin is allocated to its alternative function,
a write to the corresponding register bit has no effect on the pin state.

6.7.2

DDRG Data direction register for port G

Data direction G (DDRG)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$007F

DDG7

0000 0000

DDG7 Data direction for port G

1 (set)

0 (clear)

Pin PG7 is configured as an output.

Pin PG7 is configured as an input.

TPG

MOTOROLA
6-8

PARALLEL INPUT/OUTPUT

MC68HC11PA8

114

6.8

XIRQ and IRQ pins

These two pins may be used as general-purpose inputs. Their corresponding data bits, XPIN and
IPIN, are found in the SPSR register. The XIRQ and IRQ interrupts can be masked using the I and
X bits in the CCR (see Section 3).

6.8.1

SPSR SPI status register

SPI status (SPSR)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0029

SPIF

WCOL

MODF

XPIN

IPIN

0000 00uu

This register can be read at any time, but writing to it has no effect.

Bits [7, 6, 4] See Section 9 for details of these bits.

Bits [5, 3, 2] Not implemented; always read zero.
XPIN XIRQ pin input data bit
A read of this bit returns the logic level present on the XIRQ pin. It is not affected by reset.
IPIN IRQ pin input data bit
A read of this bit returns the logic level present on the IRQ pin. It is not affected by reset.

TPG

MC68HC11PA8

PARALLEL INPUT/OUTPUT

MOTOROLA
6-9

115

6.9

Internal pull-up resistors

Three of the ports (B, F and G) have internal, software selectable pull-up resistors under control
of the port pull-up assignment register (PPAR).

6.9.1

PPAR Port pull-up assignment register

Port pull-up assignment (PPAR)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

$002C

bit 2

bit 1

bit 0

State
on reset

GPPUE FPPUE BPPUE 0000 1111

Bits [7:4] Not implemented; always read zero.

Bit 3 This bit can be written, but has no function.

xPPUE Port x pin pull-up enable

These bits control the on-chip pull-up devices connected to all the pins on I/O ports B, F and G.
They are collectively enabled or disabled via the PAREN bit in the CONFIG register (see
Section 6.10.2).
1 (set)

Note:

Port x pin on-chip pull-up devices enabled.

0 (clear)

Port x pin on-chip pull-up devices disabled.

GPPUE, FPPUE and BPPUE have no effect in expanded mode since ports F and B are
dedicated address bus outputs, and port G provides the R/W signal.

6.10

System configuration

One bit in each of the following registers is directly concerned with the configuration of the I/O
ports. For full details on the other bits in the registers, refer to the appropriate section.

TPG

MOTOROLA
6-10

PARALLEL INPUT/OUTPUT

MC68HC11PA8

116

6.10.1

OPT2 System configuration options register 2

Address

System config. options 2 (OPT2)

$0038

bit 7

bit 6

bit 5

bit 4

bit 3

LIRDV CWOM STRCH IRVNE LSBF

bit 2

bit 1

bit 0

State
on reset

Normal operation.

IRVNE Internal read visibility/not E (refer to Section 4)

1 (set)

0 (clear)

Data from internal reads is driven out of the external data bus.
No visibility of internal reads on external bus.

In single chip mode this bit determines whether the E clock drives out from the chip.
1 (set)

0 (clear)

E pin is driven low.

E clock is driven out from the chip.

LSBF LSB first enable (refer to Section 9)

1 (set)

SPI data is transferred LSB first.

0 (clear)

SPI data is transferred MSB first.

SPR2 SPI clock rate select (refer to Section 9)

EXT4X XOUT clock output select (refer to Section 4)
1 (set)

Note:

EXTALi clock is output on the XOUT pin.

0 (clear)

4XCLK clock is output on the XOUT pin.

The XOUT pin is not available on 64-pin QFP packaged devices; see Section 4.

TPG

MC68HC11PA8

PARALLEL INPUT/OUTPUT

MOTOROLA
6-11

117

XIRQE Configure XIRQ for falling-edge-sensitive operation (refer to Section 4)

1 (set)

0 (clear)

6.10.2

Falling-edge-sensitive operation.
Low-level-sensitive operation.

CONFIG System configuration register

Address

Configuration control (CONFIG)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

4XCLK or EXTALi driven out on the XOUT pin.

XOUT pin disabled.

The XOUT pin is not available on 64-pin QFP packaged devices; see Section 4.

PAREN Pull-up assignment register enable

1 (set)

0 (clear)

Pull-ups can be enabled using PPAR register.

All pull-ups disabled.

NOSEC EEPROM security disabled (refer to Section 4)

1 (set)

Disable security.

0 (clear)

Enable security.

TPG

MOTOROLA
6-12

PARALLEL INPUT/OUTPUT

MC68HC11PA8

EEPROM is disabled from the memory map.

TPG

MC68HC11PA8

PARALLEL INPUT/OUTPUT

MOTOROLA
6-13

119

6
THIS PAGE LEFT BLANK INTENTIONALLY

TPG

MOTOROLA
6-14

PARALLEL INPUT/OUTPUT

MC68HC11PA8

120

7
SERIAL COMMUNICATIONS INTERFACE
The serial communications interface (SCI) is a universal asynchronous receiver transmitter
(UART). It has a non-return to zero (NRZ) format (one start, eight or nine data, and one stop bit)
that is compatible with standard RS-232 systems.
The SCI shares I/O with two of port Ds pins:

Pin
PD0
PD1

Alternative
function
RXD
TXD

The SCI transmit and receive functions are enabled by TE and RE respectively, in SCCR2.
The SCI features enabled on this MCU include: 13-bit modulus prescaler, idle line detect,
receiver-active flag, transmitter and receiver hardware parity. A block diagram of the enhanced
baud rate generator is shown in Figure 7-1. See Table 7-1 for example baud rate control values.

ST4XCK

Internal
phase 2 clock

13-bit counter

Reset
13-bit compare

Sync

SCBDH/L: SCI baud control

Transmitter
baud rate
clock

Receiver
baud rate
clock

Figure 7-1 SCI baud rate generator circuit diagram

TPG

MC68HC11PA8

SERIAL COMMUNICATIONS INTERFACE

MOTOROLA
7-1

121

7.1

Data format

The serial data format requires the following conditions:

An idle-line condition before transmission or reception of a message.

A start bit, logic zero, transmitted or received, that indicates the start of each
character.

Data that is transmitted and received least significant bit (LSB) first.

A stop bit, logic one, used to indicate the end of a frame. (A frame consists
of a start bit, a character of eight or nine data bits, and a stop bit.)

A break (defined as the transmission or reception of a logic zero for some

multiple number of frames).

Selection of the word length is controlled by the M bit of SCCR1.

7.2

Transmit operation

The SCI transmitter includes a parallel data register (SCDRH/SCDRL) and a serial shift register.
The contents of the shift register can only be written through the parallel data register. This double
buffered operation allows a character to be shifted out serially while another character is waiting
in the parallel data register to be transferred into the shift register. The output of the shift register
is applied to TXD as long as transmission is in progress or the transmit enable (TE) bit of serial
communication control register 2 (SCCR2) is set. The block diagram, Figure 7-2, shows the
transmit serial shift register and the buffer logic at the top of the figure.

7.3

Receive operation

During receive operations, the transmit sequence is reversed. The serial shift register receives
data and transfers it to the parallel receive data registers (SCDRH/SCDRL) as a complete word.
This double buffered operation allows a character to be shifted in serially while another character
is still in the serial data registers. An advanced data recovery scheme distinguishes valid data from
noise in the serial data stream. The data input is selectively sampled to detect receive data, and
majority sampling logic determines the value and integrity of each bit.

TPG

MOTOROLA
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SERIAL COMMUNICATIONS INTERFACE

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122

T8 SCDRH/SCDRL (transmit buffer)

LOOPS

10/11-bit TX shift register

WOMS

H 8 7

TXD

0 L

M
WAKE

ST4XCK
clock

LOOPS

ILT

Transmitter
control

TE
SBK

TIE

Rate generator

Flag control
WAKE

ILIE

RWU

Receiver

RWU

SBK

SCBDL

SCCR2

TCIE
RIE

WOMS

SCBDH

SCCR1

control

LOOPS

WOMS

ILT

10/11-bit RX shift register

8 7

STOP

RAF

SCSR2
FE

IDLE

SCSR1
RDRF

RXD

SCDRH/SCDRL (receive buffer)

TDRE

Data
recovery

START

OR
RIE

&
IDLE
ILIE

RDRF
RIE

SCI interrupt request

+
TC
TCIE

TDRE
TIE

Note: = always reads as zero

&
Internal data bus

Figure 7-2 SCI block diagram

TPG

MC68HC11PA8

SERIAL COMMUNICATIONS INTERFACE

MOTOROLA
7-3

123

7.4

Wake-up feature

The wake-up feature reduces SCI service overhead in multiple receiver systems. Software for
each receiver evaluates the first character or frame of each message. All receivers are placed in
wake-up mode by writing a one to the RWU bit in the SCCR2 register. When RWU is set, the
receiver-related status flags (RDRF, IDLE, OR, NF, FE, and PF) are inhibited (cannot be set).
Although RWU can be cleared by a software write to SCCR2, to do so would be unusual. Normally
RWU is set by software and is cleared automatically with hardware. Whenever a new message
begins, logic alerts the dormant receivers to wake up and evaluate the initial character of the new
message.
Two methods of wake-up are available: idle-line wake-up and address mark wake-up. During
idle-line wake-up, a dormant receiver activates as soon as the RXD line becomes idle. In the
address mark wake-up, logic one in the most significant bit (MSB) of a character activates all
sleeping receivers. To use either receiver wake-up method, establish a software addressing
scheme to allow the transmitting devices to direct messages to individual receivers or to groups
of receivers. This addressing scheme can take any form as long as all transmitting and receiving
devices are programmed to understand the same scheme.

7.4.1

Idle-line wake-up

Clearing the WAKE bit in SCCR1 register enables idle-line wake-up mode. In idle-line wake-up
mode, all receivers are active (RWU bit in SCCR2 = 0) when each message begins. The first
frames of each message are addressing frames. Each receiver in the system evaluates the
addressing frames of a message to determine if the message is intended for that receiver. When
a receiver finds that the message is not intended for it, it sets the RWU bit. Once set, the RWU
control bit disables all but the necessary receivers for the remainder of the message, thus reducing
software overhead for the remainder of that message. As soon as an idle line is detected by
receiver logic, hardware automatically clears the RWU bit so that the first frames of the next
message can be evaluated by all receivers in the system. This type of receiver wake-up requires
a minimum of one idle frame time between messages, and no idle time between frames within a
message.

7.4.2

Address-mark wake-up

Setting the WAKE bit in SCCR1 register enables address-mark wake-up mode. The address-mark
wake-up method uses the MSB of each frame to differentiate between address information
(MSB = 1) and actual message data (MSB = 0). All frames consist of seven information bits (eight
bits if M bit in SCCR1 = 1) and an MSB which, when set to one, indicates an address frame. The
first frames of each message are addressing frames. Receiver logic evaluates these marked
frames to determine the receivers for which that message is intended. When a receiver finds that
the message is not intended for it, it sets the RWU bit. Once set, the RWU control bit disables all
but the necessary receivers for the remainder of the message, thus reducing software overhead
TPG

MOTOROLA
7-4

SERIAL COMMUNICATIONS INTERFACE

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124

for the remainder of that message. When the next message begins, its first frame will have the
MSB set which will automatically clear the RWU bit and indicate that this is an addressing frame.
This frame is always the first frame received after wake-up because the RWU bit is cleared before
the stop bit for the first frame is received. This method of wake-up allows messages to include idle
times, however, there is a loss in efficiency due to the extra bit time required for the address bit in
each frame.

7.5

SCI error detection

Four error conditions can occur during SCI operation. These error conditions are: serial data
register overrun, received bit noise, framing, and parity error. Four bits (OR, NF, FE, and PF) in
serial communications status register 1 (SCSR1) indicate if one of these error conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be transferred from the receive
shift register to the serial data registers (SCDRH/SCDRL) and the registers are already full (RDRF
bit is set). When an overrun error occurs, the data that caused the overrun is lost and the data that
was already in serial data registers is not disturbed. The OR is cleared when the SCSR is read
(with OR set), followed by a read of the SCI data registers.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and
stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is
read (with FE equal to one) followed by a read of the SCI data registers.

When no stop bit is detected in the received data character, the framing error (FE) bit is set. FE is
set at the same time as the RDRF. If the byte received causes both framing and overrun errors,
the processor only recognizes the overrun error. The framing error flag inhibits further transfer of
data into the SCI data registers until it is cleared. The FE bit is cleared when the SCSR is read
(with FE equal to one) followed by a read of the SCI data registers.
The parity error flag (PF) is set if received data has incorrect parity. The flag is cleared by a read
of SCSR1 with PE set, followed by a read of SCDR.

7.6

SCI registers

There are eight addressable registers in the SCI. SCBDH, SCBDL, SCCR1, and SCCR2 are
control registers. The contents of these registers control functions and indicate conditions within
the SCI. The status registers SCSR1 and SCSR2 contain bits that indicate certain conditions
within the SCI. SCDRH and SCDRL are SCI data registers. These double buffered registers are
used for the transmission and reception of data, and are used to form the 9-bit data word for the
SCI. If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be accessed. Note that if
9-bit data format is used, the upper register should be written first to ensure that it is transferred
to the transmitter shift register with the lower register.

TPG

MC68HC11PA8

SERIAL COMMUNICATIONS INTERFACE

MOTOROLA
7-5

125

7.6.1

SCBDH, SCBDL SCI baud rate control registers

bit 5

bit 4

bit 7

bit 6

SCI baud rate high (SCBDH)

$0070

BTST

BSPL

BRST SBR12 SBR11 SBR10 SBR9

SBR8 0000 0000

SCI baud rate low (SCBDL)

$0071

SBR7

SBR6

SBR5

SBR0 0000 0100

SBR4

bit 3

SBR3

bit 2

SBR2

bit 1

SBR1

bit 0

State
on reset

Address

The contents of this register determine the baud rate of the SCI.
BTST Baud register test (Test mode only)
BSPL Baud rate counter split (Test mode only)
BRST Baud rate reset (Test mode only)
SBR[12:0] SCI baud rate selects
Use the following formula to calculate SCI baud rate. Refer to the table of baud rate control values
for example rates:
ST4XCK
SCI baud rate = -----------------------------16 ( 2BR )

where the baud rate control value (BR) is the contents of SCBDH/L (BR = 1, 2, 3,... 8191).
For example, to obtain a baud rate of 1200 with a ST4XCK frequency of 12MHz, the baud register
(SCBDH/L) should contain $0138 (see Table 7-1).
The clock rate generator is disabled if BR = 0, or if neither the receiver nor transmitter is enabled
(both RE and TE in SCCR2 are cleared).
Writes to the baud rate registers will only be successful if the last (or only) byte written is SCBDL.
The use of an STD instruction is recommended as it guarantees that the bytes are written in the
correct order.

Note:

ST4XCK may be the output of the PLL circuit or it may be the EXTAL input of the MCU
(see Section 2.5 and Figure 10-1).

TPG

MOTOROLA
7-6

SERIAL COMMUNICATIONS INTERFACE

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126

Table 7-1 Example SCI baud rate control values

Target
baud
rate
110
150
300
600
1200
2400
4800
9600
19200
38400

7.6.2

ST4XCK frequency
8 MHz
12 MHz
16 MHz
Dec value Hex value Dec value Hex value Dec value Hex value
2272
$08E0
3409
$0D51
4545
$11C1
1666
$0682
2500
$09C4
3333
$0D05
833
$0341
1250
$04E2
1666
$0682
416
$01A0
625
$0271
833
$0341
208
$00D0
312
$0138
416
$01A0
104
$0068
156
$009C
208
$00D0
52
$0034
78
$004E
104
$0068
26
$001A
39
$0027
52
$0034
13
$000D
20
$0014
26
$001A
13

$000D

SCCR1 SCI control register 1

Address

SCI control 1 (SCCR1)

bit 7

bit 6

$0072 LOOPS WOMS

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

WAKE

ILT

0000 0000

The SCCR1 register provides the control bits that determine word length and select the method
used for the wake-up feature.
LOOPS SCI loop mode enable
1 (set)

0 (clear)

SCI transmit and receive are disconnected from TXD and RXD pins,
and transmitter output is fed back into the receiver input.
SCI transmit and receive operate normally.

Short (SCI counts consecutive ones after start bit).

This bit determines which of two types of idle line detection method is used by the SCI receiver.
In short mode the stop bit and any bits that were ones before the stop bit will be considered as
part of that string of ones, possibly resulting in erroneous or premature detection of an idle line
condition. In long mode the SCI system does not begin counting ones until a stop bit is received.

PE Parity enable
1 (set)

Parity enabled.

0 (clear)

Parity disabled.

PT Parity type
1 (set)

0 (clear)

Parity odd (an odd number of ones causes parity bit to be zero, an
even number of ones causes parity bit to be one).
Parity even (an even number of ones causes parity bit to be zero, an
odd number of ones causes parity bit to be one).

TPG

MOTOROLA
7-8

SERIAL COMMUNICATIONS INTERFACE

MC68HC11PA8

128

7.6.3

SCCR2 SCI control register 2

SCI control 2 (SCCR2)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0073

TIE

TCIE

RIE

ILIE

RWU

SBK

0000 0000

The SCCR2 register provides the control bits that enable or disable individual SCI functions.
TIE Transmit interrupt enable
1 (set)

0 (clear)

SCI interrupt requested when TDRE status flag is set.

TDRE interrupts disabled.

TCIE Transmit complete interrupt enable

1 (set)

0 (clear)

SCI interrupt requested when TC status flag is set.

TC interrupts disabled.

RIE Receiver interrupt enable

1 (set)

0 (clear)

SCI interrupt requested when RDRF flag or the OR status flag is set.
RDRF and OR interrupts disabled.

ILIE Idle line interrupt enable

1 (set)

0 (clear)

SCI interrupt requested when IDLE status flag is set.

IDLE interrupts disabled.

TE Transmitter enable
1 (set)

Transmitter enabled.

0 (clear)

Transmitter disabled.

RE Receiver enable
1 (set)

Receiver enabled.

0 (clear)

Receiver disabled.

RWU Receiver wake-up control

1 (set)

0 (clear)

Wake-up enabled and receiver interrupts inhibited.

Normal SCI receiver.

SBK Send break

1 (set)

0 (clear)

Break codes generated as long as SBK is set.

Break generator off.
TPG

MC68HC11PA8

SERIAL COMMUNICATIONS INTERFACE

MOTOROLA
7-9

129

7.6.4

SCSR1 SCI status register 1

SCI status 1 (SCSR1)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0074

TDRE

RDRF

IDLE

1100 0000

The bits in SCSR1 indicate certain conditions in the SCI hardware and are automatically cleared
by special acknowledge sequences.
TDRE Transmit data register empty flag
1 (set)

0 (clear)

SCDR empty.
SCDR busy.

This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR1 with TDRE set and
then writing to SCDR.
TC Transmit complete flag

1 (set)

0 (clear)

Transmitter idle.
Transmitter busy.

This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress).
Clear the TC flag by reading SCSR1 with TC set and then writing to SCDR.
RDRF Receive data register full flag
1 (set)

0 (clear)

SCDR full.
SCDR empty.

Once cleared, IDLE is not set again until the RXD line has been active and becomes idle again.
RDRF is set if a received character is ready to be read from SCDR. Clear the RDRF flag by
reading SCSR1 with RDRF set and then reading SCDR.
IDLE Idle line detected flag
1 (set)

0 (clear)

RXD line is idle.

RXD line is active.

This flag is set if the RXD line is idle. Once cleared, IDLE is not set again until the RXD line has
been active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by
reading SCSR1 with IDLE set and then reading SCDR.

TPG

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SERIAL COMMUNICATIONS INTERFACE

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130

OR Overrun error flag

1 (set)

0 (clear)

Overrun detected.
No overrun.

OR is set if a new character is received before a previously received character is read from SCDR.
Clear the OR flag by reading SCSR1 with OR set and then reading SCDR.
NF Noise error flag
1 (set)

0 (clear)

Noise detected.
Unanimous decision.

NF is set if the majority sample logic detects anything other than a unanimous decision. Clear NF
by reading SCSR1 with NF set and then reading SCDR.
FE Framing error
1 (set)

0 (clear)

Zero detected.
Stop bit detected.

FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading
SCSR1 with FE set and then reading SCDR.

PF Parity error flag

1 (set)

0 (clear)

Incorrect parity detected.

Parity correct.

PF is set if received data has incorrect parity. Clear PF by reading SCSR1 with PE set and then
reading SCDR.

TPG

MC68HC11PA8

SERIAL COMMUNICATIONS INTERFACE

MOTOROLA
7-11

131

7.6.5

SCSR2 SCI status register 2

SCI status 2 (SCSR2)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0075

RAF

0000 0000

In the SCSR2 only bit 0 is used, to indicate receiver active. The other seven bits always read zero.
Bits [7:1] Not implemented; always read zero
RAF Receiver active flag (read only)
1 (set)

0 (clear)

7.6.6

A character is being received.

A character is not being received.

SCDRH, SCDRL SCI data high/low registers

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

SCI data high (SCDRH)

$0076

undefined

SCI data low (SCDRL)

$0077

R7T7

R6T6

R5T5

R4T4

R3T3

R2T2

R1T1

R0T0

undefined

SCDRH/SCDRL is a parallel register that performs two functions. It is the receive data register
when it is read, and the transmit data register when it is written. Reads access the receive data
buffer and writes access the transmit data buffer. Data received or transmitted is double buffered.
If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be accessed. Note that if 9-bit
data format is used, the upper register should be written first to ensure that it is transferred to the
transmitter shift register with the lower register.
R8 Receiver bit 8
Ninth serial data bit received when SCI is configured for a nine data bit operation
T8 Transmitter bit 8
Ninth serial data bit transmitted when SCI is configured for a nine data bit operation
Bits [5:0] Not implemented; always read zero
R/T[7:0] Receiver/transmitter data bits [7:0]
SCI data is double buffered in both directions.

TPG

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132

7.7

Status flags and interrupts

The SCI transmitter has two status flags. These status flags can be read by software (polled) to
tell when certain conditions exist. Alternatively, a local interrupt enable bit can be set to enable
each of these status conditions to generate interrupt requests. Status flags are automatically set
by hardware logic conditions, but must be cleared by software. This provides an interlock
mechanism that enables logic to know when software has noticed the status indication. The
software clearing sequence for these flags is automatic functions that are normally performed
in response to the status flags also satisfy the conditions of the clearing sequence.
TDRE and TC flags are normally set when the transmitter is first enabled (TE set to one). The
TDRE flag indicates there is room in the transmit queue to store another data character in the
transmit data register. The TIE bit is the local interrupt mask for TDRE. When TIE is zero, TDRE
must be polled. When TIE and TDRE are one, an interrupt is requested.
The TC flag indicates the transmitter has completed the queue. The TCIE bit is the local interrupt
mask for TC. When TCIE is zero, TC must be polled; when TCIE is one and TC is one, an interrupt
is requested.
Writing a zero to TE requests that the transmitter stop when it can. The transmitter completes any
transmission in progress before shutting down. Only an MCU reset can cause the transmitter to
stop and shut down immediately. If TE is cleared when the transmitter is already idle, the pin
reverts to its general purpose I/O function (synchronized to the bit-rate clock). If anything is being
transmitted when TE is cleared, that character is completed before the pin reverts to general
purpose I/O, but any other characters waiting in the transmit queue are lost. The TC and TDRE
flags are set at the completion of this last character, even though TE has been disabled.

7.7.1

Receiver flags

The SCI receiver has seven status flags, three of which can generate interrupt requests. The
status flags are set by the SCI logic in response to specific conditions in the receiver. These flags
can be read (polled) at any time by software. Refer to Figure 7-3, which shows SCI interrupt
arbitration.
When an overrun takes place, the new character is lost, and the character that was in its way in
the parallel receive data register (RDR) is undisturbed. RDRF is set when a character has been
received and transferred into the parallel RDR. The OR flag is set instead of RDRF if overrun
occurs. A new character is ready to be transferred into the RDR before a previous character is read
from the RDR.
The NF, FE and PF flags provide additional information about the character in the RDR, but do not
generate interrupt requests.
The receiver active flag (RAF) indicates that the receiver is busy.
The last receiver status flag and interrupt source come from the IDLE flag. The RXD line is idle if it has
constantly been at logic one for a full character time. The IDLE flag is set only after the RXD line has
been busy and becomes idle. This prevents repeated interrupts for the time RXD remains idle.
TPG

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133

Begin

RDRF = 1?

Yes

OR = 1?

Yes

TDRE = 1?

Yes

IDLE = 1?
No

TIE = 1?

Yes

TCIE = 1?

RE = 1?

Yes

TC = 1?

RIE = 1?

TE = 1?

Yes

ILIE = 1?
No

Yes

RE = 1?

Yes

No valid SCI
interrupt request

Valid SCI
interrupt request

Figure 7-3 Interrupt source resolution within SCI

TPG

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134

I2C BUS
The I2C bus is a two wire, bidirectional serial bus that provides a simple, efficient way to exchange
data between devices. Being a two-wire device, the I2C bus minimizes the need for large numbers
of connections between devices, and eliminates the need for an address decoder.
This interface is suitable for applications involving frequent communications between a number of
devices over short distances. The number of devices connected to the I2C bus is limited only by a
maximum bus capacitance of 400pF; it has a maximum data rate of 100 kbits per second.
The I2C bus system is a true multi-master bus including collision detection and arbitration to
prevent data corruption if two or more masters intend to control the bus simultaneously. This
feature provides the capability for complex applications with multi-processor control.
The system shares I/O either with two of port Es pins, or with two of port Ds pins, depending on
the state of the MBSP bit in the CONFIG register:

MBSP
1
0

I2C bus function

SCL
SDA
SCL
SDA

Pin
PD4
PD3
PE7
PE6

The MEN bit in the I2C bus control register (MCR) enables the I2C function.

I2C bus is a proprietary Philips interface bus.

TPG

MC68HC11PA8

I2C

BUS

MOTOROLA
8-1

135

8.1

Multi-master operation

Software-programmable for one of 32 different serial clock frequencies

Software-selectable acknowledge bit

Interrupt-driven byte-by-byte data transfer

Arbitration-lost-driven interrupt with automatic switching from master to slave mode

Calling address identification interrupt

Generates/detects the START or STOP signal

Repeated START signal generation

Generates/recognizes the acknowledge bit

Bus busy detection

8.2

I2C bus features

I2C bus system configuration

The I2C bus system uses a serial data line and a serial clock line for the transfer of data. All the
devices connected to the I2C bus must have open drain or open collector outputs; a logic AND
function is used on both lines with two pull-up resistors. Although the I2C bus operates in an
open-drain configuration, the port D drivers are implemented but in the off state (MBSP = 1). This
means that it is not possible to bring the SCL or SDA lines more than 0.5V above the VDD level
due to intrinsic on-chip diodes. When MBSP = 0, this restriction does not apply to port E (however,
maximum ratings restrictions do apply).

8.3

I2C bus protocol

A standard communication is normally composed of four parts: START signal, slave address
transmission, data transfer, and STOP signal. These signals are described in the following
sections and illustrated in Figure 8-1.

TPG

MOTOROLA
8-2

I2C

BUS

MC68HC11PA8

136

MC68HC11PA8

I2C

BUS

START signal

SDA

SCL

START signal

SDA

SCL

MSB

LSB

repeated
START signal

acknowledge bit

Figure 8-1 I2C bus transmission signal diagrams

TPG

MOTOROLA
8-3

137

MSB

LSB

STOP signal

no acknowledge

STOP signal

no acknowledge

8.3.1

START signal

When the bus is free (no master device engaging the bus; SCL and SDA lines are at a logic high),
a master may initiate communication by sending a START signal, which is defined as being a high
to low transition of SDA with SCL high. This signal denotes the beginning of a new data transfer
(each data transfer may contain several bytes of data), and wakes up all slaves.

8.3.2

Transmission of the slave address

The first byte of data transferred after the START signal is the slave address transmitted by the
master. This address is seven bits long, followed by a R/W bit which tells the slave the desired
direction of transfer of all the following bytes (until a STOP or repeated START signal).

8.3.3

Data transfer

Once successful slave addressing has been achieved, the data transfer can proceed byte by byte,
in the direction that was specified by the R/W bit.

Data can be changed only when SCL is low, and must be held stable while SCL is high. The MSB
is transmitted first. Each data byte is eight bits long, and there is one clock pulse on SCL for each
data bit. Every byte of data has to be followed by an acknowledge bit, which the receiving device
signals by pulling SDA low at the ninth clock. Therefore, one complete data byte transfer needs
nine clock pulses.
If the slave receiver does not acknowledge the master, then the SDA line is left high by the slave.
The master can then generate a STOP signal to abort the data transfer or a START signal to
commence a new calling (called a repeated start).
If the master receiver does not acknowledge the slave transmitter after one byte of transmission,
it means end of data to the slave, which then releases the SDA line so that the master can
generate the STOP or START signal.

8.3.4

STOP signal

The master can terminate the communication by generating a STOP signal to free the bus. A
STOP signal is defined as a low to high transition of SDA while SCL is high (see Figure 8-1).

TPG

MOTOROLA
8-4

I2C

BUS

MC68HC11PA8

138

8.3.5

Repeated START signal

A repeated START signal generates a START signal without first generating a STOP signal to
terminate the communication. This is used by the master to communicate with another slave, or
with the same slave in a different mode (transmit/receive mode), without releasing the bus.

8.3.6

Arbitration procedure

The I2C bus is a true multi-master system that allows more than one master to be connected to it.
If two or more masters try to control the bus at the same time, a clock synchronization procedure
determines the bus clock, for which the low period is equal to the longest clock low period and the
high period is equal to the shortest clock high period among the masters. A data arbitration
procedure determines the relative priority of the contending masters; a master loses arbitration if
it transmits logic 1 while another transmits logic 0. The losing master or masters then immediately
switch over to slave receive mode and stop all data and clock outputs. The transition from master
to slave mode does not generate a STOP condition in this case. At this point, the MAL bit in the
I2C bus status register (MSR) is set by hardware to indicate loss of arbitration.

8.3.7

Clock synchronization

Start counting high period

SCL1
Wait

SCL2

Internal counter register

SCL

Figure 8-2 Clock synchronization

Since wired-AND logic is performed on the SCL line, a high to low transition on SCL affects all the
devices connected on the bus. The devices start counting their low period and once a devices
clock has gone low, it holds the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of the SCL line if another device
TPG

MC68HC11PA8

I2C

BUS

MOTOROLA
8-5

139

clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with
the longest low period. Devices with shorter low periods enter a high wait state during this time
(see Figure 8-2). When all devices concerned have counted off their low period, the SCL line is
released and pulled high. There is then no difference between the device clocks and the state of
the SCL line, and all of them start counting their high periods. The first device to complete its high
period pulls the SCL line low again.

8.3.8

Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. The slave device
may hold SCL low after the completion of one byte of data transfer (nine bits). In such cases, it halts
the bus clock and forces the master clock in a wait state until the slave releases the SCL line.

8.4

Registers

8.4.1

CONFIG System configuration register

Address

Configuration control (CONFIG)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$003F ROMAD MBSP CLK4X PAREN NOSEC NOCOP ROMON EEON xxxx xxxx

The MBSP bit in this register configures the I2C bus system; refer to Section 4.3.2.1 for details of
the other bits.
CONFIG is made up of EEPROM cells and static working latches. The operation of the MCU is
controlled directly by these latches and not the EEPROM byte. When programming the CONFIG
register, the EEPROM byte is accessed. When the CONFIG register is read, the static latches are
accessed.
These bits can be read at any time. The value read is the one latched into the register from the
EEPROM cells during the last reset sequence. A new value programmed into this register is not
readable until after a subsequent reset sequence.
Bits in CONFIG can be written at any time if SMOD = 1 (bootstrap or special test mode). If
SMOD = 0 (single chip or expanded mode), they can only be written using the EEPROM
programming sequence, and are neither readable nor active until latched via the next reset.
MBSP Synchronous serial interface select
1 (set)

0 (clear)

SPI is disabled. The I2C bus, if enabled, uses port D[4, 3] pins.
If enabled, the I2C bus uses port E[7, 6] pins.

When MBSP is cleared, and the I2C bus is enabled, A/D channels are not available on port E[7, 6] pins.
TPG

MOTOROLA
8-6

I2C

BUS

MC68HC11PA8

140

8.4.2

MADR I2C bus address register

Address

I2C bus address (MADR)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

$0040 MADR7 MADR6 MADR5 MADR4 MADR3 MADR2 MADR1

bit 0

State
on reset

0000 0000

MADR [7:1] Slave address bits

These bits define the slave address of the I2C bus, and are used in slave mode in conjunction with
the MAAS bit in the MSR register (see Section 8.4.5). These bits can be read and written at any
time.
Bit 0 not implemented; always reads zero

8.4.3

MFDR I2C bus frequency divider register

I2C bus frequency divider (MFDR)

Address

bit 7

bit 6

bit 5

$0041

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

MBC4 MBC3 MBC2 MBC1 MBC0 0000 0000

MBC[4:0] Clock rate select bits

These bits can be read and written at any time.

The serial bit clock frequency is equal to the E clock divided by the value shown in Table 8-1. For
a 2MHz E clock, the serial bit clock frequency of the I2C bus ranges from 460Hz to 90909Hz.
Table 8-1 I2C bus prescaler

MCB[4:0]
00000
00001
00010
00011
00100
00101
00110
00111

Divide E
Divide E
MCB[4:0]
clock by
clock by
22
01000
88
24
01001
96
28
01010
112
34
01011
136
44
01100
176
48
01101
192
56
01110
224
68
01111
272

MCB[4:0]
10000
10001
10010
10011
10100
10101
10110
10111

Divide E
Divide E
MCB[4:0]
clock by
clock by
352
11000
1408
384
11001
1536
448
11010
1792
544
11011
2176
704
11100
2816
768
11101
3072
896
11110
3584
1088
11111
4352

Bits [7:5] not implemented; always read zero

TPG

MC68HC11PA8

I2C

BUS

MOTOROLA
8-7

141

MCR I2C bus control register

8.4.4

I2C bus control (MCR)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0042

MEN

MIEN

MSTA

MTX

TXAK Transmit acknowledge bit

1 (set)

0 (clear)

No acknowledge signal response.

An acknowledge signal will be sent to the bus at the ninth clock bit
after receiving one byte of data.

This bit only has meaning in master receive mode.

Bits [2:0] not implemented; always read zero.
TPG

MOTOROLA
8-8

I2C

BUS

MC68HC11PA8

142

MSR I2C bus status register

8.4.5

I2C bus status (MSR)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

$0043

MCF

MAAS

MBB

MAL

SRW

MIF

bit 0

State
on reset

RXAK 1000 0001

Bits in this register can be read at any time; Bits 4 and 1 can be cleared, but otherwise, writing to
these bits has no effect.
MCF Data transferring
1 (set)

0 (clear)

Data transmit complete.

Data is being transferred.

MAAS I2C bus addressed as a slave

1 (set)

0 (clear)

I2C bus is addressed as a slave.

I2C bus is not addressed.

This bit is set when the address of the I2C bus (specified in MADR) matches the calling address.
An interrupt is generated providing the MIEN bit in the MCR register is set; the CPU then selects
its transmit/receive mode according to the state of the SRW bit.

Writing to the MCR register clears this bit.

MBB Bus busy
1 (set)

0 (clear)

Bus is busy.
Bus is idle.

This bit indicates the status of the bus. When a START signal is detected, MBB is set. When a
STOP signal is detected, MBB is cleared.
MAL Arbitration lost
1 (set)

0 (clear)

Arbitration lost.
Default state.

MAL is set by hardware when the arbitration procedure is lost during a master transmission mode.
This bit must be cleared by software.
Bit 3 Not implemented; always reads zero.

TPG

MC68HC11PA8

I2C

BUS

MOTOROLA
8-9

143

SRW Read/write command

1 (set)

0 (clear)

R/W command bit is set (read).

R/W command bit is clear (write).

When MAAS is set, the R/W command bit of the calling address sent from a master is latched into
this bit. On checking this bit, the CPU can select slave transmit/receive mode according to the
command of the master.
MIF I2C bus interrupt flag

An I2C bus interrupt is pending.

0 (clear)

No I2C bus interrupt is pending.

1 (set)

When this bit is set, an I2C bus interrupt is generated provided the MIEN bit in the MCR register
is set. MIF is set when one of the following events occurs:
1) The transfer of one byte of data is complete; MIF is set at the falling edge of
the ninth clock after the byte has been received.
2) A calling address is received which matches the address of the I2C bus in
slave receive mode.
3) Arbitration is lost.

MIF must be cleared by software in the interrupt routine.

RXAK Received acknowledge bit
1 (set)

0 (clear)

No acknowledge signal has been detected at the ninth clock after the
transmission of a byte of data.
An acknowledge bit has been received at the ninth clock after the
transmission of a byte of data.

MDR I2C bus data register

8.4.6

Address
I2C bus data (MDR)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0044 TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 undefined

These bits can be read and written at any time.

In master transmit mode, a write to this register will cause the data in it to be sent to the bus
automatically, MSB first. In master receive mode, a read of this register initiates the transfer of the
next incoming byte of data into the register. See Figure 8-3.

TPG

MOTOROLA
8-10

I2C

BUS

MC68HC11PA8

144

In slave transmit mode, the SCL line is forced low until data is written into this register, to prevent
transmission. Similarly, in slave receive mode, the data bus must be read before a transmission
can occur. Refer to Figure 8-4.

8.5

Programming considerations

8.5.1

Initialization

After a reset, the I2C bus control register (MCR) is in a default state. Before the I2C bus can be
used, it must be initialized as follows:
1) Configure the frequency divider register for the desired SCL frequency.
2) Configure the I2C bus address register (MADR) to define the slave address
of the I2C bus.
3) Set the MEN bit in the I2C bus control register (MCR) to enable the I2C system.
4) Configure the other bits in the MCR register.

8.5.2

START signal and the first byte of data

After the initialization procedure has been completed, serial data can be transmitted by selecting
the master transmitter mode. If the device is connected to a multi-master bus system, the state
of the I2C bus busy bit (MBB) must be tested to check whether the serial bus is free. If the bus is
free (MBB = 0), the START condition and the first byte (the slave address) can be sent. An
example of a program that does this is shown below:
CHFLAG

TXSTART

SEI
BRSET

MSR #$20 CHFLAG

BSET
BSET

MCR #$10
MCR #$20

LDAA
STAA
CLI

CALLING
MDR

;DISABLE INTERRUPT
;CHECK THE MBB BIT OF THE STATUS
;REGISTER. IF IT IS SET, WAIT
;UNTIL IT IS CLEAR.
;SET TRANSMIT MODE
;SET TRANSMIT MODE
;i.e. GENERATE START CONDITION
;GET THE CALLING ADDRESS
;TRANSMIT THE CALLING ADDRESS
;ENABLE INTERRUPT

TPG

MC68HC11PA8

I2C

BUS

MOTOROLA
8-11

145

8.5.3

Software response

The transmission or reception of a byte sets the data transferring bit, MCF, which indicates that
one byte of communication is finished. Also, the I2C bus interrupt bit, MIF, is set to generate an
I2C bus interrupt (if MIEN is set). Figure 8-3 and Figure 8-4 show an example of a typical I2C bus
interrupt routine. In the interrupt routine, the first step is for software to clear the MIF bit. The MCF
bit can be cleared by reading from the I2C bus data I/O register (MDR) in receive mode, or by
writing to MDR in transmit mode. Software may service the I2C bus I/O in the main program by
monitoring the MIF bit if the interrupt function is disabled. The following is an example of a software
response by a master transmitter in the interrupt routine:
ISR

TRANSMIT

8.5.4

BCLR
BRCLR

MSR #$02
MCR #$20 SLAVE

BRCLR
BRSET

MCR #$10 RECEIVE

MSR #$01 END

LDAA

DATABUF

;CLEAR THE MIF FLAG

;CHECK THE MSTA FLAG
;BRANCH IF SLAVE MODE
;CHECK THE MODE FLAG
;CHECK ACKNOWLEDGEMENT FROM
;RECEIVER
;IF NO ACKNOWLEDGEMENT, END OF
;TRANSMISSION
;GET THE NEXT BYTE OF DATA

Generation of a STOP signal

A data transfer ends with a STOP signal generated by the master device. A master transmitter can
simply generate a STOP signal after all the data has been transmitted; for example:
MASTX

END
EMASTX

BRSET

MSR #$01 END

LDAA

TXCNT

BEQ
LDAA
STAA
DEC
BRA
BCLR
RTI

END
DATABUF
MDR
TXCNT
EMASTX
MCR #$20

;IF NO ACKNOWLEDGEMENT,
;BRANCH TO END
;GET VALUE FROM THE
;TRANSMITTING COUNTER
;IF NO MORE DATA, BRANCH TO END
;GET NEXT BYTE OF DATA
;TRANSMIT THE DATA
;DECREASE THE TXCNT
;EXIT
;GENERATE A STOP CONDITION
;RETURN FROM INTERRUPT

If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data. This can be done by setting the transmit acknowledge bit
(TXAK) before reading the second last byte of data. Before reading the last byte of data, a STOP
signal must be generated first. The following is an example showing how a STOP signal is
generated by a master receiver.

TPG

MOTOROLA
8-12

I2C

BUS

MC68HC11PA8

146

MASR

LAMAR

ENMASR
NXMAR

8.5.5

DEC
BEQ
LDAA
DECA

RXCNT
ENMASR
RXCNT

BNE
BSET

NXMAR
MCR #$08

BRA
BCLR
LDAA
STAA
RTI

NXMAR
MCR #$20
MDR
RXBUF

;LAST BYTE TO BE READ

;CHECK SECOND LAST BYTE TO BE
;READ
;NOT LAST ONE OR SECOND LAST
;SECOND LAST, DISABLE
;ACKNOWLEDGEMENT TRANSMITTING
;NXMAR
;LAST ONE, GENERATE STOP SIGNAL
;READ DATA AND STORE

Generation of a repeated START signal

At the end of the data transfer, if the master still wants to communicate on the bus, it can generate
another START signal, followed by another slave address, without first generating a STOP signal.
For example:
RESTART

8.5.6

BCLR

MCR #$20

BSET
LDAA
STAA

MCR #$20
CALLING
MDR

;ANOTHER START (RESTART) IS

;GENERATED BY THESE TWO
;CONSECUTIVE INSTRUCTIONS
;GET THE CALLING ADDRESS
;TRANSMIT THE CALLING ADDRESS

Slave mode

In the slave interrupt service routine, the MAAS bit should be tested to check if a calling of its own
address has just been received. If MAAS is set, software should set the transmit/receive mode
select bit (MTX) according to the R/W command bit, SRW. Writing to the MCR clears the MAAS
bit automatically. A data transfer may then be initiated by writing to MDR or by performing a dummy
read from MDR.
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting
the next byte of data. If RXAK is set, this means an end of data signal from the master receiver, which
must then switch from transmitter mode to receiver mode by software. This is followed by a dummy
read, which releases the SCL line so that the master can generate a STOP signal.

TPG

MC68HC11PA8

I2C

BUS

MOTOROLA
8-13

147

8.5.7

Arbitration lost

Only one master can engage the device at one time. Those devices wishing to engage the bus, but
having lost arbitration, are immediately switched to slave receive mode by hardware. Their data output
to the SDA line is stopped, but the internal transmitting clock is still generated until the end of the byte
during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer
with MAL = 1 and MSTA = 0. If one master attempts to start transmission while the bus is being
engaged by another master, the hardware inhibits the transmission; the MSTA bit is cleared without
generating a STOP condition, an interrupt is generated, and MAL is set to indicate that the attempt to
engage the bus has failed. In these cases, the slave interrupt service routine should test MAL first; if
MAL is set, it should be cleared by software.

8.5.8

Operation during STOP and WAIT modes

During STOP mode, the I2C bus is disabled.

During WAIT mode, the I2C bus is idle, but wakes up when it receives a valid start condition in
slave mode. If the interrupt is enabled, the CPU comes out of WAIT mode after the end of a byte
of transmission.

TPG

MOTOROLA
8-14

I2C

BUS

MC68HC11PA8

148

Clear MIF

Master mode?

Yes

RX
TX/ RX?

Last byte
transmitted?

Yes

Last byte to
be read?

Yes

RXAK = 0?

Yes

Second last byte

to be read?

Write next byte to

MDR

Generate STOP
signal

Set TXAK = 1

Generate STOP
signal
Read data from
MDR and store

RTI

Figure 8-3 Example of a typical I2C bus interrupt routine (sheet 1 of 2)

TPG

MC68HC11PA8

I2C

BUS

MOTOROLA
8-15

149

Yes

Clear MAL

Arbitration lost?

Yes
MAAS = 1?

MAAS = 1?

Yes

RX
SRW = 1?

TX / RX?

8
Set TX mode

Yes

Set RX mode

ACK from receiver?

No
TX next byte
Write to MDR

Dummy read from

MDR

Read MDR and

store
Switch to RX
mode

Dummy read from

MDR

RTI

Figure 8-4 Example of a typical I2C bus interrupt routine (sheet 2 of 2)

TPG

MOTOROLA
8-16

I2C

BUS

MC68HC11PA8

150

9
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI), an independent serial communications subsystem, allows
the MCU to communicate synchronously with peripheral devices, such as transistor-transistor
logic (TTL) shift registers, liquid crystal (LCD) display drivers, analog-to-digital converter
subsystems, and other microprocessors. The SPI is also capable of inter-processor
communication in a multiple master system. The SPI system can be configured as either a master
or a slave device, with data rates as high as one half of the E clock rate when configured as a
master and as fast as the E clock rate when configured as a slave.
The SPI shares I/O with four of port Ds pins and is enabled by SPE in the SPCR.
Pin
PD2
PD3
PD4
PD5

Note:

9.1

Alternative function
MISO
MOSI / SDA
SCK / SCL
SS

If the MBSP bit in CONFIG is set, then the SPI is disabled and the I2C bus system, if
enabled, uses port D pins [4,3]. See Section 8.

Functional description

The central element in the SPI system is the block containing the shift register and the read data
buffer (see Figure 9-1). The system is single buffered in the transmit direction and double buffered
in the receive direction. This means that new data for transmission cannot be written to the shifter
until the previous transfer is complete; however, received data is transferred into a parallel read
data buffer so the shifter is free to accept a second serial character. As long as the first character
is read out of the read data buffer before the next serial character is ready to be transferred, no
overrun condition occurs. A single MCU register address is used for reading data from the read
data buffer and for writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write collision, and mode
fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those
functions that control the SPI system through the serial peripheral control register (SPCR).
TPG

MC68HC11PA8

SERIAL PERIPHERAL INTERFACE

MOTOROLA
9-1

151

9.2

SPI transfer formats

During an SPI transfer, data is simultaneously transmitted and received. A serial clock line
synchronizes shifting and sampling of the information on the two serial data lines. A slave select
line allows individual selection of a slave SPI device; slave devices that are not selected do not
interfere with SPI bus activities. On a master SPI device, the select line can optionally be used to
indicate a multiple master bus contention. Refer to Figure 9-2.

MISO
PD2

S
M
M

MCU
system clock

MOSI
PD3

8-bit shift register

Read data buffer

Divider

Shift control logic

Pin
control
logic

8 16 32 64 128

Clock
logic

SCK
PD4

SS
PD5

OPT2 Options register 2

MSTR

SPE

MSTR

SPR2

LSBF

Clock

SPI clock (master)

Select

DWOM

LSBF

SPE

SPI control

SPSR SPI status register

SPR0

SPR1

CPHA

CPOL

MSTR

DWOM

SPE

SPIE

MODF

WCOL

SPIF

SPIE

SPCR SPI control register

SPDR SPI data register

SPI interrupt
request

Internal bus

Figure 9-1 SPI block diagram

TPG

MOTOROLA
9-2

SERIAL PERIPHERAL INTERFACE

MC68HC11PA8

152

SCK cycle #
(for reference)

SCK (CPOL=0)

SCK (CPOL=1)
Sample input
Data out (CPHA=0)

MSB

LSB

Sample input
Data out (CPHA=1)

MSB

LSB

SS (to slave)
Note: this figure shows the LSBF=0 (default) case. If LSBF=1, data is transferred in the reverse order (LSB first).

Figure 9-2 SPI transfer format

9.2.1

Clock phase and polarity controls

Software can select one of four combinations of serial clock phase and polarity using two bits in
the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which
selects an active high or active low clock, and has no significant effect on the transfer format. The
clock phase (CPHA) control bit selects one of two different transfer formats. The clock phase and
polarity should be identical for the master SPI device and the communicating slave device. In
some cases, the phase and polarity are changed between transfers to allow a master device to
communicate with peripheral slaves having different requirements.

When CPHA equals zero, the SS line must be deasserted and reasserted between each
successive serial byte. Also, if the slave writes data to the SPI data register (SPDR) while SS is
low, a write collision error results.
When CPHA equals one, the SS line can remain low between successive transfers.

9.3

SPI signals

The following paragraphs contain descriptions of the four SPI signals: master in slave out (MISO),
master out slave in (MOSI), serial clock (SCK), and slave select (SS).
Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR
bit is clear, that line is disconnected from the SPI logic and becomes a general-purpose input. All
SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in
DDRD register.

TPG

MC68HC11PA8

SERIAL PERIPHERAL INTERFACE

MOTOROLA
9-3

153

9.3.1

Master in slave out

MISO is one of two unidirectional serial data signals. It is an input to a master device and an output
from a slave device. The MISO line of a slave device is placed in the high-impedance state if the
slave device is not selected.

9.3.2

Master out slave in

The MOSI line is the second of the two unidirectional serial data signals. It is an output from a
master device and an input to a slave device. The master device places data on the MOSI line a
half-cycle before the clock edge that the slave device uses to latch the data.

9.3.3

Serial clock

SCK, an input to a slave device, is generated by the master device and synchronizes data
movement in and out of the device through the MOSI and MISO lines. Master and slave devices
are capable of exchanging a byte of information during a sequence of eight clock cycles.
There are four possible timing relationships that can be chosen by using control bits CPOL and CPHA
in the serial peripheral control register (SPCR). Both master and slave devices must operate with the
same timing. The SPI clock rate select bits of the master device, SPR[2:0], select the clock rate.
SPR[1:0] are found in the SPCR register and SPR2 is in the OPT2 register. In a slave device, SPR[2:0]
have no effect on the operation of the SPI.

9
9.3.4

Slave select

The slave select SS input of a slave device must be externally asserted before a master device
can exchange data with the slave device. SS must be low before data transactions begin and must
stay low for the duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag (MODF) is set
in the serial peripheral status register (SPSR). To disable the mode fault circuit, write a one in bit
5 of the port D data direction register. This sets the SS pin to act as a general-purpose output,
rather than a dedicated input to the slave select circuit, thus inhibiting the mode fault flag. The
other three lines are dedicated to the SPI whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS. CPHA settings should
be identical for master and slave. When CPHA = 0, the shift clock is the OR of SS with SCK. In
this clock phase mode, SS must go high between successive characters in an SPI message.
When CPHA = 1, SS can be left low between successive SPI characters. In cases where there is
only one SPI slave MCU, its SS line can be tied to VSS as long as only CPHA = 1 clock mode is
used.

TPG

MOTOROLA
9-4

SERIAL PERIPHERAL INTERFACE

MC68HC11PA8

154

9.4

SPI system errors

Two kinds of system errors can be detected by the SPI system. The first type of error arises in a
multiple-master system when more than one SPI device simultaneously tries to be a master. This
error is called a mode fault. The second type of error, write collision, indicates that an attempt was
made to write data to the SPDR while a transfer was in progress.
When the SPI system is configured as a master and the SS input line goes to active low, a mode
fault error has occurred usually because two devices have attempted to act as master at the
same time. In the case where more than one device is concurrently configured as a master, there
is a chance of contention between two pin drivers. For push-pull CMOS drivers, this contention
can cause permanent damage. The mode fault detection circuitry attempts to protect the device
by disabling the drivers. The MSTR control bit in the SPCR and all four DDRD control bits
associated with the SPI are cleared and an interrupt is generated (subject to masking by the SPIE
control bit and the I bit in the CCR).
Other precautions may need to be taken to prevent driver damage. If two devices are made
masters at the same time, the mode fault detector does not help protect either one unless one of
them selects the other as slave. The amount of damage possible depends on the length of time
both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in progress. Because the
SPDR is not double buffered in the transmit direction, writes to SPDR cause data to be written
directly into the SPI shift register. Because this write corrupts any transfer in progress, a write
collision error is generated. The transfer continues undisturbed, and the write data that caused the
error is not written to the shifter.
A write collision is normally a slave error because a slave has no control over when a master
initiates a transfer. A master knows when a transfer is in progress, so there is no reason for a
master to generate a write-collision error, although the SPI logic can detect write collisions in both
master and slave devices.

The SPI configuration determines the characteristics of a transfer in progress. For a master, a
transfer begins when data is written to SPDR and ends when SPIF is set. For a slave with CPHA
equal to zero, a transfer starts when SS goes low and ends when SS returns high. In this case,
SPIF is set at the middle of the eighth SCK cycle when data is transferred from the shifter to the
parallel data register, but the transfer is still in progress until SS goes high. For a slave with CPHA
equal to one, transfer begins when the SCK line goes to its active level, which is the edge at the
beginning of the first SCK cycle. The transfer ends when SPIF is set, for a slave in which CPHA=1.

9.5

SPI registers

The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data storage
functions. Refer to the following information for a description of how these registers are organized.

TPG

MC68HC11PA8

SERIAL PERIPHERAL INTERFACE

MOTOROLA
9-5

155

9.5.1

SPCR SPI control register

SPI control (SPCR)

Address

bit 7

bit 6

$0028

SPIE

SPE

bit 5

bit 4

bit 3

bit 2

bit 1

DWOM MSTR CPOL CPHA SPR1

bit 0

State
on reset

Port D [5:2] buffers configured for normal CMOS outputs.

MSTR Master mode select

1 (set)

0 (clear)

Master mode
Slave mode

TPG

MOTOROLA
9-6

SERIAL PERIPHERAL INTERFACE

MC68HC11PA8

156

CPOL Clock polarity

1 (set)

0 (clear)

SCK is active low.

SCK is active high.

When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master
device has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 9-2 and
Section 9.2.1.
CPHA Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPHA bit selects one of two different clocking protocols. Refer to Figure 9-2
and Section 9.2.1.
SPR1 and SPR0 SPI clock rate selects
These two bits select the SPI clock rate, as shown in Table 9-1. Note that SPR2 is located in the
OPT2 register, and that its state on reset is zero.

Table 9-1 SPI clock rates

SPR[2:0]

E clock
divide ratio

000
001
010
011
100
101
110
111

2
4
16
32
8
16
64
128

SPI clock frequency ( baud rate) for:

E = 2MHz
E = 3MHz
E = 4MHz
1.0 MHz
1.5 MHz
2.0 MHz
500 kHz
750kHz
1.0 MHz
125 kHz
187.5 kHz
250 kHz
62.5 kHz
93.7 kHz
125 kHz
250 kHz
375 kHz
500 kHz
125 kHz
187.5 kHz
250 kHz
31.3 kHz
46.9 kHz
62.5 kHz
15.6 kHz
23.4 kHz
31.3 kHz

TPG

MC68HC11PA8

SERIAL PERIPHERAL INTERFACE

MOTOROLA
9-7

157

9.5.2

SPSR SPI status register

SPI status (SPSR)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0029

SPIF

WCOL

MODF

XPIN

IPIN

0000 00uu

This register can be read at any time, but writing to it has no effect.
SPIF SPI interrupt complete flag
1 (set)

0 (clear)

Data transfer to external device has been completed.

No valid completion of data transfer.

SPIF is set upon completion of data transfer between the processor and the external device. If
SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit,
read the SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first,
attempts to write SPDR are inhibited.
WCOL Write collision
1 (set)

0 (clear)

Write collision.
No write collision.

Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an
access of SPDR. Refer to Section 9.3.4 and Section 9.4.

MODF Mode fault

1 (set)

0 (clear)

Mode fault.
No mode fault.

To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to
Section 9.3.4 and Section 9.4.
Bits [5, 3, 2] Not implemented; always read zero.
XPIN XIRQ pin input data bit (refer to Section 6.8)
IPIN IRQ pin input data bit (refer to Section 6.8)

TPG

MOTOROLA
9-8

SERIAL PERIPHERAL INTERFACE

MC68HC11PA8

158

9.5.3

SPDR SPI data register

SPI data (SPDR)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$002A

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this
register initiates transmission or reception of a byte, and this only occurs in the master device. At
the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave
devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte
that caused the overrun, the first SPIF must be cleared by the time a second transfer of data from
the shift register to the read buffer is initiated.
SPI is double buffered in and single buffered out.

9.5.4

OPT2 System configuration options register 2

Address

System config. options 2 (OPT2)

$0038

bit 7

bit 6

bit 5

bit 4

bit 3

LIRDV CWOM STRCH IRVNE LSBF

bit 2

bit 1

bit 0

State
on reset

Normal operation.

TPG

MC68HC11PA8

SERIAL PERIPHERAL INTERFACE

MOTOROLA
9-9

159

IRVNE Internal read visibility/not E (refer to Section 4)

1 (set)

0 (clear)

Data from internal reads is driven out of the external data bus.
No visibility of internal reads on external bus.

In single chip mode this bit determines whether the E clock drives out from the chip.
1 (set)

0 (clear)

E pin is driven low.

E clock is driven out from the chip.

LSBF LSB first enable

1 (set)

SPI data is transferred LSB first.

0 (clear)

SPI data is transferred MSB first.

If this bit is set, data, which is usually transferred MSB first, is transferred LSB first. LSBF does not
affect the position of the MSB and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
SPR2 SPI clock rate select
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the two bits in the
SPCR, this bit specifies the SPI clock rate. Refer to Table 9-1.
EXT4X XOUT clock output select (refer to Section 4)
1 (set)

9
Note:

EXTALi clock is output on the XOUT pin.

0 (clear)

4XCLK clock is output on the XOUT pin.

The XOUT pin is not available on 64-pin QFP packaged devices; see Section 4

XIRQE Configure XIRQ for falling-edge-sensitive operation (see Section 4.3.2.5)

1 (set)

0 (clear)

Falling-edge-sensitive operation.
Low-level-sensitive operation.

TPG

MOTOROLA
9-10

SERIAL PERIPHERAL INTERFACE

MC68HC11PA8

160

10
TIMING SYSTEM
The M68HC11 timing system is composed of several clock divider chains. The main clock divider
chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The
main timers programmable prescaler provides one of the four clocking rates to drive the 16-bit
counter. Two prescaler control bits select the prescale rate. The prescaler output divides the
system clock by 1, 4, 8, or 16. Taps from this main clocking chain drive circuitry are used to
generate the slower clocks used by the pulse accumulator, the real-time interrupt (RTI), and
computer operating properly (COP) watchdog subsystems. Refer to Figure 10-1.

10.1

Timer operation

All main timer system activities are referenced to the free-running counter. The counter begins
incrementing from $0000 as the MCU comes out of reset, and continues to the maximum count,
$FFFF. At the maximum count, the counter rolls over to $0000, sets an overflow flag and continues
to increment. As long as the MCU is running in a normal operating mode, there is no way to reset,
change or interrupt the counting. The capture/compare subsystem features three input capture
channels, four output compare channels and one channel that can be selected to perform either
input capture or output compare. Each of the input capture functions has its own 16-bit input
capture register (time capture latch) and each of the output compare functions has its own 16-bit
compare register. All timer functions, including the timer overflow and RTI, have their own interrupt
controls and separate interrupt vectors. See Table 10-1 for related frequencies and periods.

Clocks for the pulse accumulator, real time interrupt and COP functions are derived from the
internal ST4XCK signal. If the PLL circuit is active (VDDSYN = 1) and the MCS and BCS bits in
PLLCR are both set, then ST4XCK is equal to the output of the PLL circuit, VCOOUT. Otherwise,
ST4XCK is the same as EXTALi. Refer to Figure 10-1 and Section 2.
The pulse accumulator contains an 8-bit counter and edge select logic. The pulse accumulator
can operate in either event counting mode or gated time accumulation mode. During event
counting mode, the pulse accumulators 8-bit counter increments when a specified edge is
detected on an input pin. During gated time accumulation mode, an internal clock source
(ST4XCK/28) increments the 8-bit counter while an input signal has a predetermined logic level.
See Section 10.1.6.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-1

161

The real-time interrupt (RTI) is a programmable periodic interrupt circuit that permits pacing of the
execution of software routines by selecting one of four interrupt rates. It is clocked by the 16-bit
timer (ST4XCK/215); see Section 10.1.4.
The COP watchdog clock input is tapped off from the free-running counter chain (ST4XCK/217);
see Section 10.1.5. The COP automatically times out unless it is serviced within a specific time by
a program reset sequence. If the COP is allowed to time out, a reset is generated, which drives
the RESET pin low to reset the MCU and the external system (see Section 5).

Table 10-1 Timer resolution and capacity

4.0MHz
Control bits 1.0MHz
PR[1:0]
1000ns
1.0s
00
65.536ms
4.0s
01
262.14ms
8.0s
10
524.29ms
16.0s
11
1049 ms

8.0MHz
2.0MHz
500ns
500ns
32.768ms
2.0s
131.07ms
4.0s
262.14ms
8.0s
524.29ms

Clock
12.0MHz
3.0MHz
333ns
333ns
21.845ms
1.333s
87.381ms
2.667s
174.76ms
5.333s
349.53ms

16.0MHz
4.0MHz
250ns
250ns
16.384ms
1.0s
65.536ms
2.0s
131.07ms
4.0s
262.14ms

ST4XCK
ST4XCK/4
4/ST4XCK
4/ST4XCK
218/ST4XCK
16/ST4XCK
220/ST4XCK
32/ST4XCK
221/ST4XCK
64/ST4XCK
222/ST4XCK

Crystal(1)
Clock
Period
resolution
overflow
resolution
overflow
resolution
overflow
resolution
overflow

(1) Crystal frequencies are valid only if the PLL is not active.

TPG

MOTOROLA
10-2

TIMING SYSTEM

MC68HC11PA8

162

Bus
clock
select

PLL

4XCLK

E clock

Internal bus clock

PH2 (for CPU, A/D
and memory)

BCS

Prescaler

2, 4, 8,16, 32, 64, 128

SPI

SPR[2:0]

Crystal
oscillator

EXTALi

Baud

Module
clock
select

SCI receiver clock

1, 2, 3, 4,, 8191

SBR[12:0]

SCI transmitter clock

(baud rate)

ST4XCK
MCS

Note: If the PLL system is not active,

then MCS and BCS have no meaning,
and all system clocks are referenced to EXTALi.

TOF

TCNT

Prescaler

1, 4, 8, 16
PR[1:0]

IC/OC

Pulse accumulator

213
Prescaler

1, 2, 4, 8

Real time interrupt

RTR[1:0]

10
Prescaler

1, 4, 16, 64
CR[1:0]
Set

Q
Set

FF1

Clear COP timer

Reset

FF2

Reset

Force COP reset

System reset

Figure 10-1 Timer clock divider chains

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-3

163

10.1.1

Timer structure

The timer functions share I/O with all eight pins of port A:

Pin
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

Alternative function
IC3
IC2
IC1
OC5 and/or OC1, or IC4
OC4 and/or OC1
OC3 and/or OC1
OC2 and/or OC1
PAI and/or OC1

Figure 10-2 shows the capture/compare system block diagram. The port A pin control block
includes logic for timer functions and for general-purpose I/O. For pins PA3, PA2, PA1 and PA0,
this block contains both the edge-detection logic and the control logic that enables the selection
of which edge triggers an input capture. The digital level on PA[3:0] can be read at any time (read
PORTA register), even if the pin is being used for the input capture function. Pins PA[6:3] are used
either for general-purpose I/O, or as output compare pins. When one of these pins is being used
for an output compare function, it cannot be written directly as if it were a general-purpose output.
Each of the output compare functions (OC[5:2]) is related to one of the port A output pins. Output
compare 1 (OC1) has extra control logic, allowing it optional control of any combination of the
PA[7:3] pins. The PA7 pin can be used as a general-purpose I/O pin, as an input to the pulse
accumulator or as an OC1 output pin.

TPG

MOTOROLA
10-4

TIMING SYSTEM

MC68HC11PA8

164

Prescaler
1, 4, 8, 16
PR[1:0]

ST4XCK/4

TCNT (hi) TCNT (lo)

TOI

16-bit
free running counter

TOF

16-bit timer bus

Note

CFORC
Force O/P
compare

16-bit comparator EQ

To pulse accumulator

OC1I

PA7/
OC1/
PAI

OC1F

TOC1 (hi) TOC1 (lo)

Bit 7

FOC1
OC2I

&
16-bit comparator

OC2F

TOC2 (hi) TOC2 (lo)

Bit 6

PA6/
OC2/
OC1

Bit 5

PA5/
OC3/
OC1

Bit 4

PA4/
OC4/
OC1

Bit 3

PA3/
OC5/
OC1/
IC4

Bit 2

PA2/
IC1

FOC2
OC3I

&
16-bit comparator

OC3F

TOC3 (hi) TOC3 (lo)

FOC3
OC4I

&
16-bit comparator EQ

OC4F

TOC4 (hi) TOC4 (lo)

FOC4
I4/O5I

&
16-bit comparator

TI4/O5 (hi) TI4/O5 (lo)

16-bit latch

I4/O5F

+
FOC5

CLK

IC4
IC1I

I4/O5

&
16-bit latch
TIC1 (hi)

OC5

CLK

IC1F

TIC1 (lo)
IC2I

&
16-bit latch
TIC2 (hi)

CLK

IC2F

Bit 1

PA1/
IC2

Bit 0

PA0/
IC3

TIC2 (lo)
IC3I

&
16-bit latch
TIC3 (hi)

CLK

TIC3 (lo)

IC3F

TFLG1

TMSK1

Port A

status
flags

interrupt
enables

pin
control

Pins/
functions

Interrupt requests 19 (these are further qualified by the I-bit in the CCR)
Port A pin actions are controlled by OC1M, OC1D, PACTL, TCTL1 and TCTL2 registers

Figure 10-2 Capture/compare block diagram

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-5

165

10.1.2

Input capture

The input capture function records the time an external event occurs by latching the value of the
free-running counter when a selected edge is detected at the associated timer input pin. Software
can store latched values and use them to compute the periodicity and duration of events. For
example, by storing the times of successive edges of an incoming signal, software can determine
the period and pulse width of a signal. To measure period, two successive edges of the same
polarity are captured. To measure pulse width, two alternate polarity edges are captured.
In most cases, input capture edges are asynchronous with respect to the internal timer counter,
which is clocked relative to an internal clock (PH2). These asynchronous capture requests are
synchronized with PH2 so that latching occurs on the opposite half cycle of PH2 from when the
timer counter is being incremented. This synchronization process introduces a delay from when
the edge occurs to when the counter value is detected. Because these delays cancel out when
the time between two edges is being measured, the delay can be ignored. When an input capture
is being used with an output compare, there is a similar delay between the actual compare point
and when the output pin changes state.
The control and status bits that implement the input capture functions are contained in the PACTL,
TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDA3 bit of the DDRA register. Note that
this bit is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the
PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5
being cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes
to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the
TI4/O5 register is acting as IC4.

TPG

MOTOROLA
10-6

TIMING SYSTEM

MC68HC11PA8

166

10.1.2.1

TCTL2 Timer control register 2

Address

Timer control 2 (TCTL2)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000

Use the control bits of this register to program input capture functions to detect a particular edge
polarity on the corresponding timer input pin. Each of the input capture functions can be
independently configured to detect rising edges only, falling edges only, any edge (rising or falling),
or to disable the input capture function. The input capture functions operate independently of each
other and can capture the same TCNT value if the input edges are detected within the same timer
count cycle.
EDGxB and EDGxA Input capture edge control

EDGxB EDGxA
Configuration
0
0
ICx disabled
0
1
ICx captures on rising edges only
1
0
ICx captures on falling edges only
1
1
ICx captures on any edge

There are four pairs of these bits. Each pair is cleared by reset and must be encoded to configure
the corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in the
PACTL register is set.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-7

167

10.1.2.2

TIC1TIC3 Timer input capture registers

Timer input capture 1 (TIC1) high

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0010

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8)

undefined

Timer input capture 1 (TIC1) low

$0011

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

Timer input capture 2 (TIC2) high

$0012

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8)

undefined

Timer input capture 2 (TIC2) low

$0013

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

Timer input capture 3 (TIC3) high

$0014

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8)

undefined

Timer input capture 3 (TIC3) low

$0015

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

When an edge has been detected and synchronized, the 16-bit free-running counter value is
transferred into the input capture register pair as a single 16-bit parallel transfer. Timer counter
value captures and timer counter incrementing occur on opposite half-cycles of the phase 2 clock
so that the count value is stable whenever a capture occurs. Input capture values can be read from
a pair of 8-bit read-only registers. A read of the high-order byte of an input capture register pair
inhibits a new capture transfer for one bus cycle. If a double-byte read instruction, such as LDD,
is used to read the captured value, coherency is assured. When a new input capture occurs
immediately after a high-order byte read, transfer is delayed for an additional cycle but the value
is not lost.
The TICx registers are not affected by reset.

10.1.2.3

TI4/O5 Timer input capture 4/output compare 5

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

Capture 4/compare 5 (TI4/O5) high

$001E (bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Capture 4/compare 5 (TI4/O5) low

$001F

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

(bit 7)

Use TI4/O5 as either an input capture register or an output compare register, depending on the
function chosen for the PA3 pin. To enable it as an input capture pin, set the I4/O5 bit in the pulse
accumulator control register (PACTL) to logic level one. To use it as an output compare register,
set the I4/O5 bit to a logic level zero. Refer to Section 10.1.6.1.
The TI4/O5 register pair resets to ones ($FFFF).

TPG

MOTOROLA
10-8

TIMING SYSTEM

MC68HC11PA8

168

10.1.3

Output compare

Use the output compare (OC) function to program an action to occur at a specific time when
the 16-bit counter reaches a specified value. For each of the five output compare functions, there
is a separate 16-bit compare register and a dedicated 16-bit comparator. The value in the compare
register is compared to the value of the free-running counter on every bus cycle. When the
compare register matches the counter value, an output compare status flag is set. The flag can be
used to initiate the automatic actions for that output compare function.
To produce a pulse of a specific duration, write a value to the output compare register that
represents the time the leading edge of the pulse is to occur. The output compare circuit is
configured to set the appropriate output either high or low, depending on the polarity of the pulse
being produced. After a match occurs, the output compare register is reprogrammed to change
the output pin back to its inactive level at the next match. A value representing the width of the
pulse is added to the original value, and then written to the output compare register. Because the
pin state changes occur at specific values of the free-running counter, the pulse width can be
controlled accurately at the resolution of the free-running counter, independent of software
latency. To generate an output signal of a specific frequency and duty cycle, repeat this
pulse-generating procedure.
There are four 16-bit read/write output compare registers: TOC1, TOC2, TOC3, and TOC4, and
the TI4/O5 register, which functions under software control as either IC4 or OC5. Each of the OC
registers is set to $FFFF on reset. A value written to an OC register is compared to the
free-running counter value during each E clock cycle. If a match is found, the particular output
compare flag is set in timer interrupt flag register 1 (TFLG1). If that particular interrupt is enabled
in the timer interrupt mask register 1 (TMSK1), an interrupt is generated. In addition to an interrupt,
a specified action can be initiated at one or more timer output pins. For OC[5:2], the pin action is
controlled by pairs of bits (OMx and OLx) in the TCTL1 register. The output action is taken on each
successful compare, regardless of whether or not the OCxF flag in the TFLG1 register was
previously cleared.
OC1 is different from the other output compares in that a successful OC1 compare can affect any
or all five of the OC pins. The OC1 output action taken when a match is found is controlled by two
8-bit registers with three bits unimplemented: the output compare 1 mask register, OC1M, and the
output compare 1 data register, OC1D. OC1M specifies which port A outputs are to be used, and
OC1D specifies what data is placed on these port pins.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-9

169

10.1.3.1

TOC1TOC4 Timer output compare registers

Timer output compare 1 (TOC1) high

State
on reset

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

$0016

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 1 (TOC1) low

$0017

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Timer output compare 2 (TOC2) high

$0018

(bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 2 (TOC2) low

$0019

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Timer output compare 3 (TOC3) high

$001A (bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 3 (TOC3) low

$001B

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

Timer output compare 4 (TOC4) high

$001C (bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 1111 1111

Timer output compare 4 (TOC4) low

$001D

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 1111 1111

(bit 7)

All output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset. If an output
compare register is not used for an output compare function, it can be used as a storage location.
A write to the high-order byte of an output compare register pair inhibits the output compare
function for one bus cycle. This inhibition prevents inappropriate subsequent comparisons.
Coherency requires a complete 16-bit read or write. However, if coherency is not needed, byte
accesses can be used.
For output compare functions, write a comparison value to output compare registers TOC1TOC4
and TI4/O5. When TCNT value matches the comparison value, specified pin actions occur.
All TOCx register pairs reset to ones ($FFFF).

10.1.3.2

CFORC Timer compare force register

Timer compare force (CFORC)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$000B

FOC1

FOC2

FOC3

FOC4

FOC5

0000 0000

The CFORC register allows forced early compares. FOC[1:5] correspond to the five output
compares. These bits are set for each output compare that is to be forced. The action taken as a
result of a forced compare is the same as if there were a match between the OCx register and the
free-running counter, except that the corresponding interrupt status flag bits are not set. The
forced channels trigger their programmed pin actions to occur at the next timer count transition
after the write to CFORC.
The CFORC bits should not be used on an output compare function that is programmed to toggle
its output on a successful compare because a normal compare that occurs immediately before or
after the force can result in an undesirable operation.

TPG

MOTOROLA
10-10

TIMING SYSTEM

MC68HC11PA8

170

FOC[1:5] Force output compares

1 (set)

0 (clear)

A forced output compare action will occur on the specified pin.

No action.

Bits [2:0] Not implemented; always read zero

10.1.3.3

OC1M Output compare 1 mask register

Address

Output compare 1 mask (OC1M)

bit 7

bit 6

bit 5

bit 4

bit 3

$000C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3

bit 2

bit 1

bit 0

State
on reset

0000 0000

Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare.
The bits of the OC1M register correspond to PA7PA3.
OC1M[7:3] Output compare masks for OC1
1 (set)

0 (clear)

OC1 is configured to control the corresponding pin of port A.

OC1 will not affect the corresponding port A pin.

Bits [2:0] Not implemented; always read zero.

10.1.3.4

OC1D Output compare 1 data register

Address

Output compare 1 data (OC1D)

bit 7

bit 6

bit 5

bit 4

bit 3

$000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3

bit 2

bit 1

bit 0

State
on reset

0000 0000

Use this register with OC1 to specify the data that is to be written to the affected pin of port A after
a successful OC1 compare. When a successful OC1 compare occurs, a data bit in OC1D is written
to the corresponding pin of port A for each bit that is set in OC1M.

OC1D[7:3] Output compare data for OC1

If OC1Mx is set, data in OC1Dx is output to port A pin x on successful OC1 compares.
Bits [2:0] Not implemented; always read zero

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-11

171

10.1.3.5

TCNT Timer counter register

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

Timer count (TCNT) high

$000E (bit 15)

(14)

(13)

(12)

(11)

(10)

(9)

(bit 8) 0000 0000

Timer count (TCNT) low

$000F

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0) 0000 0000

(bit 7)

The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter
read addresses the more significant byte (MSB) first. A read of this address causes the less
significant byte (LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read
returns the full 16-bit state of the counter at the time of the MSB read cycle.
TCNT resets to $0000.

10.1.3.6

TCTL1 Timer control register 1

Timer control 1 (TCTL1)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0020

OM2

OL2

OM3

OL3

OM4

OL4

OM5

OL5

0000 0000

The bits of this register specify the action taken as a result of a successful OCx compare.
OM[5:2] Output mode
OL[5:2] Output level

OMx
0
0
1
1

OLx
0
1
0
1

Action taken on successful compare

Timer disconnected from OCx pin logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1

These control bit pairs are encoded to specify the action taken after a successful OCx compare.
OC5 functions only if the I4/O5 bit in the PACTL register is clear.

TPG

MOTOROLA
10-12

TIMING SYSTEM

MC68HC11PA8

172

10.1.3.7

TMSK1 Timer interrupt mask register 1

Timer interrupt mask 1 (TMSK1)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0022

OC1I

OC2I

OC3I

OC4I

I4/O5I

IC1I

IC2I

IC3I

0000 0000

Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts.

Note:

Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the
corresponding interrupt sources.

OC1IOC4I Output compare x interrupt enable

1 (set)

OCx interrupt is enabled.

0 (clear)

OCx interrupt is disabled.

If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is
requested.
I4/O5I Input capture 4/output compare 5 interrupt enable
1 (set)

IC4/OC5 interrupt is enabled.

0 (clear)

IC4/OC5 interrupt is disabled.

When I4/O5 in PACTL is set, I4/O5I is the input capture 4 interrupt enable bit.
When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
IC1IIC3I Input capture x interrupt enable
1 (set)

ICx interrupt is enabled.

0 (clear)

ICx interrupt is disabled.

If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is
requested.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-13

173

10.1.3.8

TFLG1 Timer interrupt flag register 1

Timer interrupt flag 1 (TFLG1)

Address

bit 7

bit 6

bit 5

$0023

OC1F

OC2F

OC3F

bit 4

bit 3

OC4F I4/O5F

bit 2

bit 1

bit 0

State
on reset

IC1F

IC2F

IC3F

0000 0000

Bits in this register indicate when timer system events have occurred. Coupled with the bits of
TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt
driven system. Clear flags by writing a one to the corresponding bit position(s).

Note:

Bits in TFLG1 correspond bit for bit with flag bits in TMSK1. Ones in TMSK1 enable the
corresponding interrupt sources.

OC1FOC4F Output compare x flag

1 (set)

0 (clear)

Counter has reached the preset output compare x value.

Counter has not reached the preset output compare x value.

These flags are set each time the counter matches the corresponding output compare x values.
I4/O5F Input capture 4/output compare 5 flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1FIC3F Input capture x flag
1 (set)

0 (clear)

Selected edge has been detected on corresponding port pin.

Selected edge has not been detected on corresponding port pin.

These flags are set each time a selected active edge is detected on the ICx input line

TPG

MOTOROLA
10-14

TIMING SYSTEM

MC68HC11PA8

174

10.1.3.9

TMSK2 Timer interrupt mask register 2

Timer interrupt mask 2 (TMSK2)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0024

TOI

RTII

PAOVI

PAII

PR1

PR0

0000 0000

Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The timer
prescaler control bits are included in this register.

Note:

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the
corresponding interrupt sources.

TOI Timer overflow interrupt enable

1 (set)

0 (clear)

Timer overflow interrupt requested when TOF is set.

TOF interrupts disabled.

RTII Real-time interrupt enable (refer to Section 10.1.4)

1 (set)

0 (clear)

Real time interrupt requested when RTIF is set.

Real time interrupts disabled.

PAOVI Pulse accumulator overflow interrupt enable (refer to Section 10.1.6)

PAII Pulse accumulator input edge interrupt enable (refer to Section 10.1.6)
Bits [3, 2] Not implemented; always read zero.
PR[1:0] Timer prescaler select

10
PR[1:0]
00
01
10
11

Prescaler
1
4
8
16

These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0] can only be
written once, and the write must be within 64 cycles after reset. See Table 10-1 for specific timing
values.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-15

175

10.1.3.10 TFLG2 Timer interrupt flag register 2

Timer interrupt flag 2 (TFLG2)

Address

bit 7

bit 6

bit 5

$0025

TOF

RTIF PAOVF

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

PAIF

0000 0000

Bits in this register indicate when certain timer system events have occurred. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a
polled or interrupt driven system. Clear flags by writing a one to the corresponding bit position(s).

Note:

Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in TMSK2 enable the
corresponding interrupt sources.

TOF Timer overflow interrupt flag

1 (set)

0 (clear)

TCNT has overflowed from $FFFF to $0000.

No timer overflow has occurred.

RTIF Real time (periodic) interrupt flag (refer to Section 10.1.4)

1 (set)

0 (clear)

RTI period has elapsed.

RTI flag has been cleared.

PAOVF Pulse accumulator overflow interrupt flag (refer to Section 10.1.6)

PAIF Pulse accumulator input edge interrupt flag (refer to Section 10.1.6.)
Bits [3:0] Not implemented; always read zero

TPG

MOTOROLA
10-16

TIMING SYSTEM

MC68HC11PA8

176

10.1.4

Real-time interrupt

The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate,
is clocked by the 16-bit free-running counter (ST4XCK/215). See Figure 10-1. The RTI clock rate
is configured by the RTR1 and RTR0 bits in the pulse accumulator control register, PACTL. The
different rates available are a product of the source frequency and the value of bits RTR[1:0]. The
source frequency, ST4XCK/215, can be divided by 1, 2, 4 or 8. Refer to Table 10-2 which shows
examples of periodic real-time interrupt rates. The RTII bit in the TMSK2 register enables the
interrupt capability.

Table 10-2 RTI periodic rates

RTR[1:0]
00
01
10
11

ST4XCK = 16MHz
2.048ms
4.096ms
8.192ms
16.384 ms

ST4XCK = 8MHz
4.096ms
8.192ms
16.384ms
32.768ms

ST4XCK = 4MHz
8.192ms
16.384ms
32.768ms
65.536ms

ST4XCK = xMHz
215/ST4XCK
216/ST4XCK
217/ST4XCK
218/ST4XCK

The clock source for the RTI function is free-running clock that cannot be stopped or interrupted
except by reset. This causes the time between successive RTI timeouts to be a constant that is
independent of the software latency associated with flag clearing and service. For this reason, an
RTI period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is
generated. After reset, one entire RTI period elapses before the RTIF flag is set for the first time.
Refer to the TMSK2, TFLG2, and PACTL registers.

10.1.4.1

TMSK2 Timer interrupt mask register 2

Timer interrupt mask 2 (TMSK2)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0024

TOI

RTII

PAOVI

PAII

PR1

PR0

0000 0000

This register contains the real-time interrupt enable bit.

Note:

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the
corresponding interrupt sources.

TOI Timer overflow interrupt enable (refer to Section 10.1.3.9)

1 (set)

0 (clear)

Timer overflow interrupt requested when TOF is set.

TOF interrupts disabled.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-17

177

RTII Real-time interrupt enable

1 (set)

0 (clear)

Real time interrupt requested when RTIF is set.

Real time interrupts disabled.

PAOVI Pulse accumulator overflow interrupt enable (refer to Section 10.1.6)

PAII Pulse accumulator input edge (refer to Section 10.1.6)
Bits[3, 2] Not implemented; always reads zero
PR[1, 0] Timer prescaler select (refer to Section 10.1.3.9)

10.1.4.2

TFLG2 Timer interrupt flag register 2

Timer interrupt flag 2 (TFLG2)

Address

bit 7

bit 6

bit 5

$0025

TOF

RTIF PAOVF

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

PAIF

0000 0000

Bits of this register indicate the occurrence of timer system events. Coupled with the four
high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled
or interrupt driven system. Clear flags by writing a one to the corresponding bit position(s).

Note:

Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in TMSK2 enable the
corresponding interrupt sources.

TOF Timer overflow interrupt flag (refer to Section 10.1.3.10)

1 (set)

0 (clear)

TCNT has overflowed from $FFFF to $0000.

No timer overflow has occurred.

RTIF Real-time interrupt flag

1 (set)

0 (clear)

RTI period has elapsed.

RTI flag has been cleared.

The RTIF status bit is automatically set at the end of every RTI period.
PAOVF Pulse accumulator overflow interrupt flag (refer to Section 10.1.6)
PAIF Pulse accumulator input edge interrupt flag (refer to Section 10.1.6)
Bits [3:0] Not implemented; always read zero

TPG

MOTOROLA
10-18

TIMING SYSTEM

MC68HC11PA8

178

10.1.4.3

PACTL Pulse accumulator control register

Pulse accumulator control (PACTL)

Address

bit 7

$0026

bit 6

bit 5

bit 4

PAEN PAMOD PEDGE

State
on reset

bit 3

bit 2

bit 1

bit 0

I4/O5

RTR1

RTR0 0000 0000

The RTR[1:0] bits in this register select the rate for the RTI system. The remaining bits control the
pulse accumulator and IC4/OC5 functions.
Bits [7, 3] Not implemented; always read zero
PAEN Pulse accumulator system enable (refer to Section 10.1.6)
1 (set)

Pulse accumulator enabled.

0 (clear)

Pulse accumulator disabled.

PAMOD Pulse accumulator mode (refer to Section 10.1.6)

1 (set)

0 (clear)

Gated time accumulation mode.

Event counter mode.

PEDGE Pulse accumulator edge control (refer to Section 10.1.6)

This bit has different meanings depending on the state of the PAMOD bit.
I4/O5 Input capture 4/output compare 5 (refer to Section 10.1.6)
1 (set)

0 (clear)

Input capture 4 function is enabled (no OC5).

Output compare 5 function is enabled (no IC4).

RTR[1:0] RTI interrupt rate select

These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven by the ST4XCK/215 clock rate that is compensated so it is independent of the timer
prescaler. These two control bits select an additional division factor. Refer to Table 10-2.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-19

179

10.1.5

Computer operating properly watchdog function

The clocking chain for the COP function is tapped off from the main timer divider chain
(ST4XCK/217). The CR[1:0] bits in the OPTION register and the NOCOP bit in the CONFIG
register control and configure the COP function. One additional register, COPRST, is used to arm
and clear the COP watchdog reset system. Refer to Section 5 for a more detailed discussion of
the COP function.

10.1.6

Pulse accumulator

The MC68HC11PA8/MC68HC11PB8 has an 8-bit counter that can be configured to operate either
as a simple event counter, or for gated time accumulation, depending on the state of the PAMOD
bit in the PACTL register. Refer to the pulse accumulator block diagram, Figure 10-3.
In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin.
The maximum clocking rate for the external event counting mode is the E clock divided by two. In
gated time accumulation mode, a free-running ST4XCK/28 signal drives the 8-bit counter, but only
while the external PAI pin is activated. Refer to Table 10-3. The pulse accumulator counter can be
read or written at any time.

Table 10-3 Pulse accumulator timing

ST4XCK
4.0 MHz
8.0 MHz
12.0 MHz
16.0 MHz

ST4XCK/4 clock Cycle time 28/ST4XCK PACNT overflow

1.0 MHz
1000 ns
64 s
16.384 ms
2.0 MHz
500 ns
32 s
8.192 ms
3.0 MHz
333 ns
21.33 s
5.461 ms
4.0 MHz
250 ns
16.0 s
4.096 ms

TPG

MOTOROLA
10-20

TIMING SYSTEM

MC68HC11PA8

180

TOF
RTIF

TFLG2

PAOVF

PAIF
0

TOI

TMSK2

Disable flag setting

ST4XCK/28 clock
(from main timer)

Interrupt
requests

RTII

PAOVI
PAII

0
0
PR1
PR0

&
Overflow
2:1
MUX

PA7/
OC1/
PAI

Clock

Input buffer
and edge detector

PACNT
Enable

RTR0

I4/O5
RTR1

PEDGE
0

PAMOD

PAEN

From
OC1

Output buffer

PACTL

From
DDRA7
Internal data bus

Figure 10-3 Pulse accumulator block diagram

Pulse accumulator control bits are located within the PACTL, TMSK2 and TFLG2 registers, as
described in the following paragraphs.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-21

181

10.1.6.1

PACTL Pulse accumulator control register

Pulse accumulator control (PACTL)

Address

bit 7

$0026

bit 6

bit 5

bit 4

State
on reset

bit 3

bit 2

bit 1

bit 0

I4/O5

RTR1

RTR0 0000 0000

PAEN PAMOD PEDGE

Four of this registers bits control an 8-bit pulse accumulator system. Another bit enables either
the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt
system.
Bits [7, 3] Not implemented; always read zero
PAEN Pulse accumulator system enable
1 (set)

Pulse accumulator enabled.

0 (clear)

Pulse accumulator disabled.

PAMOD Pulse accumulator mode

1 (set)

0 (clear)

Gated time accumulation mode.

Event counter mode.

PEDGE Pulse accumulator edge control

This bit has different meanings depending on the state of the PAMOD bit, as shown:

PAMOD PEDGE
Action of clock
0
0
PAI falling edge increments the counter.
0
1
PAI rising edge increments the counter.
1
0
A zero on PAI inhibits counting.
1
1
A one on PAI inhibits counting.

I4/O5 Input capture 4/output compare 5

1 (set)

0 (clear)

Input capture 4 function is enabled (no OC5).

Output compare 5 function is enabled (no IC4)

RTR[1:0] RTI interrupt rate selects (refer to Section 10.1.4)

TPG

MOTOROLA
10-22

TIMING SYSTEM

MC68HC11PA8

182

10.1.6.2

PACNT Pulse accumulator count register

Pulse accumulator count (PACNT)

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0027

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

This 8-bit read/write register contains the count of external input events at the PAI input, or the
accumulated count. In gated time accumulation mode, PACNT is readable even if PAI is not active.
The counter is not affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading occur during opposite
half cycles.

10.1.6.3

Pulse accumulator status and interrupt bits

The pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF are located within timer
registers TMSK2 and TFLG2.

10.1.6.4

TMSK2 Timer interrupt mask 2 register

Timer interrupt mask 2 (TMSK2)

10.1.6.5

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

$0024

TOI

RTII

PAOVI

PAII

PR1

PR0

0000 0000

TFLG2 Timer interrupt flag 2 register

Timer interrupt flag 2 (TFLG2)

Address

bit 7

bit 6

bit 5

$0025

TOF

RTIF PAOVF

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

PAIF

0000 0000

PAOVI and PAOVF Pulse accumulator interrupt enable and overflow flag
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00. To
clear this status bit, write a one in the corresponding data bit position (bit 5) of the TFLG2 register.
The PAOVI control bit allows the pulse accumulator overflow to be configured for polled or
interrupt-driven operation and does not affect the state of PAOVF. When PAOVI is zero, pulse
accumulator overflow interrupts are inhibited, and the system operates in a polled mode, which
requires that PAOVF be polled by user software to determine when an overflow has occurred.
When the PAOVI control bit is set, a hardware interrupt request is generated each time PAOVF is
set. Before leaving the interrupt service routine, software must clear PAOVF.

TPG

MC68HC11PA8

TIMING SYSTEM

MOTOROLA
10-23

183

PAII and PAIF Pulse accumulator input edge interrupt enable and flag
The PAIF status bit is automatically set each time a selected edge is detected at the PA7/PAI/OC1
pin. To clear this status bit, write to the TFLG2 register with a one in the corresponding data bit
position (bit 4). The PAII control bit allows the pulse accumulator input edge detect to be
configured for polled or interrupt-driven operation but does not affect setting or clearing the PAIF
bit. When PAII is zero, pulse accumulator input interrupts are inhibited, and the system operates
in a polled mode. In this mode, the PAIF bit must be polled by user software to determine when
an edge has occurred. When the PAII control bit is set, a hardware interrupt request is generated
each time PAIF is set. Before leaving the interrupt service routine, software must clear PAIF.

TPG

MOTOROLA
10-24

TIMING SYSTEM

MC68HC11PA8

184

11
ANALOG-TO-DIGITAL CONVERTER
The analog-to-digital (A/D) system, a successive approximation converter, uses an all-capacitive
charge redistribution technique to convert analog signals to digital values.
The A/D converter shares input pins with port E:

Pin
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7

Alternative
function
AD0
AD1
AD2
AD3
AD4
AD5
AD6 / SDA
AD7 / SCL

Note:

Pins PE5 and PE4 are not present on 64-pin MC68HC11PA8 QFP packaged devices,
on which there are only six input channels, but are available on the MC68HC11PB8.
PE[5, 4] are present on 68-pin CLCC packaged versions of the MC68HC711PA8 and
MC68HC711PB8, which are available as samples only. Contact your local Motorola
Sales Office for more information.

Note:

If the MBSP bit in the CONFIG register is set, then port E pins [7, 6] are used by the
I2C bus system; in this case, A/D conversions of the logic levels on these pins have no
meaning (see Section 4 and Section 8).

TPG

MC68HC11PA8

ANALOG-TO-DIGITAL CONVERTER

MOTOROLA
11-1

185

11.1

Overview

The A/D system is a 8-channel, 8-bit, multiplexed-input converter. The VDDAD and VSSAD pins
are used to input supply voltage to the A/D converter. This allows the supply voltage to be
bypassed independently. The converter does not require external sample and hold circuits
because of the type of charge redistribution technique used. A/D converter timing can be
synchronized to the system E clock, or to an internal resistor capacitor (RC) oscillator. The A/D
converter system consists of four functional blocks: multiplexer, analog converter, digital control
and result storage. Refer to Figure 11-1.

PE0/
AD2

VRH
VRL

8-bit capacitive DAC

with sample and hold

PE1/
AD3
Successive approximation
register and control

PE2/
AD4
PE3/
AD5
PE3/
AD5

Result
Internal
data bus

Analog
MUX

0
SCAN
MULT

PE6/
AD6

CD
CC
CB

PE7/
AD7

ADCTL A/D control

CCF

PE3/
AD5

Result register interface

11
ADR1 - A/D result 1

ADR2 - A/D result 2

ADR3 - A/D result 3

ADR4 - A/D result 4

Note: Pins PE4 and PE5 are not available on 64-pin packaged devices.

Figure 11-1 A/D converter block diagram

TPG

MOTOROLA
11-2

ANALOG-TO-DIGITAL CONVERTER

MC68HC11PA8

186

11.1.1

Multiplexer

The multiplexer selects one of 16 inputs for conversion. Input selection is controlled by the value
of bits CD CA in the ADCTL register. The port E pins are fixed-direction analog inputs to the
multiplexer, and additional internal analog signal lines are routed to it.
Port E pins can also be used as digital inputs. Digital reads of port E pins should be avoided during
the sample portion of an A/D conversion cycle, when the gate signal to the n-channel input gate
is on. Because no p-channel devices are directly connected to either input pins or reference
voltage pins, voltages above VDD do not cause a latchup problem, although current and voltage
should be limited according to maximum ratings. Refer to Figure 11-2, which is a functional
diagram of an input pin.
Input
protection
device

Analog
input

Diffusion and
poly coupler
4k

Note 1

<2pF

20pF
+20V
0.7V

400nA
junction
leakage

DAC
capacitance

VRL
Note 1: The analog switch is closed only during the 12 cycle sample time
Note 2: All component values are approximate

Figure 11-2 Electrical model of an A/D input pin (in sample mode)

11.1.2

Analog converter

Conversion of an analog input selected by the multiplexer occurs in this block. It contains a
digital-to-analog capacitor (DAC) array, a comparator, and a successive approximation register
(SAR). Each conversion is a sequence of eight comparison operations, beginning with the most
significant bit (MSB). Each comparison determines the value of a bit in the SAR.

The DAC array performs two functions. It acts as a sample and hold circuit during the entire
conversion sequence, and provides comparison voltage to the comparator during each
successive comparison.
The result of each successive comparison is stored in the SAR. When a conversion sequence is
complete, the contents of the SAR are transferred to the appropriate result register.
A charge pump provides switching voltage to the gates of analog switches in the multiplexer.
Charge pump output must stabilize between 7 and 8 volts within up to 100 s before the converter
can be used. The charge pump is enabled by the ADPU bit in the OPTION register.

TPG

MC68HC11PA8

ANALOG-TO-DIGITAL CONVERTER

MOTOROLA
11-3

187

11.1.3

Digital control

All A/D converter operations are controlled by bits in register ADCTL. In addition to selecting the
analog input to be converted, ADCTL bits indicate conversion status, and control whether single
or continuous conversions are performed. Finally, the ADCTL bits determine whether conversions
are performed on single or multiple channels.

11.1.4

Result registers

Four 8-bit registers (ADR1 ADR4) store conversion results. Each of these registers can be
accessed by the processor in the CPU. The conversion complete flag (CCF) indicates when valid
data is present in the result registers. The result registers are written during a portion of the system
clock cycle when reads do not occur, so there is no conflict.

11.1.5

A/D converter clocks

The CSEL bit in the OPTION register selects whether the A/D converter uses the system E clock
or an internal RC oscillator for synchronization. When E clock frequency is below 750kHz, charge
leakage in the capacitor array can cause errors, and the internal oscillator should be used. When
the RC clock is used, additional errors can occur because the comparator is sensitive to the
additional system clock noise.

11.1.6

Conversion sequence

A/D converter operations are performed in sequences of four conversions each. A conversion
sequence can repeat continuously or stop after one iteration. The conversion complete flag (CCF)
is set after the fourth conversion in a sequence to show the availability of data in the result
registers. Figure 11-3 shows the timing of a typical sequence. Synchronization is referenced to the
system E clock.

11.1.7

Conversion process

The A/D conversion sequence begins one E clock cycle after a write to the A/D control/status
register, ADCTL. The bits in ADCTL select the channel and the mode of conversion.
An input voltage equal to VRL converts to $00 and an input voltage equal to VRH converts to $FF
(full scale), with no overflow indication. For ratiometric conversions of this type, the source of each
analog input should use VRH as the supply voltage and be referenced to VRL.

TPG

MOTOROLA
11-4

ANALOG-TO-DIGITAL CONVERTER

MC68HC11PA8

188

12 cycles

4 cycles
MSB

2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc

bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
END

Successive approximation sequence

Set CCF flag

Sample analog input

Convert first
channel and
update ADR1
0

Convert second
channel and
update ADR2
32

Convert third
channel and
update ADR3
64

Repeat sequence if SCAN = 1

Write to ADCTL

E clock

Convert fourth
channel and
update ADR4
96

128 E clock cycles

Figure 11-3 A/D conversion sequence

11.2

A/D converter power-up and clock select

ADPU (bit 7 of the OPTION register) controls A/D converter power up. Clearing ADPU removes
power from and disables the A/D converter system; setting ADPU enables the A/D converter
system. After the A/D converter is turned on, the analog bias voltages will take up to 100s to
stabilize.
When the A/D converter system is operating from the MCU E clock, all switching and comparator
operations are synchronized to the MCU clocks. This allows the comparator results to be sampled
at quiet times, which minimizes noise errors. The internal RC oscillator is asynchronous with
respect to the MCU clock, so noise can affect the A/D converter results. This results in a slightly
lower typical accuracy when using the internal oscillator (CSEL = 1).

11.2.1

OPTION System configuration options register 1

Address

System config. options 1 (OPTION)

$0039

bit 7

bit 6

ADPU CSEL

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

IRQE

DLY

CME

FCME

CR1

CR0

0001 0000

The 8-bit special-purpose OPTION register sets internal system configuration options during
initialization. The time protected control bits, IRQE, DLY, FCME and CR[1:0] can be written to only
once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the
possibility of any accidental changes to the system configuration. They may be written at any time
in special modes.

TPG

MC68HC11PA8

ANALOG-TO-DIGITAL CONVERTER

MOTOROLA
11-5

189

Low level sensitive operation.

DLY Enable oscillator start-up delay (refer to Section 4)

1 (set)

A stabilization delay is imposed as the MCU is started up from STOP

mode or from power-on reset.

0 (clear)

The oscillator start-up delay coming out of STOP is bypassed and the
MCU resumes processing within about four bus cycles. A stable
external oscillator is required if this option is selected.

CME Clock monitor enable (refer to Section 5)

1 (set)

Clock monitor enabled.

0 (clear)

Clock monitor disabled.

FCME Force clock monitor enable (refer to Section 5)

1 (set)

0 (clear)

Clock monitor enabled, cannot be disabled until next reset.

Clock monitor follows the state of the CME bit.

CR[1:0] COP timer rate select bits (refer to Section 5)

TPG

MOTOROLA
11-6

ANALOG-TO-DIGITAL CONVERTER

MC68HC11PA8

190

11.3

Channel assignments

The multiplexer allows the A/D converter to select one of 16 analog signals. Eight of these
channels correspond to port E input lines to the MCU, four others are internal reference points or
test functions; the remaining six channels are reserved. Refer to Table 11-1.

Channel
signal
AD0
AD1
AD2
AD3
AD4(1)
AD5(1)
AD6
AD7
reserved
VRH(2)
VRL(2)
VRH/2(2)
reserved (2)

Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4

ADR1
ADR2
ADR3
ADR4

(1) Not available on 64-pin packaged

MC68HC11PA8/MC68HC711PA8 devices,
but are present on 64-pin packaged
MC68HC11PB8/MC68HC711PB8 devices.
(2) Used for factory testing.

11.3.1

Single-channel operation

There are two types of single-channel operation. In the first type (SCAN = 0), the single selected
channel is converted four consecutive times. The first result is stored in A/D result register 1
(ADR1), and the fourth result is stored in ADR4. After the fourth conversion is complete, all
conversion activity is halted until a new conversion command is written to the ADCTL register. In
the second type of single-channel operation (SCAN = 1), conversions continue to be performed
on the selected channel with the fifth conversion being stored in register ADR1 (overwriting the
first conversion result), the sixth conversion overwriting ADR2, and so on.

TPG

MC68HC11PA8

ANALOG-TO-DIGITAL CONVERTER

MOTOROLA
11-7

191

11.3.2

Multiple-channel operation

There are two types of multiple-channel operation. In the first type (SCAN = 0), a selected group
of four channels is converted once only. The first result is stored in A/D result register 1 (ADR1),
and the fourth result is stored in ADR4. After the fourth conversion is complete, all conversion
activity is halted until a new conversion command is written to the ADCTL register. In the second
type of multiple-channel operation (SCAN = 1), conversions continue to be performed on the
selected group of channels with the fifth conversion being stored in register ADR1 (replacing the
earlier conversion result for the first channel in the group), the sixth conversion overwriting ADR2,
and so on.

11.4

Control, status and results registers

11.4.1

ADCTL A/D control and status register

A/D control & status (ADCTL)

Address

bit 7

bit 6

$0030

CCF

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

SCAN MULT

u0uu uuuu

bit 5

All bits in this register can be read or written, except bit 7, which is a read-only status indicator,
and bit 6, which always reads as zero. Write to ADCTL to initiate a conversion. To quit a conversion
in progress, write to this register and a new conversion sequence begins immediately.
CCF Conversions complete flag
1 (set)

0 (clear)

All four A/D result registers contain valid conversion data.

At least one of the A/D result registers contains invalid data.

A read-only status indicator, this bit is set when all four A/D result registers contain valid
conversion results. Each time the ADCTL register is overwritten, this bit is automatically cleared
to zero and a conversion sequence is started. In the continuous mode, CCF is set at the end of
the first conversion sequence.
Bit 6 Not implemented; always reads zero.
SCAN Continuous scan control
1 (set)

0 (clear)

A/D conversions take place continuously.

Each of the four conversions is performed only once.

When this control bit is clear, the four requested conversions are performed once to fill the four
result registers. When this control bit is set, the four conversions are repeated continuously with
the result registers updated as data becomes available.

TPG

MOTOROLA
11-8

ANALOG-TO-DIGITAL CONVERTER

MC68HC11PA8

192

MULT Multiple-channel/single-channel control

1 (set)

0 (clear)

Each A/D channel has a result register allocated to it.

Four consecutive conversions from the same A/D channel are stored
in the results registers.

When this bit is clear, the A/D converter system is configured to perform four consecutive
conversions on the single channel specified by the four channel select bits CDCA (bits 30 of the
ADCTL register). When this bit is set, the A/D system is configured to perform a conversion on
each of the four channels where each result register corresponds to one channel.

Note:

When the multiple-channel continuous scan mode is used, extra care is needed in the
design of circuitry driving the A/D inputs. The charge on the capacitive DAC array before
the sample time is related to the voltage on the previously converted channel. A charge
share situation exists between the internal DAC capacitance and the external circuit
capacitance. Although the amount of charge involved is small, the rate at which it is
repeated is every 64 s for an E clock of 2 MHz. The RC charging rate of the external
circuit must be balanced against this charge sharing effect to avoid errors in accuracy.
Refer to the M68HC11 Reference Manual (M68HC11RM/AD) for further information.

1100
VRH(2)
ADR1
1101
VRL(1)
ADR2
1110
VRH/2(1)
ADR3
1111
reserved(1)
ADR4

TPG

MC68HC11PA8

ANALOG-TO-DIGITAL CONVERTER

MOTOROLA
11-9

193

(1) Not available on 64-pin packaged

MC68HC11PA8/MC68HC711PA8 devices,
but are present on 64-pin packaged
MC68HC11PB8/MC68HC711PB8 devices.
(2) Used for factory testing.

11.4.2

ADR1ADR4 A/D converter results registers

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State
on reset

A/D result 1 (ADR1)

$0031

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

A/D result 2 (ADR2)

$0032

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

A/D result 3 (ADR3)

$0033

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

A/D result 4 (ADR4)

$0034

(bit 7)

(6)

(5)

(4)

(3)

(2)

(1)

(bit 0)

undefined

These read-only registers hold an 8-bit conversion result. Writes to these registers have no effect.
Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register is set,
indicating a conversion sequence is complete. If conversion results are needed sooner, refer to
Figure 11-3, which shows the A/D conversion sequence diagram.

11.5

Operation in STOP and WAIT modes

If a conversion sequence is in progress when either the STOP or WAIT mode is entered, the
conversion of the current channel is suspended. When the MCU resumes normal operation, that
channel is resampled and the conversion sequence is resumed. As the MCU exits the WAIT mode,
the A/D circuits are stable and valid results can be obtained on the first conversion. However, in
STOP mode, all analog bias currents are disabled and it is necessary to allow a stabilization period
when leaving the STOP mode. If the STOP mode is exited with a delay (DLY = 1), there is enough
time for these circuits to stabilize before the first conversion. If the STOP mode is exited with no
delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D circuitry to stabilize to avoid invalid
results.

TPG

MOTOROLA
11-10

ANALOG-TO-DIGITAL CONVERTER

MC68HC11PA8

194

A
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the
standard supply voltage (VDD = 5V 10%) MC68HC11PA8/MC68HC11PB8 variants.

A.1

Maximum ratings
Rating
Supply voltage (1)
Input voltage (1)
Operating temperature range
MC68HC11PA8, MC68HC711PA8,
MC68HC11PB8, MC68HC711PB8
Storage temperature range
Current drain per pin (2)
not VDD, VSS, VDD AD, VSS AD, VRH or VRL

Symbol
VDD
VIN

Value
0.3 to +7.0
0.3 to +7.0

Unit
V
V

TL to TH
40 to +85

TSTG

55 to +150

(1) All voltages are with respect to VSS.

(2) Maximum current drain per pin is for one pin at a time, observing maximum power
dissipation limits.

Note:

A.2

This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given
in the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either VSS or VDD.

Thermal characteristics and power considerations

The average chip junction temperature, TJ, in degrees Celsius can be obtained from the following
equation:
TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-1

195

T J = T A + ( P D JA )

[1]

where:
TA = Ambient temperature (C)
JA = Package thermal resistance, junction-to-ambient (C/W)
PD = Total power dissipation = PINT + PI/O (W)
PINT = Internal chip power = IDD VDD (W)
PI/O = Power dissipation on input and output pins (user determined)
An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = ---------------------T J + 273

[2]

K = P D ( T A + 273 ) + JA P D2

[3]

Solving equations [1] and [2] for K gives:

where K is a constant for a particular part. K can be determined by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained for any value of TA,
by solving the above equations. The package thermal characteristics are shown below:

Characteristics
Thermal resistance
64-pin QFP package

Symbol
JA

Value

Unit
C/W

TPG

MOTOROLA
A-2

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

196

A.3

Test methods

Clocks,
strobes

~VDD
0.4V

0.4V

~VSS

VDD 0.8V

nominal

nominal
70% of VDD

Inputs

20% of VDD
nominal timing
~VDD

VDD 0.8V
0.4V

Outputs
~VSS

(a) DC testing

Clocks,
strobes

~VDD
20% of VDD

~VSS

20% of VDD

70% of VDD

spec.

Inputs

20% of VDD

spec.
70% of VDD

VDD 0.8V (2)

0.4V (2)

spec. timing
~VDD

70% of VDD
20% of VDD

Outputs
~VSS

(b) AC testing
Notes:
(1) Full test loads are applied during all DC electrical tests and AC timing measurements.
(2) During AC timing measurements, inputs are driven to 0.4V and VDD 0.8V;
timing measurements are taken at the 20% and 70% of VDD points.

Figure A-1 Test methods

TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-3

197

A.4

DC electrical characteristics
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted)
Characteristic
Output voltage(1) (ILOAD = 10 A):
All outputs except XTAL
All outputs except XTAL, RESET & MODA
Output high voltage(1) (ILOAD = 0.8mA, VDD =4.5V):
All outputs except XTAL, RESET & MODA
Output low voltage (ILOAD = +1.6mA):
All outputs except XTAL
Input high voltage:
All inputs except RESET
RESET
Input low voltage all inputs
I/O ports three-state leakage (VIN = VIH or VIL)(2):
Ports A, B, C, D, F, G, MODA/LIR, RESET
Input leakage(2) (VIN = VDD or VSS):
MODB/VSTBY
IRQ, XIRQ (ROM parts)
XIRQ (EPROM parts)
Input current with pull-up resistors (VIN = VIL):
Ports B, F, G
RAM stand-by voltage (power down)
RAM stand-by current (power down)
Input capacitance:
Port E, IRQ, XIRQ, EXTAL
Ports A, B, C, D, F, G, MODA/LIR, RESET
Output load capacitance:
All outputs except PD[4:1], 4XOUT, XTAL,
MODA/LIR
4XOUT
PD[4:1]

Symbol

Min.

Max.

Unit

VOL
VOH

VDD 0.1

0.1

V
V

VOH

VDD 0.8

VOL
VIH

0.4

V
V

0.7VDD
0.8VDD
VSS 0.3

VDD + 0.3
VDD + 0.3
0.2VDD

10
1
10

20
2.0

100
VDD
10

8
12

90
30
200

VIL
IOZ
IIN

IIPR
VSB
ISB
CIN

V
A
A

A
V
A
pF

(1) VOH specification for RESET and MODA is not applicable as they are open-drain pins.
VOH specification is not applicable to port C and port D in wired-OR mode.
(2) Refer to A/D specification for the leakage current value for port E.

TPG

MOTOROLA
A-4

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

198

A.4.1

DC electrical characteristics modes of operation

(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH,
unless otherwise noted)
Characteristic
Maximum total supply current (including PLL)(1):
RUN: Single chip mode
RUN: Expanded mode
WAIT: Single chip mode
WAIT: Expanded mode
STOP: Single chip mode
Maximum power dissipation: Single chip mode
Maximum power dissipation: Expanded mode

Symbol
IDD

3MHz

4MHz

4.4MHz

Unit

32
42
15
17
50
176
231

40
50
20
22
50
220
275

mA
mA
mA
mA
A
mW
mW

(1) All current measurements taken with suitable decoupling capacitors across the power supply to
suppress the transient switching currents inherent in CMOS designs.
EXTAL is driven with a square wave, with tCYC = 167ms for 6kHz devices; 333/250ns for 3/4MHz
devices.
VIL 0.2V; VIH VDD 0.2V; no DC loads
WAIT: all peripheral functions shut down
STOP: all clocks stopped

A.5

Control timing

(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic (1)

3.0MHz
Min.
Max.
0
3.0
fOP
tCYC
333

fXTAL

12.0
4fOP
0
12.0
tPCSU
133

PWRSTL(3)
16

PWRSTL(4)
1

tMPS
2

tMPH
10

PWIRQ
tCYC +20

Symbol

Frequency of operation
E clock period
Crystal frequency
External oscillator frequency
Processor control set-up time (tPCSU = tCYC/4 + 50ns)
Reset input pulse width (2)
Mode programming set-up time
Mode programming hold time
Interrupt pulse width (IRQ edge sensitive mode)
Timer pulse width
(Input capture and pulse accumulator inputs)
WAIT recovery start-up time
Clock monitor reset(5)

4.0MHz
4.4MHz
Min.
Max.
Min.
Max.
0
4.0
0
4.4
250

225

16.0

17.6
0
16.0
0
17.6
112

106

tCYC +20 tCYC +20

Unit
MHz
ns
MHz
MHz
ns
tCYC
tCYC
ns
ns

PWTIM

tCYC +20

tWRS
fCMON

4
200

tCYC
kHz

(1) All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.

TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-5

199

(2) Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for eight clock cycles,
releases the pin and samples the pin level four cycles later to determine the source of the interrupt. (See Section 5.)
(3) To guarantee an external reset vector.
(4) This is the minimum input time; it can be pre-empted by an internal reset.
(5) Do not use the clock monitor when the E clock is below fCMON maximum value.

PA[3:0](1)
PWTIM
PA[3:0](2)
PA7(1), (3)
PA7(2), (3)
Notes
(1) Rising edge sensitive input.
(2) Falling edge sensitive input.
(3) Maximum pulse accumulator clocking rate is E clock frequency divided by two (E/2).

Figure A-2 Timer inputs

TPG

MOTOROLA
A-6

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

200

VDD

EXTAL
tPORDELAY (1)

E
tPCSU
PWRSTL

RESET
tMPS

tMPH

MODA,
MODB

FFFE FFFE FFFE FFFE FFFF

Address

New
PC

FFFE FFFE FFFE FFFE FFFE FFFF

New
PC

(1) tPORDELAY = 4064 tCYC (or 128 tCYC depending on mask option - MC68HC11PA8/MC68HC11PB8 only)

Figure A-3 Reset timing

E clock
tPCSU

IRQ(1)
IRQ(2), XIRQ
or internal
interrupt

PWIRQ

Address(3)

Data(4)

OA+1

PCL

SP1 SP2 SP3

PCH

IYL

IYH

SP4 SP5 SP6 SP7 SP8 SP8

IXL

IXH

CCR

VA+1

New
PC

R/W
Notes:
(1) Edge sensitive IRQ pin (IRQE = 1).
(2) Level sensitive IRQ pin (IRQE = 0).

(3) Where OA = Opcode address and VA = Vector address.

(4) Where OP = Opcode, VH = Vector (MSB) and VL = Vector (LSB).

Figure A-4 Interrupt timing

TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-7

201

Internal
clocks
IRQ(1)
or XIRQ
PWIRQ

IRQ(2)
or XIRQ

tSTOPDELAY(3)

E clock

Address(5)

Notes:

SA(6)

SA+1

SA+2 SP SP7 SP8 SP8 FFF2 FFF3

New
PC

(1) Edge sensitive IRQ pin (IRQE = 1).

(2) Level sensitive IRQ pin (IRQE = 0).
(3) If DLY = 1: tSTOPDELAY = 4064 tCYC (or 128 tCYC depending on mask option - MC68HC11PA8/MC68HC11PB8 only)
If DLY = 0: tSTOPDELAY = 4 tCYC
(4) SA = STOP address.

Figure A-5 STOP recovery timing

E clock
tPCSU

IRQ, XIRQ,
or internal
interrupts

tWRS

Address

WA(1) WA+1

SP1

SP2SP8

SP8

SP8SP8

SP8 SP8 SP8

VA(2)

VA+1

New
PC

Stack registers

R/W
Notes:

RESET also causes recovery from WAIT.

(1) WA = WAIT address.

(2) VA = Vector address.

Figure A-6 WAIT recovery timing

TPG

MOTOROLA
A-8

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

202

A.5.1

Peripheral port timing

(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic (1)

Symbol

Frequency of operation (E clock frequency)

E clock period
Peripheral data set-up time, all ports (2)
Peripheral data hold time, all ports (2)
Delay time, peripheral data write
MCU write to port A, B or G
MCU write to port C, D or F (tPWD = tCYC/4 + 100ns)

fOP
tCYC
tPDSU
tPDH
tPWD

3.0MHz
Min.
Max.
0
3.0
333

100

200
183

4.0MHz
Min. Max.
0
4.0
250

100

200
162

4.4MHz
Min.
Max.
0
4.4
225

100

Unit
MHz
ns
ns
ns
ns

200
156

(1) All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
(2) Port C and D timing is valid for active drive (CWOM, DWOM, and WOMS bits clear).

MCU read of port

E clock
tPDSU

tPDH

Ports
A, C, D, F
tPDSU

tPDH

Ports
B, E, G

Figure A-7 Port read timing diagram

MCU write to port

E clock
tPWD
Ports
C, D, F

Previous port data

New data valid

tPWD

Ports
A, B, G

Previous port data

New data valid

Figure A-8 Port write timing diagram

TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-9

203

A.5.2

PLL control timing

(VDD = 5.0Vdc 10%, VSS = 0Vdc, TA = TL to TH unless otherwise noted)

Mask option 1(1)
Mask option 2(1)
Characteristic
Symbol
Min
Typ Max
Min
Typ Max
PLL reference frequency
fREF
25
32
50
50
614 2000
System frequency
fSYS
dc

4.4
dc

4.4
PLL output frequency
fVCOOUT 0.05

17.6
0.1

17.6
External clock operation
fXTAL
dc

17.6
dc

17.6
Capacitor on pin XFC
CXFC

PLL stabilization time(2)(5)

tPLLS

4XCLK stability(3)(4)(5)
Short term
CSTAB

Long term

Mask option 3
Min
Typ Max
2000 4000 16000
dc

4.4
2

17.6
dc

16.6

4.7

1.5

0.15
0.15

Units
kHz
MHz

nF
ms
%

(1) This mask option does not exist on the MC68HC711PA8/MC68HC711PB8, on which the PLL is optimized for use at
frequencies of 2MHz and above.
(2) Assumes that stable VDDSYN is applied and that the crystal oscillator is stable. Stabilization time is measured from power-up
to RESET release. This specification also applies to the period required for PLL stabilization after changing the X and Y
frequency control bits in the synthesizer control register (SYNR) while PLL is running, and to the period required for the clock to
stabilize after WAIT with WEN = 1.
(3) Short term stability is the average deviation from programmed frequency measured over a 2s interval at maximum fSYS, Long
term 4XCLK stability is the average deviation from programmed frequency measured over a 1ms interval at maximum fSYS.
Stability is measured with a stable external clock applied variation in crystal oscillator frequency is additive to this figure.
(4) This parameter is periodically sampled rather than 100% tested.
(5) These parameters guaranteed by design.

TPG

MOTOROLA
A-10

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

204

A.5.3

Analog-to-digital converter characteristics

(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, 750kHz E 3MHz, unless otherwise noted)
Characteristic
Resolution
Non-linearity
Zero error
Full-scale error
Total unadjusted
error
Quantization error
Absolute accuracy
Conversion range
VRH
VRL
VR
Conversion time

Monotonicity
Zero input reading
Full-scale reading
Sample acquisition
time

Parameter

Min.

Number of bits resolved by ADC

Maximum deviation from the ideal ADC transfer

characteristics
Difference from the output of an ideal ADC for

zero input voltage

Difference from the output of an ideal ADC for

full-scale input voltage

Maximum sum of non-linearity, zero and full-scale

errors
Uncertainty due to converter resolution

Difference between the actual input voltage and

the full-scale weighted equivalent of the binary

output code, including all error sources

Analog input voltage range
VRL
Analog reference voltage (high) (1)
VRL
Analog reference voltage (low) (2)
VSS0.1
Minimum difference between VRH and VRL (2)
3
Total time to perform a single A/D conversion:
E clock

Internal RC oscillator

Conversion result never decreases with an

increase in input voltage and has no missing
codes
$00
Conversion result when VIN = VRL
Conversion result when VIN = VRH

Analog input acquisition sampling time:

E clock

Internal RC oscillator

3MHz(1)
Max.

LSB

1.5

LSB

0.5

LSB

VRH
VDD+0.1
VRH

V
V
V
V

tCYC+32

tCYC
tCYC+32 s

Absolute

4MHz(1) 4.4MHz(1)
Unit
Max.
Max.

bits

Guaranteed

$FF

Hex
Hex

tCYC
s

Sample/hold
capacitance

Input capacitance (PE[0:7]) during sample(3)

20 (typ)

Input leakage

Input leakage on A/D pins:(3)

PE[0:7]
VRL, VRH

400
1.0

nA
A

(1) For fOP < 2MHz, source impedances should be approximately 10k. For fOP 2MHz, source impedances should be in the range
5-10k. Source impedances greater than 10k. have an adverse effect on A/D accuracy, because of input leakage

(2) Performance verified down to VR = 2.5V, however accuracy is tested and guaranteed at VR = 5V 10%
(3) PE[4,5] available on 68-pin CLCC devices and 64-pin QFP MC68HC(7)11PB8 devices only

TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-11

205

A.5.4

Serial peripheral interface timing

(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic (1)

Num

Operating frequency

Symbol
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave

Cycle time

Enable lead time (2)

Enable lag time (2)

Clock (SCK) high time

Clock (SCK) low time

Input data set-up time

Input data hold time

8
9
10
11
12

Access time (from high-z to data active)

Disable time (hold time to high-z state)
Data valid (after enable edge) (3)
Output data hold time (after enable edge)
Rise time (3)
SPI outputs (SCK, MOSI and MISO)
SPI inputs (SCK, MOSI, MISO and SS)
Fall time (3)
SPI outputs (SCK, MOSI and MISO)
SPI inputs (SCK, MOSI, MISO and SS)

fOP(M)
fOP(S)
tCYC(M)
tCYC(S)
tLEAD(M)
tLEAD(S)
tLAG(M)
tLAG(S)
tW(SCKH)M
tW(SCKH)S
tW(SCKL)M
tW(SCKL)S
tSU(M)
tSU(S)
tH(M)
tH(S)
tA
tDIS
tV(S)
tHO

3.0MHz
Min. Max.
0
0.5
0
3.0
2.0

333

240

227

127

227

127

100

0
120

167

167
0

4.0MHz
Min. Max.
0
0.5
0
4.0
2.0

250

200

130

100

0
120

125

125
0

4.4MHz
Min. Max.
0
0.5
0
4.4
2.0

225

200

130

100

0
120

125

125
0

Unit
fOP
MHz
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tRM
tRS

100
2.0

ns
s

tFM
tFS

100
2.0

ns
s

(1) All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
(2) Signal production depends on software.
(3) Assumes 200pF load on all SPI pins.

TPG

MOTOROLA
A-12

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

206

SS
(input)

SS is held high on master

SCK (CPOL=0)
(output)

SCK (CPOL=1)
(output)

5
(see note)
4
5
(see note)
4
6

MISO
(input)

7
MSB in

Bit 61
11

10 (ref.)

MOSI
(output)

Master MSB out

LSB in
10

11 (ref.)

Bit 61

Master LSB out

Note: This first clock edge is generated internally, but is not seen at the SCK pin.

Figure A-9 SPI master timing (CPHA = 0)

SS
(input)

SS is held high on master

SCK (CPOL=0)
(output)

(see note)

4
12

SCK (CPOL=1)
(output)

(see note)
4
6

MISO
(input)

MSB in
10 (ref.)

Bit 61
11

MOSI
(output)

Master MSB out

7
LSB in

10
Bit 61

11 (ref.)
Master LSB out
12

Note: This last clock edge is generated internally, but is not seen at the SCK pin.

Figure A-10 SPI master timing (CPHA = 1)

TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-13

207

SS
(input)
1

SCK (CPOL=0)
(input)

4
2
5

SCK (CPOL=1)
(input)

4
6

MOSI
(input)

7
MSB in

Bit 61

MISO
(output)

10
Slave MSB out

LSB in
11

Bit 61

Slave LSB out

(see note)

Note: Not defined, but normally the MSB of character just received.

Figure A-11 SPI slave timing (CPHA = 0)

SS
(input)
1

4
2
5

SCK (CPOL=1)
(input)

4
6

MOSI
(input)

7
MSB in

MISO
(output)

13
5

SCK (CPOL=0)
(input)

(see note)

Bit 61

LSB in
11

Slave MSB out

Bit 61

9
Slave LSB out

Note: Not defined, but normally the LSB of character last transmitted.

Figure A-12 SPI slave timing (CPHA = 1)

TPG

MOTOROLA
A-14

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

208

A.5.5

Non-multiplexed expansion bus timing

(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH)

Num

Characteristic (1)

Symbol

1
2
3
4A
4B
9
11
12
17
18
19
21
29
39
57

Frequency of operation (E clock frequency)

E clock period
Pulse width, E low (2), (3)
Pulse width, E high (2), (3)
E clock
rise time
fall time
Address hold time (3)
Address delay time (3)
Address valid to E rise time (3)
Read data set-up time
Read data hold time
Write data delay time
Write data hold time (3)
MPU address access time (3)
Write data set-up time (3)
Address valid to data three-state time

fOP
tCYC
PWEL
PWEH
tR
tF
tAH
tAD
tAV
tDSR
tDHR
tDDW
tDHW
tACCA
tDSW
tAVDZ

3.0MHz
Min. Max.
0
3.0
333

147

142

18
32

82
65

40
42

203

102

4.0MHz
Min. Max.
0
4.0
250

105

100

15
21

71
34

40
31

144

4.4MHz
Min. Max.
0
4.4
225

15
18

68
24

40
28

122

Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

(1) All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
(2) Input clock duty cycles other than 50% will affect the bus performance.
(3) For fOP 2MHz the following formulae may be used to calculate parameter values:
PWEL = tCYC/2 20ns
PWEH = tCYC/2 25ns
tAH = tCYC/8 10ns
tAD = tCYC/8 + 40ns
tAV = PWEL tAD
tDHW = tCYC/8
tACCA = tCYC tF tDSR tAD
tDSW = PWEH tDDW

TPG

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-15

209

1
3

E clock
4A
11

R/W,
Address
29

Data
(read)
57

Data
(write)

Figure A-13 Expansion bus timing

A.6

EEPROM characteristics

Characteristic

Temperature range
40 to +85C

Unit

Programming time, tEEPROG(1)

<1MHz, RCO enabled
12MHz, RCO disabled
2MHz & whenever RCO enabled
Erase time: byte, row and bulk (1)
Write/erase endurance (2)
Data retention (2)

10
20
10
10
10000
10

ms
ms
cycles
years

(1) The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register)
for EEPROM programming and erasure when the E clock frequency is less than 1.0MHz.
(2) Refer to the current issue of Motorolas quarterly Reliability Monitor Report for the latest
failure rate information.

TPG

MOTOROLA
A-16

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

210

A.7

EPROM characteristics
(VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted)
Characteristic
Symbol
Min
Programming voltage
VPPE
12
Programming voltage detect level
VPPH
TBD
Programming time
tEPROG

Max
12.75
TBD
5

Unit
V
V
ms

MC68HC11PA8

ELECTRICAL SPECIFICATIONS

MOTOROLA
A-17

THIS PAGE LEFT BLANK INTENTIONALLY

MOTOROLA
A-18

ELECTRICAL SPECIFICATIONS

MC68HC11PA8

B
MECHANICAL DATA AND ORDERING
INFORMATION

PD0/RXD

MODA/LIR

MODB/VSTBY

RESET

XTAL

EXTAL

PC7/D7

PC6/D6

PC5/D5

PC4/D4

PC3/D3

PC2/D2

PC1/D1

PC0/D0

PF0/A0

The
MC68HC11PA8/MC68HC11PB8,
and
an
OTPROM
version
of
the
MC68HC711PA8/MC68HC711PB8, are available packaged in a 64-pin quad flat pack (QFP).

PD1/TXD

PF1/A1

PD2/MISO

PF2/A2

PD3/MOSI/SDA

PF3/A3

PD4/SCK/SCL

PF4/A4

PD5/SS

PF5/A5

VSS

PF6/A6

VDDEX

PF7/A7

VDD

VSS

PE6/AD6/SDA

XIRQ/VPPE

PG7/R/W

IRQ

VDDAD

VSSEX

33
PE7/AD7/SCL

16
26

PE3/AD3

PA0/IC3

XFC

34
25

VDDSYN

PE2/AD2

PA1/IC2

PB0/A8

PE1/AD1

PA2/IC1

PB1/A9

PB2/A10

PE0/AD0

PA3/OC5/IC4/OC1

PB3/A11

VRL

PA4/OC4/OC1

PB4/A12

PB5/A13

VRH

PA5/OC3/OC1

VSSAD

PB6/A14

PB7/A15

PA7/PAI/OC1
PA6/OC2/OC1

Figure B-1 64-pin QFP pinout (MC68HC11PA8)

TPG

MC68HC11PA8

MECHANICAL DATA AND ORDERING INFORMATION

MOTOROLA
B-1

211

PD0/RXD

MODA/LIR

MODB/VSTBY

RESET

XTAL

EXTAL

PC7/D7

PC6/D6

PC5/D5

PC4/D4

PC3/D3

PC2/D2

PC1/D1

PC0/D0

PF0/A0

PD1/TXD

PF1/A1

PD2/MISO

PF2/A2

PD3/MOSI/SDA

PF3/A3

PD4/SCK/SCL

PF4/A4

PD5/SS

PF5/A5

VSS

PF6/A6

VDDEX

PF7/A7

VDD

VSS/VSSAD

PE6/AD6/SDA

XIRQ/VPPE

PG7/R/W

IRQ

VDDAD

PE5

33
PE7/AD7/SCL

16
26

PE4

PA0/IC3

XFC

34
25

VDDSYN

PE3

PA1/IC2

PB0/A8

PE2

PA2/IC1

PB1/A9

PB2/A10

PE1

PA3/OC5/IC4/OC1

PB3/A11

PE0

PA4/OC4/OC1

PB4/A12

PB5/A13

VRL

PA5/OC3/OC1

VRH

PB6/A14

PB7/A15

PA7/PAI/OC1
PA6/OC2/OC1

Figure B-2 64-pin QFP pinout (MC68HC11PB8)

TPG

MOTOROLA
B-2

MECHANICAL DATA AND ORDERING INFORMATION

MC68HC11PA8

212

L
48

-B-

Case No. 840C

64 lead QFP

0.20 M H A B S D S

-AL

0.05 A B

0.20 M C A B S D S

- A, B, D Detail A
F

Detail A
64

17
16

-DA

Base
metal

0.20 M C A B S D S

Section BB

0.05 A B

0.20 M C A B S D S

S
0.20 M H A B S D S

U
T

Detail C
M

R
C
-CSeating
plane

-H- Datum
plane
H

W
X

Dim.
A
B
C
D
E
F
G
H
J
K
L

Min.
Max.
13.90
14.10
13.90
14.10
2.067
2.457
0.30
0.45
2.00
2.40
0.30

0.80 BSC
0.067
0.250
0.130
0.230
0.50
0.66
12.00 REF

Notes
1. Datum Plane H is located at bottom of lead and is coincident with
the lead where the lead exits the plastic body at the bottom of the
parting line.
2. Datums AB and D to be determined at Datum Plane H.
3. Dimensions S and V to be determined at seating plane C.
4. Dimensions A and B do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side. Dimensions A and B do
include mould mismatch and are determined at Datum Plane H.
5. Dimension D does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 total in excess of the D dimension
at maximum material condition. Dambar cannot be located on the
lower radius or the foot.
6. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
7. All dimensions in mm.

Dim.
M
N
P
Q
R
S
T
U
V
W
X

Min.
Max.
5
10
0.130
0.170
0.40 BSC
2
8
0.13
0.30
16.20
16.60
0.20 REF
9
15
16.20
16.60
0.042 NOM
1.10
1.30

Figure B-3 64-pin QFP mechanical dimensions

TPG

MC68HC11PA8

MECHANICAL DATA AND ORDERING INFORMATION

MOTOROLA
B-3

213

B.1

Ordering information

Use the information in the following tables to specify the appropriate device when placing an
order.

Table B-1 Standard device ordering information

Package

Temperature

Description

64-pin QFP

40 to +85C

OTPROM (with security feature)

64-pin QFP

40 to +85C

OTPROM (with security feature)

Frequency
3MHz
4MHz
3MHz
4MHz

MC order number
MC68S711PA8CFU3
MC68S711PA8CFU4
MC68S711PB8CFU3
MC68S711PB8CFU4

Table B-2 Custom ROM device ordering information

Package

Temperature

Description

64-pin QFP

40 to +85C

Custom ROM

64-pin QFP

40 to +85C

Custom ROM

Frequency
3MHz
4MHz
3MHz
4MHz

Source device
MC68HC11PA8CFU3
MC68HC11PA8CFU4
MC68HC11PB8CFU3
MC68HC11PB8CFU4

To specify a custom ROM device, first select a standard source device, then complete a custom
ROM device order form. The order form can be obtained from your local Motorola sales office or
distributer.

TPG

MOTOROLA
B-4

MECHANICAL DATA AND ORDERING INFORMATION

MC68HC11PA8

214

C
DEVELOPMENT SUPPORT
The following information provides a reference to development tools for the M68HC11 family of
microcontrollers. For more detailed information please refer to the appropriate system manual.

Table C-1 M68HC11 development tools

Devices
MC68HC11PA8,
MC68HC711PA8

Note:

Evaluation
boards

Evaluation
modules

Evaluation systems/kits

Programmer boards

M68EM11PA8

M68SPGMR11

Target cables for the evaluation module should be ordered separately.

C.1

EVS Evaluation system

The EVS is an economical tool for designing, debugging and evaluating target systems based on
the MC68HC11PA8 and MC68HC711PA8 device types. The two printed circuit boards that
comprise the EVS are the M68EM11PA8 emulator module and the M68HC11PFB platform board.
The main features of the EVS are as follows:

Monitor/debugger firmware

Single-line assembler/disassembler

Host computer download capability

Dual memory maps:

64Kbyte monitor map that includes 16Kbytes of monitor EPROM

MC68HC711PA8 user map that includes 64Kbytes of emulation RAM

MCU extension I/O port for single chip, expanded and special test operating modes

RS-232C terminal and host I/O ports

Logic analyser connector

C
TPG

MC68HC11PA8

DEVELOPMENT SUPPORT

MOTOROLA
C-1

215

C.2

MMDS11 Motorola modular development system

The MMDS11 is an emulator system that provides a bus state analyser and real-time memory
windows. The units integrated design environment includes an editor, an assembler, user
interface and source-level debug. A complete MMDS11 consists of:

A station module the metal MMDS11 enclosure, containing the control board and the
internal power supply. Most system cables connect to the MMDS11 station module. (The cable
to an optional target system, however, runs through an aperture in the station module
enclosure to connect directly to the emulator module).

An emulator module (EM) such as the EM11PA8: a printed circuit board that enables
system functionality for a specific set of MCUs. The EM fits into the station module through a
sliding panel in the enclosure top. The EM has a connector for the target cable.

Two logic clip cable assemblies twisted pair cables that connect the station module to your
target system, a test fixture, a clock or any other circuitry useful for evaluation or analysis. One
end of each cable assembly has a moulded connector, which fits into station module pod A or
pod B. Leads at the other end of the cable terminate in female probe tips. Ball clips come with
the cables.

A 9-lead RS-232 serial cable the cable that connects the station module to the host
computers RS-232 port.

C.3

SPGMR11 Serial programmer system

The SPGMR11 is an economical tool for programming M68HC11 MCUs. The system consists of
the M68SPGMR11 unit and a programming module which adapts the SPGMR11 to the
appropriate MCU and package type. The programming module can be ordered as
M68PA11PA8FU64 for 64-pin QFP packaged devices, or M68PA11KA4FN68 for 68-pin CLCC
packaged devices.

C
TPG

MOTOROLA
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DEVELOPMENT SUPPORT

MC68HC11PA8

216

GLOSSARY
This section contains abbreviations and specialist words used in this data
sheet and throughout the industry. Further information on many of the terms
may be gleaned from Motorolas M68HC11 Reference Manual,
M68HC11RM/AD, or from a variety of standard electronics text books.

$xxxx

The digits following the $ are in hexadecimal format.

%xxxx

The digits following the % are in binary format.

A/D, ADC

Analog-to-digital (converter).

Bootstrap mode

In this mode the device automatically loads its internal memory from an
external source on reset and then allows this program to be executed.

Byte

Eight bits.

CCR

Condition codes register; an integral part of the CPU.

CERQUAD

A ceramic package type, principally used for EPROM and high temperature
devices.

Clear

0 the logic zero state; the opposite of set.

CMOS

Complementary metal oxide semiconductor. A semiconductor technology

chosen for its low power consumption and good noise immunity.

COP

Computer operating properly. aka watchdog. This circuit is used to detect

device runaway and provide a means for restoring correct operation.

CPU

Central processing unit.

D/A, DAC

Digital-to-analog (converter).

EEPROM

Electrically erasable programmable read only memory. aka EEROM.

EPROM

Erasable programmable read only memory. This type of memory requires

exposure to ultra-violet wavelengths in order to erase previous data. aka
PROM.

ESD

Electrostatic discharge.

Expanded mode

In this mode the internal address and data bus lines are connected to
external pins. This enables the device to be used in much more complex
systems, where there is a need for external memory for example.

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GLOSSARY

MOTOROLA
i

217

EVS

Evaluation system. One of the range of platforms provided by Motorola for

evaluation and emulation of their devices.

HCMOS

High-density complementary metal oxide semiconductor. A semiconductor

technology chosen for its low power consumption and good noise immunity.

I2C bus

The I2C bus is a two wire, bidirectional serial communications protocol. I2C
bus is a proprietary Philips interface bus.

I/O

Input/output; used to describe a bidirectional pin or function.

Input capture

(IC) This is a function provided by the timing system, whereby an external

event is captured by storing the value of a counter at the instant the event
is detected.

Interrupt

This refers to an asynchronous external event and the handling of it by the

MCU. The external event is detected by the MCU and causes a
predetermined action to occur.

IRQ

Interrupt request. The overline indicates that this is an active-low signal

format.

K byte

A kilo-byte (of memory); 1024 bytes.

LCD

Liquid crystal display.

LSB

Least significant byte.

M68HC11

Motorolas family of advanced 8-bit MCUs.

MCU

Microcontroller unit.

MSB

Most significant byte.

Nibble

Half a byte; four bits.

NRZ

Non-return to zero.

Opcode

The opcode is a byte which identifies the particular instruction and operating
mode to the CPU. See also: prebyte, operand.

Operand

The operand is a byte containing information the CPU needs to execute a

particular instruction. There may be from 0 to 3 operands associated with an
opcode. See also: opcode, prebyte.

Output compare

(OC) This is a function provided by the timing system, whereby an external

event is generated when an internal counter value matches a predefined
value.

PLCC

Plastic leaded chip carrier package.

PLL

Phase-locked loop circuit. This provides a method of frequency

multiplication, to enable the use of a low frequency crystal in a high
frequency circuit.

Prebyte

This byte is sometimes required to qualify an opcode, in order to fully specify

a particular instruction. See also: opcode, operand.

TPG

MOTOROLA
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GLOSSARY

MC68HC11PA8

218

Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are
permanently connected to either ground or VDD.
PWM

Pulse width modulation. This term is used to describe a technique where the
width of the high and low periods of a waveform is varied, usually to enable
a representation of an analog value.

QFP

Quad flat pack package.

RAM

Random access memory. Fast read and write, but contents are lost when
the power is removed.

RFI

Radio frequency interference.

RTI

Real-time interrupt.

ROM

Read-only memory. This type of memory is programmed during device

manufacture and cannot subsequently be altered.

RS-232C

A standard serial communications protocol.

SAR

Successive approximation register.

SCI

Serial communications interface.

Set

1 the logic one state; the opposite of clear.

Silicon glen

An area in the central belt of Scotland, so called because of the

concentration of semiconductor manufacturers and users found there.

Single chip mode

In this mode the device functions as a self contained unit, requiring only I/O
devices to complete a system.

SPI

Serial peripheral interface.

Test mode

This mode is intended for factory testing.

TTL

Transistor-transistor logic.

UART

Universal asynchronous receiver transmitter.

VCO

Voltage controlled oscillator.

Watchdog

see COP.

Wired-OR

A means of connecting outputs together such that the resulting composite

output state is the logical OR of the state of the individual outputs.

Word

Two bytes; 16 bits.

XIRQ

Non-maskable interrupt request. The overline indicates that this has an

active-low signal format.

TPG

MC68HC11PA8

GLOSSARY

MOTOROLA
iii

219

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

MOTOROLA
iv

GLOSSARY

MC68HC11PA8

220

INDEX
In this index numeric entries are placed first; page references in italics indicate that the reference
is to a figure.

4XCLK 2-9 2-10

A
A/D 11-1
accuracy of conversion 6-6
ADCTL A/D control and status reg. 11-8
ADR1ADR4 A/D converter results reg. 11-10
block diagram 11-2
channels 11-7 11-9
charge pump 11-3
clocks 11-4
conversion 11-3 11-4 11-5 11-8
input pin 11-3
multiple-channel operation 11-8 11-9
multiplexer 11-3 11-7
OPTION System configuration options reg. 1 11-5
overview 11-2
pins 11-1
reset 5-9
single-channel operation 11-7
STOP mode 11-10
synchronisation 11-4
WAIT mode 11-10
accumulators 3-2
ADCTL A/D control and status reg. 11-8
addressing modes 3-7
address-mark wakeup 7-4
ADPU - bit in OPTION 11-6
ADR1ADR4 A/D converter results reg. 11-10
analog-to-digital converter - see A/D
AUTO - bit in PLLCR 2-9

B
baud rates
bootloader 4-2
SCI 7-6
BCS - bit in PLLCR 2-9
block diagrams
A/D 11-2

MC68HC(7)11PA8 1-3
PLL 2-6
pulse accumulator 10-21
SCI 7-3
SCI baud rate 7-1
SPI 9-2
timer 10-5
timer clock divider chains 10-3
bootloader 4-2 4-5 4-6
BPPUE - bit in PPAR 6-10
BPROT Block protect reg. 4-20
BPRT[5:0] - bits in BPROT 4-20
BRST - bit in SCBDH 7-6
BSPL - bit in SCBDH 7-6
BTST - bit in SCBDH 7-6
BULKP - bit in BPROT 4-20
BWC - bit in PLLCR 2-10
bypassing 2-2 2-7
BYTE - bit in PPROG 4-25

C
C-bit in CCR 3-5
CCF - bit in ADCTL 11-8
CCR condition code reg. 3-4
CDCA - bits in ADCTL 11-9
CFORC Timer compare force reg. 10-10
charge pump, A/D 11-3
CLK4X - bit in CONFIG 4-13
clock monitor 5-3 5-5
clocks
4XCLK 2-9 2-10
A/D 11-4
CMOS compatible 2-3
E 2-3 4-19
monitor reset 5-3 5-5
SPI 9-4
stretching 4-18
timer divider chains 10-3
CME - bit in OPTION 5-5
coherency, timer 10-10
CONFIG System configuration reg. 4-12
programming 4-27

TPG

MC68HC11PA8

INDEX

MOTOROLA
v

221

configuration 4-12
conversion, A/D 11-3 11-4 11-5
COP 10-2 10-20
CONFIG Configuration control reg. 5-5
COPRST Arm/reset COP timer circuitry reg. 5-3
enable 5-6
OPTION System configuration options reg. 1 5-4
rates 5-2 5-5
reset 5-2 5-3 5-9
timeout 5-2
COPRST Arm/reset COP timer circuitry reg. 5-3
corruption
of A/D 6-6
of memory 2-3
CPHA - bit in SPCR 9-3 9-4 9-7
CPOL - bit in SPCR 9-7
CPU
accumulators (A, B and D) 3-2
architecture 3-1
CCR condition code reg. 3-4
index registers (IX, IY) 3-2
program counter (PC) 3-4
programming model 3-1
registers 3-1
reset 5-7
CR[1:0] - bits in OPTION 5-5
CSEL - bit in OPTION 11-6
CWOM - bit in OPT2 6-11

,
,

EEON - bit in CONFIG 4-13

EEPGM - bit in PPROG 4-25
EEPROM 4-24 4-27
erased state ($FF) 4-24
erasing 4-26 4-27
PPROG EEPROM programming control reg. 4-24
security 4-28
EEx - bits in INIT2 4-15
ELAT - bit in EPROG 4-22
EPGM - bit in EPROG 4-23
EPROG EPROM programming control reg. 4-22
EPROM 4-6 4-22 4-24
device 1-1
EPROG EPROM programming control reg. 4-22
erased state ($FF) 4-22
programming 4-23
ERASE - bit in PPROG 4-25
erased state
EEPROM ($FF) 4-24
EPROM ($FF) 4-22
error detection, SCI 7-5
ESD protection A-1
EVEN - bit in PPROG 4-24
event counter - see pulse accumulator
EVS Evaluation system C-1
EXCOL - bit in EPROG 4-23
EXROW - bit in EPROG 4-23
EXT4X - bit in OPT2 4-19
EXTAL pin 2-3
EXTALi 2-6

D
DAC 11-3
data format, SCI 7-2
data types 3-6
DDA[7:0] - bits in DDRA 6-2
DDB[7:0] - bits in DDRB 6-3
DDC[7:0] - bits in DDRC 6-4
DDD[5:0] - bits in DDRD 6-5
DDF[7:0] - bits in DDRF 6-7
DDG[7:0] - bits in DDRG 6-8
DDRA Data direction reg. for port A
DDRB Data direction reg. for port B
DDRC Data direction reg. for port C
DDRD Data direction reg. for port D
DDRF Data direction reg. for port F
DDRG Data direction reg. for port G
development tools C-1
DIR - direct addressing mode 3-7
DLY - bit in OPTION 4-17
mask option 4-17
DWOM - bit in SPCR 9-6

F
FCME - bit in OPTION 5-5
FE - bit in SCSR1 7-11
FOC[1:5] - bits in CFORC 10-11
FPPUE - bit in PPAR 6-10
free-running counter 10-1

6-2
6-3
6-4
6-5
6-7
6-8

E
E clock pin 2-5
EDGxA and EDGxB - bits in TCTL2 10-7
EELAT - bit in PPROG 4-25

G
GPPUE - bit in PPAR 6-10

H
H-bit in CCR 3-6
HPPUE - bit in PPAR 6-10
HPRIO Highest priority I-bit interrupt & misc. reg. 4-11

I
I/O, on reset 5-8
I2C bus 8-1
arbitration 8-5
clock synchronization 8-5

TPG

MOTOROLA
vi

INDEX

MC68HC11PA8

222

configuration 8-2
data transfer 8-4
handshaking 8-6
MADR I2C bus address register 8-7
MCR I2C bus control register 8-8
MDR I2C bus data register 8-10
MFDR I2C bus frequency divider register 8-7
MSR I2C bus status register 8-9
programming considerations 8-11
protocol 8-2
repeated START signal 8-5
reset 5-9
SCL 8-4 8-5
SDA 8-4
slave address transmission 8-4
START signal 8-4
STOP signal 8-4
I4/05 - bit in PACTL 10-8 10-22
I4/O5F - bit in TFLG1 10-14
I4/O5I - bit in TMSK1 10-13
I-bit in CCR 3-5 5-15
IC1FIC3F - bits in TFLG1 10-14
IC1IIC3I - bits in TMSK1 10-13
IDLE - bit in SCSR1 7-10
idle-line wakeup 7-4
ILIE - bit in SCCR2 7-9
illegal opcode trap 5-15
ILT - bit in SCCR1 7-8
IMM - immediate addressing mode 3-7
IND, X/Y - indexed addressing modes 3-8
index registers (IX, IY) 3-2
INH - inherent addressing mode 3-8
INIT RAM and I/O mapping reg. 4-14
initialization 4-12
input capture 10-6
instruction set 3-8
internal oscillator 4-16 11-4 11-5 A-16
interrupts
I-bit 3-5 5-15
illegal opcode trap 5-15
IRQ 2-12
maskable 5-16
multiple sources 2-12
non-maskable 5-15
priorities 5-10
priority resolution 5-20
SCI 5-23 7-14
sensitivity 2-12
stacking 5-14
SWI 5-15
triggering 2-12
types 5-14
vectors 5-13
wired-OR 2-12
X-bit 3-6 5-15
XIRQ 2-12 5-15
IRQ pin 2-12
IRQE - bit in OPTION 4-16
IRVNE - bit in OPT2 4-19

J
junction temperature, chip A-1

L
LCD driver interface 9-1
LIR pin 2-13
LIRDV - bit in OPT2 4-18
LOOPS - bit in SCCR1 7-7
low power modes
RAM 4-5
stand-by connections 2-13
stand-by voltage 2-13
STOP 5-17
WAIT 5-16
low voltage inhibit circuit 2-3
LSBF - bit in OPT2 9-10
LVI 2-3

M
M - bit in SCCR1 7-8
MAAS - bit in MSR 8-9
MADR I2C bus address register 8-7
MADR[7:1] - bits in MADR 8-7
MAL - bit in MAL 8-9
mask options 1-2
oscillator buffer type 2-4
PLL crystal frequency 2-7
security 4-28
stabilization delay timing 4-17
state of SYNR on reset 2-11
maximum ratings A-1
MBB - bit in MSR 8-9
MBC[4:0] - bits in MFDR 8-7
MBE - bit in EPROG 4-22
MBSP - bit in CONFIG 8-6
M-bus see I2C bus
MC68HC711PA8 1-1
MCF - bit in MSR 8-9
MCR I2C bus control register 8-8
MCS - bit in PLLCR 2-10
MDA - bit in HPRIO 4-11
MDR I2C bus data register 8-10
memory
corruption of 2-3
EEPROM 4-24 4-27
EPROM 4-6 4-22 4-24
map 4-4
mapping 4-4 4-14 4-15
protection 4-20 4-28
RAM 4-5
RAM stand-by connections 2-13
register map 4-6
ROM 4-6
stretch external access 4-18

,
,

TPG

MC68HC11PA8

INDEX

MOTOROLA
vii

223

memory map, on reset 5-7

MEN - bit in MCR 8-8
MFDR I2C bus frequency divider register 8-7
MIEN - bit in MCR 8-8
MIF - bit in MSR 8-10
MISO 9-4
MODA/LIR pin 2-13
MODB/VSTBY pin 2-13
MODF - bit in SPSR 9-8
MOSI 9-4
MSR I2C bus status register 8-9
MSTA - bit in MCR 8-8
MSTR - bit in SPCR 9-5 9-6
MTX - bit in MCR 8-8
MULT - bit in ADCTL 11-9
multiplexer, A/D 11-3 11-7
multiplication factor, PLL 2-11

overflow bit in CCR 3-5

P
,

N
N-bit in CCR 3-5
NF - bit in SCSR1 7-11
NMI 2-12 5-15
NOCOP - bit in CONFIG 5-6
noise 2-2 2-5 2-7
non-maskable interrupt 2-12
NOSEC - bit in CONFIG 4-29

,
,

packages
options 2-1 B-1
thermal characteristics A-1
PACNT Pulse accumulator count reg. 10-23
PACTL Pulse accumulator control reg. 10-22
PAEN - bit in PACTL 10-22
PAIF - bit in TFLG2 10-24
PAII - bit in TMSK2 10-24
PAMOD - bit in PACTL 10-22
PAOVF - bit in TFLG2 10-23
PAOVI - bit in TMSK2 10-23
PAREN - bit in CONFIG 6-12
PE - bit in SCCR1 7-8
PEDGE - bit in PACTL 10-22
PF - bit in SCSR1 7-11
phase-locked loop - see PLL
pins
E clock 2-5
EXTAL 2-3
IRQ 2-12
LIR 2-13
MODA/LIR 2-13
MODB/VSTBY 2-13
OC1, special features 10-4 10-9
R/W 2-13
RESET 2-3 5-2
VDD, VSS 2-2
VDDSYN 2-6
VPPE 2-12
VRH, VRL 2-13
VSTBY 2-13
XFC 2-6
XIRQ/VPPE 2-12
XOUT 4-13
XTAL 2-3
PLL 2-6
bandwidth 2-7
block diagram 2-6
changing frequency 2-8
crystal frequency mask option 2-7
maximum frequency 2-7
multiplication factor 2-11
PLLCR PLL control reg. 2-9
synchronisation 2-8
SYNR Synthesizer program reg. 2-11
VCOOUT 2-9
PLLCR PLL control reg. 2-9
PLLON - bit in PLLCR 2-9
POR 5-1
stabilization delay 5-1
PORTA Port A data register 6-2
PORTB Port B data register 6-3
PORTC Port C data register 6-4
PORTD Port D data register 6-5
PORTE Port E data register 6-6

O
OC1D Output compare 1 data reg. 10-11
OC1D[7:3] - bits in OC1D 10-11
OC1FOC4F - bits in TFLG1 10-14
OC1IOC4I - bits in TMSK1 10-13
OC1M Output compare 1 mask reg. 10-11
OC1M[7:3] - bits in OC1M 10-11
ODD - bit in PPROG 4-24
OL[2:5] - bits in TCTL1 10-12
OM[2:5] - bits in TCTL1 10-12
operating modes 4-1
baud rates 4-2
bootstrap 4-2
expanded 4-1
HPRIO register 4-11
selection of 2-13 4-10
single chip 4-1
STOP 4-5 5-17
test 4-2
VSTBY 4-5
WAIT 5-16
OPT2 System configuration options reg. 2 4-18
OPTION System configuration options reg. 1 5-4 11-5
OR - bit in SCSR1 7-11
ordering information B-4
oscillator 2-3
connections 2-4
output compare 10-9

TPG

MOTOROLA
viii

INDEX

MC68HC11PA8

224

PORTF Port F data register 6-7

PORTG Port G data register 6-8
ports
A (Timer) 2-14 6-2
B (A[15:8]) 2-14
B (ADDR[15:8]) 6-3
C (D[7:0]) 2-15
C (DATA[7:0]) 6-4
D (SCI, SPI/I2C bus) 2-16 6-5
DDRA Data direction reg. for port A 6-2
DDRB Data direction reg. for port B 6-3
DDRC Data direction reg. for port C 6-4
DDRD Data direction reg. for port D 6-5
DDRF Data direction reg. for port F 6-7
DDRG Data direction reg. for port G 6-8
E (A/D, I2C bus) 2-16 6-6
F (A[7:0]) 2-17
F (ADDR[7:0]) 6-7
G (R/W) 2-17 6-8
PORTA Port A data register 6-2
PORTB Port B data register 6-3
PORTC Port C data register 6-4
PORTD Port D data register 6-5
PORTE Port E data register 6-6
PORTF Port F data register 6-7
PORTG Port G data register 6-8
signals 2-14
power-on reset - see POR
PPAR Port pull-up assignment reg. 6-10
PPROG EEPROM programming control reg. 4-24
PR[1:0] - bits in TMSK2 4-21 10-15
prebyte 3-7
priorities, resets and interrupts 5-10 5-11
program counter (PC) 3-4
programming
CONFIG 4-27
EEPROM 4-24
EPROM 4-23
protection
of memory 4-20 4-28
registers 4-10
PSEL[4:0] - bits in HPRIO 5-11
PT - bit in SCCR1 7-8
PTCON - bit in BPROT 4-20
pull-ups 6-10
pulse accumulator 10-1 10-20
block diagram 10-21
PACNT Pulse accumulator count reg. 10-23
PACTL Pulse accumulator control reg. 10-22
reset 5-8
TFLG2 Timer interrupt flag 2 reg. 10-23
TMSK2 Timer interrupt mask 2 reg. 10-23

RAM 4-5
data retention 4-5
security 4-28
RAM[3:0] - bits in INIT 4-14
ratiometric conversions 11-4
RBOOT - bit in HPRIO 4-11
RDRF - bit in SCSR1 7-10
RE - bit in SCCR2 7-9
real-time interrupt - see RTI
receiver flags, SCI 7-13
REG[3:0] - bits in INIT 4-14
REL - relative addressing mode 3-8
RESET pin 2-3
resets
circuit 2-3
clock monitor 5-3 5-5
COP 5-2 5-3
effect on A/D 5-9
effect on COP 5-9
effect on CPU 5-7
effect on I/O 5-8
effect on I2C bus 5-9
effect on memory map 5-7
effect on pulse accumulator 5-8
effect on RTI 5-8
effect on SCI 5-9
effect on SPI 5-9
effect on system 5-9
effect on timer 5-8
effects of 5-7
external 5-2
HPRIO Highest priority I-bit interrupt and misc. reg.
5-11
power-on, POR 5-1
priorities 5-10
processing flow 5-18
RESET pin 5-2
vectors 5-7 5-13
resetting the COP watchdog 5-3
RFI 2-5
RIE - bit in SCCR2 7-9
ROM 4-6
ROMAD - bit in CONFIG 4-12
ROMON - bit in CONFIG 4-13
ROW - bit in PPROG 4-25
RTI 10-2 10-17
PACTL Pulse accumulator control reg. 10-19
rates 10-17
reset 5-8
TFLG2 Timer interrupt flag reg. 2 10-18
TMSK2 Timer interrupt mask reg. 2 10-17
RTIF - bit in TFLG2 10-18
RTII - bit in TMSK2 10-18
RTR[1:0] - bits in PACTL 10-19
RWU - bit in SCCR2 7-4 7-9
RXAK - bit in MSR 8-10

R/T[7:0] - bits in SCDRL 7-12

R/W pin 2-13
R8 - bit in SCDRH 7-12
RAF - bit in SCSR2 7-12

TPG

MC68HC11PA8

INDEX

MOTOROLA
ix

225

S
S-bit in CCR 3-6
SBK - bit in SCCR2 7-9
SBR[12:0] - bits in SCBDH/L 7-6
SCAN - bit in ADCTL 11-8
SCBDH, SCBDL SCI baud rate control reg. 7-6
SCCR1 SCI control reg. 1 7-7
SCCR2 SCI control reg. 2 7-9
SCDRH, SCDRL SCI data high/low reg. 7-12
SCI 7-1
baud rate 7-1 7-6
block diagram 7-3
data format 7-2
error detection 7-5
interrupt source resolution 5-23 7-14
pins 7-1
receive operation 7-2
reset 5-9
SCBDH, SCBDL SCI baud rate control reg. 7-6
SCCR1 SCI control reg. 1 7-7
SCCR2 SCI control reg. 2 7-9
SCDRH, SCDRL SCI data high/low reg. 7-12
SCSR1 SCI status reg. 1 7-10
SCSR2 SCI status reg. 2 7-12
status flags 7-13
transmit operation 7-2
wakeup 7-4
SCK 9-4
SCL 8-4 8-5
SCSR1 SCI status reg. 1 7-10
SCSR2 SCI status reg. 2 7-12
SDA 8-4
security 4-28
mask option 4-28
NOSEC bit 4-29
sensitivity, of interrupts 2-12 4-16 4-20 6-12
serial communications interface - see SCI
serial peripheral interface - see SPI
slave select (SS) 9-4
slow memory 4-18
SMOD - bit in HPRIO 4-11
software interrupt (SWI) 5-15
SPCR Serial peripheral control reg. 9-6
SPDR SPI data reg. 9-9
SPE - bit in SPCR 9-6
SPI 9-1
block diagram 9-2
buffering 9-1 9-9
clock phase 9-3
clock polarity 9-7
clock rate 9-4 9-7
errors 9-5
master mode 9-6
MISO 9-4
MOSI 9-4
OPT2 System configuration options reg. 2 9-9
pins 9-1
polarity 9-3
reset 5-9

SCK 9-4
signals 9-3
SPCR Serial peripheral control reg. 9-6
SPDR SPI data reg. 9-9
SPSR Serial peripheral status reg. 9-8
SS 9-4
transfer formats 9-2 9-3
SPIE - bit in SPCR 9-5 9-6
SPIF - bit in SPSR 9-8
SPR1 and SPR0 - bits in SPCR 9-7
SPR2 - bit in OPT2 9-10
SPSR Serial peripheral status reg. 9-8
SRW - bit in MSR 8-10
stack pointer (SP) 3-2
stacking operations 3-3
stand-by voltage 2-13
status flags, SCI 7-13
STOP mode 4-5 5-17
disabling 3-6
stabilization delay 4-17
STRCH - bit in OPT2 4-18
stretch, external access 4-18
SWI 5-15
synchronisation, A/D 11-4
SYNR Synthesizer program reg. 2-11
SYNX[1:0] - bits in SYNR 2-11
SYNY[5:0] - bits in SYNR 2-11
system reset 5-9

T
T8 - bit in SCDRH 7-12
TC - bit in SCSR1 7-10
TCIE - bit in SCCR2 7-9
TCNT Timer counter reg. 10-12
TCTL1 Timer control reg. 1 10-12
TCTL2 Timer control reg. 2 10-7
TDRE - bit in SCSR1 7-10
TE - bit in SCCR2 7-9
test methods A-3
TFLG1 Timer interrupt flag reg. 1 10-14
TFLG2 Timer interrupt flag reg. 2 10-16
TI4/O5 Timer input capture 4/output compare 5 reg. 10-8
TIC1TIC3 Timer input capture reg. 10-8
TIE - bit in SCCR2 7-9
time accumulation - see pulse accumulator
timer 10-1
block diagram 10-5
CFORC Timer compare force reg. 10-10
clock divider chains 10-3
coherency 10-10
COP 10-20
free-running counter 10-1
input capture 10-6
OC1, special features 10-4 10-9
OC1D Output compare 1 data reg. 10-11
OC1M Output compare 1 mask reg. 10-11
output compare 10-9
pins 10-4

TPG

MOTOROLA
x

INDEX

MC68HC11PA8

226

prescaler 10-1
reset 5-8
TCNT Timer counter reg. 10-12
TCTL1 Timer control reg. 1 10-12
TCTL2 Timer control reg. 2 10-7
TFLG1 Timer interrupt flag reg. 1 10-14
TFLG2 Timer interrupt flag reg. 2 10-16
TI4/O5 Timer input capture 4/output compare 5 reg.
10-8
TIC1TIC3 Timer input capture reg. 10-8
TMSK1 Timer interrupt mask reg. 1 10-13
TMSK2 Timer interrupt mask reg. 2 4-21 10-15
TOC1TOC4 Timer output compare reg. 10-10
TMSK1 Timer interrupt mask reg. 1 10-13
TMSK2 Timer interrupt mask reg. 2 4-21 10-15
TOC1TOC4 Timer output compare reg. 10-10
TOF - bit in TFLG2 10-16 10-18
TOI - bit in TMSK2 10-15
TRXD[7:0] - bits in MSR 8-10
TXAK - bit in MCR 8-8

XIRQ 5-15
XIRQ/VPPE 2-12
XOUT pin 4-13
xPPUE - bits in PPAR 6-10
XTAL pin 2-3

Z
Z-bit in CCR 3-5

U
UART 7-1

V
V-bit in CCR 3-5
VCOOUT 2-9
VCOT - bit in PLLCR 2-10
VDD pin 2-2
VDDSYN pin 2-6
vectors
interrupt 5-13
reset 5-7 5-13
VPPE pin 2-12
VRH, VRL pins 2-13
VSS pin 2-2
VSTBY pin 2-13

W
,

WAIT mode 2-10 5-16

WAKE - bit in SCCR1 7-8
wakeup, SCI 7-4
watchdog - see COP
WCOL - bit in SPSR 9-8
WEN - bit in PLLCR 2-10
wired-OR 2-12 2-16 4-2 6-11
WOMS - bit in SCCR1 7-7

X
,

X-bit in CCR 3-6 5-15

XFC pin 2-6

TPG

MC68HC11PA8

INDEX

MOTOROLA
xi

227

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

MOTOROLA
xii

INDEX

MC68HC11PA8

228

INTRODUCTION

PIN DESCRIPTIONS

CPU CORE AND INSTRUCTION SET

OPERATING MODES AND ON-CHIP MEMORY

RESETS AND INTERRUPTS

PARALLEL INPUT/OUTPUT

SERIAL COMMUNICATIONS INTERFACE

I2C BUS

SERIAL PERIPHERAL INTERFACE

TIMING SYSTEM

ANALOG-TO-DIGITAL CONVERTER

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA AND ORDERING INFORMATION

DEVELOPMENT SUPPORT

TPG

229

INTRODUCTION

PIN DESCRIPTIONS

CPU CORE AND INSTRUCTION SET

OPERATING MODES AND ON-CHIP MEMORY

RESETS AND INTERRUPTS

PARALLEL INPUT/OUTPUT

SERIAL COMMUNICATIONS INTERFACE

I2C BUS

SERIAL PERIPHERAL INTERFACE

TIMING SYSTEM

ANALOG-TO-DIGITAL CONVERTER

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA AND ORDERING INFORMATION

DEVELOPMENT SUPPORT
TPG

230

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

How to reach us:

Mfax: [email protected] TOUCHTONE (602) 244-6609
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USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303-675-2140
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center,
3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road,
Tai Po, N.T., Hong Kong. 852-26629298

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