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Basic Language Constructs of VHDL

This document summarizes basic language constructs in VHDL, including identifiers, reserved words, numbers/strings, signals, variables, constants, aliases, data types, operators, and VHDL guidelines. Key concepts covered are valid identifier rules, the difference between signals and variables, constant/alias usage, and an overview of data types, operators, and VHDL design guidelines.

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Dr-Eng Imad A. Shaheen
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17 views11 pages

Basic Language Constructs of VHDL

This document summarizes basic language constructs in VHDL, including identifiers, reserved words, numbers/strings, signals, variables, constants, aliases, data types, operators, and VHDL guidelines. Key concepts covered are valid identifier rules, the difference between signals and variables, constant/alias usage, and an overview of data types, operators, and VHDL design guidelines.

Uploaded by

Dr-Eng Imad A. Shaheen
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 3

Basic language constructs of VHDL


Contents

Identifiers,reserved words, numbers and strings.

Signals, variables and alias.

Data type and operators.

Relational operators, concatenation and aggregate.

Data Types.

Type conversion.

VHLD guidelines.
1

Identifiers
Basic rules:

Can only contain alphabetic letters, decimal digits


and underscore
The first character must be a letter

The last character cannot be an underscore

Two successive underscores are not allowed

Valid examples:
A10, next_state, NextState, mem_addr_enable
2

Reserved words

Loop,map, mod, and,not,


nor,xor ...etc

Numbers and strings


Number:

Integer: 0, 1234, 98E7

Real: 0.0, 1.23456 or 9.87E6

Base 2: 2#101101#
Character:

A, Z, 1
Strings

Hello, 101101
Note

0 and 0 are different

2#101101# and 101101 are different

Objects

Signals

Variables

Constants

Alias

Signal
Signal declaration:
signal signal_name, signal_name, ... : data_type
Signal assignment:
signal_name <= projected_waveform;
ex : signal p : std_logic_vector (3 downto 0 );

Ports in entity declaration are considered as signals


Can be interpreted as wires or wires with memory (i.e.,FFs,
latches etc.)

Variable

Declared and used inside a process


Variable declaration:
variable variable_name, ... : data_type
Variable assignment:
variable_name := value_expression;
ex : temp := '0';

Contains no timing info (immediate assignment)

No direct hardware counterpart

Constant

Value cannot be changed


Constant declaration:
constant const_name, ... :
data_type := value_expression
ex: constant Width :integer := 32;
8

Alias

Not a object

Alternative name for an object

Ex :
signal word:std_logic_vector (15 downto 0);
alias upper :std_logic_vector(7 downto 0) is word (15 downto 8);
alias lower :std_logic_vector(7 downto 0) is word (7 downto 0);

Data type and operators,Relational


operators,concatenation, aggregates
Type conversion

In book slides starting from


slide 32

10

VHDL Guidelines

Use the std-logic-vector and std-logic data types instead of the bit-vector.
Use the numeric-std package and the unsigned and signed data types for
synthesizing arithmetic operations.
Use only the descending range(i.e., downto) in the array specification of the
unsigned, signed and std-logic-vector data types.

Use parentheses to clarify the intended order of evaluation.

Dont use user-defined data types unless there is a compelling reason.

Dont use immediate assignment (i.e., :=) to assign an initial value to a signal.

Use operands with identical lengths for the relational operators.

11

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