Memory Organization

MEMORY ORGANIZATION

• Memory Hierarchy

• Main Memory

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Memory Organization Memory Hierarchy

MEMORY HIERARCHY
Memory Hierarchy is to obtain the highest possible
access speed while minimizing the total cost of the memory system
Auxiliary memory
Tape I/O Main
processor memory
Disk

CPU
Registers Cache

Register

Cache

Main Memory Cost

Speed

Disk

Tape

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Memory Organization Main Memory

MAIN MEMORY
RAM and ROM Chips

Chip select 1 CS1

Chip select 2 CS2
Read 128 x 8 8-bit data bus
RD RAM
Write WR
7-bit address AD 7

Typical RAM chip

CS1 CS2 RD WR Memory function State of data bus

0 0 x x Inhibit High-impedance
0 1 x x Inhibit High-impedance
1 0 0 0 Inhibit High-impedance
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High-impedance

Chip select 1 CS1

Chip select 2 CS2
512 x 8
8-bit data bus
ROM

9-bit address AD 9

Typical ROM chip

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Memory Organization Main Memory

MEMORY ADDRESS MAP

Memory Address Map: Address space assignment to each memory chip

Example: Build a 1024x8 memory system of 512 bytes of RAM and 512
bytes of ROM using 128x8 RAM chips and 512x8 ROM chips
1024 x 8
Decimal Hexa Address bus Address memory
Component Address Address 10 9 8 7 6 5 4 3 2 1 0
RAM 1 0 - 127 0000 - 007F 0 0 0 x x x x x x x : RAM 1
RAM 2 128 - 255 0080 - 00FF 0 0 1 x x x x x x x 127
0 1 0 x x x x x x x 128
RAM 3 256 - 383 0100 - 017F
0 1 1 x x x x x x x : RAM 2
RAM 4 384 - 511 0180 - 01FF 255
ROM 512 - 1023 0200 - 03FF 1 x x x x x x x x x
256
: RAM 3
383
384
Memory Connection to CPU : RAM 4
511
- RAM and ROM chips are connected to a CPU 512
: ROM
through the data and address buses 1023

- The low-order lines in the address bus select

the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs

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Memory Organization Main Memory

CONNECTION OF MEMORY TO CPU

Address bus
CPU
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2

Data
RD 128 x 8
RAM 1
WR
AD7 Address bus
Component
CS1 10 9 8 7 6 5 4 3 2 1
CS2 RAM 1 0 0 0

Data
128 x 8 x x x x x x x
RD
RAM 2 RAM 2 0 0 1 x x x x x x x
WR
AD7 RAM 3 0 1 0 x x x x x x x
RAM 4 0 1 1 x x x x x x x
CS1 ROM 1 x x x x x x x x x
CS2
Data
RD 128 x 8
RAM 3
WR
AD7

CS1
CS2
Data

RD 128 x 8
RAM 4
WR
AD7

CS1
CS2
Data

1- 7 512 x 8
8
9 } AD9 ROM

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Memory Organization

EXERCISES
Problem 12-4: Extend the memory system of Fig. 12-4 to 4096 bytes of RAM
and 4096 bytes of ROM. List the memory-address map and indicate what size
decoders are needed.
RAM and ROM chips: 128 x 8 RAM, 512 x 8 ROM
Memory system: 4096 bytes of RAM + 4096 bytes of ROM = 8192 bytes
Number of address lines: 13 (8192 = 213)
Number of needed RAM chips: 4096/128 = 32 ⇒ 5 x 32 decoder
Number of needed ROM chips: 4096/512 = 8 ⇒ 3x8 decoder
Address lines
Component Address range 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 – 007F 0 0 0 0 0 0 0 0 0 x x x x x x x
: : : : : : : : : : : : : : : : : :
RAM 32 0F80 – 0FFF 0 0 0 0 1 1 1 1 1 x x x x x x x
ROM 1 1000 – 11FF 0 0 0 1 0 0 0 x x x x x x x x x
: : : : : : : : : : : : : : : : : :
ROM 8 1E00 – 1FFF 0 0 0 1 1 1 1 x x x x x x x x x
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