Tle 8209

Data Sheet, Rev. 1.
4, October 2014
TLE8209-2
SPI Programmable H-Bridge
Automotive Power
TLE8209-2
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
2.2
2.3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
4.1
4.2
4.3
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.2
5.3
5.4
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDDIO - Digital Output Supply and Diagnostic Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Supply and VDD-Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
7.1
7.2
7.3
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel or SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H-Bridge or Single Switch Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diagnosis in Status Flag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Dependent Current Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit to Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit across the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
20
20
21
21
21
21
21
23
9
9.1
9.2
9.3
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
35
10
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Package Outlines TLE8209-2SA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12
Package Outlines TLE8209-2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Sheet
4
4
5
6
8
8
9
9
10
10
10
11
12
Rev. 1.4, 2014-10-28
SPI Programmable H-Bridge
TLE8209-2
Overview
Features
Programmable current limitation from 1.5 to 8.6 A typ.

Full path RDSon of 240 m (typ. at Tj=25C)
Operating battery supply voltage 4.5 V to 28 V
Operating logic supply voltage 4.4 to 5.25 V
Low standby current (8 A typ.)
Logic inputs TTL/CMOS-compatible
All I/O pins overvoltage tolerant up to 18 V
Enable and disable input
Short circuit and overtemperature protection
VS undervoltage shutdown
VDD over and undervoltage monitoring
Open load detection in off condition
Temperature dependent current reduction
Extensive diagnosis capabilities via SPI interface
Status Flag for basic diagnosis without SPI
Configurable as H-bridge or two independent half bridges
Control of power stages by parallel inputs or via SPI
Output switching frequency up to 11 kHz
Slewrate programmable through SPI
Excellent EMC performance
AEC qualified
Green product (RoHS compliant)
PG-DSO-20-65
PG-DSO-20-71
Functional Description
The TLE8209-2 is a SPI programmable H-bridge, designed for the control of DC motors in safety critical
automotive applications. It features four selectable current ranges, two selectable slew rate settings and extensive
diagnosis via SPI. The device monitors the digital supply voltage VDD and shuts down the output stages in case of
VDD over- or undervoltage, thus providing a safe switch off path in case of malfunction of the digital control circuitry.
In order to reduce power dissipation in extreme thermal conditions the current limitation threshold is reduced
linearly for junction temperatures over 165C. A thermal warning bit is set in the SPI.
The two half bridges can also be used independently to drive two separate loads like solenoids or unidirectional
DC motors.
Type
Package
Body Width
Marking
TLE8209-2SA
PG-DSO-20-65
430 mil
TLE8209-2SA
TLE8209-2E
PG-DSO-20-71
300 mil
TLE8209-2E
Data Sheet
Rev. 1.4, 2014-10-28
TLE8209-2
Pin Configuration
Pin Configuration
2.1
Pin Assignment
Figure 1
Figure 2
Data Sheet
GND
20
GND
SO
19
GNDABE
VDDIO
18
VDD
SS/SF
17
SCK
CP
16
SI
VS
15
VS
IN1
14
IN2
OUT1
13
OUT2
DIS
12
ABE
GND
10
11
GND
21
GND
Pinout TLE8209-2SA
GND
20
GND
SO
19
GNDABE
VDDIO
18
VDD
SS/SF
17
SCK
CP
16
SI
VS
15
VS
IN1
14
IN2
OUT1
13
OUT2
DIS
12
ABE
GND
10
11
GND
21
GND
Pinout TLE8209-2E
Rev. 1.4, 2014-10-28
TLE8209-2
Pin Configuration
2.2
Pin Definitions and Functions
Pin
Symbol
Function in SPI Mode
Function in Status Flag Mode
GND
Ground
Ground
SO
SPI Serial Data Out
no function - connect to GND
VDDIO
Supply Voltage for Logic Output Buffer
Switches to SF-mode if connected to GND
SS/SF
Slave Select (low active)
Status Flag (low active)
CP
Pin for external Charge Pump Capacitor
Pin for external Charge Pump Capacitor
VS
Battery Supply Voltage, has to be connected to Battery Supply Voltage, has to be

pin 15
connected to pin 15
IN1
Input 1
Input 1
OUT1
Output 1
Output 1
DIS
Disable
Disable
10
GND
Ground
Ground
11
GND
Ground
Ground
12
ABE
Bidirectional Enable Pin
Bidirectional Enable Pin
13
OUT2
Output 2
Output 2
14
IN2
Input 2
Input 2
15
VS
Input battery supply voltage, has to be

connected to pin 6
Input battery supply voltage, has to be

connected to pin 6
16
SI
SPI Serial Data Input
17
SCK
SPI Clock
18
VDD
VDD supply
VDD supply
19
GNDABE
Sense ground for VDD monitoring
Sense ground for VDD monitoring
20
GND
Ground
Ground
21
GND
Heatslug - connect to GND
Heatslug - connect to GND
Data Sheet
Rev. 1.4, 2014-10-28
TLE8209-2
Pin Configuration
2.3
Terms
I CP
IS
I DD
I GNDABE
VDD
VGNDABE
IIN 1
IIN 2
VIN1
I DIS
VIN2
VDIS
I ABE
CP
VDD
VCP
VS
VS
GNDABE
IN1
IN2
DIS
OUT1
I OUT1
ABE
VABE
VOUT1
OUT2
I SO
ISI
VSO
VSI
I SCK
ISS / SF
IDDIO
VSCK
VSS /SF
VDDIO
IOUT2
VOUT2
SO
SI
SCK
SS/SF
VDDIO
GND
Figure 3
Data Sheet
Terms TLE8209-2
Rev. 1.4, 2014-10-28
TLE8209-2
Block Diagram
Block Diagram
CP
VS
VDD
GNDABE
VDDMonitoring
IN1
IN2
Logic
internal
Supply
VS
Undervoltage
DIS
Gate Control
ABE
OUT1
OUT2
SO
SI
SCK
SS/SF
SPI/Flag
Diagnostics
VDDIO
GND
Figure 4
Data Sheet
Block Diagram TLE8209-2
Rev. 1.4, 2014-10-28
TLE8209-2
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 C to 150 C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Min.
Max.
4.1.1
Junction temperature
Tj
-40
150
4.1.2
Storage temperature
4.1.3
Ambient temperature
4.1.4
Battery supply voltage
Ts
Ta
VS
4.1.5
Logic supply voltage
4.1.6
Supply for logic out
4.1.7
Voltage at logic pins

ABE, IN1, IN2, DIS, SCK,
SS/SF, SI
4.1.8
Voltage at SO
Limit Values
Unit
Test Conditions / Comment
150
175
100h cumulative
-55
150
-40
125
-0.5
40
Static destruction proof
-2
40
Dynamic destruction proof

t < 0.5 s (single pulse,
Tjstart < 85 C)
VDD
VDDIO
VIN
-0.5
18
-0.5
18
-0.5
18
VSO
-0.5
VDDIO
+0.3
4.1.9
Voltage at CP
4.1.10
Voltage at GNDABE
VCP
VS-0.3
VS+5.0
V
VGNDABE VGND-0.3 VGND+0.3 V
0V < VS < 40V
VESD
ESD Susceptibility
-2
kV
HBM2)
4.1.12
-8
kV
HBM2), Pins OUT1 and OUT2
4.1.13
-500
500
CDM3)
4.1.14
-750
750
CDM3), Pins 1, 10, 11, 20
4.1.11
ESD Resistivity to GND
1) Not subject to production test, specified by design.

2) ESD susceptibility HBM according to EIA/JESD22-A114-B (1.5k, 100pF)
3) ESD susceptibility, Charged Device Model CDM EIA/JESD22-C101
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as outside normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
Rev. 1.4, 2014-10-28
TLE8209-2
4.2
Pos.
Operating Range
Parameter
Symbol
4.2.3
VS supply voltage range

VDD supply voltage
VDDIO supply voltage
4.2.4
PWM frequency
4.2.5
Junction temperature
4.2.1
4.2.2
VS
VDD
VDDIO
f
TJ
Limit Values
Unit
Remark
Min.
Max.
4.5
28
4.4
5.25
5.5
11
kHz
-40
150
Note: Within the operating range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos.
Thermal Resistance
Parameter
Symbol
Limit Values
Unit
Remark
1.6
K/W
17
K/W
2)
4.6
K/W
30
K/W
2)
Min.
Typ.
Max.
RthJC
RthJA
RthJC
RthJA
TLE8209-2SA (PG-DSO-20-65)
4.3.6
4.3.7
Junction to Case1)
1)
Junction to Ambient
TLE8209-2E (PG-DSO-20-71)
4.3.8
4.3.9
Junction to Case1)
1)
Junction to Ambient
1) Not subject to production test, specified by design.

2) Simulation according to Jedec JESD51-2,-5,-7; natural convection; FR4 2s2p board 76.2 x 114.3 x 1.5 mm (2 x 70m Cu,
2 x 35m Cu)
Data Sheet
Rev. 1.4, 2014-10-28
TLE8209-2
Power Supply
Power Supply
5.1
Basic Supply Characteristics
The TLE8209-2 has three different supply pins: VDD, VS and VDDIO. VDD is used to supply the internal logic
circuitry. VS connects to battery voltage and supplies the output stages. The voltage at pin VDDIO defines the high
level output voltage at the pin SO of the SPI interface. VDDIO is also used as a mode select pin. If VDDIO is
connected to ground, the device is set to status flag mode (SPI inactive).
On power up the device will enter a functional state when VDD rises above the functional reset threshold VDD_RES.
In this state all output stages are inactive and internal registers are cleared. When VDD rises further above the
power on reset threshold VDD_POR the device starts operation with a delay time of tPOR.
5.2
VDD Monitoring
The logic supply voltage level at the pin VDD is monitored. If the voltage at pin VDD is out of the permissible range
of VDD_L VDD_H the power stages of TLE8209-2 are switched off and pin ABE is pulled to ground. To suppress
glitches in the VDD monitoring, a glitch filter is implemented.VDD is measured with reference to pin GNDABE. The
state of VDD monitoring is stored in STATCON_REG and can be read out via SPI.
The output stages can also be turned off by pulling the ABE pin to ground externally.
In case of VDD failure, the output stages are switched off, even if the pin ABE should be connected to a high level
signal because of external short circuit to VDD or battery voltage (up to 18V). OUT1 and OUT2 cannot be switched
on in over- or undervoltage condition, switching off is always possible. A power on reset (VDD < VDD_POR) switches
off all stages without delay.
Control of VDD-monitoring is possible in SPI mode only. Detailed information (differentiation of over and undervoltage detection) is only possible by SPI interface.
Behavior of VDD monitoring in SF mode:
- monitoring is present with the specified values for over- and undervoltage
- any test of over- and undervoltage threshold is not possible
- the latch for overvoltage is disabled
VDD Undervoltage
If the VDD voltage is lower than the supply voltage supervisory lower threshold (VDD_THL), output stages are shut
off after a filtering time (tFIL_OFF) and the bi-directional pin ABE is pulled low. At the transition from undervoltage to
normal voltage the signal at pin ABE goes high and the output stages will return to normal operation after a filtering
time (tFIL_ON) has expired. For output control via SPI the bits MUX and SINx in the config register have to be reprogrammed. New failures are not stored to diagnostic registers during undervoltage, register content remains
valid, writing new information to configuration registers is possible as far as they are not reset by ABE. If VDD falls
below the power-on-reset supply voltage (VDD_POR) all stages are shut off and ABE is switched active low. When
VDD is rising above the power-on-reset supply voltage threshold (VDD_POR) a power-on-reset is generated (tPOR),
setting all registers to its default state.
VDD Overvoltage
If the VDD voltage is higher than the supply voltage supervisory upper threshold (VDD_THH), all output stages are
shut off after a filtering time (tFIL_OFF) and the bi-directional pin ABE is pulled low. The behavior of the ABE level
and output stages on the return of VDD from overvoltage to the correct range is configured in STATCON_REG,
bit CONFIG0)
CONFIG0=1: ABE is latched and outputs remain off after overvoltage. Return to normal operation is only possible
with power-on reset or by changing this bit via SPI.
Data Sheet
10
Rev. 1.4, 2014-10-28
TLE8209-2
Power Supply
CONFIG0=0: ABE is inactive after VDD returned to normal operating voltage and filtering time has expired.
At the transition from overvoltage to normal condition, the output stages will return to normal operation. For output
control via SPI the bits MUX and SINx in the config register have to be re-programmed. New failures are not stored
to diagnostic registers during overvoltage, register content remains valid, writing new information to configure
registers is possible as far as they are not reset by ABE.
VDD Monitoring Test Mode
Testing of VDD monitoring is possible in SPI mode only. The latch function for over voltage at VDD has to be
switched of (CONFIG0=0 in STATCON_REG)
Testing upper threshold:
By writing 00xxxxxxb into STATCON_REG, the overvoltage threshold is reduced to VDD_TEST_H.
STATCON_REG bit 2 and 0 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 0 in
STATCON_REG must be HIGH again
Testing lower threshold:
By writing 01xxxxxxb into STATCON_REG, the undervoltage threshold is increased to VDD_TEST_L.
STATCON_REG bit 2 and 1 have to be LOW then. After writing 1xxxxxxxb to STATCON_REG, bit 2 and 1 in
STATCON_REG must be HIGH again.
5.3
VDDIO - Digital Output Supply and Diagnostic Mode Selection
The voltage at VDDIO is used to supply the output buffer at the SO pin (serial output of SPI-interface). The VDDIO
pin is also used to select SPI- or in status flag (SF) diagnostic mode. As soon as VDDIO is lower than VDDIO_L, the
device is put into status flag mode.
.
VDDIO
to internal logic
(SF-mode / SPI-mode)
+
-
SF/SPI - mode
threshold VDDIO_L
SO
from internal logic
Figure 5
Data Sheet
VDDIO and SO-Pin
11
Rev. 1.4, 2014-10-28
TLE8209-2
Power Supply
5.4
Electrical Characteristics Power Supply and VDD-Monitoring
Electrical Characteristics: Power Supply and VDD-Monitoring
VS = 5 V to 28 V; VDD = 5.0 V, Tj = -40 C to 150 C, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
IOUT = 0 A, VDD = 0V,

VS < 18 V, Tj < 125C
bridge disabled,
IOUT = 0 A,
5 V < VS < 18 V
f = 2 kHz, IOUT = 0 A,
5 V < VS < 18 V
f = 10 kHz, IOUT = 0 A,
5 V < VS < 18 V
f = 10 kHz, IOUT = 0 A,
5 V < VS < 28 V
Min.
Typ.
Max.
20
2.1
mA
2.5
mA
mA
4.8
13
mA
Supply
5.4.1
Supply Current
IVS
5.4.2
Functional Reset Threshold VDD_RES
1.4
2.5
5.4.3
Power On Reset Threshold VDD_POR
3.5
3.75
4.0
5.4.4
Power On Reset Delay

Time
tPOR
0.22
0.5
ms
VDD = on --> output
5.4.5
VDD Input current
mA
4.5V < VDD < 5.5V
5.4.6
VDDIO Input current
IDD
IDDIO
30
100
SPI-mode
no load at SO
no SPI communication
5.4.7
SF-mode Threshold
1.0
5.4.8
SPI-mode Threshold
2.0
5.4.9
Mode selection hysteresis
VDDIO_L
VDDIO_H
VDDIO_HYS
0.2
0.5
1.0
VDD_THH
VDD_THL
VDD_TEST_H
5.25
5.4
5.5
4.2
4.3
4.4
Voltage referred to
GNDABE
4.2
4.3
4.4
stage active, no load
VDD-Monitoring
5.4.10
Overvoltage threshold
5.4.11
Undervoltage threshold
5.4.12
Test mode reduced

Overvoltage threshold
5.4.13
Test mode increased

Undervoltage threshold
VDD_TEST_L
5.25
5.4
5.5
5.4.14
Filter time for glitch

suppression
tFIL
60
100
135
5.4.15
Maximum Slew Rate on

VDD1)
VDD_slew
0.5
V/s
1) Not subject to production test; specified by design
Data Sheet
12
Rev. 1.4, 2014-10-28
TLE8209-2
Logic Inputs and Outputs
The threshold specifications for the logic inputs are compatible to both 5 and 3.3 V standard CMOS microcontroller ports. All inputs (except ABE) feature internal pull-up current sources. The logic output SO is supplied
by VDDIO. VDDIO can be supplied with either 5 or 3.3 V, so the output thresholds of SO can be configured to the
required I/O voltage.
Electrical Characteristics: Control Inputs
VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 C to 150 C, all voltages with respect to ground, positive current flowing
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Typ.
Max.
-0.3
1.0
2.0
VDD+0.3
0.2
1.0
-30
-20
-10
0 V < VINx < 2.1 V
VINx > 3.0 V
IN1, IN2
6.0.1
Low level
6.0.2
High level
6.0.3
Hysteresis
6.0.4
Input Current (Pull Up)
VINx_L
VINx_H
VINx_HYS
IINx
6.0.5
Input Capacity1)
CINx
20
pF
2)
6.0.7
Low level
-0.3
1.0
6.0.8
High level
VDIS_L
VDIS_H
VDIS_HYS
IDIS
2.0
VDD+0.3
0.2
1.0
-200
-125
-50
0 V < VDIS< 2.1 V
VDIS > 3.0 V
CDIS
20
pF
2)
tDIS
0.4
0.8
1.5
VDD_THH < VDD < 18 V

IABE < 5 mA
2.5 V < VDD < VDD_THL
IABE < 1 mA
6.0.6
DIS
6.0.9
Hysteresis
6.0.10
6.0.11
6.0.12
6.0.13
Input Capacity1)
Minimum Pulse Width
1)
ABE
6.0.14
Output low-level voltage VABE_OUTL
1.2
6.0.15
1.0
0.7*VDD
0.3*VDD
0.2
1.0
0.4
0.8
1.5
6.0.20
VABE_INH
Input threshold low
VABE_INL
Hysteresis
VABE_INHY
1)
Minimum pulse width
tABE
ABE Input current (Pull -IABE_L
20
40
120
1.5 V < VABE < 18 V
6.0.21
Down)
60
0 V < VABE < 1.5 V
-0.3
1.0
2.0
VDD+0.3
0.2
1.0
-30
-20
-10
0 V < VSI < 2.1 V
pF
2)
6.0.16
6.0.17
6.0.18
6.0.19
Input threshold high
SI
6.0.22
Low level
6.0.23
High level
6.0.24
Hysteresis
6.0.25
6.0.26
Input Capacity
Data Sheet
1)
VSI_L
VSI_H
VSI_HYS
ISI
CSI
14
13
Rev. 1.4, 2014-10-28
TLE8209-2
Electrical Characteristics: Control Inputs (contd)
VS = 5 V to 28 V; VDD = 5.0 V; Tj = -40 C to 150 C, all voltages with respect to ground, positive current flowing
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Typ.
Max.
-0.3
1.0
2.0
VDD+0.3
0.2
1.0
-30
-20
-10
0 V < VSCK < 2.1 V
SCK
6.0.27
Low level
6.0.28
High level
6.0.29
Hysteresis
6.0.30
6.0.31
Input Capacity
1)
VSCK_L
VSCK_H
VSCK_HYS
ISCK
CSCK
14
pF
2)
VSS_L
VSS_H
VSS_HYS
ISS
-0.3
1.0
2.0
VDD+0.3
0.2
1.0
-30
-20
-10
0 V < VSS < 2.1 V
-30
300
2.1 V < VSS < 3.0 V

VSS > 3.0 V
VSF = 5.0 V, SF inactive
VSF = 1.0 V, SF active
CSS
15
pF
2)
VSO_L
VSO_H
0.0
0.4
VDDIO-0.75
VDDIO
ISO = 2 mA
ISO = -2 mA
2.9 V < VDDIO < 5.5 V
CSO
ISO
19
pF
In tristate2)
-2
In tristate
0 < VSO < VDDIO
SS/SF
6.0.32
Low level
6.0.33
High level
6.0.34
Hysteresis
6.0.35
Input Current in SPI

mode (Pull Up)
6.0.36
6.0.37
6.0.38
6.0.39
6.0.40
Input Current in SF
mode (Open Drain)
Input Capacity
1)
ISF
SO
6.0.41
Low level
6.0.42
High level
6.0.43
Output capacitance1)
6.0.44
Leakage current
1) Not subject to production test; specified by design
2) Vbias = 2 V; Vtest = 20 mVpp; f = 1 MHz
Data Sheet
14
Rev. 1.4, 2014-10-28
TLE8209-2
Power Stages
Power Stages
The TLE8209-2 contains four n-channel power-DMOS transistors that can be used in an H-bridge or in dual half
bridge configuration.
Integrated circuits protect the outputs against overcurrent and over-temperature, in case of short-circuit to ground,
to the supply voltage or across the load. Positive and negative voltage spikes, which occur when switching
inductive loads, are limited by integrated freewheeling diodes (body diodes of power-DMOS).
7.1
Parallel or SPI Control
By default the setting of the power switches is controlled by the Inputs IN1, IN2 (parallel control). The outputs
OUT1 and OUT2 are set to High (high-side switch ON, low-side switch OFF) or Low (high-side switch OFF, lowside switch ON) by the parallel inputs IN1 and IN2, respectively. In SPI mode there is also the option to control the
outputs via the SPI bits SIN1 and SIN2 of the SPI configuration register. To switch to SPI control the bit MUX has
to be set to 0.
In addition, the outputs can be disabled (set to tristate, high- and low-side switch OFF) by the disable input DIS
and the bidirectional reset pin ABE. Disabling sets the device to parallel control
Table 1 shows the different options for the output control.
7.2
H-Bridge or Single Switch Usage
The IC can be set to H-bridge mode or single-switch mode by SPI. This setting changes the behavior of the device
in the following features:
current limiting
overcurrent shut-down
open load diagnosis
Table 1
Functional Truth Table
Pos.
DIS
ABE
IN1
IN2
SPI
MUX
SPI
SIN1
SPI
SIN2
OUT1
OUT2
Forward, parallel ctrl.
Reverse, parallel ctrl.
Free-wheeling low, parallel ctrl. L
Free-wheeling high, parallel ctrl. L
Forward, SPI ctrl.
Reverse, SPI ctrl.
Free-wheeling low, SPI ctrl.
Free-wheeling high, SPI ctrl.
Disabled by DIS
Disabled by ABE
Table 2
OUT States
OUT
High-Side DMOS
Low-Side DMOS
ON
OFF
OFF
ON
OFF
OFF
Data Sheet
15
Rev. 1.4, 2014-10-28
TLE8209-2
Power Stages
7.3
Electrical Characteristics Power Stages
Electrical Characteristics: Power Stage
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
IOUTx = 3 A; Tj = 25C
Min.
Typ.
Max.
ROUT1L
ROUT2L
125
215
250
ROUT1H
ROUT2H
115
200
240
IOUT1(off)
IOUT2(off)
UD
-200
200
Output stage switched off

VS = 13 V
0.9
1.1
ID = 3 A
trr
100
ns
3.5
6.0
10
3.5
6.0
10
SPI bit SL=0

VS = 8..18 V; IOUT = 3 A
3.5
6.0
8.5
3.5
6.0
8.5
15
30
48
15
30
48
SPI bit SL=1

VS = 8..18 V; IOUT = 3 A
18
30
48
18
30
48
12
VS = 8..18 V; IOUT = 3 A
13
VS = 8..18 V; IOUT = 3 A
12
41
VS = 8..18 V; IOUT = 3 A
25
42
VS = 8..18 V; IOUT = 3 A
26
Power Outputs OUT1, OUT2

7.3.1
Switch on resistance low
7.3.2
side
Switch on resistance high
side
7.3.3
Leakage current
7.3.4
Free-wheel diode forward

voltage
7.3.5
Free-wheel diode reverse

recovery time1)
Output Switching Times - Fast Slew Rate

7.3.6
Rise time HS
7.3.7
Fall time HS
7.3.8
Rise time LS
7.3.9
Fall time LS
tr (HS)
tf (HS)
tr (LS)
tf (LS)
Output Switching Times - Slow Slew Rate

7.3.10
Rise time HS
7.3.11
Fall time HS
7.3.12
Rise time LS
7.3.13
Fall time LS
tr (HS)
tf (HS)
tr (LS)
tf (LS)
Output Delay - Parallel Control, Fast Slew Rate

7.3.14
Output on-delay
7.3.15
Output off-delay
tdon
tdoff
Output Delay - SPI Control, Fast Slew Rate

7.3.16
Output on-delay
7.3.17
Output off-delay
tdon
tdoff
Output Delay - Parallel Control, Slow Slew Rate

7.3.18
Output on-delay
7.3.19
Output off-delay
tdon
tdoff
Output Delay - SPI Control, Slow Slew Rate

7.3.20
Output on-delay
7.3.21
Output off-delay
Data Sheet
tdon
tdoff
16
Rev. 1.4, 2014-10-28
TLE8209-2
Power Stages
Electrical Characteristics: Power Stage
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Test Conditions
VS = 8..18 V; IOUT = 3 A
ms
VS = on --> output stage
Enable and Disable Delay Times

7.3.22
Disable delay time, fast

slew rate
tddis
20
7.3.23
Disable delay time, slow

slew rate
tddis
38
75
7.3.24
Enable delay time, fast

slew rate
tdel
20
7.3.25
Enable delay time, slow

slew rate
tdel
38
75
7.3.26
Power on delay time
tdel
0.1
0.4
active, no load
1) Not subject to production test - specified by design
tRISE
tFALL
90%
90%
OUTx
10%
Figure 6
10%
Output Switching Time
V
5
INx
30%
30%
90%
OUTx
10%
tdon
Figure 7
Data Sheet
tdoff
Output Delay Time Low-Side FETs

17
Rev. 1.4, 2014-10-28
TLE8209-2
Power Stages
V
5
ABE
50%
50%
3A
90%
IOUT
10%
0
Figure 8
tddis
tden
/ABE pin - Enable and Disable Delay Time
V
5
DIS
30%
30%
3A
90%
IOUT
10%
0
Figure 9
Data Sheet
tddis
tden
DIS pin - Enable and Disable Delay Time
18
Rev. 1.4, 2014-10-28
TLE8209-2
Protection and Monitoring
Both output stages of the TLE8209-2 are equipped with fault diagnostic functions:
Short to battery voltage (SCB). Can be detected when low side-switches are turned on
Short to ground (SCG). Can be detected when high side-switches are turned on
Open load (OL). Can be detected in inactive mode
Over-temperature (OT). Can be detected in active and inactive mode
VDD over- and under voltage (Chapter 5.2)
Battery under voltage detection. Can be detected in active and inactive mode
Individual detection for each output in single switch operation mode (SCB, SCG, OL) is possible. The
corresponding diagnostics bits for each failure will be set in the SPI according to Table 8 Failure Encoding on
Page 31.
8.1
Diagnosis in Status Flag Mode
Instead of using the SPI interface for control and diagnosis of the TLE8209-2, the device can also be set into status
flag mode by connecting pin VDDIO to GND as described in Chapter 5.3.
In status flag mode the pin SF will be pulled low in the following cases:
undervoltage at VS
bridge disabled by ABE or DIS
bridge disabled by VDD monitoring
bridge disabled by short circuit detection
overtemperature shut down
SF will not be pulled low if VDD is below the power on reset threshold (VDD_POR).
8.2
Current Limitation
To limit the output current at low power loss, a chopper current limitation is integrated. Current measurement for
current limitation is done in the high side path. This requires high side freewheeling in case of active current
limitation.
ttrans
tb
IL
HS1
HS2
LS1
LS2
IOUT
Ihys
time
Figure 10
Chopper Current Limitation
Figure 10 shows the behavior of the current limitation for over current detection in HS1. It applies accordingly also
for HS2:
When the current in high-side switch of OUT1 (HS1) exceeds the limit IL longer than the blanking time tb, OUT2 is
switched to high (e.g. LS2->OFF, HS2->ON), independent of the input signal at IN2. This leads to a slow-decay
current decrease in the load and in HS1. As soon as the current falls below IL-Ihys, OUT2 is switched back to normal
Data Sheet
19
Rev. 1.4, 2014-10-28
TLE8209-2
operation, i.e. the outputs follow the inputs according to the truth table. The current limit IL can be programmed to
four different values by setting the SPI bits CL1 and CL2 in the SPI configuration register. To avoid high chopper
frequencies the time between two transients ttrans is limited.
Current limitation is available in H-bridge operation mode, not in single switch operation mode. This means, that
the current limit, current limit hysteresis and blanking time has no effect in single switch operation mode.
Note: Usage of current limitation level IL4 (8,6A typ.) is limited to the TLE8209-2SA in the 430 mil package.
8.3
Temperature Dependent Current Reduction
For TILR < Tj < TSD the current limit decreases from IL as set by the SPI to IL_TSD = 2.5 A typ. as shown in
Figure 11.
A
IL
range of overtemperature shut-down
tolerance of temperature
dependent current
reduction
IL_TSD
(typ. 2.5A)
TSD
TILR
(typ. 165C) (min. 175C)
Temperature Dependent Current Reduction
8.4
Short Circuit to Ground
current
Figure 11
IOUK
IL
short circuit detected

current limitation active
Tj [C]
output off
current tracking
I hys
tb
t< tb
tDF_H
tDF_OFF
I OUT
time
Short
IN1
OUT1
tristate
IN2
OUT2
Figure 12
Data Sheet
tristate
Short to Ground Detection

20
Rev. 1.4, 2014-10-28
TLE8209-2
The short circuit to ground detection is activated when the current through one of the high side switches rises over
the threshold IOUK and remains higher than IOUK for at least the filter time tDF_H within the blanking time tb.
The output stage in which the short circuit was detected will be switched off within tDF_OFF.
In H-bridge mode also the other output will be switched off after a short delay of tDF_del .
In single switch mode only the affected output will be switched off.
8.5
Short Circuit to Battery
A short circuit to battery is detected in the same way as a short circuit to ground, only in the low side switch instead
of the high side switch.
8.6
Short Circuit across the Load
Short circuit over load is indicated by two failures - short circuit to ground on one output and short circuit to battery
on the other output. Both failure bits will be set in the SPI diagnostics register. Both output stages will be turned off.
8.7
Overtemperature
In case of high DC-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above
the thermal shut-down temperature TSD (see Figure 11). In that case, all output transistors are turned off.
8.8
Undervoltage Shut-Down
If the supply voltage at the VS pins falls below the undervoltage detection threshold VUV_OFF, the outputs switches
are turned off. As soon as VS rises above VUV_ON again, the device is returning to normal operation.
8.9
Open Load Diagnosis
Open load diagnosis is only possible if outputs are switched off by DIS or ABE. The diagnostic current sources are
deactivated in status flag mode. Diagnostic current sources are disconnected if outputs are active. That means
that the diagnostic current sources are also disconnected if the outputs are deactivated due to short circuit. The
open load detection in H-bridge mode is different from the open load detection in single switch mode.
Open Load Detection in H-Bridge mode
VDD
OUT1
Vref_L
Figure 13
Data Sheet
+
-
OUT2
Vref_L
OUT1_L
+
-
OUT2_L
Open Load Detection in H-Bridge Mode
21
Rev. 1.4, 2014-10-28
TLE8209-2
Table 3
Open Load Detection in H-Bridge Mode
VOUT1 OUT1_L
VOUT2
OUT2_L
Diagnostic
Comment
< Vref_L
< Vref_L
Load o.k.
pull down current is stronger
< Vref_L
> Vref_L
Load o.k.
transient area
> Vref_L
< Vref_L
Open Load
> Vref_L
> Vref_L
Load o.k.
transient area
Open Load Detection in Single Switch Mode
VDD
Vref_M
VDD
Vref_H
OUTx
Vref_M
V ref_H
+
V ref_L
Vref_L
Figure 14
Table 4
OUTx_H
+
-
OUTx_L
+
-
VOUTx (OFF State)
OUTx_H
OUTx_L
Diagnostic
Comment
VOUTx < Vref_L
o.k.
Load to ground
Vref_L <VOUTx < Vref_H
Open Load
Output open
VOUTx > Vref_H
o.k.
Load to VS
Data Sheet
22
Rev. 1.4, 2014-10-28
TLE8209-2
8.10
Electrical Characteristics
Electrical Characteristics: Protection and Monitoring
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit Test Conditions
Chopper Current Limitation

-40 C < Tj < TILR
Dependent on SPI
setting; Default = IL3
|IL1|
1.0
1.5
2.0
8.10.2
Current Limit, Level 1

|IL2|
3.3
4.0
4.7
8.10.3
|IL3|
5.5
6.6
7.7
8.10.4

TLE8209-2SA 1)
|IL4|
7.7
8.6
10.0

TLE8209-2E 1)
|IL4|
n.a.
8.10.5
Current Limit Hysteresis
0.25
0.40
-40 C < Tj < TILR
8.10.6
Blanking time
11
15
8.10.7
Time between transients
Ihys
tb
ttrans
90
130
8.10.1
Temperature Dependent Current Limitation
2)
8.10.8
Current Limit at TSD
IL_TSD
1.4
2.5
3.6
8.10.9
Start of current limit

reduction
TILR
150
165
8.10.10
Thermal shut-down
175
8.10.11
Range of temperature
dependent current
reduction
TSD
TSD - TILR
20
25
30
-40 C < Tj < TILR

Dependent on SPIsetting for |IL|; Default =
Short Circuit Detection to GND

8.10.12
Short circuit detection

current (HS), Level 1
|IOUKH1|
2.5
5.0
6.5
8.10.13

|IOUKH2|
5.0
7.3
10
8.10.14

|IOUKH3|
7.5
9.5
11.5
8.10.15

TLE8209-2SA 1)
|IOUKH4|
9.5
11.8
17.4

TLE8209-2E 1)
|IOUKH4|
n.a.
Data Sheet
23
IOUKH3
Rev. 1.4, 2014-10-28
TLE8209-2
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Current Tracking (HS)

8.10.16
Current tracking (HS),

Level 1
|IOUKH1| - |IL1|
2.0
3.5
5.0
8.10.17

Level 2
|IOUKH2| - |IL2|
2.0
3.3
5.0
8.10.18

Level 3
|IOUKH3| - |IL3|
2.0
3.2
5.0
8.10.19

Level 4, TLE8209-2SA 1)
|IOUKH4| - |IL4|
1.8
3.0
5.0

Level 4, TLE8209-2E 1)
|IOUKH4| - |IL4|
n.a.
|IOUKL1|
2.5
4.6
6.5
|IOUKL2|
5.0
7.9
10
|IOUKL3|
7.5
9.8
11.5
|IOUKL4|
9.5
14
17.4
|IOUKL4|
n.a.
-40 C < Tj < TILR

IOUKH3
Short Circuit Detection to VS

8.10.20
8.10.21
8.10.22
8.10.23

current (LS), Level 1
current (LS), Level 4,
TLE8209-2SA 1)
current (LS), Level 4,
TLE8209-2E 1)
-40 C < Tj < TILR

IOUKL3
Current Tracking (LS)

8.10.24
Current tracking (LS),

Level 1
|IOUKL1| - |IL1|
1.5
3.0
5.0
8.10.25

Level 2
|IOUKL2| - |IL2|
2.0
4.0
5.5
8.10.26

Level 3
|IOUKL3| - |IL3|
1.8
3.5
5.5
8.10.27

Level 4, TLE8209-2SA 1)
|IOUKL4| - |IL4|
2.0
5.1
8.0

Level 4, TLE8209-2E 1)
|IOUKL4| - |IL4|
n.a.
Data Sheet
24
-40 C < Tj < TILR

IOUKL3
Rev. 1.4, 2014-10-28
TLE8209-2
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
tDF_del
17
40
Short Circuit Detection Timing
tDF_H, tDF_L
8.10.28
Delay time for fault

detection
8.10.29
Time from detected fault to tDF_OFF

high impedance of output2)
8.10.30
Delay time between

switching off of the output
stages in short circuit
Open Load
8.10.31
Open Load Diagnostic

Filter Time2)
tOL_DIAG
60
135
8.10.32
Low Diagnosis Threshold
Vref_L
0.4 *
VDD 0.2
0.4 *
VDD
0.4 * VDD V
+ 0.2
8.10.33
High Diagnosis Threshold
Vref_H
0.8 *
VDD 0.2
0.8 *
VDD
0.8 * VDD V
+ 0.2
8.10.34
Diagnosis Bias Voltage
Vref_M
0.6 *
VDD 0.2
0.6 *
VDD
0.6 * VDD V
+ 0.2
8.10.35
Positive Diagnostic Current IDIA_P

(pull down current source)
300
620
980
VOUTx = 14 V
270
610
980
VOUTx = Vref_H
Negative Diagnostic
Current
IDIA_N
-350
-240
-100
VOUTx = 0 V
-350
-210
-80
VOUTx = Vref_L
Ratio of current sources

(Pos/Neg)
RatioI_DIA
2.9
3.1
3.7
4.4
Switch off threshold
3.3
3.9
4.6
Switch on threshold
100
200
400
mV
Hysteresis
1.5
8.10.36
8.10.37
8.10.38
8.10.39
Undervoltage
VUV OFF
VUV ON
VUV HY
8.10.41 VS Undervoltage Detection tUV
8.10.40
Undervoltage at VS
Filter Time2)
1) The current limitation level 4 is applicable in the 430 mil power package only (TLE8209-2SA in PG-DSO-20-65).
Level 4 must not be used in the 300 mil exposed pad package (TLE8209-2E in PG-DSO-20-71).
2) Not subject to production test; specified by design.
Data Sheet
25
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
SPI Interface
The serial SPI interface establishes a communication link between TLE8209-2 and the systems microcontroller.
The TLE8209-2 always operates in slave mode whereas the controller provides the master function. The
maximum baud rate is 2 MBaud.
By applying an active slave select signal at SS the TLE8209-2 is selected by the SPI-master. SI is the data input
(Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI-clock is provided by the master.
In case of inactive slave select signal (High) the data output SO goes into tristate.
The first two bits of an instruction may be used to establish an extended device-addressing. This gives the
opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit (see Figure 17).
SS
SPI-Control:
SCK
SI
SO
-> state machine

-> clock counter
-> instruction recognition
shift-register
DIA_REG
Reset
Diagnostics
DIS
OR
ABE
Figure 15
SPI Block Diagram
9.1
General SPI Characteristics
1. During active reset conditions the SPI is driven into its default state. The output SO is set to high impedance
(tristate). When reset becomes inactive, the state machine enters into a wait state for the next instruction.
2. If the slave select signal at SS is inactive (high), the state machine is forced to wait for the following instruction.
3. During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to
latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the
data according to the instruction (i.e. modification of internal registers) will be triggered by the rising edge of
the SS signal.
4. In order to establish the option of extended addressing the upper two bits of the instruction byte (i.e. the first
two SI bits of a frame) are reserved to send a chip address. To avoid a bus conflict the output SO will remain
tristate during the addressing phase of a frame (i.e. until the address bits are recognized as a valid chip
Data Sheet
26
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
address). If the chip address does not match, the according frame will be ignored and SO remains tristate for
the complete frame.
5. Verification byte: Simultaneously to the receipt of an SPI instruction the TLE8209-2 transmits a verification byte
via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an
initial bit pattern and a flag indicating an invalid instruction of the previous access.
6. On a read access the data bits at the SPI input SI are rejected. During a valid write access the SPI will transmit
the data byte "00hex" at the output SO after having sent the verification byte.
7. An instruction is invalid if one of the following conditions is fulfilled:
- an unused instruction code is detected (see tables with SPI instructions).
- the previous transmission is not completed in terms of internal data processing.
- the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses.
If an unused instruction code occurres, the data byte FFhex (no error) will be transmitted after having sent the
verification byte. This transmission takes place within the same SPI-frame that contained the unused
instruction byte.
If an invalid instruction is detected, bit TRANS_F in the following verification byte (next SPI-transmission) is set
to HIGH. The TRANS_F bit must not be cleared before it has been sent to the microcontroller.
9.2
SPI Communication
The 16 input bits consist of the SPI instruction byte and an input data byte. The 16 output bits consist of the
verification byte and the output data byte (see also Figure 16). The definition of these bytes is given in the
subsequent sections. The access mode of the registers is described in the column Type (r = read, w = write).
SS
SCK
SI
SO
MSB
MSB
SPI Instruction
Verification byte
Figure 16
SPI Communication
9.2.1
Instruction Byte
LSB
LSB MSB
input data-byte
output data-byte
LSB
The upper 2 bit of the instruction byte contain the chip address. The chip address of the TLE8209-2 is 00. During
read access, the output data according to the register requested in the instruction byte are applied to SO within
the same SPI frame. That means, the output data corresponding to an instruction byte sent during one SPI frame
are transmitted to SO during the same SPI-frame
Data Sheet
27
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
Table 5
SPI Instruction Format
CPAD1
CPAD0
INSTR5
INSTR4
INSTR3
INSTR2
INSTR1
INSTR0
Field
Bits
Type
Description
CPAD1:0
7:6
Chip Address (00B)
INSTR5:0
5:0
SPI Instruction (encoding)
SO remains tristated
after SS active
Address sent by
master is "00 B "
Correct addres is recognized,

data transmitted to SO
SS
SCK
SI
SO
6
7
SO remains tristated
after SS active
Correct addres is not recognized, SO

remains tristated and SI data are ignored
Address sent by master

is different from "00 B"
SS
SCK
SI
6
7
4
5
3
4
SO
Figure 17
Data Sheet
0
1
5
6
4
5
2
3
1
2
0
0
Bus Arbitration by Chip Address
28
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
Table 6
SPI Instruction Set
Command
SPI Instruction Byte
Description
RD_ID
0000 0000
Read identifier
RD_REV
0000 0011
Read version
RD_DIA
0000 1001
Read diagnostics register
RD_CONFIG
0011 0000
Read power stage configuration
RD_STATCON
0011 1100
Read VDD monitoring status
WR_CONFIG
0010 1000
Write power stage configuration
WR_STATCON
0001 1000
Write VDD monitoring status
all other instructions
00xx xxxx
Unused - TRANS_F is set to high, ff_hex is sent as data bit.
all other chip addr.
xxxx xxxx
Invalid address - SO remains tristate during entire SPI-frame.
9.2.2
Verification Byte
Table 7
Verification Byte Format
VER6
VER5
VER4
VER3
VER2
VER1
VER0
TRANS_F
Field
Bits
Type
Description
VER6
Fixed to tristate (Z)
VER5
Fixed to tristate (Z)
VER4
Fixed to high (1)
VER3
Fixed to low (0)
VER2
Fixed to high (1)
VER1
Fixed to low (0)
VER0
Fixed to high (1)
TRANS_F
Transfer failure:
1B
Error detected during previous transfer
0B
Previous transfer was recognized as valid
9.2.3
Device Identifier and Revision
The ICs identifier (device ID) and revision number are used for production test purposes and features plug & play
functionality depending on the systems software release. The two numbers are read-only accessible via the SPIinstructions RD_ID and RD_REV as described in Section 9.2.1. The device ID is defined to allow identification of
different IC-types by software and is fixed for the TLE8209-2.
The revision number may be utilized to distinguish different states of hardware and is updated with each redesign
of the TLE8209-2. It is divided into an upper 4 bit field reserved to define revisions (SWR) corresponding to specific
software releases and a lower 4 bit field utilized to identify the actual mask set revision (MSR).
Data Sheet
29
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
ID_REG
Device Identifier
7
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Field
Bits
Type
Description
ID7:0
7:0
Device-ID
TLE8209-2: DE hex
REV_REG
Device Revision
7
SWR3
SWR2
SWR1
SWR0
MSR3
MSR2
MSR1
MSR0
Field
Bits
Type
Description
SWR3:0
7:4
Revision corresponding to software release
MSR3:0
3:0
Revision corresponding to mask set
9.2.4
Diagnostics Register
DIA_REG
Diagnostics Register
Reset Value: x111 1111B
ABE/DIS
OT
CurrRed
CurrLim
DIA21
DIA20
DIA11
DIA10
Field
Bits
Type
Description
ABE/DIS
Is set to 0 in case of ABE = L or DIS = H
OT
Is set to 0 in case of over temperature
CurrRed
Is set to 0 in case of temperature dependent current limitation
CurrLim
Is set to 0 in case of current limitation
DIA21
Diagnosis-Bit2 of OUT2
DIA20
DIA11
DIA10
Data Sheet
30
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
Table 8
ABE/DIS
Failure Encoding
DIA21 DIA20 DIA11
DIA10 Description
Comment
no failure
short circuit to battery at OUT1 (SCB1)
latched
short circuit to ground at OUT1 (SCG1)
latched
no error detected at OUT1
short circuit to battery at OUT2 (SCB2)
latched
short circuit to ground at OUT2 (SCG2)
latched
no error detected at OUT2
short circuit accross load (HS1+LS2 active)
latched
short circuit accross load (HS2+LS1 active)
latched
Undervoltage at pin VS
not latched
open load (H-Bridge)
latched
open load at OUT1 (single switch operation)
latched
open load at OUT2 (single switch operation)
latched
Note:
The bit ABE/DIS shows directly the status of inputs ABE and DIS. It is set to 0 if the power stages are disabled
by ABE or DIS.
The bits OT, CurrRed and CurrLim are latched. They will be reset with each read access. If the failure condition is
still present the according bits are set again.
Undervoltage at VS is reported and the outputs are switched off as long as the undervoltage condition is present.
The previous setting of the DIAx bits is masked but not reset. Once the supply voltage is back in the operating
range the diagnostic bits DIAxx will return to their setting before VS undervoltage. The outputs will return to normal
operation.
Detection of short circuit will switch of the output stages. In single half bridge operation only the affected output is
switched off. In H-Bridge mode both outputs are shut down. The outputs remain off until the failure condition is
removed and the diagnosis register is reset.
A short across the load may also be reported as SCG at one output and SCB at the other.
The diagnostic information DIAxx in the SPI interface is reset in the following cases:
Read out of DIA_REG: only bit 4, 5 and 6 will be reset

Enabling or disabling of the bridge via ABE or DIS
Undervoltage at VDD
Reset command via SPI
Data Sheet
31
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
9.2.5
Configuration Register
CONFIG_REG
Configuration Register
Reset Value: 1111 1010B
MODE
MUX
SIN1
SIN2
CL1
CL2
RESET
SL
Field
Bits
Type
Description
MODE
wr
1: H-bridge mode
0: single output stages (for current levels 1 to 3 only)
MUX
wr
1: control by parallel inputs IN1 and IN2

0: control by SPI bits SIN1 and SIN2
SIN1
wr
control of OUT1 if MUX=0
SIN2
wr
control of OUT2 if MUX=0
CL1
wr
current limitation level (see table below)
CL2
wr
current limitation level (see table below)
RESET
wr
0: reset of digital logic
SL
wr
slew rate setting

1: slow
0: fast
Table 9
Current Limitation Levels
CL1
CL2
Current Limitation Level
Typical Current Limitation Threshold
1.5A
4.0A
3 (default)
1)
6.6A
8.6A
1) The current limitation level 4 is applicable in the 430 mil power package only (TLE8209-2SA in PG-DSO-20-65).
Level 4 must not be used in the 300 mil exposed pad package (TLE8209-2E in PG-DSO-20-71).
Data Sheet
32
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
9.2.6
STATCON Register
STATCON_REG
STATCON Register
Reset Value: 1101 1xxxB
CONFIG2
CONFIG1
CONFIG0
DIACLR2
DIACLR1
STATUS2
STATUS1
STATUS0
Field
Bits
Type
Description
CONFIG2
wr
VDD threshold test mode

1: VDD monitoring in normal operation
0: VDD thresholds are changed according to CONFIG1
CONFIG1
wr
changes thresholds in VDD threshold test mode (CONFIG2=0)

1: increase lower threshold of VDD monitoring to test switch off path
0: decrease upper threshold of VDD monitoring to test switch off path
CONFIG0
wr
latch function for overvoltage at VDD

1: overvoltage at VDD latched
0: overvoltage at VDD not latched
DIACLR2
wr
0: clears diagnosis of OUT2

always returns 1 at read access
DIACLR1
wr
0: clears diagnosis of OUT1

always returns 1 at read access
STATUS2
returns level at ABE
STATUS1
0: under voltage at VDD

1: VDD voltage above lower limit
STATUS0
0: over voltage at VDD

1: VDD voltage below upper limit
Data Sheet
33
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
9.2.7
Contents of the SPI registers after a reset condition
Note: The registers for device identifier and revision (ID_REG and REV_REG) are not affected by reset.
DIA_REG
7
ABE/DIS
OT
CurrRed
CurLim
DIA21
DIA20
DIA11
DIA10
POR
SPIR
ABE/DISR
RDR
DIACLR1
DIACLR2
CONFIG_REG
MODE
MUX
SIN1
SIN2
CL1
CL2
RESET
SL
POR
SPIR
DISR
SFMODE
STATCON_REG
CONFIG2 CONFIG1 CONFIG0 DIACLR2
DIACLR1 STATUS2 STATUS1 STATUS0
POR
SPIR
SFMODE
POR: Reset due to VDD power up

SPIR: Reset via SPI by writing 0 into the RESET of CONFIG_REG
ABE/DISR: Reset due to enabling or disabling the power stages via DIS or ABE (edge triggered)
DISR: Reset due to a disabled power stage by DIS or ABE (level triggered)
RDR: Reset due to a read access to DIA_REG
DIACLR1: Reset via SPI by writing 0 into the DIACLR1 of STATCON_REG
DIACLR2: Reset via SPI by writing 0 into the DIACLR2 of STATCON_REG
SFMODE: Reset by setting the TLE8209-2 into the Status Flag Mode (VDDIO = 0V)
x: No change
Note: If a reset condition is not listed for a particular register it has no effect on the contents of this register.
Data Sheet
34
Rev. 1.4, 2014-10-28
TLE8209-2
SPI Interface
9.3
Electrical Characteristics SPI
Electrical Characteristics: SPI Interface
VS = 5 V to 28 V; VDD = 5.0 V; VDDIO = 2.9 V to 5.5 V, Tj = -40 C to 150 C, all voltages with respect to ground,
positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
Typ. Max.
490
ns
referred to master
50
ns
referred to master
150
ns
referred to master
150
230
ns
CL = 200 pF
CL = 350 pF
SPI-Timing (see Figure 18)1)

9.3.1
Cycle-time (1)
9.3.2
Enable Lead Time (2)
9.3.3
Enable Lag Time (3)
9.3.4
Data Valid (4)

H->L: VSCK=2V -> VSO=0.2 VDDIO
L->H: VSCK=2V -> VSO=0.8 VDDIO
if VDDIO < 4.5V:
L->H: VSCK=2V -> VSO=0.7 VDDIO
9.3.5
Data Setup Time (5)
9.3.6
Data Hold Time (6)
9.3.7
Disable Time (7)
9.3.8
Transfer Delay (8)
9.3.9
Disable Lead Time (9)
9.3.10
Disable Lag Time (10)
9.3.11
Access time (11)
tcyc
tlead
tlag
tv
referred to TLE8209-2
tsu
th
tdis
tdt
tdld
tdlg
tacc
40
ns
referred to master
40
ns
referred to master
100
ns
referred to TLE8209-2
250
ns
referred to master
250
ns
referred to master
250
ns
referred to master
8.35
referred to master
1) All timing parameters specified by design - not subject to production test
11
SS
8
3
9
1
10
SCK
7
SO
tristate
5
SI
Bit (n-3)
Bit (n-4)1
Bit 0; LSB
MSB IN
Bit (n-2)
Bit (n-3)
Bit (n-4)1
LSB IN
n=16
Figure 18
Data Sheet
SPI Timing
35
Rev. 1.4, 2014-10-28
TLE8209-2
Application Information
10
Note: The following simplified application examples are given as a hint for the implementation of the device only
and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the
device. The function of the described circuits must be verified in the real application
10 nF
Vbat
Vs <
40V
100nF
100 uF
VS
CP
TLE8209-2
5V ECU supply
V DD
8.2k
Enable
input (s)
ABE
open -drain
output (s)
OUT1
IN1
IN2
DIS
C
M
OUT2
SO
SI
<33 nF
<33 nF
SCK
SS/ SF
3.3 or 5V port supply
VDDIO
GNDABE
VDD voltage
regulator GND pin
Figure 19
Data Sheet
GND
Application Example H-Bridge with SPI-Interface
36
Rev. 1.4, 2014-10-28
TLE8209-2
10 nF
Vbat
Vs<
40V
100 uF
100 nF
VS
CP
TLE8209-2
5V ECU supply
V DD
3.3 or 5V port supply
8.2k
47k
Enable
input (s)
ABE
open -drain
output (s)
SS/ SF
OUT1
uC
IN1
IN2
DIS
OUT2
<33 nF
<33 nF
SO
SI
SCK
VDDIO
GNDABE
VDD voltage
regulator GND pin
Figure 20
GND
Application Example with Status Flag
Reverse polarity protection via main relay

VS
ignition
switch
100F
Vs < 40V
main
relay
100 nF
battery
Figure 21
Data Sheet
Application Examples for Overvoltage and Reverse-Voltage Protection

37
Rev. 1.4, 2014-10-28
TLE8209-2
Package Outlines TLE8209-2SA
110.151)
1.3
15.740.1
(Heatslug)
0.25 +0.07
-
53
0.20
2.8
6.3
0.1
Heatslug
(Mold)
0.950.15
0.25M A 20x
14.2 0.3
Bottom View
11
20
11
20
0.25B
5.90.1
(Metal)
0.4 +0.13
3.20.1
(Metal)
1.27
3.5 MAX.
1.10.1
3.250.1
Package Outlines TLE8209-2SA
0 +0.1
11
Index Marking
1 x 45
10
15.90.151)
(Mold)
10
13.7 -0.2
(Metal
)
Heatslug
1)
Does not include plastic or metal protrusion of 0.15 max. per side
GPS05791
0.68
13.48
1.83
Footprint:
1.27
9 x 1.27 = 11.43
hlg09550
Figure 22
PG-DSO-20-65 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page: http://www.infineon.com/packages
Data Sheet
38
Dimensions in mm
Rev. 1.4, 2014-10-28
TLE8209-2
Package Outlines TLE8209-2E
2.55 MAX.
Package Outlines TLE8209-2E

0.35 x 45
7.6 -0.2 1)
1.27
8 MAX.
0.23 +0.09
0...0.1
2.45 -0.2
12
0.7 0.2
0.4 0.08 2)
0.25 M
A
11
10.3 0.3
Bottom View
Ejector Mark
Ejector Mark
11
20
Exposed Diepad
4.8
20
0.1 C 20x
C
A-B C D 20x
Index Marking
10
10
Index Marking
12.8 -0.2 1)
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
PG-DSO-20-30-PO V01
0.65
1.67
4.8
Footprint:
9.73
1.27
PG-DSO-20-30-FP V01
Figure 23
PG-DSO-20-71 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page: http://www.infineon.com/packages
Data Sheet
39
Dimensions in mm
Rev. 1.4, 2014-10-28
TLE8209-2
Revision History
13
Revision History
Revision
Date
Comments / Changes
1.2
2012-12-20
Data sheets TLE8209-2SA Rev. 1.2 and TLE8209-2E Rev 1.2 merged into a dual
package version
1.3
2014-07-08
Current limitation level 4 excluded from use in 300 mil exposed pad package (PGDSO-20-71).
1.4
2014-10-28
Chapter 8.10. (Electrical Characteristics Protection and Monitoring): Introduced

separate rows for specification of current limitation level 4 of TLE8209-2SA and
TLE8209-2E.
Added and updated notes regarding exclusion of current limitation level 4 from use
in 300 mil exposed pad package.
Data Sheet
40
Rev. 1.4, 2014-10-28
Edition 2014-10-28
Published by
Infineon Technologies AG
81726 Munich, Germany
2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

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Data Sheet, Rev. 1.

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Logic Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Outlines TLE8209-2SA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package Outlines TLE8209-2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Rev. 1.4, 2014-10-28

SPI Programmable H-Bridge

Programmable current limitation from 1.5 to 8.6 A typ.

Rev. 1.4, 2014-10-28

Rev. 1.4, 2014-10-28

Pin Definitions and Functions

Function in SPI Mode

Function in Status Flag Mode

SPI Serial Data Out

no function - connect to GND

Supply Voltage for Logic Output Buffer

Switches to SF-mode if connected to GND

Slave Select (low active)

Status Flag (low active)

Pin for external Charge Pump Capacitor

Pin for external Charge Pump Capacitor

Battery Supply Voltage, has to be connected to Battery Supply Voltage, has to be

Bidirectional Enable Pin

Bidirectional Enable Pin

Input battery supply voltage, has to be

Input battery supply voltage, has to be

SPI Serial Data Input

no function - connect to GND

no function - connect to GND

Sense ground for VDD monitoring

Sense ground for VDD monitoring

Heatslug - connect to GND

Heatslug - connect to GND

Rev. 1.4, 2014-10-28

Rev. 1.4, 2014-10-28

Block Diagram TLE8209-2

Rev. 1.4, 2014-10-28

General Product Characteristics

Absolute Maximum Ratings

Absolute Maximum Ratings 1)

Battery supply voltage

Logic supply voltage

Supply for logic out

Voltage at logic pins

Test Conditions / Comment

Static destruction proof

Dynamic destruction proof

0V < VS < 40V

HBM2), Pins OUT1 and OUT2

CDM3), Pins 1, 10, 11, 20

ESD Resistivity to GND

1) Not subject to production test, specified by design.

Rev. 1.4, 2014-10-28

VS supply voltage range

1) Not subject to production test, specified by design.

Rev. 1.4, 2014-10-28

Basic Supply Characteristics

Rev. 1.4, 2014-10-28

VDDIO - Digital Output Supply and Diagnostic Mode Selection