Card VHDL PDF
Card VHDL PDF
[{block_config | comp_config}]
end for;
VHDL QUICK
REFERENCE CARD
Revision 2.2
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VHDL-1993
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User Identifier
1. LIBRARY UNITS
[{use_clause}]
entity ID is
[generic ({ID : TYPEID [:= expr];});]
[port ({ID : in | out | inout TYPEID [:= expr];});]
[{declaration}]
[begin
{parallel_statement}]
end [entity] ENTITYID;
[{use_clause}]
architecture ID of ENTITYID is
[{declaration}]
begin
[{parallel_statement}]
end [architecture] ARCHID;
[{use_clause}]
package ID is
[{declaration}]
end [package] PACKID;
comp_config::=
for all | LABELID : COMPID
(use entity [LIBID.]ENTITYID [( ARCHID )]
[[generic map ( {GENID => expr ,} )]
port map ({PORTID => SIGID | expr ,})];
[for ARCHID
[{block_config | comp_config}]
end for;]
end for;) |
(use configuration [LIBID.]CONFID
[[generic map ({GENID => expr ,})]
port map ({PORTID => SIGID | expr,})];)
end for;
2. DECLARATIONS
2.1. TYPE DECLARATIONS
type ID is ( {ID,} );
type ID is range number downto | to number;
type ID is array ( {range | TYPEID ,}) of TYPEID;
type ID is record
{ID : TYPEID;}
end record;
3. EXPRESSIONS
relation ::=
shexpr ::=
sexpr ::=
term ::=
range ::=
(integer | ENUMID to | downto integer | ENUMID) |
(OBJID[reverse_]range) | (TYPEID range <>)
factor ::=
(prim [** prim]) | (abs prim) | (not prim)
prim ::=
literal | OBJID | OBJIDATTRID | OBJID({expr,})
| OBJID(range) | ({[choice [{| choice}] =>] expr,})
| FCTID({[PARID =>] expr,}) | TYPEID(expr) |
TYPEID(expr) | new TYPEID[(expr)] | ( expr )
choice ::=
[{use_clause}]
configuration ID of ENTITYID is
for ARCHID
[{block_config | comp_config}]
end for;
end [configuration] CONFID;
block_config::=
expression ::=
(relation and relation) | (relation nand relation) |
(relation or relation) | (relation nor relation) |
(relation xor relation) | (relation xnor relation)
[{use_clause}]
package body ID is
[{declaration}]
end [package body] PACKID;
use_clause::=
library ID;
[{use LIBID.PKGID[. all | DECLID];}]
component ID [is]
[generic ( {ID : TYPEID [:= expr];} );]
[port ({ID : in | out | inout TYPEID [:= expr];});]
end component [COMPID];
4. SEQUENTIAL STATEMENTS
wait [on {SIGID,}] [until expr] [for time];
assert expr
[report string]
[severity note | warning | error | failure];
report string
[severity note | warning | error | failure];
SIGID <= [transport] | [[reject TIME] inertial]
{expr [after time],};
VARID := expr;
PROCEDUREID[({[PARID =>] expr,})];
[LABEL:] if expr then
{sequential_statement}
[{elsif expr then
{sequential_statement}}]
[else
{sequential_statement}]
end if [LABEL];
[LABEL:] case expr is
{when choice [{| choice}] =>
{sequential_statement}}
end case [LABEL];
[LABEL:] [while expr] loop
{sequential_statement}
end loop [LABEL];
[LABEL:] for ID in range loop
{sequential_statement}
end loop [LABEL];
next [LOOPLBL] [when expr];
exit [LOOPLBL] [when expr];
return [expression];
null;
5. PARALLEL STATEMENTS
LABEL: block [is]
[generic ( {ID : TYPEID;} );
[generic map ( {[GENID =>] expr,} );]]
[port ( {ID : in | out | inout TYPEID } );
[port map ( {[PORTID =>] SIGID | expr,} )];]
[{declaration}]
begin
[{parallel_statement}]
end block [LABEL];
[LABEL:] [postponed] process [( {SIGID,} )]
[{declaration}]
begin
[{sequential_statement}]
end [postponed] process [LABEL];
[LBL:] [postponed] PROCID({[PARID =>] expr,});
6. PREDEFINED ATTRIBUTES
TYPIDbase
Base type
TYPIDleft
Left bound value
TYPIDright
Right-bound value
TYPIDhigh
Upper-bound value
TYPIDlow
Lower-bound value
TYPIDpos(expr)
Position within type
TYPIDval(expr)
Value at position
TYPIDsucc(expr)
Next value in order
TYPIDpred(expr)
Previous value in order
TYPIDleftof(expr)
Value to the left in order
TYPIDrightof(expr)
Value to the right in order
TYPIDascending
Ascending type predicate
TYPIDimage(expr)
String image of value
TYPIDvalue(string)
Value of string image
ARYIDleft[(expr)]
Left-bound of [nth] index
ARYIDright[(expr)]
Right-bound of [nth] index
ARYIDhigh[(expr)]
Upper-bound of [nth] index
ARYIDlow[(expr)]
Lower-bound of [nth] index
ARYIDrange[(expr)]
left down/to right
ARYIDreverse_range[(expr)] right down/to left
ARYIDlength[(expr)]
Length of [nth] dimension
ARYIDascending[(expr)]
right >= left ?
SIGIDdelayed[(TIME)] Delayed copy of signal
SIGIDstable[(TIME)]
Signals event on signal
SIGIDquiet[(TIME)]
Signals activity on signal
SIGIDtransaction
Toggles if signal active
SIGIDevent
SIGIDactive
SIGIDlast_event
SIGIDlast_active
SIGIDlast_value
SIGIDdriving
SIGIDdriving_value
OBJIDsimple_name
OBJIDinstance_name
OBJIDpath_name
7. PREDEFINED TYPES
BOOLEAN
INTEGER
NATURAL
POSITIVE
REAL
BIT
BIT_VECTOR(NATURAL)
CHARACTER
STRING(POSITIVE)
TIME
DELAY_LENGTH
True or false
32 or 64 bits
Integers >= 0
Integers > 0
Floating-point
0, 1
Array of bits
7-bit ASCII
Array of characters
hr, min, sec, ms,
us, ns, ps, fs
Time >= 0
8. PREDEFINED FUNCTIONS
NOW
Returns current simulation time
DEALLOCATE(ACCESSTYPOBJ)
Deallocate dynamic object
FILE_OPEN([status], FILEID, string, mode)
Open file
FILE_CLOSE(FILEID)
Close file
9. LEXICAL ELEMENTS
Identifier ::= letter { [underline] alphanumeric }
decimal literal ::=integer [. integer] [E[+|-] integer]
based literal ::=
integer # hexint [. hexint] # [E[+|-]
integer]
bit string literal ::=
comment ::=
B|O|X hexint
-- comment text
Event on signal ?
Activity on signal ?
Time since last event
Time since last active
Value before last event
Active driver predicate
Value of driver
Name of object
Pathname of object
Pathname to object
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