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This document provides a concise summary of VHDL concepts and syntax elements in 3 sentences or less per section. It includes summaries of libraries and packages, entity architecture and configuration, declarations, expressions, sequential and parallel statements, attributes and predefined types and functions.

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0% found this document useful (0 votes)
63 views2 pages

Card VHDL PDF

This document provides a concise summary of VHDL concepts and syntax elements in 3 sentences or less per section. It includes summaries of libraries and packages, entity architecture and configuration, declarations, expressions, sequential and parallel statements, attributes and predefined types and functions.

Uploaded by

giri_placid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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for LABELID

[{block_config | comp_config}]
end for;

VHDL QUICK
REFERENCE CARD
Revision 2.2
()
{}
bold
italic

Grouping
Repeated
As is
VHDL-1993

[]
|
CAPS

Optional
Alternative
User Identifier

1. LIBRARY UNITS
[{use_clause}]
entity ID is
[generic ({ID : TYPEID [:= expr];});]
[port ({ID : in | out | inout TYPEID [:= expr];});]
[{declaration}]
[begin
{parallel_statement}]
end [entity] ENTITYID;
[{use_clause}]
architecture ID of ENTITYID is
[{declaration}]
begin
[{parallel_statement}]
end [architecture] ARCHID;
[{use_clause}]
package ID is
[{declaration}]
end [package] PACKID;

comp_config::=
for all | LABELID : COMPID
(use entity [LIBID.]ENTITYID [( ARCHID )]
[[generic map ( {GENID => expr ,} )]
port map ({PORTID => SIGID | expr ,})];
[for ARCHID
[{block_config | comp_config}]
end for;]
end for;) |
(use configuration [LIBID.]CONFID
[[generic map ({GENID => expr ,})]
port map ({PORTID => SIGID | expr,})];)
end for;

2. DECLARATIONS
2.1. TYPE DECLARATIONS
type ID is ( {ID,} );
type ID is range number downto | to number;
type ID is array ( {range | TYPEID ,}) of TYPEID;
type ID is record
{ID : TYPEID;}
end record;

for LABELID | others | all : COMPID use


(entity [LIBID.]ENTITYID [( ARCHID )]) |
(configuration [LIBID.]CONFID)
[[generic map ( {GENID => expr,} )]
port map ( {PORTID => SIGID | expr,} )];

3. EXPRESSIONS

type ID is file of TYPEID;

relation ::=

subtype ID is SCALARTYPID range range;

shexpr ::=

sexpr [shop sexpr]

subtype ID is ARRAYTYPID( {range,});

sexpr ::=

[+|-] term {addop term}

subtype ID is RESOLVFCTID TYPEID;

term ::=

factor {mulop factor}

range ::=
(integer | ENUMID to | downto integer | ENUMID) |
(OBJID[reverse_]range) | (TYPEID range <>)

shexpr [relop shexpr]

factor ::=
(prim [** prim]) | (abs prim) | (not prim)

[shared] variable ID : TYPEID [:= expr];

prim ::=
literal | OBJID | OBJIDATTRID | OBJID({expr,})
| OBJID(range) | ({[choice [{| choice}] =>] expr,})
| FCTID({[PARID =>] expr,}) | TYPEID(expr) |
TYPEID(expr) | new TYPEID[(expr)] | ( expr )

signal ID : TYPEID [:= expr];

choice ::=

2.2. OTHER DECLARATIONS

[{use_clause}]
configuration ID of ENTITYID is
for ARCHID
[{block_config | comp_config}]
end for;
end [configuration] CONFID;

file ID : TYPEID (is in | out string;) |


(open read_mode | write_mode |
append_mode is string;)

1995-2000 Qualis Design Corporation

procedure ID[({[constant | variable | signal] ID :


in | out | inout TYPEID [:= expr];})]
[is begin
[{sequential_statement}]
end [procedure] ID];

type ID is access TYPEID;

constant ID : TYPEID := expr;

block_config::=

[impure | pure] function ID


[( {[constant | variable | signal | file] ID :
[in]TYPEID [:= expr];})]
return TYPEID [is
begin
{sequential_statement}
end [function] ID];

expression ::=
(relation and relation) | (relation nand relation) |
(relation or relation) | (relation nor relation) |
(relation xor relation) | (relation xnor relation)

[{use_clause}]
package body ID is
[{declaration}]
end [package body] PACKID;

use_clause::=
library ID;
[{use LIBID.PKGID[. all | DECLID];}]

component ID [is]
[generic ( {ID : TYPEID [:= expr];} );]
[port ({ID : in | out | inout TYPEID [:= expr];});]
end component [COMPID];

alias ID : TYPEID is OBJID;


attribute ID : TYPEID;
attribute ATTRID of OBJID | others | all : class is expr;
class ::=
entity | architecture | configuration |
procedure | function | package | type |
subtype | constant | signal | variable |
component | label

1995-2000 Qualis Design Corporation

sexpr | range | RECFID | others

3.1. OPERATORS, INCREASING PRECEDENCE


logop
relop
shop
addop
mulop
miscop

and | or | xor | nand | nor | xnor


= | /= | < | <= | > | >=
sll | srl | sla | sra | rol | ror
+|-|&
* | / | mod | rem
** | abs | not

1995-2000 Qualis Design Corporation. Permission to


reproduce and distribute strictly verbatim copies of this
document in whole is hereby granted.
See reverse side for additional information.

4. SEQUENTIAL STATEMENTS
wait [on {SIGID,}] [until expr] [for time];
assert expr
[report string]
[severity note | warning | error | failure];
report string
[severity note | warning | error | failure];
SIGID <= [transport] | [[reject TIME] inertial]
{expr [after time],};
VARID := expr;
PROCEDUREID[({[PARID =>] expr,})];
[LABEL:] if expr then
{sequential_statement}
[{elsif expr then
{sequential_statement}}]
[else
{sequential_statement}]
end if [LABEL];
[LABEL:] case expr is
{when choice [{| choice}] =>
{sequential_statement}}
end case [LABEL];
[LABEL:] [while expr] loop
{sequential_statement}
end loop [LABEL];
[LABEL:] for ID in range loop
{sequential_statement}
end loop [LABEL];
next [LOOPLBL] [when expr];
exit [LOOPLBL] [when expr];
return [expression];
null;

5. PARALLEL STATEMENTS
LABEL: block [is]
[generic ( {ID : TYPEID;} );
[generic map ( {[GENID =>] expr,} );]]
[port ( {ID : in | out | inout TYPEID } );
[port map ( {[PORTID =>] SIGID | expr,} )];]
[{declaration}]
begin
[{parallel_statement}]
end block [LABEL];
[LABEL:] [postponed] process [( {SIGID,} )]
[{declaration}]
begin
[{sequential_statement}]
end [postponed] process [LABEL];
[LBL:] [postponed] PROCID({[PARID =>] expr,});

[LABEL:] [postponed] assert expr


[report string]
[severity note | warning | error | failure];
[LABEL:] [postponed] SIGID <=
[transport] | [[reject TIME] inertial]
[{{expr [after TIME,]} | unaffected when expr else}]
{expr [after TIME,]} | unaffected;
[LABEL:] [postponed] with expr select
SIGID <= [transport] | [[reject TIME] inertial]
{{expr [after TIME,]} | unaffected
when choice [{| choice}]};
LABEL: COMPID
[[generic map ( {GENID => expr,} )]
port map ( {[PORTID =>] SIGID | expr,} )];
LABEL: entity [LIBID.]ENTITYID [(ARCHID)]
[[generic map ( {GENID => expr,} )]
port map ( {[PORTID =>] SIGID | expr,} )];
LABEL: configuration [LIBID.]CONFID
[[generic map ( {GENID => expr,} )]
port map ( {[PORTID =>] SIGID | expr,} )];
LABEL: if expr generate
[{parallel_statement}]
end generate [LABEL];
LABEL: for ID in range generate
[{parallel_statement}]
end generate [LABEL];

6. PREDEFINED ATTRIBUTES
TYPIDbase
Base type
TYPIDleft
Left bound value
TYPIDright
Right-bound value
TYPIDhigh
Upper-bound value
TYPIDlow
Lower-bound value
TYPIDpos(expr)
Position within type
TYPIDval(expr)
Value at position
TYPIDsucc(expr)
Next value in order
TYPIDpred(expr)
Previous value in order
TYPIDleftof(expr)
Value to the left in order
TYPIDrightof(expr)
Value to the right in order
TYPIDascending
Ascending type predicate
TYPIDimage(expr)
String image of value
TYPIDvalue(string)
Value of string image
ARYIDleft[(expr)]
Left-bound of [nth] index
ARYIDright[(expr)]
Right-bound of [nth] index
ARYIDhigh[(expr)]
Upper-bound of [nth] index
ARYIDlow[(expr)]
Lower-bound of [nth] index
ARYIDrange[(expr)]
left down/to right
ARYIDreverse_range[(expr)] right down/to left
ARYIDlength[(expr)]
Length of [nth] dimension
ARYIDascending[(expr)]
right >= left ?
SIGIDdelayed[(TIME)] Delayed copy of signal
SIGIDstable[(TIME)]
Signals event on signal
SIGIDquiet[(TIME)]
Signals activity on signal
SIGIDtransaction
Toggles if signal active

SIGIDevent
SIGIDactive
SIGIDlast_event
SIGIDlast_active
SIGIDlast_value
SIGIDdriving
SIGIDdriving_value
OBJIDsimple_name
OBJIDinstance_name
OBJIDpath_name

7. PREDEFINED TYPES
BOOLEAN
INTEGER
NATURAL
POSITIVE
REAL
BIT
BIT_VECTOR(NATURAL)
CHARACTER
STRING(POSITIVE)
TIME
DELAY_LENGTH

1995-2000 Qualis Design Corporation

True or false
32 or 64 bits
Integers >= 0
Integers > 0
Floating-point
0, 1
Array of bits
7-bit ASCII
Array of characters
hr, min, sec, ms,
us, ns, ps, fs
Time >= 0

8. PREDEFINED FUNCTIONS
NOW
Returns current simulation time
DEALLOCATE(ACCESSTYPOBJ)
Deallocate dynamic object
FILE_OPEN([status], FILEID, string, mode)
Open file
FILE_CLOSE(FILEID)
Close file

9. LEXICAL ELEMENTS
Identifier ::= letter { [underline] alphanumeric }
decimal literal ::=integer [. integer] [E[+|-] integer]
based literal ::=
integer # hexint [. hexint] # [E[+|-]
integer]
bit string literal ::=
comment ::=

B|O|X hexint

-- comment text

1995-2000 Qualis Design Corporation. Permission to


reproduce and distribute strictly verbatim copies of this
document in whole is hereby granted.

Qualis Design Corporation


Elite Training / Consulting in Reuse and Methodology
Phone: +1-503-670-7200
E-mail: [email protected] com
Also available:

1995-2000 Qualis Design Corporation

Event on signal ?
Activity on signal ?
Time since last event
Time since last active
Value before last event
Active driver predicate
Value of driver
Name of object
Pathname of object
Pathname to object

FAX: +1-503-670-0809
Web:www.qualis.com

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