Part IV: Complex Cell Layout

Mapping Schematics to Layout

Layout organization: how to optimize layout connections
trial and error
works OK for simple gates but can require a lot of iterations

Stick Diagrams
simple method to draw layout options and see what is best before
committing to real layouts

Mapping techniques: how to arrange txs in layout

trial and error
works OK for simple gates

Euler Graph (pronounced oiler)

graphical method to determine transistor arrangement in layout

Best approach: combine some Euler Graph methods and

Stick Diagrams
ECE 410, Prof. A. Mason

Lecture Notes Page 3.54

Stick Diagram

Part IV: Complex Cell Layout

method for sketching layouts

Motivation
often hard to predict best way to make connections within a cell
Stick Diagram is a simple sketch of the layout that can easily be
changed/modified/redrawn with minimal effort

Stick Diagram

shows only active, poly, metal, contact, and n-well layers

each layer is color coded (typically use colored pencils or pens)
active, poly, metal traces are drawn with lines (not rectangles)
contacts are marked with an X
typically only need to show contacts between metal and active

n-well are indicated by a rectangle around pMOS transistors

typically using dashed lines

Show routing between txs, to VDD, Ground and Output

ECE 410, Prof. A. Mason

Lecture Notes Page 3.55

Part IV: Complex Cell Layout

Stick Diagram NAND & NOR

Simplified NAND Layout

Simplified NOR Layout

Stick Diagram
Metal supply rails
blue

n and p Active
green

VDD

VDD
a
X

b
X

Poly gates
red

out

Metal connections

out

supply, outputs

Contacts

black X

N-Well (optional)

dashed rectangle

ground
ECE 410, Prof. A. Mason

ground
Lecture Notes Page 3.56

Part IV: Complex Cell Layout

Euler Path
Euler Path
simplified layout methodology for multi-input circuits; based on
Euler Graphs
see textbook for full Euler Graph method; unnecessarily confusing for
most students

used to determine what order (left to right) to layout transistors

identifies if all transistors will fit onto a single (non-broken)
active strip

Method
try to draw a loop through all transistors
separate loop for nMOS and pMOS
starting point can be anywhere; may need to try different points to
achieve goals

Rules
can only trace through each transistor once
otherwise layout wont match schematic

can only re-cross any point/node once

otherwise multiple active strips will be required to complete layout

must trace through nMOS in the same order as pMOS

may have to rearrange txs in schematic
(without changing function) to achieve rules
ECE 410, Prof. A. Mason

Lecture Notes Page 3.57

Part IV: Complex Cell Layout

Euler Path Example

Example: OUT = a + bc
PMOS Loop
start pMOS at node c, through b to VDD,
through c to c, through a to OUT
check loop follows rules

NMOS Loop
trace through same tx order as pMOS
start nMOS at ground, through b and to
c OUT then through a to OUT again

Form stick diagram with polys in order b,

c, a determined by Euler Path

Alternative Loops
start pMOS loop at OUT, through a, then b,
then c.
to follow pMOS loop order, start at OUT,
through a to ground then b, then c
ECE 410, Prof. A. Mason

out

X
b

Lecture Notes Page 3.58

Part IV: Complex Cell Layout

Example
Circuit with pMOS and nMOS paths

Stick Diagram
VDD
a

start

Rule for single active strip:

loop can not cross the same
point/node more than twice
pMOS through W twice
nMOS through Y twice

X
out

ground
start

Shows layout can be constructed with a single p/n active trace.

Order of txs (poly traces) is a, b, c, d, on both p- and n-side
ECE 410, Prof. A. Mason

Lecture Notes Page 3.59

Part IV: Complex Cell Layout

Structured Layout

General Approach

Structured Layout

good example of a regular

power rails
cell layout useful for general
horizontal Active
logic functions
vertical Poly (inputs from top/bottom)
Metal1 connects nodes as needed in schematic
AOI circuit figure
useful for many logic functions
see examples in textbook

Disadvantages

not optimized for speed

large S/D regions =

higher capacitance
interconnect paths
could be shorter

not optimized for area/size

notice, need room inside cell

(between VDD and Ground)
to route internal connections

ECE 410, Prof. A. Mason

Lecture Notes Page 3.60

Part IV: Complex Cell Layout

Transistor Orientation
Horizontal Tx (W run vertically)
can increase tx W with fixed pitch
cells short & wide

Vertical Tx (W runs horizontally)

pitch sets max tx W
cells taller & narrow

D=pitch

ECE 410, Prof. A. Mason

Lecture Notes Page 3.61

Part IV: Complex Cell Layout

Inverter Layout Options

Layout with Horizontal Tx
pitch sets max tx size

Layout with Vertical Tx

horizontal

allows tx size scaling without

changing pitch

Vertical Tx with 2x scaling

vertical

ECE 410, Prof. A. Mason

Lecture Notes Page 3.62

Part IV: Complex Cell Layout

NAND/NOR Layout Alternatives

vertical transistors
for smaller pitch
(height) and wider cell

large horizontal
transistors
for larger pitch (height)
and narrower cell

ECE 410, Prof. A. Mason

Lecture Notes Page 3.63

Part II: Layout Basics

Design Rules: Intro

Why have Design Rules
fabrication process has minimum/maximum feature sizes that can be
produced for each layer
alignment between layers requires adequate separation (if layers
unconnected) or overlap (if layers connected)
proper device operation requires adequate separation

Lambda Design Rules

lambda, O, = 1/2 minimum feature size, e.g., 0. 6Pm process -> O =0.3Pm
can define design rules in terms of lambdas
allows for scalable design using same rules

Basic Rules
minimum layer size/width
minimum layer separation
minimum layer overlap
ECE 410, Prof. A. Mason

Lecture Notes Page 3.27

Part II: Layout Basics

Design Rules: 1
n-well

MOSIS SCMOS rules; O =0.3Pm for AMI C5N

required everywhere pMOS is needed

rules

10O
minimum width
minimum separation to self
minimum separation to nMOS Active
minimum overlap of pMOS Active

6O
5O

Active
required everywhere a transistor is needed
any non-Active region is FOX
rules
minimum width
3O
minimum separation to other Active
ECE 410, Prof. A. Mason

3O

Lecture Notes Page 3.28

Part II: Layout Basics

Design Rules: 2
n/p Select

defines regions to be doped n+ and p+

tx S/D = Active AND Select NOT Poly
tx gate = Active AND Select AND Poly
rules
2O

minimum overlap of Active

same for pMOS and nMOS

several more complex rules available

Poly
high resistance conductor (can be used for short routing)
2O
primarily used for tx gates
gate =
rules
2O

minimum size
minimum space to self
minimum overlap of gate
minimum space to Active
ECE 410, Prof. A. Mason

Active-Poly-Select

1O
2O
Lecture Notes Page 3.29

Part II: Layout Basics

Design Rules: 3
Contacts
Contacts to Metal1, from Active or Poly

note: due to contact size

and overlap rules, min.
active size at contact will
be 2+1.5+1.5=5O

use same layer and rules for both

must be SQUARE and MINIMUM SIZED

rules

exact size
minimum overlap by Active/Poly
minimum space to Contact
minimum space to gate

1.5O
5O

2O
2O
2O

2O

Metal1
low resistance conductor used for routing
rules
minimum size
minimum space to self
minimum overlap of Contact

3O
4O
if wide

ECE 410, Prof. A. Mason

2O

1O
Lecture Notes Page 3.30

Part II: Layout Basics

Design Rules: 4
Vias
Connects Metal1 to Metal2
must be SQUARE and MINIMUM SIZED
rules

exact size 2O
space to self 3O
minimum overlap by Metal1/Metal2 1O
minimum space to Contact 2O
minimum space to Poly/Active edge 2O

see MOSIS site

for illustrations

Metal2

low resistance conductor used for routing

rules
minimum size
minimum space to self
minimum overlap of Via

3O
6O
if wide

ECE 410, Prof. A. Mason

3O

1O
Lecture Notes Page 3.31

Part II: Layout Basics

Substrate/well Contacts
Substrate and nWells must be
connected to the power supply
within each cell

n+plug
to VDD

use many connections to reduce

resistance
generally place
~ 1 substrate contact per nMOS tx
~ 1 nWell contact per pMOS tx

this connection is called a tap, or plug

often done on top of VDD/Ground rails
need p+ plug to Ground at substrate
need n+ plug to VDD in nWell
p+plug
to Ground
ECE 410, Prof. A. Mason

Lecture Notes Page 3.32

Part II: Layout Basics

Latch-Up
Latch-up is a very real, very important factor in circuit design that
must be accounted for
Due to (relatively) large current in substrate or n-well
create voltage drops across the resistive substrate/well
most common during large power/ground current spikes

turns on parasitic BJT devices, effectively shorting power & ground

often results in device failure with fused-open wire bonds or interconnects

hot carrier effects can also result in latch-up

latch-up very important for short channel devices

Avoid latch-up by
including as many substrate/well contacts as possible
rule of thumb: one plug each time a tx connects to the power rail

limiting the maximum supply current on the chip

ECE 410, Prof. A. Mason

Lecture Notes Page 3.33

Part II: Layout Basics

Multiple Contacts
Each contact has a characteristic resistance, Rc
Contact resistances are much higher than the resistance
of most interconnect layers
Multiple contacts can be used to reduce resistance
Rc,eff = Rc / N, N=number of contacts

N=6

Generally use as many contacts as space allows

use several
Contacts
in wide txs

ECE 410, Prof. A. Mason

add Vias
if room
allows

Lecture Notes Page 3.34