DOC/LP/01/28.02.
02
LESSON PLAN
LP- AP7103
LP Rev. No: 00
Sub Code & Name : AP7103
ADVANCED MICROPROCESSORS AND
MICROCONTROLLERS
Unit: I
Branch: M.E- AE & CS
Date:05/09/2013
Page 01 of 06
Semester :I
Unit syllabus:
UNIT I
OVERVIEW
9
Generic Architecture-Instruction Set Data formats Addressing modes Memory
hierarchy register file Cache Virtual memory
and paging Segmentation-
pipelining the instruction pipeline pipeline hazards instruction level parallelism
reduced instruction set Computer principles RISC versus CISC.
Objective: To study basics of Microprocessor & concepts of various architecture.
Session
No
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Time
Ref
Teaching
Method
Introduction to Microprocessor architectures
Introduction to the Generic architecture of
Microprocessors
Classification of Instruction Set, Data formats
Various types of Addressing modes
Direct,Indirect,Register,Index
Memory hierarchy-Cache Memory, Virtual
Memory
Cache memory, Register file
Virtual memory and paging
Segmentation of memory
50m
50m
1
1
BB
BB
50m
50m
1
8
BB
BB
50m
BB
50m
50m
50m
1
1
1
BB
BB
BB
Instruction level Parallelism, Reduced Instruction
Set
Computer Principles-RISC versus CISC
50m
BB
50m
BB
Topics to be covered
DOC/LP/01/28.02.02
LESSON PLAN
LP- AP7103
LP Rev. No: 00
Sub Code & Name : AP7103
ADVANCED MICROPROCESSORS AND
MICROCONTROLLERS
Unit: II
Branch: M.E- AE & CS
Date:05/09/2013
Page 02 of 06
Semester :I
Unit syllabus:
UNIT II HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM
CPU Architecture- Bus Operations Pipelining Branch predication floating
point unit-Operating Modes Paging Multitasking Exception and Interrupts
Instruction set addressing modes Programming the Pentium processor.
Objective: To study about Pentium Processor and its programming
Session
No
Topics to be covered
11. CPU Architecture
12. Bus Operations
13. Pipelining, Pipelining Hazards in CISC
architecture
14. Branch prediction
15. Floating point unit ,Operating Modes
16.
17.
18.
19.
Ref
Time
50m
50m
50m
2
2,6
2
Teaching
Method
BB
BB
BB
50m
50m
2
6
BB
BB
Paging, Multitasking
Exception handling and Interrupts
Instruction set, addressing modes
Programming the Pentium processor
50m
50m
50m
50m
2,6
2
6
6
BB
BB
BB
BB
CAT-I
180m
DOC/LP/01/28.02.02
LESSON PLAN
LP- AP7103
LP Rev. No: 00
Sub Code & Name : AP7103
ADVANCED MICROPROCESSORS AND
MICROCONTROLLERS
Unit: III
Branch: M.E- AE & CS
Date:05/09/2013
Page 03 of 06
Semester :I
Unit syllabus:
UNIT III
HIGH PERFORMANCE RISC ARCHITECTURE ARM 9
Organization of CPU Bus architecture Memory management unit - ARM instruction
set- Thumb Instruction set- addressing modes Programming the ARM processor.6
Objective: To study the ARM RISC architecture and its programming.
Session
No
Topics to be covered
Time
Ref with
page no
3
Teachin
g
Method
BB
20.
Organization of CPU and its functions
50m
21.
Bus architecture
BB
22.
Memory management unit
50m
50m
BB
23.
ARM instruction set
50m
BB
50m
BB
24.
-Do-
25.
Thumb Instruction set
50m
BB
26.
Various types of Addressing modes
50m
OHP
27.
Programming in ARM processor
50m
OHP
28.
Floating point unit in ARM
50m
OHP
DOC/LP/01/28.02.02
LESSON PLAN
LP- AP7103
LP Rev. No: 00
Sub Code & Name : AP7103
ADVANCED MICROPROCESSORS AND
MICROCONTROLLERS
Unit: IV Branch: M.E- AE & CS
Date:05/09/2013
Page 04 of 06
Semester :I
Unit syllabus:
UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS
Instruction set, addressing modes operating modes- Interrupt system- RTC-Serial
Communication Interface A/D Converter PWM and UART.
Objective:
To learn in detail about Motorola Microcontrollers.
Session
No
Time
50m
Ref
4
30.
Topics to be covered
Introduction to MOTOROLA
Microcontrollers
Classification of Instruction set
Teaching
Method
BB
50m
BB
31.
Various types of Addressing modes
50m
4,7
BB
32.
Operating modes
50m
4,7
BB
33.
Interrupt system
50m
OHP
34.
Real Time Controller(RTC)
50m
BB
35.
Serial Communication Interface
50m
BB
36.
A/D Converter PWM
50m
OHP
37.
UART
50m
OHP
29.
CAT-II
90m
DOC/LP/01/28.02.02
LESSON PLAN
LP- AP7103
LP Rev. No: 00
Sub Code & Name : AP7103
ADVANCED MICROPROCESSORS AND
MICROCONTROLLERS
Unit: V
Branch: M.E- AE & CS
Date:05/09/2013
Page 05 of 06
Semester :I
Unit syllabus:
UNIT V PIC MICROCONTROLLER
CPU Architecture Instruction set interrupts- Timers- I2C Interfacing
UART- A/D Converter PWM and introduction to C-Compilers.
Objective:
To learn about the functioning of PIC Microcontroller.
Session
No
Topics to be covered
Time
Ref
Teaching
Method
38.
Introduction to PIC Microcontroller
50m
BB
39.
CPU Architecture
50m
BB
40.
Classification of Instruction set
50m
BB
41.
Interrupts
50m
BB
42.
Timers in PIC microcontroller
50m
BB
43.
I2C Interfacing in PIC microcontroller
50m
BB
44.
UART
50m
BB
45.
A/D Converter
50m
BB
46.
PWM and introduction to C-Compilers
50m
BB
DOC/LP/01/28.02.02
LESSON PLAN
LP- AP7103
LP Rev. No: 00
Sub Code & Name : AP7103
ADVANCED MICROPROCESSORS AND
MICROCONTROLLERS
Branch: M.E- AE & CS
Date:05/09/2013
Page 06 of 06
Semester :I
Course Delivery Plan:
Week
Units
10
11 12
I
I II I II I II I II I II I II I II I II I II I II
I II
II
1
2
3
4
5
REFERENCES
1. Daniel Tabak , Advanced Microprocessors McGraw Hill.Inc., 1995
2. James L. Antonakos , The Pentium Microprocessor Pearson Education , 1997.
3. Steve Furber , ARM System On Chip architecture Addision Wesley , 2000.
4. Gene .H.Miller . Micro Computer Engineering , Pearson Education , 2003.
5. John .B.Peatman , Design with PIC Microcontroller , Prentice hall, 1997.
6. James L.Antonakos , An Introduction to the Intel family of Microprocessors
Pearson Education 1999.
7. Barry.B.Breg, The Intel Microprocessors Architecture , Programming and
Interfacing , PHI,2002.
8. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprint
2001.
Prepared by
Signature
Name
Ms.L.Anju,Ms.S.Kalyani
Designation Assistant Professor
Date
05/09/2013
Approved by
Dr.S.Ganesh Vaidyanthan
HOD-EC
05/09/2013
