Getting Started With the NEXYS2

Spartan 3E Kit and Xilinx ISE

OVER VIEW
TheNexys2circuitboardisacomplete,readytousecircuitdevelopmentplatformbasedona
Xilinx Spartan 3E FPGA. The Nexys2 board input power input bus can be driven from a USB
cable,froma5VDC15VDC,centerpositive,2.1mmwallplugsupply,orfromabatterypack.A
shortingblockloadedonthepowerselectjumperselectsthepowersource.TheUSBcircuitry
is always powered from the USB cable if no USB cable is attached, the USB circuitry is left
unpowered.

Features:

500KgateXilinxSpartan3EFPGA
USB2basedFPGAconfigurationandhighspeeddata
transfers(usingthefreeAdeptSuiteSoftware)
USBpowered(batteriesand/orwallplugcanalsobeused)
16MBofMicronPSDRAM&16MBofIntelStrataFlashROM
XilinxPlatformFlashfornonvolatileFPGAconfigurations
Efficientswitchmodepowersupplies(goodforbatterypoweredapplications)
50MHzoscillatorplussocketforsecondoscillator
60FPGAI/Osroutedtoexpansionconnectors(onehighspeedHiroseFX2connectorand
four6pinheaders)
8LEDs,4digit7segdisplay,4buttons,8slideswitches
ShipsinaplasticcarrycasewithUSBcable

FPGA and Platform Flash Configuration

TheFPGAontheNexys2boardmustbeconfigured(orprogrammed)bytheuserbeforeitcan
performanyfunctions.Duringconfiguration,abitfileistransferredintomemorycellswithin
theFPGAtodefinethelogicalfunctionsandcircuitinterconnects.ThefreeISE/WebPackCAD
software from Xilinx can be used to create bit files from VHDL, Verilog, or schematicbased
sourcefiles.
TheFPGAcanbeprogrammedintwoways:directlyfromaPCusingtheonboardUSBport,
andfromanonboardPlatformFlashROM(theFlashROMisalsouserprogrammableviathe
USBport).AjumperontheNexys2boarddetermineswhichsource(PCorROM)theFPGAwill
use to load its configuration. The FPGA will automatically load a configuration from the
PlatformFlashROMatpoweroniftheconfigurationModejumperissettoMasterserial.If

theModejumperissettoJTAG,theFPGAwillawaitprogrammingfromthePC(viatheUSB
cable).
Digilents freely available PCbased Adept software can be used to configure the FPGA and
Platform Flash with any suitable file stored on the computer. Adept uses the USB cable to
transferaselectedbitfilefromthePCtotheFPGAorPlatformFlashROM.AftertheFPGAis
configured,itwillremainsountilitisresetbyapowercycleeventorbytheFPGAresetbutton
(BTNR)beingpressed.ThePlatformFlashROMwillretainabitfileuntilitisreprogrammed,
regardlessofpowercycleevents.

ToinstallDriversofthesoftware:

DownloadandinstallDigilentAdeptsuite(ADEPT1.10,32bitwindows)fromthefollowinglink
http://www.digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=451&Prod=NEXYS2

User I/O

TheNexys2boardincludesseveralinputdevices,outputdevices,anddataports,allowingmany
designstobeimplementedwithouttheneedforanyothercomponents.

Fourpushbuttonsandeightslideswitchesareprovidedforcircuitinputs.Pushbuttoninputsare
normally low, and they are driven high only when the pushbutton is pressed. Slide switches
generateconstanthighorlowinputsdependingontheirposition.Pushbuttonandslideswitch
inputsuseaseriesresistorforprotectionagainstshortcircuits(ashortcircuitwouldoccurifan
FPGApinassignedtoapushbuttonorslideswitchwasinadvertentlydefinedasanoutput).

TheNexys2boardcontainsafourdigitcommonanodesevensegmentLEDdisplay.Eachofthe
four digits is composed of seven segments arranged in a figure 8 pattern, with an LED
embeddedineachsegment.

PIN ASSIGNMENT:

TheProject

LetuswriteacodeforANDgateandimplementitonnexys2board.Wewouldliketoplacethe
ANDvalueoftwoinputsontherightmost7segmentdisplay,andleavetherestblank.

Tostartthedesign,firststartXilinxISE,andcreateanewProjectwithFile NewProject.When
specifyingtheprojectnameanddirectory,pickalocationwithoutanyspacesinthepath(i.e.
not the desktop) You will often find the Xilinx tools behaving very strangely with difficult to
diagnoseerrorsifyouhavespacesintheprojectpath.

ThenextstepwillbetospecifytheFPGAyouaretargeting.Thisisobviouslytheonethatison
theNEXYS2board.


Skipoverthenexttwopages,andclickFinishtocompletetheprojectcreationandbeginthe
designprocess.

EnteringVHDL

To describe the design, we will add one simple VHDL file to our project. Though this can be
donewithanytexteditor,itisconvenienttoallowtheISEtoolstocreatetheframeworkforus
sincewearestartingthefilefromscratch.Addinganexistingfileissimilarlyeasy,andcanbe
done with Project Add Copy of Source. Select Project New Source, and fill out the
dialogtellingthetoolstocreateanewVHDLmodulewiththenameand2_demo.vhd

Onthenextpage,youwillbepromptedtoentertheportsofyournewmodule.Thisisstrictly
optional,andsavesyouthetypingofcreatingtheVHDLentitymanually.Whetheryoufillthis
outornot,theresultanttextfilewillbetotallyunderyourcontrolforlaterediting.

WehaveenteredtheportswhichwillbeplacedintoourentityintheVHDLfile:theswitchesas
our inputs, and the seven segments to drive on the display as our outputs. Furthermore, we
haveincludedtheportanodeswhichwillbeusedtoenable/disableeachofthe4displays
individually.TheresultantVHDLfilelooksessentiallylikethis:

Xilinxhasconvenientlyleftaplaceforustoinsertthearchitectureofourdesign,whichwillbe
twoverysimplestatements:

AfterenteringtheVHDL,savethefile,andChecktheSyntaxforerrorsbyclickingonCheck
SyntaxunderSynthesizeintheProcessesPane.

AssigningPins

Thenexttaskistoassignourinputandoutputportstothecorrectlocations.Ifweneglected
thisstep,thepinswouldbeassignedbytheXilinxsoftwaretorandomlocations,whichwould
notbegood.Todothis,wemustfirstcreateonemorenewfile,theUniversalConstraintsFile
(.ucf).

Nowthatwehaveaconstraintsfilefortheproject,wecaneasilyassignpinsgraphicallyusing
AssignPackagePinsundertheUserConstraintssectionintheProcessPane.Thiscanalso
be entered by double clicking on the .ucf file that you just created from within Project
Navigator.Forthisexercisethough,wearegoingtoeditthe.ucffileintext,togetagoodfeel
forhowsimpleitis.
Single Click on your ucf file from within Project Navigator, and then Select Edit Constraints
(Text)fromtheProcessPaneasbelow.Thenyoucanedittheconstraintsasshownbelow.

NET"anode<0>"LOC="F17";
NET"anode<1>"LOC="H17";
NET"anode<2>"LOC="C18";
NET"anode<3>"LOC="F15";
NET"sevenseg<0>"LOC="L18";
NET"sevenseg<1>"LOC="F18";
NET"sevenseg<2>"LOC="D17";
NET"sevenseg<3>"LOC="D16";
NET"sevenseg<4>"LOC="G14";

NET"sevenseg<5>"LOC="J17";
NET"sevenseg<6>"LOC="H14";
NET"x"LOC="G18";
NET"y"LOC="H18";
NET"z"LOC="J14";

Savethefile,nowwearereadytotrythedesignontheFPGA.

Synthesis,Place+Route,ProgrammingFile

The next step in the process is to have the Xilinx ISE create a programming file for you. The
wholeprocesscanbecompletedbyclickingonceonyourtopleveldesignintheSourcesPane,
followed by a doubleclick on Generate Programming File. This will run the whole process,
andshouldcompleteasinthescreenshotbelow.

Nowthattheprogrammingfilehasbeengenerated,itistimetoloadyourdesignintotheFPGA,
andtestitout.

ConfigurationUsingtheUSBportandDigilentADEPTSoftwareSuite

OpentheExport.exefilefromthedigilentadeptfolder.

WhiletheUSBisattached,clickonInitializeChaintoidentifythedevicesontheboard.

ToprogramtheFPGA,browsetotheconfigurationfileandselectyourand2_demo.bit.
Similarly,ifyouwouldliketoprogramtheboardtostartonpowerupprogramthePROM
(XCF04S)withthefileaswell.

ClickProgramChainandwait.Whenconfigurationiscomplete,yourFPGAshouldbe
operatingasyourVHDLspecified.